ISL12029IBAZ-T

ISL12029, ISL12029A ® Data Sheet Real Time Clock/Calendar with I2C Bus™ and EEPROM The ISL12029 device is a low power real time clock with clock/calendar, power-fail indicator, clock output and crystal compensation, two periodic or polled alarms (open drain output), intelligent battery backup switching, CPU Supervisor, integrated 512x8-bit EEPROM configured in 16 bytes per page. The oscillator uses an external, low-cost 32.768kHz crystal. The real-time clock tracks time with separate registers for hours, minutes and seconds. The device has calendar registers for date, month, year and day of the week. The calendar is accurate through 2099, with automatic leap year correction. The ISL12029 and ISL12029A Power Control Settings are different. The ISL12029 uses the Legacy Mode Setting, and the ISL12029A uses the Standard Mode Setting. Applications that have VBAT > VDD will require only the ISL12029A. Please refer to “Power Control Operation” on page 14 for more details. Also, please refer to “I2C Communications During Battery Backup” on page 24 for important details. Pinout ISL12029, ISL12029A (14 LD TSSOP, SOIC) TOP VIEW X1 X2 NC NC NC RESET GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VDD December 16, 2010 Features • Real Time Clock/Calendar - Tracks Time in Hours, Minutes and Seconds - Day of the Week, Day, Month and Year - 3 Selectable Frequency Outputs • Two Non-Volatile Alarms - Settable on the Second, Minute, Hour, Day of the Week, Day or Month - Repeat Mode (periodic interrupts) • Automatic Backup to Battery or SuperCap - Power Failure Detection - 800nA Battery Supply Current • On-Chip Oscillator Compensation: - Internal Feedback Resistor and Compensation Capacitors - 64 Position Digitally Controlled Trim Capacitor - 6 Digital Frequency Adjustment Settings to ±30ppm • 512x8 Bits of EEPROM - 16-Byte Page Write Mode (32 total pages) - 8 Modes of BlockLock™ Protection - Single Byte Write Capability - Data Retention: 50 years - Endurance: >2,000,000 Cycles Per Byte • CPU Supervisor Functions - Power-On Reset, Low Voltage Sense - Watchdog Timer (0.25s, 0.75s, 1.5s) • I2C Interface - 400kHz Data Transfer Rate VBAT IRQ/FOUT NC NC • 14 Ld SOIC and 14 Ld TSSOP Packages SCL SDA • Pb-Free (RoHS Compliant) NC = No internal connection Applications • • • • • • • • • • • • • • 1 FN6206.10 Utility Meters HVAC Equipment Audio/Video Components Modems Network Routers, Hubs, Switches, Bridges Cellular Infrastructure Equipment Fixed Broadband Wireless Equipment Pagers/PDA POS Equipment Test Meters/Fixtures Office Automation (Copiers, Fax) Home Appliances Computer Products Other Industrial/Medical/AutomotivePAR CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. I2C Bus™ is a trademark owned by NXP Semiconductors Netherlands, B.V. BlockLock™ is a trademark of Intersil Corporation or one of its subsidiaries. Copyright Intersil Americas Inc. 2005, 2006, 2008, 2010. All Rights Reserved. All other trademarks mentioned are the property of their respective owners. ISL12029, ISL12029A Block Diagram OSC COMPENSATION 32.768kHZ X1 OSCILLATOR X2 IRQ/FOUT SDA TIME KEEPING REGISTERS (SRAM) BATTERY SWITCH CIRCUITRY VDD VBACK SELECT CONTROL SERIAL INTERFACE DECODE LOGIC DECODER CONTROL/ REGISTERS (EEPROM) STATUS REGISTERS 8 WATCHDOG TIMER RESET COMPARE ALARM (SRAM) MASK SCL TIMER FREQUENCY 1Hz CALENDAR DIVIDER LOGIC LOW VOLTAGE RESET ALARM REGS (EEPROM) 4k EEPROM ARRAY Pin Descriptions PIN NUMBER SYMBOL DESCRIPTION 1 X1 The X1 pin is the input of an inverting amplifier and is intended to be connected to one pin of an external 32.768kHz quartz crystal. 2 X2 The X2 pin is the output of an inverting amplifier and is intended to be connected to one pin of an external 32.768kHz quartz crystal. 6 RESET 7 GND Ground. 8 SDA Serial Data (SDA) is a bidirectional pin used to transfer serial data into and out of the device. It has an open drain output and may be wire OR’ed with other open drain or open collector outputs. 9 SCL The Serial Clock (SCL) input is used to clock all serial data into and out of the device. The input buffer on this pin is always active (not gated). 12 IRQ/FOUT Interrupt Output/Frequency Output is a multi-functional pin that can be used as interrupt or frequency output pin. It is an open drain output. The function is set via the configuration register. 13 VBAT This input provides a backup supply voltage to the device. VBAT supplies power to the device in the event that the VDD supply fails. This pin should be tied to ground if not used. 14 VDD Power Supply. 3, 4, 5, 10, 11 NC No Internal Connection. RESET. This is a reset signal output. This signal notifies a host processor that the “Watchdog” time period has expired or that the voltage has dropped below a fixed VTRIP threshold. It is an open drain active LOW output. Recommended value for the pull-up resistor is 5kΩ. If unused, connect to ground. 2 FN6206.10 December 16, 2010 ISL12029, ISL12029A Ordering Information VBAT TRIP POINT PART MARKING (V) BSW BIT DEFAULT SETTING VRESET VOLTAGE (V) TEMP. RANGE (°C) ISL12029IB27Z 12029IB27Z VDD < VBAT BSW = 1 2.63 -40 to +85 14 Ld SOIC M14.15 ISL12029IB27AZ 12029IB27 AZ VDD < VBAT BSW = 1 2.92 -40 to +85 14 Ld SOIC M14.15 ISL12029IB30AZ 12029IB30 AZ VDD < VBAT BSW = 1 3.09 -40 to +85 14 Ld SOIC M14.15 ISL12029IBZ 12029IBZ VDD < VBAT BSW = 1 4.38 -40 to +85 14 Ld SOIC M14.15 ISL12029IBAZ 12029IBAZ VDD < VBAT BSW = 1 4.64 -40 to +85 14 Ld SOIC M14.15 ISL12029IV27Z 12029 IV27Z VDD < VBAT BSW = 1 2.63 -40 to +85 14 Ld TSSOP M14.173 ISL12029IV27AZ 12029 27AZ VDD < VBAT BSW = 1 2.92 -40 to +85 14 Ld TSSOP M14.173 ISL12029IV30AZ 12029 30AZ VDD < VBAT BSW = 1 3.09 -40 to +85 14 Ld TSSOP M14.173 ISL12029IVZ 12029 IVZ VDD < VBAT BSW = 1 4.38 -40 to +85 14 Ld TSSOP M14.173 ISL12029IVAZ 12029 IVAZ VDD < VBAT BSW = 1 4.64 -40 to +85 14 Ld TSSOP M14.173 ISL12029AIB27Z 12029AIB 27Z 2.2 BSW = 0 2.63 -40 to +85 14 Ld SOIC M14.15 ISL12029AIV27Z 2029A IV27Z 2.2 BSW = 0 2.63 -40 to +85 14 Ld TSSOP M14.173 PART NUMBER (Notes 1, 2, 3) PACKAGE (Pb-free) PKG. DWG. # NOTES: 1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL12029, ISL12029A. For more information on MSL please see techbrief TB363. 3 FN6206.10 December 16, 2010 ISL12029, ISL12029A Absolute Maximum Ratings Thermal Information Voltage on VDD, VBAT, SCL, SDA, and IRQ/FOUT Pins (respect to ground) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V Voltage on X1 and X2 Pins (respect to ground) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.5V Latchup (Note 4) . . . . . . . . . . . . . . . . . . . Class II, Level B @ +85°C ESD Rating Human Body Model (MIL-STD-883, Method 3014) . . . . . . .>±2kV Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>175V Thermal Resistance (Typical) θJA (°C/W) θJC (°C/W) 14 Ld SOIC Package (Notes 5, 6) . . . . 90 40 14 Ld TSSOP Package (Note 5, 6) . . . 110 35 Maximum Junction Temperature (Plastic Package) . . . . . . . +150°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 4. Jedec Class II pulse conditions and failure criterion used. Level B exceptions are: Using a max positive pulse of 8.35V on all pins except X1 and X2, Using a max positive pulse of 2.75V on X1 and X2, and using a max negative pulse of -1V for all pins. 5. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 6. For θJC, the “case temp” location is taken at the package top center. DC Electrical Specifications Unless otherwise noted, VDD = +2.7V to +5.5V, TA = -40°C to +85°C, Typical values are at TA = +25°C and VDD = 3.3V. Boldface limits apply over the operating temperature range, -40°C to +85°C. SYMBOL PARAMETER CONDITIONS MIN (Note 16) TYP MAX (Note 16) UNIT VDD Main Power Supply 2.7 5.5 V VBAT Backup Power Supply 1.8 5.5 V Electrical Specifications SYMBOL IDD1 IDD2 IDD3 IBAT NOTES Boldface limits apply over the operating temperature range, -40°C to +85°C. MAX (Note 16) UNIT NOTES VDD = 2.7V 500 µA 7, 8, 9 VDD = 5.5V 800 µA Supply Current for Non-Volatile Programming VDD = 2.7V 2.5 mA VDD = 5.5V 3.5 mA Supply Current for Main Timekeeping (Low Power Mode) VDD = VSDA = VSCL = 2.7V 10 µA VDD = VSDA = VSCL = 5.5V 20 µA Battery Supply Current VBAT = 1.8V, VDD = VSDA = VSCL= VRESET = 0V 800 1000 nA VBAT = 3.0V, VDD = VSDA = VSCL= VRESET = 0V 850 1200 nA 100 nA 2.6 V 11 PARAMETER 2 Supply Current with I C Active IBATLKG Battery Input Leakage VTRIP VBAT Mode Threshold CONDITIONS VDD = 5.5V, VBAT = 1.8V MIN (Note 16) TYP -100 1.8 2.2 7, 8, 9 , 9 7, 10, 11 VTRIPHYS VTRIP Hysteresis 30 mV 11, 13 VBATHYS VBAT Hysteresis 50 mV 11, 13 VDD SR- VDD Negative Slew Rate 10 V/ms 12 VDD = 5.5V IOL = 3mA 0.4 V VDD = 2.7V IOL = 1mA 0.4 V 400 nA IRQ/FOUT, RESET OUTPUTS VOL ILO Output Low Voltage Output Leakage Current 4 VDD = 5.5V VOUT = 5.5V 100 FN6206.10 December 16, 2010 ISL12029, ISL12029A Watchdog Timer/Low Voltage Reset Parameters SYMBOL tRPD PARAMETER CONDITIONS MIN (Note 16) VDD Detect to RESET LOW TYP (Note 11) MAX (Note 16) 500 UNITS NOTES ns 13 tPURST Power-Up Reset Time-Out Delay 100 VRVALID Minimum VDD for Valid RESET Output 1.0 VRESET ISL12029-4.5A Reset Voltage Level 4.59 4.64 4.69 V ISL12029 Reset Voltage Level 4.33 4.38 4.43 V ISL12029-3 Reset Voltage Level 3.04 3.09 3.14 V ISL12029-2.7A Reset Voltage Level 2.87 2.92 2.97 V ISL12029-2.7 Reset Voltage Level 2.58 2.63 2.68 V 1.70 1.75 1.801 s 725 750 775 ms 225 250 275 ms 225 250 275 ms tWDO Watchdog Timer Period tRST Watchdog Timer Reset Time-Out Delay tRSP I2C Interface Minimum Restart Time 32.768kHz crystal between X1 and X2 32.768kHz crystal between X1 and X2 250 400 ms V 1.2 µs >2,000,000 Cycles 50 Years EEPROM SPECIFICATIONS EEPROM Endurance Temperature ≤ +75°C EEPROM Retention Serial Interface (I2C) Specifications - DC/AC Characteristics SYMBOL PARAMETER CONDITIONS MIN (Note 16) TYP MAX (Note 16) UNITS VIL SDA, and SCL Input Buffer LOW Voltage SBIB = 1 (Under VDD mode) -0.3 0.3 x VDD V VIH SDA, and SCL Input Buffer HIGH Voltage SBIB = 1 (Under VDD mode) 0.7 x VDD VDD + 0.3 V SBIB = 1 (Under VDD mode) 0.05 x VDD Hysteresis SDA and SCL Input Buffer Hysteresis SDA Output Buffer LOW Voltage IOL = 4mA ILI Input Leakage Current on SCL VIN = 5.5V ILO I/O Leakage Current on SDA VIN = 5.5V VOL NOTES V 0 0.4 V 0.1 10 µA 0.1 10 µA TIMING CHARACTERISTICS fSCL 400 kHz tIN SCL Frequency Pulse Width Suppression Time at SDA and SCL Inputs Any pulse narrower than the max spec is suppressed. 50 ns tAA SCL Falling Edge to SDA Output Data Valid SCL falling edge crossing 30% of VDD, until SDA exits the 30% to 70% of VDD window. 900 ns tBUF Time the Bus Must be Free Before the Start of a New Transmission SDA crossing 70% of VDD during a STOP condition, to SDA crossing 70% of VDD during the following START condition. 1300 ns tLOW Clock LOW Time Measured at the 30% of VDD crossing. 1300 ns 5 FN6206.10 December 16, 2010 ISL12029, ISL12029A Serial Interface (I2C) Specifications - DC/AC Characteristics (Continued) SYMBOL tHIGH PARAMETER CONDITIONS MIN (Note 16) TYP MAX (Note 16) UNITS Clock HIGH Time Measured at the 70% of VDD crossing. 600 ns tSU:STA START Condition Setup Time SCL rising edge to SDA falling edge. Both crossing 70% of VDD. 600 ns tHD:STA START Condition Hold Time From SDA falling edge crossing 30% of VDD to SCL falling edge crossing 70% of VDD. 600 ns tSU:DAT Input Data Setup Time From SDA exiting the 30% to 70% of VDD window, to SCL rising edge crossing 30% of VDD 100 ns tHD:DAT Input Data Hold Time From SCL falling edge crossing 70% of VDD to SDA entering the 30% to 70% of VDD window. 0 ns tSU:STO STOP Condition Setup Time From SCL rising edge crossing 70% of VDD, to SDA rising edge crossing 30% of VDD. 600 ns tHD:STO STOP Condition Hold Time for Read, or Volatile Only Write From SDA rising edge to SCL falling edge. Both crossing 70% of VDD. 600 ns tDH Output Data Hold Time From SCL falling edge crossing 30% of VDD, until SDA enters the 30% to 70% of VDD window. 0 ns Cpin SDA, and SCL Pin Capacitance tWC Non-Volatile Write Cycle Time 12 10 pF NOTES 20 ms 14 tR SDA and SCL Rise Time From 30% to 70% of VDD 20 + 0.1 x Cb 250 ns 15 tF SDA and SCL Fall Time From 70% to 30% of VDD 20 + 0.1 x Cb 250 ns 15 Cb Capacitive Loading of SDA or SCL Total on-chip and off-chip 10 400 pF 15 Rpu SDA and SCL Bus Pull-up Resistor Maximum is determined by tR and tF. Off-chip For Cb = 400pF, max is about 2kΩ~2.5kΩ. For Cb = 40pF, max is about 15kΩ~20kΩ 1 kΩ 15 NOTES: 7. IRQ/FOUT Inactive (no frequency output and no alarms). 8. VIL = VDD x 0.1, VIH = VDD x 0.9, fSCL = 400kHz. 9. VRESET = 2.63V (VDD must be greater than VRESET), VBAT = 0V. 10. Bit BSW = 0 (Standard Mode), ATR = 00h, VBAT ≥ 1.8V. 11. Specified at +25°C. 12. In order to ensure proper timekeeping, the VDD SR- specification must be followed. 13. Parameter is not 100% tested. 14. tWC is the minimum cycle time to be allowed for any non-volatile Write by the user, it is the time from valid STOP condition at the end of Write sequence of a serial interface Write operation, to the end of the self-timed internal non-volatile write cycle. 15. These are I2C specific parameters and are not directly tested, however they are used during device testing to validate device specification. 16. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. 6 FN6206.10 December 16, 2010 ISL12029, ISL12029A Timing Diagrams tHIGH tF SCL tLOW tR tHD:STO tSU:DAT tSU:STA tHD:DAT tSU:STO tHD:STA SDA (INPUT TIMING) tAA tDH tBUF SDA (OUTPUT TIMING) FIGURE 1. BUS TIMING SCL 8TH BIT OF LAST BYTE SDA ACK tWC STOP CONDITION START CONDITION FIGURE 2. WRITE CYCLE TIMING tRSP tRSP>tWDO tRSP>tWDO tRSP20ppm frequency deviation translates into an accuracy of >1 minute per month. These parameters are available from the crystal manufacturer. Intersil’s RTC family provides on-chip crystal compensation networks to adjust load-capacitance to tune oscillator frequency from -34ppm to +80ppm when using a 12.5pF load crystal. For more detailed information, see “Application Section” on page 23. Clock/Control Registers (CCR) The Control/Clock Registers are located in an area separate from the EEPROM array and are only accessible following a slave byte of “1101111x” and reads or writes to addresses [0000h:003Fh]. The clock/control memory map has memory addresses from 0000h to 003Fh. The defined addresses are described in Table 2. Writing to and reading from the undefined addresses are not recommended. Reading the Real Time Clock CCR Access The RTC is read by initiating a Read command and specifying the address corresponding to the register of the Real Time Clock. The RTC Registers can then be read in a Sequential Read Mode. Since the clock runs continuously and read takes a finite amount of time, there is a possibility that the clock could change during the course of a read operation. In this device, the time is latched by the read command (falling edge of the clock on the ACK bit prior to RTC data output) into a separate latch to avoid time changes during the read operation. The clock continues to run. Alarms occurring during a read are unaffected by the read operation. The contents of the CCR can be modified by performing a byte or a page write operation directly to any address in the CCR. Prior to writing to the CCR (except the status register), however, the WEL and RWEL bits must be set using a three step process (See “Writing to the Clock/Control Registers” on page 15.) Writing to the Real Time Clock The time and date may be set by writing to the RTC registers. RTC Register should be written ONLY with Page Write. To avoid changing the current time by an uncompleted write operation, write to the all 8 bytes in one write operation. When writing the RTC registers, the new time value is loaded into a separate buffer at the falling edge of the clock 10 The CCR is divided into 5 sections. These are: 1. Alarm 0 (8 bytes; non-volatile) 2. Alarm 1 (8 bytes; non-volatile) 3. Control (5 bytes; non-volatile) 4. Real Time Clock (8 bytes; volatile) 5. Status (1 byte; volatile) Each register is read and written through buffers. The non-volatile portion (or the counter portion of the RTC) is updated only if RWEL is set and only after a valid write operation and stop bit. A sequential read or page write operation provides access to the contents of only one section of the CCR per operation. Access to another section FN6206.10 December 16, 2010 ISL12029, ISL12029A requires a new operation. A read or write can begin at any address in the CCR. status and two alarm bits. This register is separate from both the array and the Clock/Control Registers (CCR). It is not necessary to set the RWEL bit prior to writing the status register. Section 5 (status register) supports a single byte read or write only. Continued reads or writes from this section terminates the operation. TABLE 1. STATUS REGISTER (SR) The state of the CCR can be read by performing a random read at any address in the CCR at any time. This returns the contents of that register location. Additional registers are read by performing a sequential read. The read instruction latches all Clock registers into a buffer, so an update of the clock does not change the time being read. A sequential read of the CCR will not result in the output of data from the memory array. At the end of a read, the master supplies a stop condition to end the operation and free the bus. After a read of the CCR, the address remains at the previous address +1 so the user can execute a current address read of the CCR and continue reading the next Register. Real Time Clock Registers (Volatile) SC, MN, HR, DT, MO, YR: Clock/Calendar Registers These registers depict BCD representations of the time. As such, SC (Seconds) and MN (Minutes) range from 00 to 59, HR (Hour) is 1 to 12 with an AM or PM indicator (H21-bit) or 0 to 23 (with MIL = 1), DT (Date) is 1 to 31, MO (Month) is 1 to 12, YR (Year) is 0 to 99. DW: Day of the Week Register This register provides a Day of the Week status and uses three bits DY2 to DY0 to represent the seven days of the week. The counter advances in the cycle 0-1-2-3-4-5-6-0-12-… The assignment of a numerical value to a specific day of the week is arbitrary and may be decided by the system software designer. The default value is defined as ‘0’. Y2K: Year 2000 Register Can have value 19 or 20. As of the date of the introduction of this device, there would be no real use for the value 19 in a true real time clock, however. 24-Hour Time If the MIL bit of the HR register is 1, the RTC uses a 24-hour format. If the MIL bit is 0, the RTC uses a 12-hour format and H21-bit functions as an AM/PM indicator with a ‘1’, representing PM. The clock defaults to standard time with H21 = 0. Leap Years Leap years add the day February 29 and are defined as those years that are divisible by 4. ADDR 7 6 003Fh BAT AL1 Default 0 0 5 4 AL0 OSCF 0 0 3 2 1 0 0 RWEL WEL RTCF 0 0 0 1 BAT: Battery Supply This bit set to “1” indicates that the device is operating from VBAT, not VDD. It is a read-only bit and is set/reset by hardware (ISL12029 internally). Once the device begins operating from VDD, the device sets this bit to “0”. AL1, AL0: Alarm Bits These bits announce if either alarm 0 or alarm 1 match the real time clock. If there is a match, the respective bit is set to ‘1’. The falling edge of the last data bit in a SR Read operation resets the flags. Note: Only the AL bits that are set when an SR read starts will be reset. An alarm bit that is set by an alarm occurring during an SR read operation will remain set after the read operation is complete. OSCF: Oscillator Fail Indicator This bit is set to "1" if the oscillator is not operating or is operating but has clock jitter, which does not affect the accuracy of RTC counting. The bit is set to "0" if the oscillator is functioning and does not have clock jitter. This bit is read only, and is set/reset by hardware. RWEL: Register Write Enable Latch This bit is a volatile latch that powers up in the LOW (disabled) state. The RWEL bit must be set to “1” prior to any writes to the Clock/Control Registers. Writes to RWEL bit do not cause a non-volatile write cycle, so the device is ready for the next operation immediately after the stop condition. A write to the CCR requires both the RWEL and WEL bits to be set in a specific sequence. WEL: Write Enable Latch The WEL bit controls the access to the CCR during a write operation. This bit is a volatile latch that powers up in the LOW (disabled) state. While the WEL bit is LOW, writes to the CCR address will be ignored, although acknowledgment is still issued. The WEL bit is set by writing a “1” to the WEL bit and zeroes to the other bits of the Status Register. Once set, WEL remains set until either reset to 0 (by writing a “0” to the WEL bit and zeroes to the other bits of the Status Register) or until the part powers up again. Writes to WEL bit do not cause a non-volatile write cycle, so the device is ready for the next operation immediately after the stop condition. Status Register (SR) (Volatile) RTCF: Real Time Clock Fail Bit The Status Register is located in the CCR memory map at address 003Fh. This is a volatile register only and is used to control the WEL and RWEL write enable latches, read power This bit is set to a “1” after a total power failure. This is a read only bit that is set by hardware (ISL12029 internally) when the device powers up after having lost all power to 11 FN6206.10 December 16, 2010 ISL12029, ISL12029A to their default states and the clock will not increment until at least one byte is written to the clock register. The first valid write to the RTC section after a complete power failure resets the RTCF bit to “0” (writing one byte is sufficient). the device (both VDD and VBAT go to 0V). The bit is set regardless of whether VDD or VBAT is applied first. The loss of only one of the supplies does not set the RTCF bit to “1”. On power-up after a total power failure, all registers are set ISL12029 DEFAULT ISL12029A DEFAULT TABLE 2. CLOCK/CONTROL MEMORY MAP 01h 01h 19/20 20h 20h 0-6 00h 00h Y10 0-99 00h 00h G10 1-12 00h 00h 1-31 01h 01h 0-23 00h 00h 0-59 00h 00h BIT ADDR. TYPE REG NAME 7 6 5 4 3 2 1 0 003F Status SR BAT AL1 AL0 OSCF 0 RWEL WEL RTCF 0037 RTC (SRAM) Y2K 0 0 Y2K21 Y2K20 Y2K13 0 0 Y2K10 DW 0 0 0 0 0 DY2 DY1 DY0 0035 YR Y23 Y22 Y21 Y20 Y13 Y12 Y11 0034 MO 0 0 0 G20 G13 G12 G11 0033 DT 0 0 D21 D20 D13 D12 D11 D10 0032 HR MIL 0 H21 H20 H13 H12 H11 H10 0031 MN 0 M22 M21 M20 M13 M12 M11 M10 0-59 0036 0030 0014 0013 Control (EEPROM) RANGE SC 0 S22 S21 S20 S13 S12 S11 S10 00h 00h PWR SBIB BSW 0 0 0 VTS2 VTS1 VTS0 4Xh 0Xh DTR 0 0 0 0 0 DTR2 DTR1 DTR0 00h 00h 0012 ATR 0 0 ATR5 ATR4 ATR3 ATR2 ATR1 ATR0 00h 00h 0011 INT IM AL1E AL0E FO1 FO0 0 0 0 00h 00h 0010 BL BP2 BP1 BP0 WD1 WD0 0 0 0 18h 18h Y2K1 0 0 0 0 A1Y2K10 19/20 20h 20h DWA1 EDW1 0 DY2 DY1 DY0 0-6 00h 00h 000F 000E Alarm1 (EEPROM) A1Y2K21 A1Y2K20 A1Y2K13 0 0 0 000D YRA1 Unused - Default = RTC Year value (No EEPROM) - Future expansion 000C MOA1 EMO1 0 0 A1G20 A1G13 A1G12 A1G11 A1G10 1-12 00h 00h 000B DTA1 EDT1 0 A1D21 A1D20 A1D13 A1D12 A1D11 A1D10 1-31 00h 00h 000A HRA1 EHR1 0 A1H21 A1H20 A1H13 A1H12 A1H11 A1H10 0-23 00h 00h 0009 MNA1 EMN1 A1M22 A1M21 A1M20 A1M13 A1M12 A1M11 A1M10 0-59 00h 00h 0008 SCA1 ESC1 A1S22 A1S21 A1S20 A1S13 A1S12 A1S11 A1S10 0-59 00h 00h Y2K0 0 0 0 0 A0Y2K10 19/20 20h 20h DWA0 EDW0 0 DY2 DY1 DY0 0-6 00h 00h 0007 0006 Alarm0 (EEPROM) A0Y2K21 A0Y2K20 A0Y2K13 0 0 0 0005 YRA0 0004 MOA0 EMO0 Unused - Default = RTC Year value (No EEPROM) - Future expansion 0 0 A0G20 A0G13 A0G12 A0G11 A0G10 1-12 00h 00h 0003 DTA0 EDT0 0 A0D21 A0D20 A0D13 A0D12 A0D11 A0D10 1-31 00h 00h 0002 HRA0 EHR0 0 A0H21 A0H20 A0H13 A0H12 A0H11 A0H10 0-23 00h 00h 0001 MNA0 EMN0 A0M22 A0M21 A0M20 A0M13 A0M12 A0M11 A0M10 0-59 00h 00h 0000 SCA0 ESC0 A0S22 A0S21 A0S20 A0S13 A0S12 A0S11 A0S10 0-59 00h 00h NOTE: Shaded cells indicate that NO other value is to be written to that bit. X indicates the bits are set according to the product variation, see device “Ordering Information on “” on page 3. 12 FN6206.10 December 16, 2010 ISL12029, ISL12029A Unused Bits: Bit 3 in the SR is not used, but must be zero. The Data Byte output during a SR read will contain a zero in this bit location. Alarm Registers (Non-Volatile) Alarm0 and Alarm1 The alarm register bytes are set up identical to the RTC register bytes, except that the MSB of each byte functions as an enable bit (enable = “1”). These enable bits specify which alarm registers (seconds, minutes, etc.) are used to make the comparison. Note that there is no alarm byte for year. The alarm function works as a comparison between the alarm registers and the RTC registers. As the RTC advances, the alarm will be triggered once a match occurs between the alarm registers and the RTC registers. Any one alarm register, multiple registers, or all registers can be enabled for a match. See “Device Operation” on page 15 and “Application Section” on page 23 for more information. Control Registers (Non-Volatile) The Control Bits and Registers described in the following are non-volatile. BL Register both bits are set to ‘1’ and both the FO1 and FO0 bits are set to 0 (FOUT disabled). The IM bit enables the pulsed interrupt mode. To enter this mode, the AL0E or AL1E bits are set to “1”, and the IM bit to “1”. The IRQ/FOUT output will now be pulsed each time an alarm occurs. This means that once the interrupt mode alarm is set, it will continue to alarm for each occurring match of the alarm and present time. This mode is convenient for hourly or daily hardware interrupts in microcontroller applications such as security cameras or utility meter reading. In the case that both Alarm 0 and Alarm 1 are enabled, the IRQ/FOUT pin will be pulsed each time either alarm matches the RTC (both alarms can provide hardware interrupt). If the IM bit is also set to "1", the IRQ/FOUT will be pulsed for each of the alarms as well. FO1, FO0 - Programmable Frequency Output Bits These are two output control bits. They select one of three divisions of the internal oscillator, that is applied to the IRQ/ FOUT output pin. Table 4 shows the selection bits for this output. When using this function, the Alarm output function is disabled. TABLE 4. PROGRAMMABLE FREQUENCY OUTPUT BITS BP2, BP1, BP0 - Block Protect Bits The Block Protect Bits, BP2, BP1 and BP0, determine which blocks of the array are write protected. A write to a protected block of memory is ignored. The block protect bits will prevent write operations to one of eight segments of the array. The partitions are described in Table 3. TABLE 3. BLOCK PROTECT BITS PARTITIONS PROTECTED ADDRESSES ISL12029 ARRAY LOCK FO1 FO0 OUTPUT FREQUENCY 0 0 Alarm output (FOUT disabled) 0 1 32.768kHz 1 0 4096Hz 1 1 1Hz Oscillator Compensation Registers BP2 BP1 BP0 There are two trimming options. 0 0 0 None (Default) None 0 0 1 180h – 1FFh Upper 1/4 0 1 0 100h – 1FFh Upper 1/2 0 1 1 000h – 1FFh Full Array 1 0 0 000h – 03Fh First 4 Pages 1 0 1 000h – 07Fh First 8 Pages 1 1 0 000h – 0FFh First 16 Pages 1 1 1 000h – 1FFh Full Array INT Register: Interrupt Control and Frequency Output Register - ATR - Analog Trimming Register - DTR - Digital Trimming Register These registers are non-volatile. The combination of analog and digital trimming can give up to -64ppm to +110 ppm of total adjustment. ATR Register - ATR5, ATR4, ATR3, ATR2, ATR1, ATR0: Analog Trimming Register Six analog trimming bits, ATR0 to ATR5, are provided in order to adjust the on-chip load capacitance value for frequency compensation of the RTC. Each bit has a different weight for capacitance adjustment. For example, using a Citizen CFS-206 crystal with different ATR bit combinations provides an estimated ppm adjustment range from -34ppm to +80ppm to the nominal frequency compensation. IM, AL1E, AL0E - Interrupt Control and Status Bits There are two Interrupt Control bits, Alarm 1 Interrupt Enable (AL1E) and Alarm 0 Interrupt Enable (AL0E) to specifically enable or disable the alarm interrupt signal output (IRQ/FOUT). The interrupts are enabled when either the AL1E or AL0E or 13 FN6206.10 December 16, 2010 ISL12029, ISL12029A TABLE 5. DIGITAL TRIMMING REGISTERS (Continued) X1 DTR REGISTER CX1 CRYSTAL OSCILLATOR X2 CX2 FIGURE 12. DIAGRAM OF ATR The effective on-chip series load capacitance, CLOAD, ranges from 4.5pF to 20.25pF with a mid-scale value of 12.5pF (default). CLOAD is changed via two digitally controlled capacitors, CX1 and CX2, connected from the X1 and X2 pins to ground (see Figure 11). The value of CX1 and CX2 is given by Equation 1: C X = ( 16 ⋅ b5 + 8 ⋅ b4 + 4 ⋅ b3 + 2 ⋅ b2 + 1 ⋅ b1 + 0.5 ⋅ b0 + 9 )pF (EQ. 1) The effective series load capacitance is the combination of CX1 and CX2 given in Equation 2: C 1 LOAD = ----------------------------------- 1 1 ⎛ ---------- + -----------⎞ ⎝C C ⎠ X1 X2 16 ⋅ b5 + 8 ⋅ b4 + 4 ⋅ b3 + 2 ⋅ b2 + 1 ⋅ b1 + 0.5 ⋅ b0 + 9 C LOAD = ⎛ -----------------------------------------------------------------------------------------------------------------------------⎞ pF ⎝ ⎠ 2 (EQ. 2) For example, CLOAD(ATR = 00000) = 12.5pF, CLOAD(ATR = 100000) = 4.5pF, and CLOAD(ATR = 011111) = 20.25pF. The entire range for the series combination of load capacitance goes from 4.5pF to 20.25pF in 0.25pF steps. Note that these are typical values. DTR Register - DTR2, DTR1, DTR0: Digital Trimming Register The digital trimming Bits DTR2, DTR1 and DTR0 adjust the number of counts per second and average the ppm error to achieve better accuracy. DTR2 is a sign bit. DTR2 = 0 means frequency compensation is > 0. DTR2 = 1 means frequency compensation is < 0. DTR1 and DTR0 are scale bits. DTR1 gives 10ppm adjustment and DTR0 gives 20ppm adjustment. A range from -30ppm to +30ppm can be represented by using the three DTR bits. TABLE 5. DIGITAL TRIMMING REGISTERS DTR REGISTER DTR2 DTR1 DTR0 ESTIMATED FREQUENCY PPM 0 0 0 0 14 DTR2 DTR1 DTR0 ESTIMATED FREQUENCY PPM 0 1 0 +10 0 0 1 +20 0 1 1 +30 1 0 0 0 1 1 0 -10 1 0 1 -20 1 1 1 -30 PWR Register: SBIB, BSW, VTS2, VTS1, VTS0 SBIB: Serial Bus Interface (Enable) The serial bus can be disabled in battery backup mode by setting this bit to “1”. This will minimize power drain on the battery. The Serial Interface can be enabled in battery backup mode by setting this bit to “0”. (default is “0”). See “RESET” on page 9 and “Power Control Operation” on page 16. BSW: Power Control Bit The Power Control bit, BSW, determines the conditions for switching between VDD and Back Up Battery. There are two options. Option 1 Standard Mode: Set “BSW = 0” (default for ISL12029A) Option 2 Legacy/Default Mode: Set “BSW = 1” (default for ISL12029) See “Power Control Operation” on page 16 for more details. Also see “I2C Communications During Battery Backup and LVR Operation” on page 25 for important details. VTS2, VTS1, VTS0: VRESET Select Bits The ISL12029 is shipped with a default VDD threshold (VRESET) per the ordering information table. This register is a non-volatile with no protection, therefore any writes to this location can change the default value from that marked on the package. If not changed with a non-volatile write, this value will not change over normal operating and storage conditions. However, ISL12029 has four (4) additional selectable levels to fit the customers application. Levels are: 4.64V(default), 4.38V, 3.09V, 2.92V and 2.63V. The VRESET selection is via 3 bits (VTS2, VTS1 and VTS0) (see Table 6). Care should be taken when changing the VRESET select bits. If the VRESET voltage selected is higher than VDD, then the device will go into RESET and unless VDD is increased, the device will no longer be able to communicate using the I2C bus. FN6206.10 December 16, 2010 ISL12029, ISL12029A TABLE 6. VRESET SELECT BITS VTS2 VTS1 VTS0 VRESET (V) 0 0 0 4.64 0 0 1 4.38 0 1 0 3.09 0 1 1 2.92 1 0 0 2.63 In battery mode, the RESET signal output is asserted LOW when the VDD voltage supply has dipped below the VRESET threshold, but the RESET signal output will not return HIGH until the device is back to VDD mode even the VDD voltage is above VRESET threshold. Device Operation Writing to the Clock/Control Registers Changing any of the bits of the clock/control registers requires the following steps: 1. Write a 02h to the Status Register to set the Write Enable Latch (WEL). This is a volatile operation, so there is no delay after the write. (Operation preceded by a start and ended with a stop). 2. Write a 06h to the Status Register to set both the Register Write Enable Latch (RWEL) and the WEL bit. This is also a volatile cycle. The zeros in the data byte are required. (Operation proceeded by a start and ended with a stop). Write all eight bytes to the RTC registers, or one byte to the SR, or one to five bytes to the control registers. This sequence starts with a start bit, requires a slave byte of “11011110” and an address within the CCR and is terminated by a stop bit. A write to the EEPROM registers in the CCR will initiate a non-volatile write cycle and will take up to 20ms to complete. A write to the RTC registers (SRAM) will require much shorter cycle time (t = tBUF). Writes to undefined areas have no effect. The RWEL bit is reset by the completion of a write to the CCR, so the sequence must be repeated to again initiate another change to the CCR contents. If the sequence is not completed for any reason (by sending an incorrect number of bits or sending a start instead of a stop, for example) the RWEL bit is not reset and the device remains in an active mode. Writing all zeros to the status register resets both the WEL and RWEL bits. A read operation occurring between any of the previous operations will not interrupt the register write operation. Alarm Operation Since the alarm works as a comparison between the alarm registers and the RTC registers, it is ideal for notifying a host processor of a particular time event and trigger some action as a result. The host can be notified by either a hardware interrupt (the IRQ/FOUT pin) or by polling the Status Register (SR) Alarm bits. These two volatile bits (AL1 for Alarm 1 and AL0 for Alarm 0), indicate if an alarm has happened. The bits are set on an alarm condition regardless of whether the IRQ/ 15 FOUT interrupt is enabled. The AL1 and AL0 bits in the status register are reset by the falling edge of the eighth clock of status register read. There are two alarm operation modes: Single Event and periodic Interrupt Mode: 1. Single Event Mode is enabled by setting the AL0E or AL1E bit to “1”, the IM bit to “0”, and disabling the frequency output. This mode permits a one-time match between the alarm registers and the RTC registers. Once this match occurs, the AL0 or AL1 bit is set to “1” and the IRQ/FOUT output will be pulled low and will remain low until the AL0 or AL1 bit is read, which will automatically resets it. Both Alarm registers can be set at the same time to trigger alarms. The IRQ/FOUT output will be set by either alarm, and will need to be cleared to enable triggering by a subsequent alarm. Polling the SR will reveal which alarm has been set. 2. Interrupt Mode (or “Pulsed Interrupt Mode” or PIM) is enabled by setting the AL0E or AL1E bit to “1” the IM bit to “1”, and disabling the frequency output. If both AL0E and AL1E bits are set to "1", then both AL0E and AL1E PIM alarms will function. The IRQ/FOUT output will now be pulsed each time each of the alarms occurs. This means that once the interrupt mode alarm is set, it will continue to alarm for each occurring match of the alarm and present time. This mode is convenient for hourly or daily hardware interrupts in microcontroller applications such as security cameras or utility meter reading. Interrupt Mode CANNOT be used for general periodic alarms, however, since a specific time period cannot be programmed for interrupt, only matches to a specific time of day. The interrupt mode is only stopped by disabling the IM bit or the Alarm Enable bits. Writing to the Alarm Registers The Alarm Registers are non-volatile but require special attention to insure a proper non-volatile write takes place. Specifically, byte writes to individual registers are good for all but registers 0006h and 0000Eh, which are the DWA0 and DWA1 registers, respectively. Those registers will require a special page write for non-volatile storage. The recommended page write sequences are as follows: 1. 16-byte page writes: The best way to write or update the Alarm Registers is to perform a 16-byte write beginning at address 0001h (MNA0) and wrapping around and ending at address 0000h (SCA0). This will insure that non-volatile storage takes place. This means that the code must be designed so that the Alarm0 data is written starting with Minutes register, and then all the Alarm1 data, with the last byte being the Alarm0 Seconds (the page ends at the Alarm1 Y2k register and then wraps around to address 0000h). Alternatively, the 16-byte page write could start with address 0009h, wrap around and finish with address 0008h. Note that any page write ending at address 0007h or 000Fh (the highest byte in each Alarm) will not trigger a non-volatile write, so wrapping around or FN6206.10 December 16, 2010 ISL12029, ISL12029A overlapping to the following Alarm's Seconds register is advised. 2. Other non-volatile writes: It is possible to do writes of less than an entire page, but the final byte must always be addresses 0000h through 0004h or 0008h though 000Ch to trigger a non-volatile write. Writing to those blocks of 5 bytes sequentially, or individually, will trigger a non-volatile write. If the DWA0 or DWA1 registers need to be set, then enough bytes will need to be written to overlap with the other Alarm register and trigger the non-volatile write. For Example, if the DWA0 register is being set, then the code can start with a multiple byte write beginning at address 0006h, and then write 3 bytes ending with the SCA1 register as follows: Addr 0006h 0007h 0008h Name DWA0 Y2K0 SCA1 prevented since the battery backup input will only be used when the VDD supply is shut off. To select Option 1, BSW bit in the Power Register must be set to “BSW = 0”. A description of power switchover follows. Standard Mode Power Switchover • Normal Operating Mode (VDD) to Battery Backup Mode (VBAT) To transition from the VDD to VBAT mode, both of the following conditions must be met: - Condition 1: VDD < VBAT - VBATHYS where VBATHYS ≈ 50mV - Condition 2: VDD < VTRIP where VTRIP ≈ 2.2V If the Alarm1 is used, SCA1 would need to have the correct data written. Power Control Operation The power control circuit accepts a VDD and a VBAT input. Many types of batteries can be used with Intersil RTC products. For example, 3.0V or 3.6V Lithium batteries are appropriate, and battery sizes are available that can power an Intersil RTC device for up to 10 years. Another option is to use a SuperCap for applications where VDD is interrupted for up to a month. See “Application Section” on page 23 for more information. There are two options for setting the change-over conditions from VDD to Battery back-up mode. The BSW bit in the PWR register controls this operation. Option 1 - Standard Mode (Default for ISL12029A) Option 2 - Legacy Mode (Default for ISL12029) TABLE 7. VBAT TRIP POINT WITH DIFFERENT BSW SETTING BSW BIT VBAT TRIP POINT (V) 0 2.2 1 VDD < VBAT POWER CONTROL SETTING Standard Mode (ISL12029A) Legacy Mode (ISL12029) Note that applications that have VBAT > VDD will require the ISL12029A (standard mode) for proper startup. Note that the I2C bus may or may not be operational during battery backup, that function is controlled by the SBIB bit. That operation is covered after the power control section. OPTION 1 - STANDARD POWER CONTROL MODE (DEFAULT FOR ISL12029A) In the Standard mode, the supply will switch over to the battery when VDD drops below VTRIP or VBAT, whichever is lower. In this mode, accidental operation from the battery is • Battery Backup Mode (VBAT) to Normal Mode (VDD) The ISL12029 device will switch from the VBAT to VDD mode when one of the following conditions occurs: - Condition 1: VDD > VBAT + VBATHYS where VBATHYS ≈ 50mV - Condition 2: VDD > VTRIP + VTRIPHYS where VTRIPHYS ≈ 30mV There are two discrete situations that are possible when using Standard Mode: VBAT < VTRIP and VBAT > VTRIP. These two power control situations are illustrated in Figures 13 and 14. BATTERY BACKUP MODE VDD VTRIP 2.2V VBAT 1.8V VBAT + VBATHYS VBAT - VBATHYS FIGURE 13. BATTERY SWITCHOVER WHEN VBAT < VTRIP BATTERY BACKUP MODE VDD VBAT 3.0V VTRIP 2.2V VTRIP VTRIP + VTRIPHYS FIGURE 14. BATTERY SWITCHOVER WHEN VBAT > VTRIP 16 FN6206.10 December 16, 2010 ISL12029, ISL12029A OPTION 2 - LEGACY POWER CONTROL MODE (DEFAULT FOR ISL12029) system to begin operation. Recommended slew rate is between 0.2V/ms and 50V/ms. The Legacy Mode follows conditions set in X1226 products. In this mode, switching from VDD to VBAT is simply done by comparing the voltages and the device operates from whichever is the higher voltage. Care should be taken when changing from Normal to Legacy Mode. If the VBAT voltage is higher than VDD, then the device will enter battery backup and unless the battery is disconnected or the voltage decreases, the device will no longer operate from VDD. If that is the situation on initial power-up, then I2C communication may not be possible. For these applications, the ISL12029A should be used. NOTE: If the VBAT voltage drops below the data sheet minimum of 1.8V and the VDD power cycles to 0V then back to VDD voltage, then the RESET output may stay low and the I2C communications will not operate. The VBAT and VDD power will need to be cycled to 0V together to allow normal operation again. To select the Option 2, BSW bit in the Power Register must be set to “BSW = 1.” Watchdog Timer Operation The Watchdog timer time-out period is selectable. By writing a value to WD1 and WD0, the Watchdog timer can be set to 3 different time-out periods or off. When the Watchdog timer is set to off, the Watchdog circuit is configured for low power operation (see Table 8). TABLE 8. WATCHDOG TIMER OPERATION • Normal Mode (VDD) to Battery Backup Mode (VBAT) WD1 WD0 DURATION 1 1 disabled 1 0 250ms VDD < VBAT - VBATHYS 0 1 750ms • Battery Backup Mode (VBAT) to Normal Mode (VDD) 0 0 1.75s To transition from the VDD to VBAT mode, the following conditions must be met: The device will switch from the VBAT to VDD mode when the following condition occurs: VDD > VBAT +VBATHYS The Legacy Mode power control conditions are illustrated in Figure 15. VDD VOLTAGE ON VBAT IN OFF FIGURE 15. BATTERY SWITCHOVER IN LEGACY MODE Watchdog Timer Restart The Watchdog Timer is started by a falling edge of SDA when the SCL line is high (START condition). The start signal restarts the Watchdog timer counter, resetting the period of the counter back to the maximum. If another START fails to be detected prior to the Watchdog timer expiration, then the RESET pin becomes active for one reset time out period. In the event that the start signal occurs during a reset time out period, the start will have no effect. When using a single START to refresh Watchdog timer, a STOP condition should be followed to reset the device back to stand-by mode (see Figure 3). In battery mode, the Watchdog timer function is disabled. Low Voltage Reset (LVR) Operation Power-on Reset Application of power to the ISL12029 activates a Power-on Reset Circuit that pulls the RESET pin active. This signal provides several benefits. - It prevents the system microprocessor from starting to operate with insufficient voltage. - It prevents the processor from operating prior to stabilization of the oscillator. - It allows time for an FPGA to download its configuration prior to initialization of the circuit. - It prevents communication to the EEPROM, greatly reducing the likelihood of data corruption on power-up. When VDD exceeds the device VRESET threshold value for typically 250ms the circuit releases RESET, allowing the 17 When a power failure occurs, a voltage comparator compares the level of the VDD line versus a preset threshold voltage (VRESET), then generates a RESET pulse if it is below VRESET. The reset pulse will time-out 250ms after the VDD line rises above VRESET. If the VDD remains below VRESET, then the RESET output will remain asserted low. Power-up and power-down waveforms are shown in Figure 4. The LVR circuit is to be designed so the RESET signal is valid down to VDD = 1.0V. When the LVR signal is active, unless the part has been switched into the battery mode, the completion of an in-progress non-volatile write cycle is unaffected, allowing a non-volatile write to continue as long as possible (down to the Reset Valid Voltage). The LVR signal, when active, will terminate any in-progress communications to the device and prevents new commands from disrupting any current write FN6206.10 December 16, 2010 ISL12029, ISL12029A operations. See “I2C Communications During Battery Backup and LVR Operation” on page 25. STOP CONDITION In battery mode, the RESET signal output is asserted LOW when the VDD voltage supply has dipped below the VRESET threshold. The RESET signal output will not return HIGH until the device is back to VDD mode even the VDD voltage is above VRESET threshold. All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA when SCL is HIGH. The stop condition is also used to place the device into the Standby power mode after a read sequence. A stop condition can only be issued after the transmitting device has released the bus (see Figure 17). ACKNOWLEDGE Serial Communication The device supports the I2C bidirectional serial bus protocol. CLOCK AND DATA Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions (see Figure 16). START CONDITION All commands are preceded by the start condition, which is a HIGH to LOW transition of SDA when SCL is HIGH. The device continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met (see Figure 17). Acknowledge is a software convention used to indicate successful data transfer. The transmitting device, either master or slave, will release the bus after transmitting 8-bits. During the ninth clock cycle, the receiver will pull the SDA line LOW to acknowledge that it received the 8-bits of data (refer to Figure 18). The device will respond with an acknowledge after recognition of a start condition and if the correct Device Identifier and Select bits are contained in the Slave Address Byte. If a write operation is selected, the device will respond with an acknowledge after the receipt of each subsequent 8-bit word. The device will not acknowledge if the slave address byte is incorrect. SCL SDA DATA STABLE DATA CHANGE DATA STABLE FIGURE 16. VALID DATA CHANGES ON THE SDA BUS SCL SDA START STOP FIGURE 17. VALID START AND STOP CONDITIONS SCL FROM MASTER 1 8 9 DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER START ACKNOWLEDGE FIGURE 18. ACKNOWLEDGE RESPONSE FROM RECEIVER 18 FN6206.10 December 16, 2010 ISL12029, ISL12029A The last bit of the Slave Address Byte defines the operation to be performed. When this R/W bit is a one, then a read operation is selected. A zero selects a write operation (refer to Figure 19). In the read mode, the device will transmit 8 bits of data, release the SDA line, then monitor the line for an acknowledge. If an acknowledge is detected and no stop condition is generated by the master, the device will continue to transmit data. The device will terminate further data transmissions if an acknowledge is not detected. The master must then issue a stop condition to return the device to Standby mode and place the device into a known state. After loading the entire Slave Address Byte from the SDA bus, the ISL12029 compares the device identifier and device select bits with ‘1010111’ or ‘1101111’. Upon a correct compare, the device outputs an acknowledge on the SDA line. Device Addressing Following the Slave Byte is a two byte word address. The word address is either supplied by the master device or obtained from an internal counter. On power-up the internal address counter is set to address 0h, so a current address read of the EEPROM array starts at address 0. When required, as part of a random read, the master must supply the 2 Word Address Bytes as shown in Figure 19. Following a start condition, the master must output a Slave Address Byte. The first 4 bits of the Slave Address Byte specify access to either the EEPROM array or to the CCR. Slave bits ‘1010’ access the EEPROM array. Slave bits ‘1101’ access the CCR. When shipped from the factory, EEPROM array is UNDEFINED, and should be programmed by the customer to a known state. In a random read operation, the slave byte in the “dummy write” portion must match the slave byte in the “read” section. That is if the random read is from the array the slave byte must be 1010111x in both instances. Similarly, for a random read of the Clock/Control Registers, the slave byte must be 1101111x in both places. Bit 3 through Bit 1 of the slave byte specify the device select bits. These are set to ‘111’. DEVICE IDENTIFIER ARRAY CCR SLAVE ADDRESS BYTE BYTE 0 1 1 0 1 1 0 0 1 1 1 1 R/W 0 0 0 0 0 0 0 A8 WORD ADDRESS 1 BYTE 1 A7 A6 A5 A4 A3 A2 A1 A0 WORD ADDRESS 0 BYTE 2 D7 D6 D5 D4 D3 D2 D1 D0 DATA BYTE BYTE 3 FIGURE 19. SLAVE ADDRESS, WORD ADDRESS, AND DATA BYTES (64 BYTE PAGES) 19 FN6206.10 December 16, 2010 ISL12029, ISL12029A Write Operations Byte Write For a write operation, the device requires the Slave Address Byte and the Word Address Bytes. This gives the master access to any one of the words in the array or CCR. (Note: Prior to writing to the CCR, the master must write a 02h, then 06h to the status register in two preceding operations to enable the write operation. See “Writing to the Clock/Control Registers” on page 15. Upon receipt of each address byte, the ISL12029 responds with an acknowledge. After receiving both address bytes the ISL12029 awaits the eight bits of data. After receiving the 8 data bits, the ISL12029 again responds with an acknowledge. The master then terminates the transfer by generating a stop condition. The ISL12029 then begins an internal write cycle of the data to the non-volatile memory. During the internal write cycle, the device inputs are disabled, so the device will not respond to any requests from the master. The SDA output is at high impedance (see Figure 20). A write to a protected block of memory is ignored, but will still receive an acknowledge. At the end of the write command, the ISL12029 will not initiate an internal write cycle, and will continue to ACK commands. Byte writes to all of the non-volatile registers are allowed, except the DWAn registers which require multiple byte writes or page writes to trigger non-volatile writes. See “Device Operation” on page 15 for more information. Page Write The ISL12029 has a page write operation. It is initiated in the same manner as the byte write operation; but instead of terminating the write cycle after the first data byte is transferred, the master can transmit up to 15 more bytes to the memory array and up to 7 more bytes to the clock/control registers. The SIGNALS FROM THE MASTER SDA BUS SIGNALS FROM THE SLAVE S T A R T After the receipt of each byte, the ISL12029 responds with an acknowledge, and the address is internally incremented by one. The address pointer remains at the last address byte written. When the counter reaches the end of the page, it “rolls over” and goes back to the first address on the same page. This means that the master can write 16 bytes to a memory array page or 8 bytes to a CCR section starting at any location on that page. For example, if the master begins writing at location 10 of the memory and loads 15 bytes, then the first 6 bytes are written to addresses 10 through 15, and the last 6 bytes are written to columns 0 through 5. Afterwards, the address counter would point to location 6 on the page that was just written. If the master supplies more than the maximum bytes in a page, then the previously loaded data is over-written by the new data, one byte at a time (refer to Figure 21).The master terminates the Data Byte loading by issuing a stop condition, which causes the ISL12029 to begin the non-volatile write cycle. As with the byte write operation, all inputs are disabled until completion of the internal write cycle. Refer to Figure 22 for the address, acknowledge and data transfer sequence. Stops and Write Modes Stop conditions that terminate write operations must be sent by the master after sending at least 1 full data byte and it’s associated ACK signal. If a stop is issued in the middle of a data byte, or before 1 full data byte + ACK is sent, then the ISL12029 resets itself without performing the write. The contents of the array are not affected. WORD ADDRESS 1 SLAVE ADDRESS 1 RTC registers require a page write (8 bytes), individual register writes are not allowed. (Note: Prior to writing to the CCR, the master must write a 02h, then 06h to the status register in two preceding operations to enable the write operation. See “Writing to the Clock/Control Registers” on page 15.) WORD ADDRESS 0 S T O P DATA 0000000 1 110 A C K A C K A C K A C K FIGURE 20. BYTE WRITE SEQUENCE 6 BYTES 6 BYTES ADDRESS = 5 ADDRESS ADDRESS ADDRESS POINTER ENDS AT ADDR = 5 10 15 FIGURE 21. WRITING 12 BYTES TO A 16-BYTE MEMORY PAGE STARTING AT ADDRESS 10 20 FN6206.10 December 16, 2010 ISL12029, ISL12029A . SIGNALS FROM THE MASTER SDA BUS 1 ≤ n ≤ 16 FOR EEPROM ARRAY 1 ≤ n ≤ 8 FOR CCR S T A R T WORD ADDRESS 1 SLAVE ADDRESS 1 DATA (1) S T O P DATA (n) 0 0 0 00 0 0 1 1 1 0 A C K SIGNALS FROM THE SLAVE WORD ADDRESS 0 A C K A C K A C K FIGURE 22. PAGE WRITE SEQUENCE Acknowledge Polling Disabling of the inputs during non-volatile write cycles can be used to take advantage of the typical 5ms write cycle time. Once the stop condition is issued to indicate the end of the master’s byte load operation, the ISL12029 initiates the internal non-volatile write cycle. Acknowledge polling can begin immediately. To do this, the master issues a start condition followed by the Memory Array Slave Address Byte for a write or read operation (AEh or AFh). If the ISL12029 is still busy with the non-volatile write cycle then no ACK will be returned. When the ISL12029 has completed the write operation, an ACK is returned and the host can proceed with the read or write operation. Refer to the flow chart in Figure 24. Note: Do not use the CCR Slave byte (DEh or DFh) for Acknowledge Polling. SIGNALS FROM THE MASTER SDA BUS S T A R T S T O P SLAVE ADDRESS 1 1 1 1 1 A C K SIGNALS FROM THE SLAVE DATA FIGURE 23. CURRENT ADDRESS READ SEQUENCE BYTE LOAD COMPLETED BY ISSUING STOP. ENTER ACK POLLING Read Operations There are three basic read operations: Current Address Read, Random Read and Sequential Read. Current Address Read Internally the ISL12029 contains an address counter that maintains the address of the last word read incremented by one. Therefore, if the last read was to address n, the next read operation would access data from address n + 1. On power-up, the 16-bit address is initialized to 0h. In this way, a current address read immediately after the power-on reset can download the entire contents of memory starting at the first location. Upon receipt of the Slave Address Byte with the R/W bit set to one, the ISL12029 issues an acknowledge, then transmits 8 data bits. The master terminates the read operation by not responding with an acknowledge during the ninth clock and issuing a stop condition. Refer to Figure 23 for the address, acknowledge, and data transfer sequence. ISSUE START ISSUE MEMORY ARRAY SLAVE ADDRESS BYTE AFH (READ) OR AEH (WRITE) ISSUE STOP NO ACK RETURNED? YES NON-VOLATILE WRITE CYCLE COMPLETE. CONTINUE COMMAND SEQUENCE? NO ISSUE STOP YES CONTINUE NORMAL READ OR WRITE COMMAND SEQUENCE PROCEED FIGURE 24. ACKNOWLEDGE POLLING SEQUENCE 21 FN6206.10 December 16, 2010 ISL12029, ISL12029A It should be noted, that the ninth clock cycle of the read operation is not a “don’t care.” To terminate a read operation, the master must either issue a stop condition during the ninth cycle or hold SDA HIGH during the ninth clock cycle and then issue a stop condition. ignored until a start is detected. This operation loads the new address into the address counter. The next Current Address Read operation will read from the newly loaded address. This operation could be useful if the master knows the next address it needs to read, but is not ready for the data. Random Read Sequential Read Random read operations allow the master to access any location in the ISL12029. Prior to issuing the Slave Address Byte with the R/W bit set to zero, the master must first perform a “dummy” write operation. Sequential reads can be initiated as either a current address read or random address read. The first data byte is transmitted as with the other modes; however, the master now responds with an acknowledge, indicating it requires additional data. The device continues to output data for each acknowledge received. The master terminates the read operation by not responding with an acknowledge and then issuing a stop condition. The master issues the start condition and the slave address byte, receives an acknowledge, then issues the word address bytes. After acknowledging receipt of each word address byte, the master immediately issues another start condition and the slave address byte with the R/W bit set to one. This is followed by an acknowledge from the device and then by the 8-bit data word. The master terminates the read operation by not responding with an acknowledge and then issuing a stop condition. Refer to Figure 25 for the address, acknowledge, and data transfer sequence. The data output is sequential, with the data from address n followed by the data from address n + 1. The address counter for read operations increments through all page and column addresses, allowing the entire memory contents to be serially read during one operation. At the end of the address space the counter “rolls over” to the start of the address space and the ISL12029 continues to output data for each acknowledge received. Refer to Figure 26 for the acknowledge and data transfer sequence. In a similar operation called “Set Current Address,” the device sets the address if a stop is issued instead of the second start shown in Figure 25. The ISL12029 then goes into standby mode after the stop and all bus activity will be S T A R T SIGNALS FROM THE MASTER SDA BUS SLAVE ADDRESS 1 WORD ADDRESS 0 WORD ADDRESS 1 00 00000 1 1 1 0 A C K SIGNALS FROM THE SLAVE S T A R T 1 1 1 11 A C K A C K S T O P SLAVE ADDRESS A C K DATA FIGURE 25. RANDOM ADDRESS READ SEQUENCE SLAVE ADDRESS SIGNALS FROM THE MASTER SDA BUS A C K A C K S T O P A C K 1 A C K SIGNALS FROM THE SLAVE DATA (1) DATA (2) DATA (n - 1) DATA (n) (n IS ANY INTEGER GREATER THAN 1) FIGURE 26. SEQUENTIAL READ SEQUENCE 22 FN6206.10 December 16, 2010 ISL12029, ISL12029A Application Section Crystal Oscillator and Temperature Compensation Intersil has now integrated the oscillator compensation circuity on-chip, to eliminate the need for external components and adjust for crystal drift over-temperature and enable very high accuracy time keeping (110ppm occurs at the temperature extremes of -40 and +85°C. It is possible to address this variable drift by adjusting the load capacitance of the crystal, which will result in predictable change to the crystal frequency. The Intersil RTC family allows this adjustment over-temperature since the devices include on-chip load capacitor trimming. This control is handled by the Analog Trimming Register, or ATR, which has 6 bits of control. The load capacitance range covered by the ATR circuit is approximately 3.25pF to 18.75pF, in 0.25pF increments. Note that actual capacitance would also include about 2pF of package related capacitance. In-circuit tests with commercially available crystals demonstrate that this range of capacitance allows frequency control from +116ppm to -37ppm, using a 12.5pF load crystal. In addition to the analog compensation afforded by the adjustable load capacitance, a digital compensation feature is available for the Intersil RTC family. There are 3 bits known as the Digital Trimming Register or DTR, and they operate by adding or skipping pulses in the clock signal. The range provided is ±30ppm in increments of 10ppm. The default setting is 0ppm. The DTR control can be used for coarse adjustments of frequency drift over-temperature or for crystal initial accuracy correction. A final application for the ATR control is in-circuit calibration for high accuracy applications, along with a temperature sensor chip. Once the RTC circuit is powered up with battery backup, the IRQ/FOUT output is set at 32.768kHz and frequency drift is measured. The ATR control is then adjusted to a setting which minimizes drift. Once adjusted at a particular temperature, it is possible to adjust at other discrete temperatures for minimal overall drift, and store the resulting settings in the EEPROM. Extremely low overall temperature drift is possible with this method. The Intersil evaluation board contains the circuitry necessary to implement this control. TABLE 9. CRYSTAL PARAMETERS REQUIRED FOR INTERSIL RTCs PARAMETER MIN Frequency TYP MAX 32.768 Frequency Tolerance Turnover-Temperature 20 Operating Temperature Range -40 Parallel Load Capacitance 25 NOTES kHz ±100 ppm 30 °C 85 °C 12.5 Equivalent Series Resistance UNITS Down to 20ppm if desired Typically the value used for most crystals pF 50 kΩ For best oscillator performance TABLE 10. CRYSTAL MANUFACTURERS MANUFACTURER PART NUMBER TEMP RANGE (°C) +25°C FREQUENCY TOLERANCE (ppm) Citizen CM201, CM202, CM200S -40 to +85 ±20 Epson MC-405, MC-406 -40 to +85 ±20 Raltron RSM-200S-A or B -40 to +85 ±20 SaRonix 32S12A or B -40 to +85 ±20 Ecliptek ECPSM29T-32.768K -10 to +60 ±20 ECS ECX-306/ECX-306I -10 to +60 ±20 Fox FSM-327 -40 to +85 ±20 23 FN6206.10 December 16, 2010 ISL12029, ISL12029A Layout Considerations The crystal input at X1 has a very high impedance and will pick up high frequency signals from other circuits on the board. Since the X2 pin is tied to the other side of the crystal, it is also a sensitive node. These signals can couple into the oscillator circuit and produce double clocking or misclocking, seriously affecting the accuracy of the RTC. Care needs to be taken in layout of the RTC circuit to avoid noise pickup. Figure 27 shows a suggested layout for the ISL12029 device. C1 C1 0.1µF 0.1µF R110k 10k R1 U1 U1 ISL12029 X1228 XTALXTAL1 32.768kGz 32.768kGz FIGURE 27. SUGGESTED LAYOUT FOR INTERSIL RTC IN SO-14 The X1 and X2 connections to the crystal are to be kept as short as possible. A thick ground trace around the crystal is advised to minimize noise intrusion, but ground near the X1 and X2 pins should be avoided as it will add to the load capacitance at those pins. Keep in mind these guidelines for other PCB layers in the vicinity of the RTC device. A small decoupling capacitor at the VDD pin of the chip is mandatory, with a solid connection to ground. For other RTC products, the same rules stated above should be observed, but adjusted slightly since the packages and pinouts are slightly different. Oscillator Measurements When a proper crystal is selected and the layout guidelines above are observed, the oscillator should start-up in most circuits in less than one second. Some circuits may take slightly longer, but start-up should definitely occur in less than 5s. When testing RTC circuits, the most common impulse is to apply a scope probe to the circuit at the X2 pin (oscillator output) and observe the waveform. DO NOT DO THIS! Although in some cases you may see a usable waveform, due to the parasitics (usually 10pF to ground) applied with the scope probe, there will be no useful information in that waveform other than the fact that the circuit is oscillating. The X2 output is sensitive to capacitive impedance so the voltage levels and the frequency will be affected by the parasitic elements in the scope probe. Applying a scope probe can possibly cause a faulty oscillator to start-up, hiding other issues (although in the Intersil RTCs, the internal circuitry assures start-up when using the proper crystal and layout). 24 The best way to analyze the RTC circuit is to power it up and read the real time clock as time advances, or if the chip has the IRQ/FOUT output, look at the output of that pin on an oscilloscope (after enabling it with the control register, and using a pull-up resistor for the open-drain output). Alternatively, the ISL12029 IRQ/FOUT- output can be checked by setting an alarm for each minute. Using the pulse interrupt mode setting, the once-per-minute interrupt functions are an indication of proper oscillation. Backup Battery Operation Many types of batteries can be used with the Intersil RTC products. 3.0V or 3.6V Lithium batteries are appropriate, and sizes are available that can power a Intersil RTC device for up to 10 years. Another option is to use a supercapacitor for applications where VDD may disappear intermittently for short periods of time. Depending on the value of supercapacitor used, backup time can last from a few days to two weeks (with >1F). A simple silicon or Schottky barrier diode can be used in series with VDD to charge the supercapacitor, which is connected to the VBAT pin. Try to use Schottky diodes with very low leakages, VRESET. Bus must have pull-ups to VBAT. No nonvolatile writes with VBAT>VDD C 1 0 Standard Mode, VTRIP = 2.2V typ NO NO YES Operation of I2C bus down to VDD = VRESET, then below that no communications. Battery switchover at VTRIP. D 1 1 Legacy Mode, VDD < VBAT NO NO YES Operation of I2C bus down to VRESET or VBAT, whichever is higher. MODE SBIB BIT BSW BIT A 0 B (X1228 mode) 25 NOTES FN6206.10 December 16, 2010 ISL12029, ISL12029A VBAT (3.0V) VDD VRESET (2.63V) VTRIP (2.2V) tPURST RESET I2C BUS ACTIVE IBAT (BATTERY BACKUP MODE) (VDD POWER, VBAT NOT CONNECTED) FIGURE 29. EXAMPLE RESET OPERATION IN MODE A OR C VBAT (3.0V) VDD VRESET(2.63V) VTRIP (2.2V) tPURST RESET I2C BUS ACTIVE IBAT (BATTERY BACKUP MODE) FIGURE 30. RESET OPERATION IN MODE D Alarm Operation Examples Following are examples of both Single Event and periodic Interrupt Mode alarms. ALARM0 REGISTER 7 BIT 6 5 4 3 2 1 0 HEX MOA0 1 0 0 0 0 0 0 1 81h Month set to 1, enabled DWA0 0 0 0 0 0 0 0 0 00h Day of week disabled EXAMPLE 1 Alarm 0 set with single interrupt (IM = ”0”) A single alarm will occur on January 1 at 11:30am. A. Set Alarm 0 registers as follows: ALARM0 REGISTER 7 B. Also the AL0E bit must be set as follows: BIT 6 5 4 3 2 1 0 HEX DESCRIPTION SCA0 0 0 0 0 0 0 0 0 00h Seconds disabled MNA0 1 0 1 1 0 0 0 0 B0h Minutes set to 30, enabled HRA0 1 0 0 1 0 0 0 1 91h Hours set to 11, enabled DTA0 1 0 0 0 0 0 0 1 81h Date set to 1, enabled 26 DESCRIPTION CONTROL REGISTER 7 INT 0 BIT 6 5 4 3 2 1 0 HEX 0 1 0 0 0 0 0 x0h DESCRIPTION Enable Alarm After these registers are set, an alarm will be generated when the RTC advances to exactly 11:30am on January 1 (after seconds changes from 59 to 00) by setting the AL0 bit in the status register to “1” and also bringing the IRQ/FOUT output low. FN6206.10 December 16, 2010 ISL12029, ISL12029A EXAMPLE 2 B. Set the Interrupt register as follows: Pulsed interrupt once per minute (IM = ”1”) Interrupts at one minute intervals when the seconds register is at 30 seconds. INT A. Set Alarm 0 registers as follows: BIT ALARM0 REGISTER 7 6 5 4 3 2 1 0 HEX BIT CONTROL REGISTER 7 6 5 4 3 2 1 0 HEX DESCRIPTION 1 0 1 x x 0 0 0 x0h Enable Alarm and Int Mode XX indicate other control bits DESCRIPTION SCA0 1 0 1 1 0 0 0 0 B0h Seconds set to 30, enabled MNA0 0 0 0 0 0 0 0 0 00h Minutes disabled HRA0 0 0 0 0 0 0 0 0 00h Hours disabled DTA0 0 0 0 0 0 0 0 0 00h Date disabled MOA0 0 0 0 0 0 0 0 0 00h Month disabled DWA0 0 0 0 0 0 0 0 0 00h Day of week disabled Once the registers are set, the following waveform will be seen at IRQ/FOUT: RTC AND ALARM REGISTERS ARE BOTH 30s 60s Note that the status register AL0 bit will be set each time the alarm is triggered, but does not need to be read or cleared. All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 27 FN6206.10 December 16, 2010 ISL12029, ISL12029A Package Outline Drawing M14.15 14 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE Rev 1, 10/09 4 0.10 C A-B 2X 8.65 A 3 6 14 DETAIL"A" 8 0.22±0.03 D 6.0 3.9 4 0.10 C D 2X 0.20 C 2X 7 PIN NO.1 ID MARK 5 0.31-0.51 B 3 (0.35) x 45° 4° ± 4° 6 0.25 M C A-B D TOP VIEW 0.10 C 1.75 MAX H 1.25 MIN 0.25 GAUGE PLANE C SEATING PLANE 0.10 C 0.10-0.25 1.27 SIDE VIEW (1.27) DETAIL "A" (0.6) NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSEY14.5m-1994. 3. Datums A and B to be determined at Datum H. (5.40) 4. Dimension does not include interlead flash or protrusions. Interlead flash or protrusions shall not exceed 0.25mm per side. 5. The pin #1 indentifier may be either a mold or mark feature. (1.50) 6. Does not include dambar protrusion. Allowable dambar protrusion shall be 0.10mm total in excess of lead width at maximum condition. 7. Reference to JEDEC MS-012-AB. TYPICAL RECOMMENDED LAND PATTERN 28 FN6206.10 December 16, 2010 ISL12029, ISL12029A Package Outline Drawing M14.173 14 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP) Rev 3, 10/09 A 1 3 5.00 ±0.10 SEE DETAIL "X" 8 14 6.40 PIN #1 I.D. MARK 4.40 ±0.10 2 3 1 0.20 C B A 7 B 0.65 0.09-0.20 TOP VIEW END VIEW 1.00 REF 0.05 H C 0.90 +0.15/-0.10 1.20 MAX SEATING PLANE 0.25 +0.05/-0.06 0.10 C 0.10 GAUGE PLANE 0.25 5 0°-8° 0.05 MIN 0.15 MAX CBA SIDE VIEW 0.60 ±0.15 DETAIL "X" (1.45) NOTES: 1. Dimension does not include mold flash, protrusions or gate burrs. (5.65) Mold flash, protrusions or gate burrs shall not exceed 0.15 per side. 2. Dimension does not include interlead flash or protrusion. Interlead flash or protrusion shall not exceed 0.25 per side. 3. Dimensions are measured at datum plane H. 4. Dimensioning and tolerancing per ASME Y14.5M-1994. 5. Dimension does not include dambar protrusion. Allowable protrusion shall be 0.80mm total in excess of dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm. (0.65 TYP) (0.35 TYP) 6. Dimension in ( ) are for reference only. 7. Conforms to JEDEC MO-153, variation AB-1. TYPICAL RECOMMENDED LAND PATTERN 29 FN6206.10 December 16, 2010