ISL12032IVZ

IGNS E W DES FOR NReal Time Clock N DED EM ENT COMME RE PL AC r at N OT R E E NDED rt Sheet OM M Data Cente NO R E C al Suppo il.com/tsc nic ters our Tech contact ERSIL or www.in -INT 1-888 ® ISL12032 with 50/60 Hz clock and Crystal Backup April 16, 2009 FN6618.2 Low Power RTC with Battery Backed SRAM and 50/60 Cycle AC Input and Xtal Back-up The ISL12032 device is a low power real time clock with 50/60 AC input for timing synchronization. It also has an oscillator utilizing an external crystal for timing back-up, clock/calendar registers, intelligent battery back-up switching, battery voltage monitor, brownout indicator, integrated trickle charger for super capacitor, single periodic or polled alarms, POR supervisory function, and up to 4 Event Detect with time stamp. There are 128 bytes of battery-backed user SRAM. The oscillator uses a 50/60 cycle sine wave input, backed by an external, low-cost, 32.768kHz crystal. The real time clock tracks time with separate registers for hours, minutes, and seconds. The calendar registers contain the date, month, year, and day of the week. The calendar is accurate through year 2100, with automatic leap year correction and auto daylight savings correction. Features • 50/60 Cycle AC as a Primary Clock Input for RTC Timing • Redundant Crystal Clock Input Selectable by User - Dynamically Switch from AC Clock Input to Crystal in Case of Power Failure • Real Time Clock/Calendar - Tracks Time in Hours, Minutes, Seconds and Tenths of a Second - Day of the Week, Day, Month, and Year • Auto Daylight Saving Time Correction - Programmable Forward and Backward Dates • Security and Event Functions - Event Detection with Time Stamp - Stores First and Last Three Event Time Stamps • Separate FOUT Pin - 7 Selectable Frequency Outputs • Dual Alarms with Hardware and Register Indicators - Hardware Single Event or Pulse Interrupt Mode • Automatic Backup to Battery or Super Capacitor - VBAT Operation Down to 1.8V - 1.0µA Battery Supply Current • Two Battery Status Monitors with Selectable Levels - Seven Selectable Voltages for Each Level - 1st Level, Trip Points from 4.675V to 2.125V - 2nd Level, Trip Points from 4.125V to 1.875V • VDD Power Brownout Monitor - Six Selectable Trip Levels, from 4.675V to 2.295V • Time Stamp during Power-to-Battery and Battery-to-Power Switchover • Integrated Trickle Charger - Four Selectable Charging Rates • 128 Bytes Battery-Backed User SRAM • I2C Interface - 400kHz Data Transfer Rate • Pb-free (RoHS compliant) Pinout ISL12032 (14 LD TSSOP) TOP VIEW X1 X2 VBAT GND AC LV EVIN 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VDD IRQ SCL SDA ACRDY FOUT EVDET Applications • Utility Meters • Control Applications • Security Related Applications • Vending Machines • White Goods • Consumer Electronics 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2007-2009. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL12032 Ordering Information PART NUMBER (Note) ISL12032IVZ* PART MARKING 12032 IVZ VDD RANGE 2.7V to 5.5V TEMP RANGE (°C) -40 to +85 PACKAGE (Pb-free) 14 Ld TSSOP PKG DWG # M14.173 *Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. Block Diagram SDA SCL SDA BUFFER SCL BUFFER I2C INTERFACE SECONDS CONTROL LOGIC REGISTERS MINUTES HOURS DAY OF WEEK CRYSTAL OSCILLATOR POR/LV COMPARE VTRIP SWITCH VBAT INTERNAL SUPPLY RTC DIVIDER FREQUENCY OUT DATE MONTH VDD YEAR ALARM CONTROL REGISTERS USER SRAM IRQ FOUT AC INPUT BUFFER AC POWER QUALITY EVALUATE LV ACRDY X1 X2 AC EVIN GND EVDET 2 FN6618.2 April 16, 2009 ISL12032 Functional Pin Descriptions PIN NUMBER 1 2 3 4 5 6 7 8 9 10 11 12 13 14 SYMBOL X1 X2 VBAT GND AC LV EVIN EVDET FOUT ACRDY SDA SCL IRQ VDD DESCRIPTION The input of an inverting amplifier and is intended to be connected to one pin of an external 32.768kHz quartz crystal. X1 also can be driven directly from a 32.768kHz source with no crystal connected. The output of an inverting amplifier and is intended to be connected to one pin of an external 32.768kHz quartz crystal. X2 should be left open when X1 is driven from an external source. Battery Voltage. This pin provides a backup supply voltage to the device. VBAT supplies power to the device in the event that the VDD supply fails. This pin should be tied to ground if not used. Ground. AC Input. The AC input pin accepts either 50Hz of 60Hz AC 2.5VP-P sine wave signal. Low Voltage detection output/Brownout Alarm. Open drain active low output. Event Input - The EVIN is a logic input pin that is used to detect an externally monitored event. When a high signal is present at the EVIN pin, an “event” is detected. Event Detect Output. Active when EVIN is triggered. Open Drain active low output. Frequency Output. Register selectable frequency clock output. CMOS output levels. AC Ready. Open Drain output. When High, AC input signal is qualified for timing use. Serial Data. SDA is a bi-directional pin used to transfer serial data into and out of the device. It has an open drain output and may be wire OR’ed with other open drain or open collector outputs. Serial Clock. The SCL input is used to clock all serial data into and out of the device. Interrupt Output. Open Drain active low output. Interrupt output pin to indicate alarm is triggered. Power supply. 3 FN6618.2 April 16, 2009 ISL12032 Absolute Maximum Ratings Voltage on VDD, VBAT, SCL, SDA, ACRDY, AC, LV, EVDET, EVIN, IRQ, FOUT pins (respect to ground) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V Voltage on X1 and X2 pins (respect to ground) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.5V ESD Rating Human Body Model (Per MIL-STD-883 Method 3014) . . . . .>2kV Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>200V Thermal Information Thermal Resistance (Typical, Note 1) θJA (°C/W) 14 Ld TSSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Recommended Operating Conditions Temperature (TA) . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C Supply Voltage (VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V Supply Voltage (VBAT) . . . . . . . . . . . . . . . . . . . . . . . . . 1.8V to 5.5V CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTE: 1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. DC Operating Characteristics SYMBOL VDD VBAT IDD1 Specifications apply for: VDD = 2.7V to 5.5V, TA = -40°C to +85°C, unless otherwise stated. CONDITIONS MIN (Note 10) 2.7 1.8 VDD = 5V, SCL, SDA = VDD VDD = 3V, SCL, SDA = VDD 27 16 43 9.0 1.0 0.8 0.7 TYP (Note 4) MAX (Note 10) 5.5 5.5 60 45 75 18.0 1.8 1.2 1.0 100 1 1 VDD = 5.5V, VBAT = 1.8V -150 -150 2.0 2.2 30 50 VDD = 5.5V, VBAT = 3.0V, TRKR01 = 0, TRKR00 = 0 VDD = 5.5V, VBAT = 3.0V, TRKR01 = 0, TRKR00 = 1 VDD = 5.5V, VBAT = 3.0V, TRKR01 = 1, TRKR00 = 0 VDD = 5.5V, VBAT = 3.0V, TRKR01 = 1, TRKR00 = 1 1300 2200 3600 7800 VDD 50mV 50 +150 +150 2.4 µA nA µA µA mV mV V mV mV Ω Ω Ω Ω V mV UNITS V V µA µA µA µA µA 3 3 2, 5 2, 3 2, 8 2, 8 2, 8 NOTES PARAMETER Main Power Supply Battery Supply Voltage Supply Current IDD2 IDD3 IBAT Supply Current (I2C communications active) Supply Current for Timekeeping at AC Input Battery Supply Current VDD = 5V VDD = 5.5V at TA=+25°C, FOUT disabled VBAT = 5.5V at TA=+25°C VBAT = 2.7V VBAT = 1.8V IBATLKG ILI ILO VBATM VPBM VTRIP VTRIPHYS VBATHYS RTRK Battery Input Leakage Input Leakage Current on SCL I/O Leakage Current on SDA Battery Level Monitor Threshold Brownout Level Monitor Threshold VBAT Mode Threshold VTRIP Hysteresis VBAT Hysteresis Trickle Charge Resistance VDD = 5.5V, VBAT = 1.8V TRKEN = 0 VTRKTERM VTRKHYS VBAT Charging Termination Point Trickle Charge ON-OFF Hysteresis 4 FN6618.2 April 16, 2009 ISL12032 DC Operating Characteristics SYMBOL Specifications apply for: VDD = 2.7V to 5.5V, TA = -40°C to +85°C, unless otherwise stated. (Continued) CONDITIONS MIN (Note 10) TYP (Note 4) MAX (Note 10) UNITS NOTES PARAMETER IRQ/ACRDY/LV/EVDET (OPEN DRAIN OUTPUTS) VOL Output Low Voltage VDD = 5V, IOL = 3mA VDD = 2.7V, IOL = 1mA FOUT (CMOS OUTPUT) VOL VOH EVIN IEVPU EVIN Pull-up Current VDD = 5.5V, VBAT = 3.0V VDD = 0V, VBAT = 1.8V VIL VIH IEVPD Input Low Voltage Input High Voltage EVIN Disabled Pull-down Current VDD = 5.5V 0.7 x VDD 200 1.0 100 3.0 8.0 600 0.3 x VDD µA nA V V nA Output Low Voltage Output High Voltage IOH = 1mA 0.7 x VDD 0.3 x VDD V V 0.4 0.4 V V Power-Down Timing Specifications apply for: VDD = 2.7V to 5.5V, TA = -40°C to +85°C, unless otherwise stated. SYMBOL VDD SRPARAMETER VDD Negative Slew Rate CONDITIONS MIN TYP MAX (Note 10) (Note 4) (Note 10) 10 UNITS V/ms NOTES 6 I2C Interface Specifications Specifications apply for: VDD = 2.7V to 5.5V, TA = -40°C to +85°C, unless otherwise stated. MIN (Note 10) -0.3 0.7 x VDD 0.05 x VDD VDD = 5V, IOL = 3mA TA = +25°C, f = 1MHz, VDD = 5V, VIN = 0V, VOUT = 0V Any pulse narrower than the max spec is suppressed. SCL falling edge crossing 30% of VDD, until SDA exits the 30% to 70% of VDD window. 1300 10 0.4 TYP (Note 4) MAX (Note 10) UNITS 0.3 x VDD VDD + 0.3 V V V V pF SYMBOL VIL VIH Hysteresis VOL CPIN PARAMETER SDA and SCL Input Buffer LOW Voltage SDA and SCL Input Buffer HIGH Voltage SDA and SCL Input Buffer Hysteresis SDA Output Buffer LOW Voltage, Sinking 3mA SDA and SCL Pin Capacitance TEST CONDITIONS NOTES fSCL tIN tAA SCL Frequency Pulse Width Suppression Time at SDA and SCL Inputs SCL Falling Edge to SDA Output Data Valid 400 50 900 kHz ns ns tBUF Time the Bus Must be Free Before SDA crossing 70% of VDD the Start of a New Transmission during a STOP condition, to SDA crossing 70% of VDD during the following START condition. Clock LOW Time Measured at the 30% of VDD crossing. ns tLOW 1300 ns 5 FN6618.2 April 16, 2009 ISL12032 I2C Interface Specifications Specifications apply for: VDD = 2.7V to 5.5V, TA = -40°C to +85°C, unless otherwise stated. (Continued) SYMBOL tHIGH tSU:STA PARAMETER Clock HIGH Time START Condition Setup Time TEST CONDITIONS Measured at the 70% of VDD crossing. SCL rising edge to SDA falling edge. Both crossing 70% of VDD. From SDA falling edge crossing 30% of VDD to SCL falling edge crossing 70% of VDD. From SDA exiting the 30% to 70% of VDD window, to SCL rising edge crossing 30% of VDD. From SCL falling edge crossing 30% of VDD to SDA entering the 30% to 70% of VDD window. From SCL rising edge crossing 70% of VDD, to SDA rising edge crossing 30% of VDD. From SDA rising edge to SCL falling edge. Both crossing 70% of VDD. From SCL falling edge crossing 30% of VDD, until SDA enters the 30% to 70% of VDD window. From 30% to 70% of VDD. From 70% to 30% of VDD. Total on-chip and off-chip MIN (Note 10) 600 600 TYP (Note 4) MAX (Note 10) UNITS ns ns NOTES tHD:STA START Condition Hold Time 600 ns tSU:DAT Input Data Setup Time 100 ns tHD:DAT Input Data Hold Time 0 900 ns tSU:STO STOP Condition Setup Time 600 ns tHD:STO STOP Condition Hold Time 600 ns tDH Output Data Hold Time 0 ns tR tF Cb RPU SDA and SCL Rise Time SDA and SCL Fall Time Capacitive loading of SDA or SCL 20 + 0.1 x Cb 20 + 0.1 x Cb 10 1 300 300 400 ns ns pF kΩ 7, 9 7, 9 7, 9 7, 9 SDA and SCL Bus Pull-up Resistor Maximum is determined by Off-chip tR and tF. For Cb = 400pF, max is about 2kΩ. For Cb = 40pF, max is about 15kΩ NOTES: 2. IRQ and FOUT Inactive. 3. VDD > VBAT +VBATHYS 4. Specified at TA =+25°C. 5. FSCL = 400kHz. 6. In order to ensure proper timekeeping, the VDD SR- specification must be followed. 7. Parameter is not 100% tested. 8. VDD = 0V. IBAT increases at VDD voltages between 0.5V and 1.5V. 9. These are I2C specific parameters and are not tested, however, they are used to set conditions for testing devices to validate specification. 10. Parts are 100% tested at +25°C. Temperature limits established by characterization and are not production tested. 6 FN6618.2 April 16, 2009 ISL12032 SDA vs SCL Timing tF tHIGH tLOW tR SCL tSU:STA tHD:STA SDA (INPUT TIMING) tSU:DAT tHD:DAT tSU:STO tAA SDA (OUTPUT TIMING) tDH tBUF Symbol Table WAVEFORM INPUTS Must be steady OUTPUTS Will be steady May change from LOW to HIGH May change from HIGH to LOW Don’t Care: Changes Allowed N/A Will change from LOW to HIGH Will change from HIGH to LOW Changing: State Not Known Center Line is High Impedance EQUIVALENT AC OUTPUT LOAD CIRCUIT FOR VDD = 5V 5.0V 1533Ω SDA AND IRQ/FOUT FOR VOL= 0.4V AND IOL = 3mA 100pF FIGURE 1. STANDARD OUTPUT LOAD FOR TESTING THE DEVICE WITH VDD = 5.0V 7 FN6618.2 April 16, 2009 ISL12032 General Description The ISL12032 device is a low power real time clock with 50/60 AC input for timing synchronization. It also has an oscillator utilizing an external crystal for timing back-up, clock/calendar registers, intelligent battery back-up switching, battery voltage monitor, brownout indicator, integrated trickle charger for super capacitor, single periodic or polled alarms, POR supervisory function, and up to 4 Event Detect with time stamp. There are 128 bytes of battery-backed user SRAM. The oscillator uses a 50/60 cycle sine wave input, backed by an external, low-cost, 32.768kHz crystal. The real time clock tracks time with separate registers for hours, minutes, and seconds. The calendar registers contain the date, month, year, and day of the week. The calendar is accurate through year 2100, with automatic leap year correction and auto daylight savings correction. The ISL12032’s alarm can be set to any clock/calendar value for a match. Each alarm’s status is available by checking the Status Register. The device also can be configured to provide a hardware interrupt via the IRQ pin. There is a repeat mode for the alarms allowing a periodic interrupt every minute, every hour, every day, etc. The device also offers a backup power input pin. This VBAT pin allows the device to be backed up by battery or Super Capacitor with automatic switchover from VDD to VBAT. The ISL12032 devices are specified for VDD = 2.7V to 5.5V and the clock/calendar portion of the device remains fully operational in battery backup mode down to 1.8V (Standby Mode). The VBAT level is monitored and warnings are reported against preselected levels. The first report is registered when the VBAT level falls below 85% of nominal level, the second level is set for 75% of nominal level. Battery levels are stored in the PWRBAT registers. The ISL12032 offers a “Brownout” alarm once the VDD falls below a pre-selected trip level. In the ISL12032, this allows the system microcontroller to save vital information to memory before complete power loss. There are six VDD trip levels for the brownout alarm. The event detection function accepts a normally low logic input, and when triggered will store the time/date information for the event. The first event is stored in the memory until reset; subsequent events are stored on-chip memory and the last 3 events are retained and accessible by performing an indexed register read. Pin Descriptions X1, X2 The X1 and X2 pins are the input and output, respectively, of an inverting amplifier. An external 32.768kHz quartz crystal is used with the device to supply a backup timebase for the real time clock if there is no AC input. The device also can be driven directly from a 32.768kHz source at pin X1, in which case, pin X2 should be left unconnected. No external load capacitors are needed for the X1 and X2 pins. X1 X2 FIGURE 2. RECOMMENDED CRYSTAL CONNECTION VBAT (Battery Input) This input provides a backup supply voltage to the device. VBAT supplies power to the device in the event that the VDD supply fails. This pin can be connected to a battery, a Super Capacitor or tied to ground if not used. AC (AC Input) The AC input is the main clock input for the real time clock. It can be either 50Hz or 60Hz, sine wave. The preferred amplitude is 2.5VP-P, although amplitudes >0.25VDD are acceptable. An AC coupled (series capacitor) sine wave clock waveform is desired as the AC clock input provides DC biasing. LV (Low Voltage) This pin indicates the VDD supply is below the programmed level. This signal notifies a host processor that the main supply is low and requests action. It is an open drain active LOW output. EVIN (Event Input) The EVIN pin input detects an externally monitored event. When a HIGH signal is present at the EVIN pin, an “event” is detected.This input may be used for various monitoring functions, such as the opening of a detection switch on a chassis or door. The event detection circuit can be user enabled or disabled (see EVIN bit) and provides the option to be operational in battery backup modes (see EVATB bit). When the event detection is disabled, the EVIN pin is gated OFF. See “Functional Pin Descriptions” on page 3 for more details. EVDET (Event Detect Output) The EVDET is an open drain output, which will go low when an event is detected at the EVIN pin. If the event detection function is enabled, the EVDET output will go LOW and stay there until the EVT bit is cleared. 8 FN6618.2 April 16, 2009 ISL12032 IRQ (Interrupt Output) This pin provides an interrupt signal output. This signal notifies a host processor that an alarm has occurred and requests action. It is an open drain active LOW output. Battery Backup Mode (VBAT) to Normal Mode (VDD) The ISL12032 device will switch from the VBAT to VDD mode when one of the following conditions occurs: Condition 1: VDD > VBAT + VBATHYS where VBATHYS ≈ 50mV Condition 2: VDD > VTRIP + VTRIPHYS where VTRIPHYS ≈ 30mV These power control situations are illustrated in Figures 3 and Figure 4. FOUT (Frequency Output) This pin outputs a clock signal, which is related to the crystal frequency. The frequency output is user selectable and enabled via the I2C bus. The options include seven different frequencies or disable. It is a CMOS output. Serial Clock (SCL) The SCL input is used to clock all serial data into and out of the device. The input buffer on this pin is always active (not gated). It is disabled when the backup power supply on the VBAT pin is activated to minimize power consumption. Serial Data (SDA) SDA is a bi-directional pin used to transfer data into and out of the device. It has an open drain output and may be OR’ed with other open drain or open collector outputs. The input buffer is always active (not gated) in normal mode. An open drain output requires the use of a pull-up resistor. The output circuitry controls the fall time of the output signal with the use of a slope controlled pull-down. The circuit is designed for 400kHz I2C interface speeds. It is disabled when the backup power supply on the VBAT pin is activated. VDD VTRIP VBAT BATTERY BACKUP MODE 2.2V 1.8V VBAT + VBATHYS VBAT - VBATHYS FIGURE 3. BATTERY SWITCHOVER WHEN VBAT < VTRIP VDD, GND Chip power supply and ground pins. The device will operate with a power supply from VDD = 2.7V to 5.5VDC. A 0.1µF capacitor is recommended on the VDD pin to ground. BATTERY BACKUP MODE VDD VBAT VTRIP VTRIP Functional Description Power Control Operation The power control circuit accepts a VDD and a VBAT input. Many types of batteries can be used with Intersil RTC products. For example, 3.0V or 3.6V Lithium batteries are appropriate, and battery sizes are available that can power the ISL12032 for up to 10 years. Another option is to use a Super Capacitor for applications where VDD is interrupted for up to a month. See the “Application Section” on page 24 for more information. 3.0V 2.2V VTRIP + VTRIPHYS FIGURE 4. BATTERY SWITCHOVER WHEN VBAT > VTRIP Normal Mode (VDD) to Battery Backup Mode (VBAT) To transition from the VDD to VBAT mode, both of the following conditions must be met: Condition 1: VDD < VBAT - VBATHYS where VBATHYS ≈ 50mV Condition 2: VDD < VTRIP where VTRIP ≈ 2.2V The I2C bus is normally deactivated in battery backup mode to reduce power consumption, but can be enabled by setting the I2CBAT bit. All the other inputs and outputs of the ISL12032 are active during battery backup mode unless disabled via the control register. Power Failure Detection The ISL12032 provides a Real Time Clock Failure Bit (RTCF) to detect total power failure. It allows users to determine if the device has powered up after having lost all power to the device (both VDD and VBAT very near 0.0VDC). Note that in cases where the VBAT input is at 0.0V and the VDD input dips to