DATASHEET
ISL12082
FN6731
Rev 4.00
Sep 25, 2015
I2C-Bus Real Time Clock with Two Interrupts, Alarm, and Timer, Low Power RTC with
Battery ReSeal, 2 IRQs, Hundredths of a Second Time and Crystal Compensation
The ISL12082 device is a low power real time clock with
timing and crystal compensation, clock/calendar, power fail
indicator, 2 IRQs, periodic or polled alarm, timer/watchdog,
and intelligent battery backup switching.
The oscillator uses an external, low-cost 32.768kHz crystal.
The real time clock tracks time with separate registers for
hours, minutes, seconds and hundredths of a second. The
device has calendar registers for date, month, year and day
of the week. The calendar is accurate through 2099, with
automatic leap year correction.
Pinouts
Features
• Real Time Clock/Calendar
- Tracks Time in Hours, Minutes, Seconds, and
Hundredths of a Second
- Day of the Week, Day, Month, and Year
• 4 Selectable Frequency Outputs
• Alarm
- Settable to the Second, Minute, Hour, Day of the Week,
Day, or Month
- Single Event or Pulse Interrupt Mode
• Timer
- 4 Selectable Timer Functions
- 4 Selectable Timer Clock Frequencies
- Single Event or Pulse Interrupt Mode
ISL12082
(8 LD SOIC)
TOP VIEW
X1
1
8
VDD
X2
2
7
IRQ1/fOUT
GND
3
6
SCL
IRQ2
4
5
SDA
• Automatic Backup to Battery or Supercapacitor
• Power Failure Detection
• Battery ReSeal™
• On-Chip Oscillator Compensation
• I2C Interface
- 400kHz Data Transfer Rate
ISL12082
(10 LD MSOP)
TOP VIEW
X1
1
X2
2
VBAT
BL
IL A
3 AVA
ER
• 800nA Battery Supply Current
VDD D
TE
OR
P
P
U
9 S IRQ1/fOUT
R
10
EO
• Pb-Free (RoHS Compliant)
8
SCL
NG
LO
GND
4
NO
7
SDA
5
6
IRQ2
NC
• Small Package Options
- 8 Ld SOIC Package
- 10 Ld MSOP Package
Applications
• Utility Meters
• HVAC Equipment
• Audio/Video Components
• Set-Top Box/Television
• Modems
• Network Routers, Hubs, Switches, Bridges
• Cellular Infrastructure Equipment
• Fixed Broadband Wireless Equipment
• Pagers/PDA
• POS Equipment
• Test Meters/Fixtures
• Office Automation (Copiers, Fax)
• Home Appliances
• Computer Products
FN6731 Rev 4.00
Sep 25, 2015
Page 1 of 28
ISL12082
.
Ordering Information
PART NUMBER
(Note)
PART
MARKING
VDD RANGE
(V)
TEMP. RANGE
(°C)
PACKAGE
(RoHS Compliant)
PKG.
DWG. #
ISL12082IB8Z
12082 IBZ
2.7 to 5.5
-40 to +85
8 Ld SOIC
M8.15
ISL12082IB8Z-T*
12082 IBZ
2.7 to 5.5
-40 to +85
8 Ld SOIC
(Tape and Reel)
M8.15
ISL12082IUZ
(No longer available
or supported)
12082
2.7 to 5.5
-40 to +85
10 Ld MSOP
M10.118
ISL12082IUZ-T*
(No longer available
or supported)
12082
2.7 to 5.5
-40 to +85
10 Ld MSOP
(Tape and Reel)
M10.118
*Please refer to TB347 for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100%
matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Block Diagram
SDA
SDA
BUFFER
SCL
SCL
BUFFER
I2C
INTERFACE
SECONDS
RTC
CONTROL
LOGIC
MINUTES
HOURS
DAY OF WEEK
X1
CRYSTAL
OSCILLATOR
X2
RTC
DIVIDER
DATE
MONTH
VDD
POR
FREQUENCY
OUT
VTRIP
YEAR
ALARM
TIMER
CONTROL
REGISTERS
SWITCH
IRQ2
VBAT
INTERNAL
SUPPLY
IRQ1/fOUT
FN6731 Rev 4.00
Sep 25, 2015
Page 2 of 28
ISL12082
Pin Descriptions
PIN
NUMBER
SOIC
MSOP
SYMBOL
1
1
X1
The X1 pin is the input of an inverting amplifier and is intended to be connected to one pin of an external
32.768kHz quartz crystal. X1 can also be driven directly from a 32.768kHz source.
2
2
X2
The X2 pin is the output of an inverting amplifier and is intended to be connected to one pin of an external
32.768kHz quartz crystal.
-
3
VBAT
This input provides a backup supply voltage to the device. VBAT supplies power to the device in the event
that the VDD supply fails. This pin should be tied to ground if not used.
3
4
GND
Ground
-
5
NC
4
6
IRQ2
Interrupt Output 2 is a multi-functional pin that can be used as alarm interrupt or timer interrupt pin. The
function is set via the configuration register.
5
7
SDA
Serial Data (SDA) is a bi-directional pin used to transfer serial data into and out of the device. It has an open
drain output and may be wire OR’ed with other open drain or open collector outputs.
6
8
SCL
The Serial Clock (SCL) input is used to clock all serial data into and out of the device.
7
9
8
10
FN6731 Rev 4.00
Sep 25, 2015
DESCRIPTION
No Connect
IRQ1/fOUT Interrupt Output 1/Frequency Output is a multi-functional pin that can be used as alarm interrupt or frequency
output pin. The function is set via the configuration register.
VDD
Power supply
Page 3 of 28
ISL12082
Absolute Maximum Ratings
Thermal Information
Voltage on VDD, VBAT, SCL, SDA, IRQ1/fOUT and IRQ2 Pins
(respect to GND) . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6.5V
Voltage on X1 and X2 Pins
(respect to GND) . . . . . . . . . . . . .-0.5V to VDD + 0.5 (VDD Mode)
-0.5V to VBAT + 0.5 (VBAT Mode)
Thermal Resistance (Typical, Note 1)
JA (°C/W)
8 Ld SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
120
10 Ld MSOP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
152
Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTE:
1. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
DC Operating Characteristics - RTC
SYMBOL
Temperature = -40°C to +85°C, unless otherwise stated.
PARAMETER
CONDITIONS
MIN
(Note 6)
TYP
(Note 5)
MAX
(Note 6)
UNITS
VDD
Main Power Supply
2.7
5.5
V
VBAT
Battery Supply Voltage
1.8
5.5
V
IDD1
Supply Current
IDD2
Supply Current With I2C Active
IDD3
IBAT
NOTES
VDD = 5V
2.8
6
µA
2, 3
VDD = 3V
1.6
4
µA
VDD = 5V
40
120
µA
2, 3
Supply Current (Low Power Mode)
VDD = 5V, LPMODE = 1
2.3
5
µA
2
Battery Supply Current
VBAT = 3V, +25°C
800
950
nA
2, 9
ILI
Input Leakage Current on SCL
-1
0.1
+1
µA
ILO
I/O Leakage Current on SDA
-1
0.1
+1
µA
VBAT Mode Threshold
1.8
2.15
2.4
V
9
VTRIP
VTRIPHYS
VTRIP Hysteresis
36
mV
7, 9
VBATHYS
VBAT Hysteresis
53
mV
7, 9
IRQ1/fOUT and IRQ2
VOL
Output Low Voltage
Power-Down Timing
SYMBOL
VDD SR-
VDD = 5V
IOL = 3mA
0.02
0.4
V
VDD = 2.7V
IOL = 1mA
0.02
0.4
V
TYP
(Note 5)
MAX
(Note 6)
UNITS
NOTES
5
V/ms
4, 9
Timing Temperature = -40°C to +85°C, unless otherwise stated.
PARAMETER
CONDITIONS
MIN
(Note 6)
VDD Negative Slewrate
Serial Interface Specifications Over the recommended operating conditions, unless otherwise specified.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
(Note 6) (Note 5) (Note 6)
UNITS
VIL
SDA and SCL Input Buffer LOW
Voltage
-0.3
0.3 x
VDD
V
VIH
SDA and SCL Input Buffer HIGH
Voltage
0.7 x
VDD
VDD +
0.3
V
Hysteresis
VOL
SDA and SCL Input Buffer
Hysteresis
SDA Output Buffer LOW Voltage,
Sinking 3mA
FN6731 Rev 4.00
Sep 25, 2015
0.05 x
VDD
0
0.02
V
0.4
NOTES
7, 8
V
Page 4 of 28
ISL12082
Serial Interface Specifications Over the recommended operating conditions, unless otherwise specified. (Continued)
SYMBOL
PARAMETER
Cpin
SDA and SCL Pin Capacitance
fSCL
SCL Frequency
TEST CONDITIONS
MIN
TYP
MAX
(Note 6) (Note 5) (Note 6)
TA = +25°C, f = 1MHz, VDD = 5V, VIN = 0V,
VOUT = 0V
UNITS
NOTES
10
pF
7, 8
400
kHz
tIN
Pulse Width Suppression Time at
SDA and SCL Inputs
Any pulse narrower than the max spec is
suppressed
50
ns
tAA
SCL Falling Edge to SDA Output
Data Valid
SCL falling edge crossing 30% of VDD, until
SDA exits the 30% to 70% of VDD window
900
ns
tBUF
Time the Bus Must Be Free Before SDA crossing 70% of VDD during a STOP
the Start of a New Transmission
condition, to SDA crossing 70% of VDD
during the following START condition
1300
ns
tLOW
Clock LOW Time
Measured at the 30% of VDD crossing
1300
ns
tHIGH
Clock HIGH Time
Measured at the 70% of VDD crossing
600
ns
tSU:STA
START Condition Setup Time
SCL rising edge to SDA falling edge. Both
crossing 70% of VDD
600
ns
tHD:STA
START Condition Hold Time
From SDA falling edge crossing 30% of VDD
to SCL falling edge crossing 70% of VDD
600
ns
tSU:DAT
Input Data Setup Time
From SDA exiting the 30% to 70% of VDD
window, to SCL rising edge crossing 30% of
VDD
100
ns
tHD:DAT
Input Data Hold Time
From SCL falling edge crossing 30% of VDD
to SDA entering the 30% to 70% of VDD
window
0
tSU:STO
STOP Condition Setup Time
From SCL rising edge crossing 70% of VDD,
to SDA rising edge crossing 30% of VDD
600
ns
tHD:STO
STOP Condition Hold Time
From SDA rising edge to SCL falling edge
Both crossing 70% of VDD
600
ns
Output Data Hold Time
From SCL falling edge crossing 30% of VDD,
until SDA enters the 30% to 70% of VDD
window
0
ns
tR
SDA and SCL Rise Time
From 30% to 70% of VDD
20 +
0.1 x Cb
300
ns
7, 8
tF
SDA and SCL Fall Time
From 70% to 30% of VDD
20 +
0.1 x Cb
300
ns
7, 8
Cb
Capacitive Loading of SDA or SCL Total on-chip and off-chip
10
400
pF
7, 8
Rpu
SDA and SCL Bus Pull-Up
Resistor Off-Chip
1
k
7, 8
tDH
Maximum is determined by tR and tF
For Cb = 400pF, max is about 2k to ~2.5k
For Cb = 40pF, max is about 15kto ~20k
900
ns
NOTES:
2. IRQ and fOUT Inactive.
3. LPMODE = 0 (default).
4. In order to ensure proper timekeeping, the VDD SR- specification must be followed.
5. Typical values are for T = +25°C and 3.3V supply voltage.
6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by
characterization and are not production tested.
7. Limits should be considered typical and are not production tested.
8. These are I2C specific parameters and are not tested, however, they are used to set conditions for testing devices to validate
specification.
9. Parameters are for 10 Ld MSOP package only.
FN6731 Rev 4.00
Sep 25, 2015
Page 5 of 28
ISL12082
SDA vs SCL Timing
tHIGH
tF
SCL
tSU:STA
SDA
(INPUT TIMING)
tLOW
tR
tSU:DAT
tHD:DAT
tHD:STA
tSU:STO
tAA
tDH
tBUF
SDA
(OUTPUT TIMING)
Symbol Table
WAVEFORM
INPUTS
OUTPUTS
Must be steady
Will be steady
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
Don‚ÄöÐÑÐ¥t
Changes Allowed
Changing:
State Not Known
N/A
Center Line is
High Impedance
FN6731 Rev 4.00
Sep 25, 2015
Page 6 of 28
ISL12082
Temperature is +25°C unless otherwise specified
0.2
1.00
1.8
0.95
1.6
0.90
1.4
0.85
1.2
0.80
IBAT (µA)
IBAT (µA)
Typical Performance Curves
1.0
0.8
0.75
0.70
0.6
0.65
0.4
0.60
0.2
0.55
0
1.8
2.3
2.8
3.3
3.8
VBAT (V)
4.3
4.8
5.3
0.50
-40
FIGURE 1. IBAT vs VBAT
-20
0
20
40
TEMPERATURE (°C)
60
80
FIGURE 2. IBAT vs TEMPERATURE AT VBAT = 3V
3.5
3.5
VDD = 5V
3.0
3.0
ICC (µA)
IDD (µA)
2.5
2.5
2.0
LP MODE OFF
2.0
1.5
LP MODE ON
VDD = 3.3V
1.5
1.0
1.0
-40
-20
0
20
VDD (V)
40
60
0.5
1.8
80
FIGURE 3. IDD1 vs TEMPERATURE
3.3
3.8
VCC (V)
4.3
4.8
5.3
4.5
IDD (µA)
IDD (µA)
2.8
FIGURE 4. IDD1 vs VCC WITH LPMODE ON AND OFF
3.5
2.5
1.5
2.3
1
512
4096
FOUT (Hz)
FIGURE 5. IDD1 vs fOUT AT VDD = 3.3V
FN6731 Rev 4.00
Sep 25, 2015
32768
3.5
2.5
1
512
4096
FOUT (Hz)
32768
FIGURE 6. IDD1 vs fOUT AT VDD = 5V
Page 7 of 28
ISL12082
EQUIVALENT AC OUTPUT LOAD CIRCUIT FOR VDD = 5V
5.0V
1533
SDA
IRQ1/fOUT
AND
IRQ2
FOR VOL= 0.4V
X1
AND IOL = 3mA
X2
100pF
FIGURE 7. STANDARD OUTPUT LOAD FOR TESTING THE
DEVICE WITH VDD = 5.0V
General Description
The ISL12082 device is a low power real time clock with timing
and crystal compensation, clock/calendar, power fail indicator,
periodic or polled alarm, timer/watchdog, and intelligent battery
backup switching.
The oscillator uses an external, low-cost 32.768kHz crystal.
The real time clock tracks time with separate registers for
hours, minutes, seconds, and sub-seconds. The device has
calendar registers for date, month, year and day of the week.
The calendar is accurate through 2099, with automatic leap
year correction.
The ISL12082's powerful alarm can be set to any
clock/calendar value for a match. For example, every minute,
every Tuesday or at 5:23 AM on March 21. The alarm status is
available by checking the Status Register, or the device can be
configured to provide a hardware interrupt via the IRQ1/fOUT
or IRQ2 pin. There is a repeat mode for the alarm allowing a
periodic interrupt every minute, every hour, every day, etc.
The ISL12082 has a powerful timer function. The timer status is
available by checking the Status Register, or the device can be
configured to provide a hardware interrupt via the IRQ2 pin.
The device also offers a backup power input pin. This VBAT pin
allows the device to be backed up by battery or Supercapacitor
with automatic switchover from VDD to VBAT. The entire
ISL12082 device is fully operational from 2.7V to 5.5V and the
clock/calendar portion of the device remains fully operational
down to 1.8V (Standby Mode).
Pin Description
X1, X2
The X1 and X2 pins are the input and output, respectively, of an
inverting amplifier. An external 32.768kHz quartz crystal is used
with the ISL12082 to supply a timebase for the real time clock.
Internal compensation circuitry provides high accuracy over the
operating temperature range from -40°C to +85°C. This
oscillator compensation network can be used to calibrate the
crystal timing accuracy over-temperature either during
manufacturing or with an external temperature sensor and
microcontroller for active compensation. The device can also be
driven directly from a 32.768kHz source at pin X1.
FN6731 Rev 4.00
Sep 25, 2015
FIGURE 8. RECOMMENDED CRYSTAL CONNECTION
VBAT
This input provides a backup supply voltage to the device.
VBAT supplies power to the device in the event that the VDD
supply fails. This pin can be connected to a battery, a
Supercapacitor or tied to ground if not used.
IRQ1/fOUT (Interrupt Output 1/Frequency Output)
The IRQ1/fOUT is an open drain output.
This dual function pin can be used as an interrupt or frequency
output pin. The IRQ1/fOUT mode is selected via the IRQ1E bit
of the control register (address 08h).
• Interrupt Mode. The pin provides an interrupt signal output.
This signal notifies a host processor that an alarm has
occurred and requests action.
• Frequency Output Mode. The pin outputs a clock signal
which is related to the crystal frequency. The frequency
output is user selectable and enabled via the I2C bus.
IRQ2 (Interrupt Output 2)
The IRQ2 is an open drain output.
The IRQ2 pin can be used as an alarm interrupt or timer
interrupt output pin. The IRQ2 mode is selected via the IRQ2E
control bits of the control register (address 08h). The pin
provides an interrupt signal output. This signal notifies a host
processor that an alarm or timer has occurred and requests
action.
Serial Clock (SCL)
The SCL input is used to clock all serial data into and out of the
device. The input buffer on this pin is always active (not gated).
It is disabled when the backup power supply on the VBAT pin is
activated to minimize power consumption.
Serial Data (SDA)
SDA is a bi-directional pin used to transfer data into and out of
the device. It has an open drain output and may be ORed with
other open drain or open collector outputs. The input buffer is
always active (not gated) in normal mode.
An open drain output requires the use of a pull-up resistor. The
output circuitry controls the fall time of the output signal with
the use of a slope controlled pull-down. The circuit is designed
for 400kHz I2C interface speeds. It is disabled when the
backup power supply on the VBAT pin is activated.
Page 8 of 28
ISL12082
VDD, GND
Chip power supply and ground pins. The device will operate
with a power supply from 2.7V to 5.5VDC. A 0.1µF decoupling
capacitor is recommended on the VDD pin to ground.
Functional Description
BATTERY BACKUP
MODE
VDD
VBAT
3.0V
VTRIP
2.2V
Power Control Operation
The power control circuit accepts a VDD and a VBAT input.
Many types of batteries can be used with Intersil RTC
products. For example, 3.0V or 3.6V Lithium batteries are
appropriate, and battery sizes are available that can power the
ISL12082 for up to 10 years. Another option is to use a
Supercapacitor for applications where VDD is interrupted for up
to a month. See the “Application Section” on page 23 for more
information.
Normal Mode (VDD) to Battery Backup Mode (VBAT)
To transition from the VDD to VBAT mode, both of the following
conditions must be met:
Condition 1:
VDD < VBAT - VBATHYS
where VBATHYS 50mV
Battery Backup Mode (VBAT) to Normal Mode (VDD)
The ISL12082 device will switch from the VBAT to VDD mode
when one of the following conditions occurs:
Condition 1:
VDD > VBAT + VBATHYS
where VBATHYS 50mV
Condition 2:
VDD > VTRIP + VTRIPHYS
where VTRIPHYS 30mV
These power control situations are illustrated in Figures 9 and
10.
BATTERY BACKUP
MODE
VTRIP
2.2V
VBAT
1.8V
VBAT - VBATHYS
VBAT + VBATHYS
FIGURE 9. BATTERY SWITCHOVER WHEN VBAT < VTRIP
FN6731 Rev 4.00
Sep 25, 2015
VTRIP + VTRIPHYS
FIGURE 10. BATTERY SWITCHOVER WHEN VBAT > VTRIP
The I2C bus is deactivated in battery backup mode to provide
lower power. Aside from this, all RTC functions are operational
during battery backup mode. Except for SCL and SDA, all the
inputs and outputs of the ISL12082 are active during battery
backup mode unless disabled via the control register.
Power Failure Detection
The ISL12082 provides a Real Time Clock Failure Bit (RTCF,
address 0Bh) to detect total power failure. It allows users to
determine if the device has powered up after having lost all
power to the device (both VDD and VBAT).
Low Power Mode
Condition 2:
VDD < VTRIP
where VTRIP 2.2V
VDD
VTRIP
The normal power switching of the ISL12082 is designed to
switch into battery backup mode only if the VDD power is lost.
This will ensure that the device can accept a wide range of
backup voltages from many types of sources while reliably
switching into backup mode. Another mode, called Low Power
Mode, is available to allow direct switching from VDD to VBAT
without requiring VDD to drop below VTRIP. Since the
additional monitoring of VDD vs VTRIP is no longer needed,
that circuitry is shut down and less power is used while
operating from VDD. Power savings are typically 600nA at VDD
= 5V. Low Power Mode is activated via the LPMODE bit in the
control and status registers.
Low Power Mode is useful in systems where VDD is normally
higher than VBAT at all times. The device will switch from VDD
to VBAT when VDD drops below VBAT, with about 50mV of
hysteresis to prevent any switchback of VDD after switchover.
In a system with a VDD = 5V and backup lithium battery of
VBAT = 3V, Low Power Mode can be used. However, it is not
recommended to use Low Power Mode in a system with VDD =
3.3V ±10%, VBAT 3.0V, and when there is a finite I-R voltage
drop in the VDD line.
InterSeal™ and ReSeal™ Battery Saver
The ISL12082 has the InterSeal™ Battery Saver, which
prevents initial battery current drain before it is first used. For
example, battery-backed RTCs are commonly packaged on a
board with a battery connected. In order to preserve battery
life, the ISL12082 will not draw any power from the battery
source until after the device is first powered up from the VDD
source. Thereafter, the device will switchover to battery backup
mode whenever VDD power is lost.
Page 9 of 28
ISL12082
The ISL12082 has the ReSeal™ function, which allows the
device to enter into the InterSeal™ Battery Saver mode after
manufacture testing for board functionality. To use the
ReSeal™ function, simply set RESEAL bit to “1” (address 07h)
after the testing is completed. It will enable the InterSeal™
Battery Saver mode and prevents battery current drain before
it is first used.
Real Time Clock Operation
The Real Time Clock (RTC) uses an external 32.768kHz
quartz crystal to maintain an accurate internal representation of
sub-second, second, minute, hour, day of week, date, month,
and year. The RTC also has leap-year correction. The RTC
also corrects for months having fewer than 31 days and has a
bit that controls 24 hour or AM/PM format. When the ISL12082
powers up after the loss of both VDD and VBAT, the clock will
not begin incrementing until at least one byte is written to the
clock register.
Accuracy of the Real Time Clock
The accuracy of the Real Time Clock depends on the
frequency of the quartz crystal that is used as the time base for
the RTC. Since the resonant frequency of a crystal is
temperature dependent, the RTC performance will also be
dependent upon temperature. The frequency deviation of the
crystal is a function of the turnover-temperature of the crystal
from the crystal’s nominal frequency. For example, a ~20ppm
frequency deviation translates into an accuracy of ~1 minute
per month. These parameters are available from the crystal
manufacturer. The ISL12082 provides on-chip crystal
compensation networks to adjust load capacitance to tune
oscillator frequency from -94ppm to +140ppm. For more
detailed information, see “Application Section” on page 23.
Single Event and Interrupt
The alarm mode is enabled via the ALME bit (address 08h).
Choosing single event or interrupt alarm mode is selected via
the IM bit (address 08h). Note that when the frequency output
function is enabled, the alarm function is disabled.
The standard alarm allows for alarms of time, date, day of the
week, month, and year. When a time alarm occurs in single
event mode, an IRQ1/fOUT and/or IRQ2 pin will be pulled low
and the alarm status bit (ALM) will be set to “1”.
The pulsed interrupt mode allows for repetitive or recurring
alarm functionality. Hence, once the alarm is set, the device
will continue to alarm for each occurring match of the alarm
and present time. Thus, it will alarm as often as every minute (if
only the nth second is set) or as infrequently as once a year (if
at least the nth month is set). During pulsed interrupt mode, the
IRQ1/fOUT and/or IRQ2 pin will be pulled low for 210ms and
the alarm status bit (ALM) will be set to “1”.
Note: The ALM bit can be reset by the user or cleared
automatically using the auto reset mode (see ARST bit,
address 07h).
FN6731 Rev 4.00
Sep 25, 2015
The alarm function can be enabled/disabled during battery
backup mode using the FOBATB bit (address 08h). For more
information on the alarm, see “Alarm Registers” on page 14.
Frequency Output Mode
The ISL12082 has the option to provide a frequency output
signal using the IRQ/fOUT pin. The frequency output mode is
set by using the FO bits to select 4 possible output frequency
values from 1kHz to 32.768kHz. The frequency output can be
enabled/disabled during battery backup mode using the
FOBATB bit (address 08h).
I2C Serial Interface
The ISL12082 has an I2C serial bus interface that provides
access to the control and status registers and the user SRAM.
The I2C serial interface is compatible with other industry I2C
serial bus protocols using a bi-directional data signal (SDA)
and a clock signal (SCL).
Oscillator Compensation
The ISL12082 provides the option of timing correction due to
temperature variation of the crystal oscillator for either
manufacturing calibration or active calibration. The total
possible compensation is typically -94ppm to +140ppm. Two
compensation mechanisms that are available are as follows:
1. An analog trimming (ATR) register that can be used to
adjust individual on-chip digital capacitors for oscillator
capacitance trimming. The individual digital capacitor is
selectable from a range of 9pF to 40.5pF (based upon
32.758kHz). This translates to a calculated compensation
of approximately -34ppm to +80ppm. See “ATR description”
on page 23.
2. A digital trimming register (DTR) that can be used to adjust
the timing counter by -63ppm to +126ppm. See “DTR
description” on page 23.
Also provided is the ability to adjust the crystal capacitance
when the ISL12082 switches from VDD to battery backup
mode.
Register Descriptions
The battery-backed registers are accessible following a slave
byte of “1101111x” and reads or writes to addresses [00h:1Fh].
The defined addresses and default values are described in
Table 1. Address 16h to 1Eh are not used. Reads or writes to
addresses 16h to 1Eh will not affect operation of the device but
should be avoided.
Register Access
The contents of the registers can be modified by performing a
byte or a page write operation directly to any register address.
The registers are divided into 4 sections. These are:
1. Real Time Clock (8 bytes): Address 00h to 06h, and 1Fh,
with address 1Fh as read-only byte.
2. Control and Status (5 bytes): Address 07h to 0Bh.
3. Alarm (6 bytes): Address 0Ch to 11h.
Page 10 of 28
ISL12082
A register can be read by performing a random read at any
address at any time. This returns the contents of that register
location. Additional registers are read by performing a
sequential read. For the RTC and alarm registers, the read
instruction latches all clock registers into a buffer, so an update
of the clock does not change the time being read. A sequential
read will not result in the output of data from the memory array.
At the end of a read, the master supplies a stop condition to
end the operation and free the bus. After a read, the address
remains at the previous address +1 so the user can execute a
current address read and continue reading the next register.
4. TIMER (4 bytes): Address 12h to 14h, with address 14h as
write-only byte and read back ‘0’..
There are no addresses above 1Fh.
Address 15h to 1Eh are not used. Reads or writes to
addresses 15h to 1Eh will not affect operation of the device but
should be avoided.
Write capability is allowable into the RTC registers (00h to 06h,
and 1Fh) only when the WRTC bit (bit 4 of address 07h) is set
to “1”. A multi-byte read or write operation is limited to one
section per operation. Access to another section requires a
new operation. A read or write can begin at any address within
the section.
TABLE 1. REGISTER MEMORY MAP
BIT
REG
REG
NAME
7
6
5
4
3
2
1
0
SS
SS23
SS22
SS21
SS20
SS13
SS12
SS11
SS10
0 to 99
00h
00h
SC
0
SC22
SC21
SC20
SC13
SC12
SC11
SC10
0 to 59
00h
01h
MN
OF
MN22
MN21
MN20
MN13
MN12
MN11
MN10
0 to 59
80h
02h
HR
MIL
0
HR21
HR20
HR13
HR12
HR11
HR10
0 to 23
00h
03h
DT
0
0
DT21
DT20
DT13
DT12
DT11
DT10
1 to 31
00h
04h
MO
0
0
0
MO20
MO13
MO12
MO11
MO10
1 to 12
00h
05h
YR
YR23
YR22
YR21
YR20
YR13
YR12
YR11
YR10
0 to 99
00h
06h
DW
0
0
0
0
0
DW12
DW11
DW10
0 to 6
00h
ADDR. SECTION
1Fh
RTC
RANGE DEFAULT
07h
Status
SR
ARST
XSTOP
RESEAL
WRTC
TMR
ALM
BAT
RTCF
N/A
03h
08h
Control
INT
IM
ALME
LPMODE
FOBATB
IRQ2E
IRQ1E
FO1
FO0
N/A
00h
09h
TMRC
TIM
TMRE
TMOD1
TMOD0
0
0
TCLK1
TCLK0
N/A
00h
0Ah
ATR
BMATR1
BMATR0
ATR5
ATR4
ATR3
ATR2
ATR1
ATR0
N/A
00h
0Bh
DTR
0
0
DTR5
DTR4
DTR3
DTR2
DTR1
DTR0
N/A
80h
0Ch
SCA
ESCA
ASC22
ASC21
ASC20
ASC13
ASC12
ASC11
ASC10
00 to 59
00h
0Dh
MNA
EMNA
AMN22
AMN21
AMN20
AMN13
AMN12
AMN11
AMN10
00 to 59
00h
HRA
EHRA
0
AHR21
AHR20
AHR13
AHR12
AHR11
AHR10
0 to 23
00h
DTA
EDTA
0
ADT21
ADT20
ADT13
ADT12
ADT11
ADT10
1 to 31
00h
10h
MOA
EMOA
0
0
AMO20
AMO13
AMO12
AMO11
AMO10
1 to 12
00h
11h
DWA
EDWA
0
0
0
0
ADW12
ADW11
ADW10
0 to 6
00h
12h
TDAT
TDAT7
TDAT6
TDAT5
TDAT4
TDAT3
TDAT2
TDAT1
TDAT0
0 to 255
00h
TCNT
TCNT7
TCNT6
TCNT5
TCNT4
TCNT3
TCNT2
TCNT1
TCNT0
0 to 255
00h
TSDAT
X
TSDAT6
TSDAT5
TSDAT4
TSDAT3
TSDAT2
TSDAT1
TSDAT0
0 to 99
00h
0Eh
0Fh
13h
Alarm0
TIMER
14h
FN6731 Rev 4.00
Sep 25, 2015
Page 11 of 28
ISL12082
Real Time Clock Registers
Addresses [00h to 06h, and 1Fh]
RTC REGISTERS (SC, MN, HR, DW, DT, MO, YR, SS)
These registers depict BCD representations of the time. As
such, SC (Seconds, address 00h) and MN (Minutes, address
01h) range from 0 to 59, HR (Hour, address 02h) can either be
a 12-hour or 24-hour mode, DT (Date, address 03h) is 1 to 31,
MO (Month, address 04h) is 1 to 12, YR (Year, address 05h) is
0 to 99, DW (Day of the Week, address 03h) is 0 to 6, and SS
(Sub-Seconds/Hundredths of a Second, address 1Fh) is 0 to
99. The SS register is read only. A Page read operation to read
all the RTC regsiters is possible by setting up the address to
1Fh then do a page read of 8 bytes. The first data read will be
SS, then follows by SC, MN, HR, DT, MO, YR, and DW at the
end. This is done by using address wrap around feature of the
ISL12082. The address wraps around from 1Fh to 00h in page
read instruction.
The DW register provides a Day of the Week status and uses
three bits DW2 to DW0 to represent the seven days of the week.
The counter advances in the cycle 0-1-2-3-4-5-6-0-1-2-…
The assignment of a numerical value to a specific day of the
week is arbitrary and may be decided by the system software
designer. The default value is defined as “0”.
Bit D7 of MN register contains the Oscillator Fail Indicator bit
(OF). This bit is set to a “1” when there is no oscillation on X1
pin. The OF bit can only be reset by having an oscillation on X1
and a write operation to reset it.
24 HOUR TIME
If the MIL bit of the HR register is “1”, the RTC uses a 24-hour
format. If the MIL bit is “0”, the RTC uses a 12-hour format and
HR21 bit functions as an AM/PM indicator with a “1”
representing PM. The clock defaults to 12-hour formattime with
HR21 = “0”.
LEAP YEARS
Leap years add the day February 29 and are defined as those
years that are divisible by 4. Years divisible by 100 are not leap
years, unless they are also divisible by 400. This means that the
year 2000 is a leap year, the year 2100 is not. The ISL12082 does
not correct for the leap year in the year 2100.
Control and Status Registers
Addresses [07h to 0Bh]
The Control and Status Registers consist of the Status
Register, Interrupt and alarm register, Analog Trimming and
Digital Trimming Registers.
Status Register (SR) [Address 07h]
The Status Register is located in the memory map at address
0Bh. This is a volatile register that provides either control or
status of RTC failure, battery mode, alarm trigger, write
FN6731 Rev 4.00
Sep 25, 2015
protection of clock counter, crystal oscillator enable and auto
reset of status bits.
TABLE 2. STATUS REGISTER (SR)
ADDR
07h
Default
7
6
5
4
3
2
1
0
ARST XSTOP RESEAL WRTC TMR ALM BAT RTCF
0
0
1
0
0
0
1
1
REAL TIME CLOCK FAIL BIT (RTCF)
This bit is set to a “1” after a total power failure. This is a read
only bit that is set by hardware (ISL12082 internally) when the
device powers up after having lost all power (both VDD and
VBAT go to 0V). The bit is set regardless of whether VDD or
VBAT is applied first. The loss of only one of the supplies does
not set the RTCF bit to “1”. On power-up after a total power
failure, all registers are set to their default states and the clock
will not increment until at least one byte is written to the clock
register. The first valid write to the RTC section after a
complete power failure resets the RTCF bit to “0” (writing one
byte is sufficient).
BATTERY BIT (BAT)
This bit is set to a “1” when the device enters battery backup
mode. This bit can be reset either manually by the user or
automatically reset by enabling the auto-reset bit (see ARST
bit). A write to this bit in the SR can only set it to “0”, not “1”.
ALARM BIT (ALM)
This bit announces that the alarm matches the real time clock.
If there is a match, the respective bit is set to “1”. This bit can
be manually reset to “0” by the user or automatically reset by
enabling the auto-reset bit (see ARST bit). A write to this bit in
the SR can only set it to “0”, not “1”.
Note: An alarm bit that is set by an alarm occurring during an
SR read operation will remain set after the read operation is
complete.
TIMER BIT (TMR)
This bit announces that the timer has expired. If the timer has
expired, the respective bit is set to “1”. This bit can be manually
reset to “0” by the user or automatically reset by enabling the
auto-reset bit (see ARST bit). A write to this bit in the SR can
only set it to “0”, not “1”.
WRITE RTC ENABLE BIT (WRTC)
The WRTC bit enables or disables write capability into the RTC
Timing Registers. The factory default setting of this bit is “0”.
Upon initialization or power-up, the WRTC must be set to “1” to
enable the RTC. Upon the completion of a valid write (STOP),
the RTC starts counting. The RTC internal 1Hz signal is
synchronized to the STOP condition during a valid write cycle.
ReSeal™ (RESEAL)
The ReSeal™ enables the device enter into the InterSeal™
Battery Saver mode after board functional testing. The factory
default setting of this bit is “0” to enable the backup battery
Page 12 of 28
ISL12082
operation. To use the ReSeal™ function, simply set RESEAL bit
to “1” after the testing is completed. It will enable the InterSeal™
Battery Saver mode and prevents battery current drain before it
is first used. Upon the next VDD powerup, the bit will reset to “0”
and the backup battery will be utilized.
CRYSTAL OSCILLATOR ENABLE BIT (XSTOP)
This bit enables/disables the crystal oscillator. When the
XSTOP is set to “1”, the oscillator is disabled. The XSTOP bit is
set to “0” on power-up for normal operation.
AUTO RESET ENABLE BIT (ARST)
This bit enables/disables the automatic reset of the BAT, ALM
and TMR status bits only. When ARST bit is set to “1”, these
status bits are reset to “0” after a valid read of the respective
status register (with a valid STOP condition). When the ARST
is cleared to “0”, the user must manually reset the BAT, ALM
and TMR bits.
Interrupt Control Register (INT) [Address 08h]
7
6
5
4
3
2
1
IM ALME LPMODE FOBATB IRQ2E IRQ1E FO1 FO0
Default
0
0
0
0
0
0
TABLE 5. FUNCTION SELECTION OF IRQ1/fOUT
PIN
IRQ1/fOUT FUNCTION
IRQ2E
IRQ1E
fOUT
X
0
ALARM IRQ
X
1
TABLE 6. FUNCTION SELECTION OF IRQ2 PIN
IRQ2 FUNCTION
IRQ2E
IRQ1E
ALARM IRQ
0
X
TIMER IRQ
1
X
FREQUENCY OUTPUT AND INTERRUPT BIT (FOBATB)
0
08h
0
These bits select the function of IRQ1/fOUT and IRQ2 pin. See
Table 5 for function selection of IRQ1/fOUT pin and Table 6 for
function selection of IRQ2 pin.
TABLE 3. INTERRUPT CONTROL REGISTER (INT)
ADDR
IRQ FUNCTION SELECTION BITS (IRQ1E, IRQ2E)
0
FREQUENCY OUT CONTROL BITS (FO )
These bits select the output frequency at the IRQ/fOUT pin.
IRQ1E must be set to “0” for frequency output at the IRQ/fOUT
pin. See Table 4 for frequency selection.
TABLE 4. FREQUENCY SELECTION OF fOUT PIN
FREQUENCY,
fOUT
UNITS
FO1
FO0
32768
Hz
0
0
Free running
crystal clock
4096
Hz
0
1
Free running
crystal clock
512
Hz
1
0
Free running
crystal clock
1
Hz
1
1
Sync. with
second, 30µs jitter
COMMENT
Note: The falling edge of 1Hz frequency output is synchronized
with the seconds.
This bit enables/disables the IRQ1/fOUT pin during battery
backup mode (i.e. VBAT power source active). When the
FOBATB is set to “1”, the IRQ1/fOUT pin is disabled during
battery backup mode. This means that both the frequency
output and alarm output functions are disabled. When the
FOBATB is cleared to “0”, the IRQ1/fOUT pin is enabled during
battery backup mode.
LOW POWER MODE BIT (LPMODE)
This bit enables/disables low power mode. With
LPMODE = “0”, the device will be in normal mode and the
VBAT supply will be used when VDD < VBAT - VBATHYS and
VDD < VTRIP. With LPMODE = “1”, the device will be in low
power mode and the VBAT supply will be used when
VDD < VBAT - VBATHYS. There is a supply current saving of
about 600nA when using LPMODE = “1” with VDD = 5V (See
“Typical Performance Curves” on page 7: IDD vs VCC with
LPMODE ON and OFF). see also “Power Control Operation”
under “Functional Description” on page 9.
ALARM ENABLE BIT (ALME)
This bit enables/disables the alarm function. When the ALME bit
is set to “1”, the alarm function is enabled. When the ALME is
cleared to “0”, the alarm function is disabled. The alarm function
can operate in either a single event alarm or a periodic interrupt
alarm (see IM bit).
Note: When the frequency output mode is enabled, the alarm
function is disabled.
ALARM PULSE/EVENT INTERRUPT BIT (IM)
This bit enables/disables the interrupt mode of the alarm
function. When the IM bit is set to “1”, the alarm will operate in
the interrupt mode, where an active low pulse width of 210ms
will appear at the IRQ1/fOUT and/or IRQ2 pin when the RTC is
triggered by the alarm as defined by the alarm registers (0Ch
FN6731 Rev 4.00
Sep 25, 2015
Page 13 of 28
ISL12082
to 11h). When the IM bit is cleared to “0”, the alarm will operate
in standard mode, where the IRQ1/FOUT and/or IRQ2 pin will
be tied low until the ALM status bit is cleared to “0”. The IM bit
is set to “0” on power-up.
IM BIT
ALARM PULSE/EVENT INTERRUPT FUNCTION
BATTERY MODE ATR SELECTION (BMATR )
0
Single Time Event Set By Alarm
1
Repetitive/Recurring Time Event Set By Alarm
Since the accuracy of the crystal oscillator is dependent on the
VDD/VBAT operation, the ISL12082 provides the capability to
adjust the capacitance between VDD and VBAT when the
device switches between power sources.
Analog Trimming Register (ATR) [Address 0Ah]
TABLE 7. ANALOG TRIMMING REGISTER (ATR)
ADDR
0Ah
7
6
5
4
3
For example, CLOAD(ATR = 00000) = 12.5pF, CLOAD
(ATR = 100000) = 4.5pF and CLOAD (ATR = 011111) =
20.25pF. The entire range for the series combination of load
capacitance goes from 4.5pF to 20.25pF in 0.25pF steps. Note
that these are typical values.
2
1
BMATR1 BMATR0 ATR5 ATR4 ATR3 ATR2 ATR1 ATR0
Default
0
0
0
0
0
0
0
BMATR1
BMATR0
0
0
0pF
0
1
-0.5pF ( +2ppm)
1
0
+0.5pF ( -2ppm)
1
1
+1pF ( -4ppm)
0
ANALOG TRIMMING REGISTER (ATR)
X1
CX1
DELTA
CAPACITANCE
(CBAT TO CVDD)
0
CRYSTAL
OSCILLATOR
Digital Trimming Register (DTR) [Address 07h]
TABLE 8. DIGITAL TRIMMING REGISTER (DTR)
X2
CX2
FIGURE 11. DIAGRAM OF ATR
ADDR
7
6
07h
0
0
Default
0
0
5
4
3
2
1
0
DTR5 DTR4 DTR3 DTR2 DTR1 DTR0
0
0
0
0
0
0
DIGITAL TRIMMING REGISTER (DTR)
Six analog trimming bits, ATR0 to ATR5, are provided in order
to adjust the on-chip load capacitance value for frequency
compensation of the RTC. Each bit has a different weight for
capacitance adjustment. For example, using a Citizen CFS206 crystal with different ATR bit combinations provides an
estimated ppm adjustment range from -34ppm to +80ppm to
the nominal frequency compensation. The combination of
analog and digital trimming can give up to -97ppm to +206ppm
of total adjustment.
Six digital trimming bits, DTR0 to DTR5, are provided to adjust
the average number of counts per second and average the
ppm error to achieve better accuracy.
The effective on-chip series load capacitance, CLOAD, ranges
from 4.5pF to 20.25pF with a mid-scale value of 12.5pF
(default). CLOAD is changed via two digitally controlled
capacitors, CX1 and CX2, connected from the X1 and X2 pins
to ground (see Figure 11). The value of CX1 and CX2 are given
in Equation 1:
A range from -63.0696ppm to +126.139ppm can be
represented by using these 6 bits.
C
X
= 16 b5 + 8 b4 + 4 b3 + 2 b2 + 1 b1 + 0.5 b0 + 9 pF (EQ. 1)
The effective series load capacitance is the combination of CX1
and CX2 in Equation 2:
1
1
1
---------- + -----------
C
C
C LOAD = ----------------------------------X1
X2
(EQ. 2)
16 b5 + 8 b4 + 4 b3 + 2 b2 + 1 b1 + 0.5 b0 + 9
C LOAD = ----------------------------------------------------------------------------------------------------------------------------- pF
FN6731 Rev 4.00
Sep 25, 2015
2
• DTR5 is a sign bit. DTR5 = “0” means frequency
compensation is < 0. DTR5 = “1” means frequency
compensation is > 0.
• DTR are scale bits. With DTR5 = “0”, DTR gives
2.0345ppm adjustment per step. With DTR5 = “1”,
DTR gives 4.0690ppm adjustment per step.
For example, with DTR = 11111, the digital adjustment is
(1111b[15d]*4.0690) = +126.139ppm. With DTR = 01111, the
digital adjustment is (-(1111b[15d]*2.0345)) = -63.0696ppm.
Alarm Registers
Addresses [Address 0Ch to 11h]
The alarm register bytes are set up identical to the RTC
register bytes, except that the MSB of each byte functions as
an enable bit (enable = “1”). These enable bits specify which
alarm registers (seconds, minutes, etc) are used to make the
comparison. Note that there is no alarm byte for year and subsecond, and the register order for alarm register is not a 100%
matching to the RTC register so please take caution on
programming the alarm function.
Page 14 of 28
ISL12082
The alarm function works as a comparison between the alarm
registers and the RTC registers. As the RTC advances, the
alarm will be triggered once a match occurs between the alarm
registers and the RTC registers. Any one alarm register,
multiple registers, or all registers can be enabled for a match.
There are two alarm operation modes: Single Event and
Periodic Interrupt Mode:
• Single Event Mode is enabled by setting the ALME bit to
“1”, the IM bit to “0”, and IRQ1E bit to “1” and/or IRQ2E bit to
“0”. This mode permits a one-time match between the alarm
registers and the RTC registers. Once this match occurs, the
ALM status bit is set to “1” and the IRQ1/fOUT and/or IRQ2
output will be pulled low and will remain low until the ALM
status bit is reset to “0”. This can be done manually or by
using the auto-reset feature.
• Periodic Interrupt Mode is enabled by setting the ALME bit
to “1”, the IM bit to “1”, and IRQ1E bit to “1” and/or IRQ2E bit
to “0”. The IRQ1/fOUT and/or IRQ2 output will now be pulsed
each time an alarm occurs. This means that once the
interrupt mode alarm is set, it will continue to alarm for each
occurring match of the alarm and present time. This mode is
convenient for hourly or daily hardware interrupts in
microcontroller applications such as security cameras or
utility meter reading.
To clear an alarm, the ALM status bit must be set to “0” with a
write. Note that if the ARST bit is set to “1” (address 07h, Bit 7),
the ALM bit will automatically be cleared when the status
register is read.
Following are examples of both Single Event and periodic
Interrupt Mode alarms.
Example 1 – Alarm set with single interrupt (IM = ”0”)
A single alarm will occur on January 1 at 11:30am.
A. Set Alarm registers as follows:
ALARM
REGISTER 7
BIT
6
5
4
3
2
1
0
HEX
DESCRIPTION
SCA
0
0
0
0
0
0
0
0
00h Seconds disabled
MNA
1
0
1
1
0
0
0
0
B0h Minutes set to 30,
enabled
HRA
1
0
0
1
0
0
0
1
91h Hours set to 11,
enabled
DTA
1
0
0
0
0
0
0
1
81h Date set to 1,
enabled
MOA
1
0
0
0
0
0
0
1
81h Month set to 1,
enabled
DWA
0
0
0
0
0
0
0
0
00h Day of week
disabled
CONTROL
REGISTER 7
BIT
6
5
4
3
2
1
0
HEX
DESCRIPTION
NOTE: x indicate other control bits
After these registers are set, an alarm will be generated when
the RTC advances to exactly 11:30am on January 1 (after
seconds changes from 59 to 00) by setting the ALM bit in the
status register to “1” and also bringing the IRQ1/fOUT and IRQ2
output low if IRQ1E bit is set to “1” and IRQ2E bit is set to “0”.
Example 2 – Pulsed interrupt once per minute (IM = ”1”)
Interrupts at one minute intervals when the seconds register is
at 30s.
A. Set alarm registers as follows:
BIT
ALARM
REGISTER 7 6 5 4 3 2 1 0 HEX
DESCRIPTION
SCA
1 0 1 1 0 0 0 0 B0h Seconds set to 30,
enabled
MNA
0 0 0 0 0 0 0 0 00h Minutes disabled
HRA
0 0 0 0 0 0 0 0 00h Hours disabled
DTA
0 0 0 0 0 0 0 0 00h Date disabled
MOA
0 0 0 0 0 0 0 0 00h Month disabled
DWA
0 0 0 0 0 0 0 0 00h Day of week disabled
B. Set the Interrupt register as follows:
BIT
CONTROL
REGISTER 7 6 5 4 3 2 1 0 HEX
INT
DESCRIPTION
1 1 x x 0 0 0 0 x0h Enable Alarm and Int
Mode
NOTE: x indicate other control bits
Once the registers are set, the following waveform will be seen
at IRQ:
RTC AND ALARM REGISTERS ARE BOTH 30s
60s
Note that the status register ALM bit will be set each time the
alarm is triggered, but does not need to be read or cleared.
B. Set the ALME bit as follows:
CONTROL
REGISTER 7
INT
0
BIT
6
5
4
3
2
1
0
HEX
1
x
x
0
0
0
0
x0h
FN6731 Rev 4.00
Sep 25, 2015
DESCRIPTION
Enable Alarm
Page 15 of 28
ISL12082
Timer Control Register (TMRC) [Address 09h]
TABLE 9. TIMER CONTROL REGISTER (TMRC)
ADDR
09h
Default
7
6
5
4
TIM TMRE TMOD1 TMOD0
0
0
0
0
3
2
0
0
0
0
1
0
TCLK1 TCLK0
0
0
TIMER CLOCK FREQUENCY SELECTION BITS
(TCLK )
For detailed timer operation, please refer to “TIMER
COUNTER OPERATION” on page 17.
These bits select the Timer/Watchdog clock frequency for the
Timer Counter Register (TCNT, address 13h) and the internal
Sub-Timer Counter Register (TSCNT). When the Sub-Timer
Initial Register (TSDAT, address 14h) is set to “0”, the number
of counts changes to the default value. The maximum register
value for the TSDAT register is 127 which means the maximum
limit for the internal Sub-Timer Counter Register is also 127.
See Table 10 for Timer/Watchdog clock frequency selection
and the default counts for the Sub-Timer Counter Register.
TABLE 10. TIMER CLOCK FREQUENCY SELECTION AND
DEFAULT VALUE FOR TSDAT REGISTER
TCLK1 TCLK0 FUNCTION
0
0
1
1
0
1
0
1
COMMENT
Counter reaches to 10, the Timer Counter will increment by
one which means the Timer Counter will increment every ten
seconds.
Example 3- TCLK1 is set to “0”, TCLK0 is set to “1”, and SubTimer Initial Register is set to “0”. The internal Sub-Timer
Counter will increment every 1ms (100Hz). When the internal
Sub-Timer Counter reaches to 100, the default value2, the
Timer Counter will increment by one which means the Timer
Counter will increment every one second.
TIMER FUNCTION SELECTION BITS (TMOD )
The Timer interrupt has four different functions:
1. Count Down Timer
2. Secondary Alarm Timer
3. Watchdog Timer
4. Power Fail Count-up Timer
Please see Table 11 for Timer counting functions selection.
TABLE 11. TIMER COUNTING FUNCTION SELECTION
TMOD1 TMOD0
FUNCTION
COMMENT
0
0
Count Down
Timer
Basic count down timer
(TCNT register decrement)
0
1
100Hz/4kHz 100Hz for TCNT, 4kHz for TSCNT
Default Value for TSDAT = 41
(41 TSCNT counts = 1ms)
(Not available for Watchdog Timer)
Secondary
Alarm Timer
Basic count down timer activated by
ALARM IRQ (ALM bit)
(TCNT register decrement)
1
0
Watchdog
Timer
1sec/100Hz 1sec for TCNT, 100Hz for TSCNT
Default Value for TSDAT = 100
(100 TSCNT counts = 1s)
Count up timer with periodic
interrupt
(TCNT register increment)
1
1
Power Fail
Count-up
Timer
Count up after device entered into
battery mode
(TCNT register increment)
1min/1sec
1hr/1min
1min for TCNT, 1sec for TSCNT
Default Value for TSDAT = 60
(60 TSCNT counts = 1min)
(RTC must be enabled)
1hour for TCNT, 1min for TSCNT
Default Value for TSDAT = 60
(60 TSCNT counts = 1hr)
(RTC must be enabled)
The Timer Counter and Sub-Timer Counter Registers advance
the counter value based on the frequency or time setting by the
TCLK bits.
The following are examples of Timer clock frequency selection
bits on Timer Counter and Sub-Timer Counter Registers.
Example 1 - TCLK1 is set to “1”, TCLK0 is set to “0”, and SubTimer Initial Register is set to “0”. The internal Sub-Timer
Counter will increment every 1s. When the internal Sub-Timer
Counter reaches to 60, the default value, the Timer Counter
will increment by one which means the Timer Counter will
increment every one minute.
Example 2- TCLK1 is set to “1”, TCLK0 is set to “0”, and SubTimer Initial Register is set to “10d”. The internal Sub-Timer
Counter will increment every 1s. When the internal Sub-Timer
FN6731 Rev 4.00
Sep 25, 2015
TIMER ENABLE BIT (TMRE)
This bit enables/disables the timer function. When the TMRE
bit is set to “1”, the timer is enabled. To display timer interrupt
on the IRQ2 pin, the IRQ2E has to be set to “1”. When the
TMRE bit is cleared to “0”, the timer function is disabled. The
TMRE bit is set to “0” on power-up.
TIMER PULSE/EVENT INTERRUPT BIT (TIM)
This bit enables/disables the interrupt mode of the timer
function. When the TIM bit is set to “1”, the timer will operate in
the interrupt mode. An active low pulse width of 210ms will
appear at the IRQ2 pin when the RTC is triggered by the timer
as defined by the timer registers (12h to 15h). When the TIM
bit is cleared to “0”, the timer will operate in standard mode,
where the IRQ2 pin will be held low until TMR status bit is
cleared to “0”. The TIM bit is set to “0” on power-up.
TIM BIT
TIMER PULSE/EVENT INTERRUPT FUNCTION
0
Single Time Event Set By Timer
1
Repetitive/Recurring Time Event Set By Timer
Page 16 of 28
ISL12082
Timer Registers
Addresses [12h to 15h]
Timer Initial Register (TDAT) [Address 12h]
The Timer Initial Register is located in the memory map at
address 12h. This is a volatile register that stores the timer limit
for the timer counter register.
TABLE 12. TIMER INITIAL REGISTER (TDAT)
ADDR
12h
Default
7
6
5
4
3
2
1
0
TDAT7 TDAT6 TDAT5 TDAT4 TDAT3 TDAT2 TDAT1 TDAT0
0
0
0
0
0
0
0
0
Timer Counter Register (TCNT) [Address 13h]
The Timer Counter Register is located in the memory map at
address 13h. This is a volatile register that keeps the current
timer counter value. This byte is read only.
TABLE 13. TIMER COUNTER REGISTER (TCNT)
ADDR
13h
Default
7
6
5
4
3
2
1
0
TCNT7 TCNT6 TCNT5 TCNT4 TCNT3 TCNT2 TCNT1 TCNT0
0
0
0
0
0
0
0
0
for the internal sub-timer counter register. This byte is write
only and only read back a “0”
Sub-Timer Initial Register (TSDAT) [Address 14h]
The Sub-Timer Initial Register is located in the memory map at
address 14h. This is a volatile register that stores the timer limit
TABLE 14. SUB-TIMER INITIAL REGISTER (TSDAT)
ADDR
14h
Default
7
6
5
3
2
1
0
TSDAT7 TSDAT6 TSDAT5 TSDAT4 TSDAT3 TSDAT2 TSDAT1 TSDAT0
0
0
0
Internal Sub-Timer Counter Register (TSCNT)
The Internal Sub-Timer Counter Register is an internal volatile
register that keeps the current sub-timer counter value. This
byte is not accessible.
Timer Counter Operation
The ISL12082 timer consists of a timer counter and a sub-timer
counter. The timer counter can be an incremental or a
decremental counter which depends on the setting of the Timer
Function Selection Bits (TMOD[1:0], address 09h, bits 5 and
4). Sub-timer counter works as an incremental counter. The
timer counter is represented by the Timer Counter Register
(TCNT, address 13h) and the sub-timer counter is represented
by the internal Sub-Timer Counter Register (TSCNT) which is
not accessible by the user. The Timer Initial Register (TDAT,
address 12h) and the Sub-Timer Initial Register (TSDAT,
address 14h) are used to set the limit for the TCNT register
and internal TSCNT register respectively. The TDAT register
must contain a minimum value of 2 in order to operate the
timer properly and the TSAT register can be set to any value
up to 127 decimal. If the TSDAT register is set to “0”, the
FN6731 Rev 4.00
Sep 25, 2015
4
0
0
0
0
0
TSDAT will reset to the default value which depends on the
TCLK[1:0] bits setting which is shown in Table 10.
Once the timer function is enabled by setting the TMRE bit to
“1”, the TCNT register is set to the TDAT value or one
depending on the setting of the TMOD[1:0] bits, and the
internal TSCNT register is set to one. Then the internal TSCNT
will increment one bit at a time and at a frequency set by the
Timer Clock Frequency Selection Bits ( TCLK[1:0], address
09h bits 1 and 0). The internal TSCNT register will overflow
when it counts up to the value in the TSDAT register. If the
TSDAT register is set to “0”, the internal TSCNT will count up
to the default TSDAT register value to overflow. If the internal
TSCNT register overflows, the TCNT register will increment or
decrement by one depending on the setting of the TMOD[1:0]
bits and the internal TSCNT register resets back to “1” and
repeats the counting cycle. The timer expires when the TCNT
register increments to the TDAT register value or decrements
to zero depending on the setting of the TMOD[1:0] bits. The
TMR bit is set and the IRQ2 is held low to indicate the timer
interrupt. The IRQ2 only activates for the timer interrupt when
the IRQ2E (address 8h, bit 3) sets to “1”.
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ISL12082
There are two timer operation modes for the IRQ2: Single
Event and Periodic Interrupt Mode:
• Single Event Mode is enabled by setting the TMRE bit to “1”,
the TIM bit to “0”, and IRQ2E bit to “1”. This mode permits a
one-time timer counting cycle. Once the timer expires, the TMR
status bit is set to “1” and the IRQ2 output will be held low until
the TMR status bit is reset to “0”. This can be done manually or
by using the auto-reset feature. Once the TMR status bit is
reset, the timer will reset and restart the counting cycle. If the
TMRE bit is set to “0” before the TMR status bit is reset, then
counting is halted.
The IRQ2 can be reset by setting the TMRE bit to “0” but the
TMR status bit will remain at “1”. The timer can be re-enabled
with TMR status remaining at “1”.
• Periodic Interrupt Mode is enabled by setting the TMRE bit
to “1”, the TIM bit to “1”, and IRQ2E bit to “1”. The timer must
be disabled prior to setting TIM bit to “1” in order to enable
the Periodic Interrupt Mode. In the Periodic Interrupt Mode,
the IRQ2 output will be pulsed each time a timer expires.
The low and the high pulse width of the IRQ2 can be
calculated by the TCLK[1:0] bits, the TDAT register and the
TSDAT register. After the interrupt, the internal TSCNT
register will keep counting until it overflows. When the
internal TSCNT register overflows, the IRQ2 pin is pulled
high and the TSCNT register is reset to the value in TDAT
register or “1” depended on the TMOD[1:0] setting. Then the
new counting cycle begins.
The TMR bit is still set each time when the timer expired.
Resetting the TMR status bit to “0” from “1” in the Periodic
Interrupt Mode will cause the TCNT register and the internal
TSCNT register to reset. Depending on when the TMR bit is
being reset, the low pulse width or the high pulse width will
be prolonged for the amount of time the counter has
counted.
The Interrupt Mode can be disabled by setting the TIM bit to
“0” when timer is enabled. The interrupt mode can not be
enabled after the timer is enabled.
When the timer is disabled by setting the TMRE bit to “0”, the
register value for the timer counter and the sub-timer are set
back to the default value. The default value for the Timer
Counter Register (TCNT, address 13h) is “0” and Sub-Timer
Counter Register (TSCNT, address 15h) is “1”.
Following are the detailed descriptions of the four different
timer modes.
Count Down Timer
The Count Down timer is a basic countdown timer. Once the
timer is enabled by setting TMRE bit to “1”, the TCNT register
is set to the value in TDAT register. The TDAT register must
have a value of two or greater in order for the timer to start. If
the timer is enabled with TDAT register less than two, then the
timer is disabled and the TDAT register has to be set to an
appropriate value before the timer can be enabled again. The
internal TSCNT register increments from one, and the
FN6731 Rev 4.00
Sep 25, 2015
incremental frequency is set by the TCLK[1:0] bits. Once the
internal TSCNT register overflows, the TCNT register will
decrement by one and the internal TSCNT register will reset
back to one and start counting again until the TCNT register
reaches zero. Once the TCNT register reaches zero, the timer
will issue an interrupt that will set the TMR status bit to “1” and
set the IRQ2 pin to low (if IRQ2E bit is set to “1”).
When the TIM = “0” (single event mode), the timer stops after
the timer expires. The timer will restart and the IRQ2 pin will be
high when the TMR bit is cleared to “0”. The timer can also be
restarted by resetting the TMRE bit to “1” after setting it to “0”.
This method is not recommended since the TMR status will not
clear by this method and may cause confusion in the system.
In single event mode, the time interval for the timer expiration
is calculated by using Equation 3.
Timer Interval = TDAT*TSDAT*TCLK
(EQ. 3)
Where, TDAT is the value in the TDAT register. TSDAT is the
value in the TSDAT register (use default if 0). TCLK is the
period set by the TCLK[1:0] bits. For 4kHz setting, please use
244µs for the period. For 100Hz setting please use 10ms for
the period.
When the TIM = “1” (periodic interrupt mode), the timer repeats
the countdown function automatically after the timer expires.
The periodic interrupt function can only be monitored on the
IRQ2 pin; therefore, the IRQ2E bit must be set to “1” to show
timer interrupt on the IRQ2 pin. The IRQ2 pin is pulsed each
time the timer expires. Once the timer expires, the TMR status
bit set to “1” and the IRQ2 pin goes low. The internal TSCNT
register will reset and continue counting. Once the internal
TSCNT overflows after the timer expires, the IRQ2 pin will pull
back to high but the TMR status bit will remain at “1” until the
user clears it. The TCNT register will reset back to the value in
the TDAT register to start the new count cycle. The timer will
continue counting until the TMRE = “0” to disable the timer. In
periodic interrupt mode, the time interval for the timer
expiration is calculated differently for the first timer expiration
and for the next and succeeding timer expiration. For the first
timer expiration, the time interval is calculated by using
Equation 3. For the next and succeeding timer expiration, the
time interval can be treated as the high pulse width of IRQ2 pin
(THIGH_CDT), and it is calculated by using Equation 4. The low
interrupt pulse width of IRQ2 pin (TLOW_CDT) is calculated by
using Equation 5. Since the TMR status bit is not reset
automatically by the device at the new count cycle, if the user
resets it, the timer will reset and the next count cycle will be
seen as the first count cycle by the device.
THIGH_CDT = (TDAT-1)*TSDAT*TCLK
(EQ. 4)
Where, TDAT is the value in the TDAT register. TSDAT is the
value in the TSDAT register (use default if 0). TCLK is the
period set by the TCLK[1:0] bits. For 4kHz setting, please use
Page 18 of 28
ISL12082
244µs for the period. For 100Hz setting please use 10ms for
the period.
TLOW_CDT = TSDAT*TCLK
(EQ. 5)
Where, TSDAT is the value in the TSDAT register (use default
if 0). TCLK is the period set by the TCLK[1:0] bits. For 4kHz
setting, please use 244µs for the period. For 100Hz setting
please use 10ms for the period.
Since the pulse width of the IRQ2 pin is adjustable with setting
in the TDAT register, the TSDAT register and the TCLK[1:0]
bits, the IRQ2 pin can be use as a variable frequency/pulse
width generator.
Secondary Alarm Timer
The secondary alarm timer function has the exact same
function as the count down timer function except the timer
activates when the device has an alarm interrupt (ALM set to
“1”) with TMRE set to “1” to enable the timer. Once the timer is
activated by the alarm interrupt, the timer will work
independently. Another alarm interrupt will not reset the timer
function while the timer is counting. When the timer is stopped
by the timer interrupt or disabled by the TMRE bit, the timer
has to wait for the new alarm interrupt to activate it. Please
refer to the “Count Down Timer” on page 18 for the detailed
timer function.
Watchdog Timer
The watchdog timer is used as an I2C bus activity monitor. If
the I2C bus does not have an activity for a period of time which
is longer than its normal condition, then the watchdog timer will
issue an interrupt to set the TMR status bit to “1” and pulse the
IRQ2 pin low for 210ms if IRQ2E bit is set to “1” for timer
interrupt. It is recommended to set the IRQ2E to “1” for IRQ2
pin to show the timer interrupt because the I2C may be in a
fault condition where monitoring the TMR status bit will be
impossible. The watchdog timer is reset and will start a new
count cycle by an I2C “start” condition on the I2C bus.
will pulse low for 210ms if the IRQ2E bit is set to “1” for timer
interrupt and TSDAT register is set to “0” for default count
value (refer to Table 10 for the default count values). The timer
will reset and start a new count cycle after the interrupt;
therefore, the watchdog timer is in periodic interrupt mode only
with TIM bit set to “0” or “1”.
The time interval for the watchdog interrupt is calculated
differently for the first watchdog interrupt and for the next and
succeeding watchdog interrupt. For the first watchdog interrupt
(TWD_1st), the time interval is calculated by using Equation 6.
For the next and succeeding watchdog interrupt (TWD_2nd),
the time interval is calculated by using Equation 7. The low
interrupt pulse width of IRQ2 pin (TWD_IRQ) is calculated by
using Equation 8. The interrupt pulse width has a maximum
pulse width of 210ms. If the interrupt is less than 210ms, then
the remaining time (210ms-actual interrupt pulse) from the
interrupt pulse width will be added to the time interval of the
next count cycle.
(EQ. 6)
TWD_1st = TDAT*TSDAT*TCLK
Where, TDAT is the value in the TDAT register. TSDAT is the
value in the TSDAT register (use default if 0). TCLK is the
period set by the TCLK[1:0] bits. For 100Hz setting, please use
10ms for the period.
TWD_2nd = (TDAT-1)*TSDAT*TCLK+[(TWD_IRQ)-210ms]
(EQ. 7)
Where, TDAT is the value in the TDAT register. TSDAT is the
value in the TSDAT register (use default if 0). TCLK is the
period set by the TCLK[1:0] bits. For 100Hz setting, please use
10ms for the period.
Note: Apply Equation 7 only when TWD_IRQ is greater than
210ms.
TWD_IRQ(maximum 210ms) = TSDAT*TCLK
(EQ. 8)
The watchdog timer only works with the TCLK[1:0] setting of
“01”, “10” and “11”. The timer is disabled with the TCLK[1:0]
setting of “00”.
Once the timer is enabled by setting TMRE=“1”, the TCNT
register is set to “1” and counts up to the TDAT register value.
The TDAT register must has a value of one or greater in order
for the timer to start. If the timer is enabled with TDAT register
less than one, then the timer is disabled and the TDAT register
has to be set to an appropriate value before the timer can be
enabled again. The internal TSCNT register increments from
one, and the incremental frequency is set by the TCLK[1:0]
bits. Once the internal TSCNT register overflows, the TCNT
register will increment by one and the internal TSCNT register
will reset back to one and start counting again until the TCNT
register reaches the TDAT register value. Once the TCNT
register reaches the TDAT register value, the timer will issue
an interrupt that will set the TMR status bit to “1”. The IRQ2 pin
FN6731 Rev 4.00
Sep 25, 2015
Page 19 of 28
ISL12082
Where, TSDAT is the value in the TSDAT register (use default
if 0). TCLK is the period set by the TCLK[1:0] bits. For 100Hz
setting, please use 10ms for the period.
Power Fail Timer
In Power Fail Timer function, the Timer will start counting when
the device is switched from normal mode to battery mode.
The power fail timer only works with the TCLK[1:0] setting of
“01”, “10” and “11”. The timer is disabled with the TCLK[1:0]
setting of “00”.
Once the timer is enabled by setting TMRE bit to “1” and the
device switches from normal mode to battery mode, the TCNT
register is set to “1”. The timer expires when TCNT counts to
FFh (255d) and the value in the TDAT register is ignored.
Protocol Conventions
Data states on the SDA line can change only during SCL LOW
periods. SDA state changes during SCL HIGH are reserved for
indicating START and STOP conditions (see Figure 12). On
power-up of the ISL12082, the SDA pin is in the input mode.
All I2C interface operations must begin with a START
condition, which is a HIGH to LOW transition of SDA while SCL
is HIGH. The ISL12082 continuously monitors the SDA and
SCL lines for the START condition and does not respond to
any command until this condition is met
(see Figure 12). A START condition is ignored during the
power-up sequence.
The internal TSCNT register increments from one, and the
incremental frequency is set by the TCLK[1:0] bits. Once the
internal TSCNT register overflows, the TCNT register
increments by one and the internal TSCNT register resets back
to one and starts counting again until the TCNT register
reaches FFh (255d). Once the TCNT register reaches FFh
(255d), the timer issues an interrupt to set the TMR status bit to
“1” and pull IRQ2 pin low if IRQ2E = “1” (timer interrupt). The
timer stops after the time expires, and the power fail timer is in
single event mode only regarding the status of TIM bit. The
timer restarts and the IRQ2 pin pulls high when the TMR bit is
cleared by the user. The timer can also restart by resetting the
TMRE bit to “1” after setting it to “0” but this method is not
recommended since the TMR status will not clear by this
method and may cause confusion in the system. In single
event mode, the time interval for the timer expiration is
calculated by using Equation 3.
The power fail timer will store the timer value in the TCNT
register after the device switches back to normal mode from
battery mode. The next time the device enters battery mode
from normal mode, the timer will start its count from the value
stored in the TCNT register. The stored value in TCNT register
is only clear when the timer is disabled by setting the TMRE bit
to “0”.
I2C Serial Interface
The ISL12082 supports a bi-directional bus oriented protocol.
The protocol defines any device that sends data onto the bus
as a transmitter and the receiving device as the receiver. The
device controlling the transfer is the master and the device
being controlled is the slave. The master always initiates data
transfers and provides the clock for both transmit and receive
operations. Therefore, the ISL12082 operates as a slave
device in all applications.
All communication over the I2C interface is conducted by
sending the MSB of each byte of data first.
FN6731 Rev 4.00
Sep 25, 2015
Page 20 of 28
ISL12082
All I2C interface operations must be terminated by a STOP
condition, which is a LOW to HIGH transition of SDA while SCL
is HIGH (see Figure 13). A STOP condition at the end of a read
operation or at the end of a write operation to memory only
places the device in its standby mode.
SDA line LOW to acknowledge the reception of the eight bits of
data (see Figure 14).
The ISL12082 responds with an ACK after recognition of a
START condition followed by a valid Identification Byte, and
once again after successful receipt of an Address Byte. The
ISL12082 also responds with an ACK after receiving a Data
Byte of a write operation. The master must respond with an
ACK after receiving a Data Byte of a read operation.
An acknowledge (ACK) is a software convention used to
indicate a successful data transfer. The transmitting device,
either master or slave, releases the SDA bus after transmitting
eight bits. During the ninth clock cycle, the receiver pulls the
SCL
SDA
DATA
STABLE
START
DATA
CHANGE
DATA
STABLE
STOP
FIGURE 12. VALID DATA CHANGES, START, AND STOP CONDITIONS
SCL FROM
MASTER
1
8
9
SDA OUTPUT FROM
TRANSMITTER
HIGH IMPEDANCE
HIGH IMPEDANCE
SDA OUTPUT FROM
RECEIVER
START
ACK
FIGURE 13. ACKNOWLEDGE RESPONSE FROM RECEIVER
WRITE
SIGNALS FROM
THE MASTER
SIGNAL AT SDA
S
T
A
R
T
ADDRESS
BYTE
IDENTIFICATION
BYTE
1 1 0 1 1 1 1 0
SIGNALS FROM
THE ISL12082
S
T
O
P
LAST DATA
BYTE
FIRST DATA
BYTE
0 0 0 0
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
FIGURE 14. SEQUENTIAL BYTE WRITE SEQUENCE
Device Addressing
Following a start condition, the master must output a Slave
Address Byte. The 7 MSBs are the device identifier. These bits
are “1101111”. Slave bits “1101” access the register. Slave bits
“111” specify the device select bits.
The last bit of the Slave Address Byte defines a read or write
operation to be performed. When this R/W bit is a “1”, then a
FN6731 Rev 4.00
Sep 25, 2015
read operation is selected. A “0” selects a write operation (see
Figure 15).
After loading the entire Slave Address Byte from the SDA bus,
the ISL12082 compares the device identifier and device select
bits with “1101111”. Upon a correct compare, the device
outputs an acknowledge on the SDA line.
Following the Slave Byte is a one byte word address. The word
address is either supplied by the master device or obtained
Page 21 of 28
ISL12082
responds with an ACK. At this time, the I2C interface enters a
standby state.
from an internal counter. On power-up the internal address
counter is set to address 0h, so a current address read of the
CCR array starts at address 0h. When required, as part of a
random read, the master must supply the 1 Word Address
Bytes as shown in Figure 16.
Read Operation
In a random read operation, the slave byte in the “dummy
write” portion must match the slave byte in the “read” section.
For a random read of the Clock/Control Registers, the slave
byte must be “1101111x” in both places.
R/W
SLAVE
ADDRESS BYTE
A1
A0
WORD ADDRESS
D1
D0
DATA BYTE
1
1
0
1
1
1
1
A7
A6
A5
A4
A3
A2
D7
D6
D5
D4
D3
D2
FIGURE 15. SLAVE ADDRESS, WORD ADDRESS, AND DATA
BYTES
Write Operation
A Write operation requires a START condition, followed by a
valid Identification Byte, a valid Address Byte, a Data Byte, and
a STOP condition. After each of the three bytes, the ISL12082
SIGNALS
FROM THE
MASTER
S
T
A
R
T
SIGNAL AT
SDA
SIGNALS FROM
THE SLAVE
IDENTIFICATION
BYTE WITH
R/W = 0
A Read operation consists of a three byte instruction followed
by one or more Data Bytes (see Figure 16). The master
initiates the operation issuing the following sequence: a
START, the Identification byte with the R/W bit set to “0”, an
Address Byte, a second START, and a second Identification
byte with the R/W bit set to “1”. After each of the three bytes,
the ISL12082 responds with an ACK. Then the ISL12082
transmits Data Bytes as long as the master responds with an
ACK during the SCL cycle following the eighth bit of each byte.
The master terminates the read operation (issuing a STOP
condition) following the last bit of the last Data Byte (see Figure
16).
The Data Bytes are from the memory location indicated by an
internal pointer. This pointer initial value is determined by the
Address Byte in the Read operation instruction, and
increments by one during transmission of each Data Byte.
After reaching the memory location 13h the pointer “rolls over”
to 00h, and the device continues to output data for each ACK
received.
S
T IDENTIFICATION
A
BYTE WITH
R
R/W = 1
T
ADDRESS
BYTE
A
C
K
S
T
O
P
A
C
K
1 1 0 1 1 1 1 1
1 1 0 1 1 1 1 0
A
C
K
A
C
K
A
C
K
FIRST READ
DATA BYTE
LAST READ
DATA BYTE
FIGURE 16. SEQUENTIAL BYTE READ SEQUENCE
FN6731 Rev 4.00
Sep 25, 2015
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ISL12082
Application Section
Oscillator Crystal Requirements
The ISL12082 uses a standard 32.768kHz crystal. Either
through hole or surface mount crystals can be used. Table 15
lists some recommended surface mount crystals and the
parameters of each. This list is not exhaustive and other
surface mount devices can be used with the ISL12082 if their
specifications are very similar to the devices listed. The
crystal should have a required parallel load capacitance of
12.5pF and an equivalent series resistance of
