ISL1208IB8

® ISL1208 I2C® Real Time Clock/Calendar Data Sheet August 23, 2006 FN8085.5 Low Power RTC with Battery Backed SRAM The ISL1208 device is a low power real time clock with timing and crystal compensation, clock/calendar, power fail indicator, periodic or polled alarm, intelligent battery backup switching and battery-backed user SRAM. The oscillator uses an external, low-cost 32.768kHz crystal. The real time clock tracks time with separate registers for hours, minutes, and seconds. The device has calendar registers for date, month, year and day of the week. The calendar is accurate through 2099, with automatic leap year correction. Features • Real Time Clock/Calendar - Tracks Time in Hours, Minutes, and Seconds - Day of the Week, Day, Month, and Year • 15 Selectable Frequency Outputs • Single Alarm - Settable to the Second, Minute, Hour, Day of the Week, Day, or Month - Single Event or Pulse Interrupt Mode • Automatic Backup to Battery or Super Cap • Power Failure Detection • On-Chip Oscillator Compensation Ordering Information PART PART NUMBER MARKING ISL1208IU8 ISL1208IU8-TK ISL1208IU8Z (Note) AGS AGS ANW VDD RANGE TEMP. RANGE (°C) PACKAGE • 2 Bytes Battery-Backed User SRAM • I2C Interface - 400kHz Data Transfer Rate • 400nA Battery Supply Current • Same Pin Out as ST M41Txx and Maxim DS13xx Devices • Small Package Options - 8 Ld MSOP and SOIC Packages • Pb-Free Plus Anneal Available (RoHS Compliant) 2.7V to 5.5V -40 to +85 8 Ld MSOP 2.7V to 5.5V -40 to +85 8 Ld MSOP Tape & Reel 2.7V to 5.5V -40 to +85 8 Ld MSOP (Pb-free) 2.7V to 5.5V -40 to +85 8 Ld MSOP Tape & Reel (Pb-free) 2.7V to 5.5V -40 to +85 8 Ld SOIC 2.7V to 5.5V -40 to +85 8 Ld SOIC Tape & Reel 2.7V to 5.5V -40 to +85 8 Ld SOIC (Pb-free) 2.7V to 5.5V -40 to +85 8 Ld SOIC Tape & Reel (Pb-free) ISL1208IU8Z-TK ANW (Note) ISL1208IB8 ISL1208IB8-TK ISL1208IB8Z (Note) 1208I 1208I 1208ZI Applications • Utility Meters • HVAC Equipment • Audio/Video Components • Set Top Box/Television • Modems • Network Routers, Hubs, Switches, Bridges • Cellular Infrastructure Equipment • Fixed Broadband Wireless Equipment • Pagers/PDA • POS Equipment ISL1208IB8Z-TK 1208ZI (Note) NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. * Contact Factory for availability. Pinout ISL1208 (8 LD MSOP, SOIC) TOP VIEW X1 X2 VBAT GND 1 2 3 4 8 7 6 5 VDD IRQ/FOUT SCL SDA • Test Meters/Fixtures • Office Automation (Copiers, Fax) • Home Appliances • Computer Products • Other Industrial/Medical/Automotive 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2004-2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL1208 Block Diagram SDA SCL SDA BUFFER SCL BUFFER Seconds RTC CONTROL LOGIC Minutes Hours Day of Week X1 X2 VDD CRYSTAL OSCILLATOR RTC DIVIDER Date Month POR VTRIP SWITCH VBAT INTERNAL SUPPLY FREQUENCY OUT Year ALARM CONTROL REGISTERS USER SRAM IRQ/ FOUT I2C INTERFACE Pin Descriptions PIN NUMBER SYMBOL 1 2 3 4 5 6 7 8 X1 X2 VBAT GND SDA SCL DESCRIPTION The X1 pin is the input of an inverting amplifier and is intended to be connected to one pin of an external 32.768kHz quartz crystal. X1 can also be driven directly from a 32.768kHz source. The X2 pin is the output of an inverting amplifier and is intended to be connected to one pin of an external 32.768kHz quartz crystal. This input provides a backup supply voltage to the device. VBAT supplies power to the device in the event that the VDD supply fails. This pin should be tied to ground if not used. Ground. Serial Data (SDA) is a bidirectional pin used to transfer serial data into and out of the device. It has an open drain output and may be wire OR’ed with other open drain or open collector outputs. The Serial Clock (SCL) input is used to clock all serial data into and out of the device. IRQ/FOU Interrupt Output/Frequency Output is a multi-functional pin that can be used as interrupt or frequency output pin. The function is set via the configuration register. T VDD Power supply. 2 FN8085.5 August 23, 2006 ISL1208 Absolute Maximum Ratings Voltage on VDD, VBAT, SCL, SDA, and IRQ Pins (respect to ground) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7.0V Voltage on X1 and X2 Pins (respect to ground) . . . . . . . . . . . .-0.5V to VDD + 0.5 (VDD Mode) -0.5V to VBAT + 0.5 (VBAT Mode) Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Lead Temperature (Soldering, 10s) . . . . . . . . . . . . . . . . . . . . +300°C CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. DC Operating Characteristics – RTC Temperature = -40°C to +85°C, unless otherwise stated. SYMBOL VDD VBAT IDD1 PARAMETER Main Power Supply Battery Supply Voltage Supply Current VDD = 5V VDD = 3V IDD2 IDD3 IBAT ILI ILO VTRIP VTRIPHYS VBATHYS IRQ/FOUT VOL Output Low Voltage VDD = 5V IOL = 3mA VDD = 2.7V IOL = 1mA 0.4 0.4 V V Supply Current With I2C Active Supply Current (Low Power Mode) Battery Supply Current Input Leakage Current on SCL I/O Leakage Current on SDA VBAT Mode Threshold VTRIP Hysteresis VBAT Hysteresis 1.6 10 15 VDD = 5V VDD = 5V, LPMODE = 1 VBAT = 3V CONDITIONS MIN 2.7 1.8 2 1.2 40 1.4 400 100 100 2.2 30 50 2.6 75 100 TYP (Note 4) MAX 5.5 5.5 6 4 120 5 950 UNITS V V µA µA µA µA nA nA nA V mV mV 1, 2 1 1 1, 2 NOTES Power-Down Timing Temperature = -40°C to +85°C, unless otherwise stated. SYMBOL VDD SRPARAMETER VDD Negative Slewrate CONDITIONS MIN TYP (Note 4) MAX 10 UNITS V/ms NOTES 3 Serial Interface Specifications Over the recommended operating conditions unless otherwise specified. SYMBOL PARAMETER TEST CONDITIONS MIN TYP (Note 4) MAX UNITS NOTES SERIAL INTERFACE SPECS VIL VIH Hysteresis VOL SDA and SCL Input Buffer LOW Voltage SDA and SCL Input Buffer HIGH Voltage SDA and SCL Input Buffer Hysteresis SDA Output Buffer LOW Voltage, Sinking 3mA -0.3 0.7 x VDD 0.05 x VDD 0 0.4 0.3 x VDD VDD + 0.3 V V V V 3 FN8085.5 August 23, 2006 ISL1208 Serial Interface Specifications Over the recommended operating conditions unless otherwise specified. (Continued) SYMBOL Cpin fSCL tIN tAA PARAMETER SDA and SCL Pin Capacitance SCL Frequency Pulse width Suppression Time at SDA and SCL Inputs SCL Falling Edge to SDA Output Data Valid Any pulse narrower than the max spec is suppressed. SCL falling edge crossing 30% of VDD, until SDA exits the 30% to 70% of VDD window. 1300 TEST CONDITIONS TA = 25°C, f = 1MHz, VDD = 5V, VIN = 0V, VOUT = 0V MIN TYP (Note 4) MAX 10 400 50 900 UNITS pF kHz ns ns NOTES tBUF Time the Bus Must Be Free Before the SDA crossing 70% of VDD during a Start of a New Transmission STOP condition, to SDA crossing 70% of VDD during the following START condition. Clock LOW Time Clock HIGH Time START Condition Setup Time START Condition Hold Time Measured at the 30% of VDD crossing. Measured at the 70% of VDD crossing. SCL rising edge to SDA falling edge. Both crossing 70% of VDD. From SDA falling edge crossing 30% of VDD to SCL falling edge crossing 70% of VDD. From SDA exiting the 30% to 70% of VDD window, to SCL rising edge crossing 30% of VDD From SCL falling edge crossing 30% of VDD to SDA entering the 30% to 70% of VDD window. From SCL rising edge crossing 70% of VDD, to SDA rising edge crossing 30% of VDD. From SDA rising edge to SCL falling edge. Both crossing 70% of VDD. From SCL falling edge crossing 30% of VDD, until SDA enters the 30% to 70% of VDD window. From 30% to 70% of VDD From 70% to 30% of VDD Total on-chip and off-chip Maximum is determined by tR and tF. For Cb = 400pF, max is about 2~2.5kΩ. For Cb = 40pF, max is about 15~20kΩ ns tLOW tHIGH tSU:STA tHD:STA 1300 600 600 600 ns ns ns ns tSU:DAT Input Data Setup Time 100 ns tHD:DAT Input Data Hold Time 20 900 ns tSU:STO STOP Condition Setup Time 600 ns tHD:STO tDH STOP Condition Hold Time Output Data Hold Time 600 0 ns ns tR tF Cb Rpu SDA and SCL Rise Time SDA and SCL Fall Time Capacitive Loading of SDA or SCL SDA and SCL Bus Pull-Up Resistor Off-Chip 20 + 0.1 x Cb 20 + 0.1 x Cb 10 1 300 300 400 ns ns pF kΩ NOTES: 1. IRQ & FOUT Inactive. 2. LPMODE = 0 (default). 3. In order to ensure proper timekeeping, the VDD SR- specification must be followed. 4. Typical values are for T = 25°C and 3.3V supply voltage. 4 FN8085.5 August 23, 2006 ISL1208 SDA vs SCL Timing tF tHIGH tLOW tR SCL tSU:STA tHD:STA SDA (INPUT TIMING) tSU:DAT tHD:DAT tSU:STO tAA SDA (OUTPUT TIMING) tDH tBUF Symbol Table WAVEFORM INPUTS Must be steady OUTPUTS Will be steady May change from LOW to HIGH May change from HIGH to LOW Don’t Care: Changes Allowed N/A Will change from LOW to HIGH Will change from HIGH to LOW Changing: State Not Known Center Line is High Impedance 5 FN8085.5 August 23, 2006 ISL1208 Typical Performance Curves 1E-6 900E-9 800E-9 700E-9 IBAT (A) IBAT(A) 1.5 2.0 2.5 3.0 3.5 4.0 VBAT (V) 4.5 5.0 5.5 600E-9 500E-9 400E-9 300E-9 200E-9 100E-9 000E+0 000E+0 -40 -20 0 20 40 TEMPERATURE (°C) 60 80 200E-9 600E-9 800E-9 Temperature is 25°C unless otherwise specified 1E-6 400E-9 FIGURE 1. IBAT vs VBAT FIGURE 2. IBAT vs TEMPERATURE AT VBAT = 3V 2.4E-06 2.2E-06 VCC = 5V 2.0E-06 IDD1 (A) 1.8E-06 1.6E-06 VCC = 3.3V 1.4E-06 1.2E-06 1.0E-06 -40 -20 0 20 40 60 80 IDD1 (A) 2.4E-6 2.2E-6 2.0E-6 1.8E-6 1.6E-6 1.4E-6 1.2E-6 1.0E-6 800.0E-9 600.0E-9 400.0E-9 2.5 3.0 3.5 4.0 VCC (V) 4.5 5.0 5.5 LPMODE = 1 LPMODE = 0 TEMPERATURE (°C) FIGURE 3. IDD1 vs TEMPERATURE FIGURE 4. IDD1 vs VCC WITH LPMODE ON & OFF 2.1E-6 2.0E-6 1.9E-6 IDD1 (A) 1.8E-6 1.7E-6 1.6E-6 1.5E-6 1.4E-6 1.3E-6 1/4 1/2 1 1/32 1/16 1/8 2 4 8 16 32 64 1024 4096 32768 1.2E-6 IDD1 (A) 1/32 1/16 1/4 1/2 1 1/8 2 4 8 16 32 64 1024 4096 FOUT (Hz) FOUT (Hz) FIGURE 5. IDD1 vs FOUT AT VDD = 3.3V FIGURE 6. IDD1 vs FOUT AT VDD = 5V 6 FN8085.5 August 23, 2006 32768 3.0E-6 2.9E-6 2.8E-6 2.7E-6 2.6E-6 2.5E-6 2.4E-6 2.3E-6 2.2E-6 2.1E-6 2.0E-6 1.9E-6 1.8E-6 ISL1208 EQUIVALENT AC OUTPUT LOAD CIRCUIT FOR VDD = 5V 5.0V 1533Ω SDA AND IRQ/FOUT 100pF FOR VOL= 0.4V AND IOL = 3mA X1 X2 FIGURE 8. RECOMMENDED CRYSTAL CONNECTION VBAT FIGURE 7. STANDARD OUTPUT LOAD FOR TESTING THE DEVICE WITH VDD = 5.0V General Description The ISL1208 device is a low power real time clock with timing and crystal compensation, clock/calendar, power fail indicator, periodic or polled alarm, intelligent battery backup switching, and battery-backed user SRAM. The oscillator uses an external, low-cost 32.768kHz crystal. The real time clock tracks time with separate registers for hours, minutes, and seconds. The device has calendar registers for date, month, year and day of the week. The calendar is accurate through 2099, with automatic leap year correction. The ISL1208's powerful alarm can be set to any clock/calendar value for a match. For example, every minute, every Tuesday or at 5:23 AM on March 21. The alarm status is available by checking the Status Register, or the device can be configured to provide a hardware interrupt via the IRQ pin. There is a repeat mode for the alarm allowing a periodic interrupt every minute, every hour, every day, etc. The device also offers a backup power input pin. This VBAT pin allows the device to be backed up by battery or SuperCap with automatic switchover from VDD to VBAT. The entire ISL1208 device is fully operational from 2.0V to 5.5V and the clock/calendar portion of the device remains fully operational down to 1.8V (Standby Mode). This input provides a backup supply voltage to the device. VBAT supplies power to the device in the event that the VDD supply fails. This pin can be connected to a battery, a Super Cap or tied to ground if not used. IRQ/FOUT (Interrupt Output/Frequency Output) This dual function pin can be used as an interrupt or frequency output pin. The IRQ/FOUT mode is selected via the frequency out control bits of the control/status register. • Interrupt Mode. The pin provides an interrupt signal output. This signal notifies a host processor that an alarm has occurred and requests action. It is an open drain active low output. • Frequency Output Mode. The pin outputs a clock signal which is related to the crystal frequency. The frequency output is user selectable and enabled via the I2C bus. It is an open drain active low output. Serial Clock (SCL) The SCL input is used to clock all serial data into and out of the device. The input buffer on this pin is always active (not gated). It is disabled when the backup power supply on the VBAT pin is activated to minimize power consumption. Serial Data (SDA) SDA is a bidirectional pin used to transfer data into and out of the device. It has an open drain output and may be ORed with other open drain or open collector outputs. The input buffer is always active (not gated) in normal mode. An open drain output requires the use of a pull-up resistor. The output circuitry controls the fall time of the output signal with the use of a slope controlled pull-down. The circuit is designed for 400kHz I2C interface speeds. It is disabled when the backup power supply on the VBAT pin is activated. Pin Description X1, X2 The X1 and X2 pins are the input and output, respectively, of an inverting amplifier. An external 32.768kHz quartz crystal is used with the ISL1208 to supply a timebase for the real time clock. Internal compensation circuitry provides high accuracy over the operating temperature range from -40°C to +85°C. This oscillator compensation network can be used to calibrate the crystal timing accuracy over temperature either during manufacturing or with an external temperature sensor and microcontroller for active compensation. The device can also be driven directly from a 32.768kHz source at pin X1. VDD, GND Chip power supply and ground pins. The device will operate with a power supply from 2.0V to 5.5VDC. A 0.1µF capacitor is recommended on the VDD pin to ground. Functional Description Power Control Operation The power control circuit accepts a VDD and a VBAT input. Many types of batteries can be used with Intersil RTC products. For example, 3.0V or 3.6V Lithium batteries are appropriate, and battery sizes are available that can power 7 FN8085.5 August 23, 2006 ISL1208 the ISL1208 for up to 10 years. Another option is to use a Super Cap for applications where VDD is interrupted for up to a month. See the Applications Section for more information. The I2C bus is deactivated in battery backup mode to provide lower power. Aside from this, all RTC functions are operational during battery backup mode. Except for SCL and SDA, all the inputs and outputs of the ISL1208 are active during battery backup mode unless disabled via the control register. The User SRAM is operational in battery backup mode down to 2V. Normal Mode (VDD) to Battery Backup Mode (VBAT) To transition from the VDD to VBAT mode, both of the following conditions must be met: Condition 1: VDD < VBAT - VBATHYS where VBATHYS ≈ 50mV Condition 2: VDD < VTRIP where VTRIP ≈ 2.2V Power Failure Detection The ISL1208 provides a Real Time Clock Failure Bit (RTCF) to detect total power failure. It allows users to determine if the device has powered up after having lost all power to the device (both VDD and VBAT). Low Power Mode The normal power switching of the ISL1208 is designed to switch into battery backup mode only if the VDD power is lost. This will ensure that the device can accept a wide range of backup voltages from many types of sources while reliably switching into backup mode. Another mode, called Low Power Mode, is available to allow direct switching from VDD to VBAT without requiring VDD to drop below VTRIP. Since the additional monitoring of VDD vs VTRIP is no longer needed, that circuitry is shut down and less power is used while operating from VDD. Power savings are typically 600nA at VDD = 5V. Low Power Mode is activated via the LPMODE bit in the control and status registers. Low Power Mode is useful in systems where VDD is normally higher than VBAT at all times. The device will switch from VDD to VBAT when VDD drops below VBAT, with about 50mV of hysteresis to prevent any switchback of VDD after switchover. In a system with a VDD = 5V and backup lithium battery of VBAT = 3V, Low Power Mode can be used. However, it is not recommended to use Low Power Mode in a system with VDD = 3.3V ±10%, VBAT ≥ 3.0V, and when there is a finite I-R voltage drop in the VDD line. Battery Backup Mode (VBAT) to Normal Mode (VDD) The ISL1208 device will switch from the VBAT to VDD mode when one of the following conditions occurs: Condition 1: VDD > VBAT + VBATHYS where VBATHYS ≈ 50mV Condition 2: VDD > VTRIP + VTRIPHYS where VTRIPHYS ≈ 30mV These power control situations are illustrated in Figures 9 and 10. VDD VTRIP VBAT VBAT - VBATHYS BATTERY BACKUP MODE 2.2V 1.8V InterSeal™ Battery Saver VBAT + VBATHYS FIGURE 9. BATTERY SWITCHOVER WHEN VBAT < VTRIP VDD VBAT VTRIP VTRIP BATTERY BACKUP MODE The ISL1208 has the InterSeal™ Battery Saver which prevents initial battery current drain before it is first used. For example, battery-backed RTCs are commonly packaged on a board with a battery connected. In order to preserve battery life, the ISL1208 will not draw any power from the battery source until after the device is first powered up from the VDD source. Thereafter, the device will switchover to battery backup mode whenever VDD power is lost. Real Time Clock Operation 3.0V 2.2V VTRIP + VTRIPHYS FIGURE 10. BATTERY SWITCHOVER WHEN VBAT > VTRIP The Real Time Clock (RTC) uses an external 32.768kHz quartz crystal to maintain an accurate internal representation of second, minute, hour, day of week, date, month, and year. The RTC also has leap-year correction. The clock also corrects for months having fewer than 31 days and has a bit that controls 24 hour or AM/PM format. When the ISL1208 powers up after the loss of both VDD and VBAT, the clock will 8 FN8085.5 August 23, 2006 ISL1208 not begin incrementing until at least one byte is written to the clock register. I2C Serial Interface The ISL1208 has an I2C serial bus interface that provides access to the control and status registers and the user SRAM. The I2C serial interface is compatible with other industry I2C serial bus protocols using a bidirectional data signal (SDA) and a clock signal (SCL). Accuracy of the Real Time Clock The accuracy of the Real Time Clock depends on the frequency of the quartz crystal that is used as the time base for the RTC. Since the resonant frequency of a crystal is temperature dependent, the RTC performance will also be dependent upon temperature. The frequency deviation of the crystal is a function of the turnover temperature of the crystal from the crystal’s nominal frequency. For example, a ~20ppm frequency deviation translates into an accuracy of ~1 minute per month. These parameters are available from the crystal manufacturer. The ISL1208 provides on-chip crystal compensation networks to adjust load capacitance to tune oscillator frequency from -94ppm to +140ppm. For more detailed information see the Application Section. Oscillator Compensation The ISL1208 provides the option of timing correction due to temperature variation of the crystal oscillator for either manufacturing calibration or active calibration. The total possible compensation is typically -94ppm to +140ppm. Two compensation mechanisms that are available are as follows: 1. An analog trimming (ATR) register that can be used to adjust individual on-chip digital capacitors for oscillator capacitance trimming. The individual digital capacitor is selectable from a range of 9pF to 40.5pF (based upon 32.758kHz). This translates to a calculated compensation of approximately -34ppm to +80ppm. (See ATR description.) 2. A digital trimming register (DTR) that can be used to adjust the timing counter by ±60ppm. (See DTR description.) Also provided is the ability to adjust the crystal capacitance when the ISL1208 switches from VDD to battery backup mode. (See Battery Mode ATR Selection for more details.) Single Event and Interrupt The alarm mode is enabled via the ALME bit. Choosing single event or interrupt alarm mode is selected via the IM bit. Note that when the frequency output function is enabled, the alarm function is disabled. The standard alarm allows for alarms of time, date, day of the week, month, and year. When a time alarm occurs in single event mode, an IRQ pin will be pulled low and the alarm status bit (ALM) will be set to “1”. The pulsed interrupt mode allows for repetitive or recurring alarm functionality. Hence, once the alarm is set, the device will continue to alarm for each occurring match of the alarm and present time. Thus, it will alarm as often as every minute (if only the nth second is set) or as infrequently as once a year (if at least the nth month is set). During pulsed interrupt mode, the IRQ pin will be pulled low for 250ms and the alarm status bit (ALM) will be set to “1”. NOTE: The ALM bit can be reset by the user or cleared automatically using the auto reset mode (see ARST bit). Register Descriptions The battery-backed registers are accessible following a slave byte of “1101111x” and reads or writes to addresses [00h:13h]. The defined addresses and default values are described in the Table 1. Address 09h is not used. Reads or writes to 09h will not affect operation of the device but should be avoided. REGISTER ACCESS The contents of the registers can be modified by performing a byte or a page write operation directly to any register address. The registers are divided into 4 sections. These are: 1. Real Time Clock (7 bytes): Address 00h to 06h. 2. Control and Status (5 bytes): Address 07h to 0Bh. 3. Alarm (6 bytes): Address 0Ch to 11h. 4. User SRAM (2 bytes): Address 12h to 13h. There are no addresses above 13h. The alarm function can be enabled/disabled during battery backup mode using the FOBATB bit. For more information on the alarm, please see the Alarm Registers Description. Frequency Output Mode The ISL1208 has the option to provide a frequency output signal using the IRQ/FOUT pin. The frequency output mode is set by using the FO bits to select 15 possible output frequency values from 0 to 32kHz. The frequency output can be enabled/disabled during battery backup mode using the FOBATB bit. General Purpose User SRAM The ISL1208 provides 2 bytes of user SRAM. The SRAM will continue to operate in battery backup mode. However, it should be noted that the I2C bus is disabled in battery backup mode. 9 FN8085.5 August 23, 2006 ISL1208 Write capability is allowable into the RTC registers (00h to 06h) only when the WRTC bit (bit 4 of address 07h) is set to “1”. A multi-byte read or write operation is limited to one section per operation. Access to another section requires a new operation. A read or write can begin at any address within the section. A register can be read by performing a random read at any address at any time. This returns the contents of that register location. Additional registers are read by performing a sequential read. For the RTC and Alarm registers, the read instruction latches all clock registers into a buffer, so an update of the clock does not change the time being read. A sequential read will not result in the output of data from the memory array. At the end of a read, the master supplies a stop condition to end the operation and free the bus. After a read, the address remains at the previous address +1 so the user can execute a current address read and continue reading the next register. It is not necessary to set the WRTC bit prior to writing into the control and status, alarm, and user SRAM registers. TABLE 1. REGISTER MEMORY MAP REG ADDR. SECTION NAME 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh Alarm 0Fh 10h 11h 12h User 13h USR2 USR27 USR26 USR25 USR24 USR23 USR22 USR21 USR20 N/A 00h DTA MOA DWA USR1 EDTA EMOA EDWA USR17 0 0 0 USR16 ADT21 0 0 USR15 ADT20 AMO20 0 USR14 ADT13 AMO13 0 USR13 ADT12 AMO12 ADW12 USR12 ADT11 AMO11 ADW11 USR11 ADT10 AMO10 ADW10 USR10 1-31 1-12 0-6 N/A 00h 00h 00h 00h Control and Status RTC SC MN HR DT MO YR DW SR INT BIT 7 0 0 MIL 0 0 YR23 0 ARST IM 6 SC22 MN22 0 0 0 YR22 0 5 SC21 MN21 HR21 DT21 0 YR21 0 4 SC20 MN20 HR20 DT20 MO20 YR20 0 WRTC FOBATB Reserved ATR DTR SCA MNA HRA BMATR1 Reserved ESCA EMNA EHRA ASC22 AMN22 0 ASC21 AMN21 AHR21 ASC20 AMN20 AHR20 ASC13 AMN13 AHR13 BMATR0 ATR5 ATR4 ATR3 ATR2 DTR2 ASC12 AMN12 AHR12 ATR1 DTR1 ASC11 AMN11 AHR11 ATR0 DTR0 ASC10 AMN10 AHR10 3 SC13 MN13 HR13 DT13 MO13 YR13 0 Reserved FO3 2 SC12 MN12 HR12 DT12 MO12 YR12 DW2 ALM FO2 1 SC11 MN11 HR11 DT11 MO11 YR11 DW1 BAT FO1 0 SC10 MN10 HR10 DT10 MO10 YR10 DW0 RTCF FO0 RANGE 0-59 0-59 0-23 1-31 1-12 0-99 0-6 N/A N/A N/A N/A N/A 00-59 00-59 0-23 DEFAULT 00h 00h 00h 00h 00h 00h 00h 01h 00h 00h 00h 00h 00h 00h 00h XTOSCB Reserved ALME LPMODE 10 FN8085.5 August 23, 2006 ISL1208 Real Time Clock Registers Addresses [00h to 06h] RTC REGISTERS (SC, MN, HR, DT, MO, YR, DW) These registers depict BCD representations of the time. As such, SC (Seconds) and MN (Minutes) range from 0 to 59, HR (Hour) can either be a 12-hour or 24-hour mode, DT (Date) is 1 to 31, MO (Month) is 1 to 12, YR (Year) is 0 to 99, and DW (Day of the Week) is 0 to 6. The DW register provides a Day of the Week status and uses three bits DW2 to DW0 to represent the seven days of the week. The counter advances in the cycle 0-1-2-3-4-5-6-0-12-… The assignment of a numerical value to a specific day of the week is arbitrary and may be decided by the system software designer. The default value is defined as “0”. 24 HOUR TIME If the MIL bit of the HR register is “1”, the RTC uses a 24hour format. If the MIL bit is “0”, the RTC uses a 12-hour format and HR21 bit functions as an AM/PM indicator with a “1” representing PM. The clock defaults to 12-hour format time with HR21 = “0”. LEAP YEARS Leap years add the day February 29 and are defined as those years that are divisible by 4. Years divisible by 100 are not leap years, unless they are also divisible by 400. This means that the year 2000 is a leap year, the year 2100 is not. The ISL1208 does not correct for the leap year in the year 2100. REAL TIME CLOCK FAIL BIT (RTCF) This bit is set to a “1” after a total power failure. This is a read only bit that is set by hardware (ISL1208 internally) when the device powers up after having lost all power to the device (both VDD and VBAT go to 0V). The bit is set regardless of whether VDD or VBAT is applied first. The loss of only one of the supplies does not set the RTCF bit to “1”. On power-up after a total power failure, all registers are set to their default states and the clock will not increment until at least one byte is written to the clock register. The first valid write to the RTC section after a complete power failure resets the RTCF bit to “0” (writing one byte is sufficient). BATTERY BIT (BAT) This bit is set to a “1” when the device enters battery backup mode. This bit can be reset either manually by the user or automatically reset by enabling the auto-reset bit (see ARST bit). A write to this bit in the SR can only set it to “0”, not “1”. ALARM BIT (ALM) These bits announce if the alarm matches the real time clock. If there is a match, the respective bit is set to “1”. This bit can be manually reset to “0” by the user or automatically reset by enabling the auto-reset bit (see ARST bit). A write to this bit in the SR can only set it to “0”, not “1”. NOTE: An alarm bit that is set by an alarm occurring during an SR read operation will remain set after the read operation is complete. WRITE RTC ENABLE BIT (WRTC) The WRTC bit enables or disables write capability into the RTC Timing Registers. The factory default setting of this bit is “0”. Upon initialization or power-up, the WRTC must be set to “1” to enable the RTC. Upon the completion of a valid write (STOP), the RTC starts counting. The RTC internal 1Hz signal is synchronized to the STOP condition during a valid write cycle. CRYSTAL OSCILLATOR ENABLE BIT (XTOSCB) This bit enables/disables the internal crystal oscillator. When the XTOSCB is set to “1”, the oscillator is disabled, and the X1 pin allows for an external 32kHz signal to drive the RTC. The XTOSCB bit is set to “0” on powerup. AUTO RESET ENABLE BIT (ARST) This bit enables/disables the automatic reset of the BAT and ALM status bits only. When ARST bit is set to “1”, these status bits are reset to “0” after a valid read of the respective status register (with a valid STOP condition). When the ARST is cleared to “0”, the user must manually reset the BAT and ALM bits. Control and Status Registers Addresses [07h to 0Bh] The Control and Status Registers consist of the Status Register, Interrupt and Alarm Register, Analog Trimming and Digital Trimming Registers. Status Register (SR) The Status Register is located in the memory map at address 07h. This is a volatile register that provides either control or status of RTC failure, battery mode, alarm trigger, write protection of clock counter, crystal oscillator enable and auto reset of status bits. TABLE 2. STATUS REGISTER (SR) ADDR 07h Default 7 6 5 4 3 2 1 0 ARST XTOSCB reserved WRTC reserved ALM BAT RTCF 0 0 0 0 0 0 0 0 Interrupt Control Register (INT) TABLE 3. INTERRUPT CONTROL REGISTER (INT) ADDR 08h Default 7 IM 0 6 5 4 3 2 1 0 ALME LPMODE FOBATB FO3 FO2 FO1 FO0 0 0 0 0 0 0 0 11 FN8085.5 August 23, 2006 ISL1208 FREQUENCY OUT CONTROL BITS (FO ) These bits enable/disable the frequency output function and select the output frequency at the IRQ/FOUT pin. See Table 4 for frequency selection. When the frequency mode is enabled, it will override the alarm mode at the IRQ/FOUT pin. TABLE 4. FREQUENCY SELECTION OF FOUT PIN FREQUENCY, FOUT UNITS 0 32768 4096 1024 64 32 16 8 4 2 1 1/2 1/4 1/8 1/16 1/32 Hz Hz Hz Hz Hz Hz Hz Hz Hz Hz Hz Hz Hz Hz Hz Hz FO3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 FO2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 FO1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 FO0 0 1 0 1 0 IM BIT 1 0 0 1 1 0 1 0 1 0 1 0 1 Repetitive/Recurring Time Event Set By Alarm Single Time Event Set By Alarm INTERRUPT/ALARM FREQUENCY is cleared to “0”, the alarm function is disabled. The alarm function can operate in either a single event alarm or a periodic interrupt alarm (see IM bit). NOTE: When the frequency output mode is enabled, the alarm function is disabled. INTERRUPT/ALARM MODE BIT (IM) This bit enables/disables the interrupt mode of the alarm function. When the IM bit is set to “1”, the alarm will operate in the interrupt mode, where an active low pulse width of 250ms will appear at the IRQ/FOUT pin when the RTC is triggered by the alarm as defined by the alarm registers (0Ch to 11h). When the IM bit is cleared to “0”, the alarm will operate in standard mode, where the IRQ/FOUT pin will be tied low until the ALM status bit is cleared to “0”. Analog Trimming Register ANALOG TRIMMING REGISTER (ATR) X1 CX1 X2 Crystal Oscillator FREQUENCY OUTPUT AND INTERRUPT BIT (FOBATB) This bit enables/disables the FOUT/IRQ pin during battery backup mode (i.e. VBAT power source active). When the FOBATB is set to “1” the FOUT/IRQ pin is disabled during battery backup mode. This means that both the frequency output and alarm output functions are disabled. When the FOBATB is cleared to “0”, the FOUT/IRQ pin is enabled during battery backup mode. LOW POWER MODE BIT (LPMODE) This bit enables/disables low power mode. With LPMODE = “0”, the device will be in normal mode and the VBAT supply will be used when VDD < VBAT - VBATHYS and VDD < VTRIP. With LPMODE = “1”, the device will be in low power mode and the VBAT supply will be used when VDD < VBAT - VBATHYS. There is a supply current saving of about 600nA when using LPMODE = “1” with VDD = 5V. (See Typical Performance Curves: IDD vs VCC with LPMODE ON & OFF.) ALARM ENABLE BIT (ALME) This bit enables/disables the alarm function. When the ALME bit is set to “1”, the alarm function is enabled. When the ALME CX2 FIGURE 11. DIAGRAM OF ATR Six analog trimming bits, ATR0 to ATR5, are provided in order to adjust the on-chip load capacitance value for frequency compensation of the RTC. Each bit has a different weight for capacitance adjustment. For example, using a Citizen CFS-206 crystal with different ATR bit combinations provides an estimated ppm adjustment range from -34 to +80ppm to the nominal frequency compensation. The combination of analog and digital trimming can give up to -94 to +140ppm of total adjustment. The effective on-chip series load capacitance, CLOAD, ranges from 4.5pF to 20.25pF with a mid-scale value of 12.5pF (default). CLOAD is changed via two digitally controlled capacitors, CX1 and CX2, connected from the X1 12 FN8085.5 August 23, 2006 ISL1208 and X2 pins to ground (see Figure 11). The value of CX1 and CX2 is given by the following formula: C X = ( 16 ⋅ b5 + 8 ⋅ b4 + 4 ⋅ b3 + 2 ⋅ b2 + 1 ⋅ b1 + 0.5 ⋅ b0 + 9 ) pF TABLE 5. DIGITAL TRIMMING REGISTERS DTR REGISTER DTR2 0 0 0 0 1 1 1 1 DTR1 0 0 1 1 0 0 1 1 DTR0 0 1 0 1 0 1 0 1 ESTIMATED FREQUENCY PPM 0 (default) +20 +40 +60 0 -20 -40 -60 The effective series load capacitance is the combination of CX1 and CX2: 1 C = ---------------------------------LOAD 1 1 ⎛ ---------- + ---------- ⎞ ⎝C ⎠ X1 C X2 C LOAD 16 ⋅ b5 + 8 ⋅ b4 + 4 ⋅ b3 + 2 ⋅ b2 + 1 ⋅ b1 + 0.5 ⋅ b0 + 9 = ⎛ ---------------------------------------------------------------------------------------------------------------------------- ⎞ pF ⎝ 2 ⎠ For example, CLOAD(ATR=00000) = 12.5pF, CLOAD(ATR=100000) = 4.5pF, and CLOAD(ATR=011111) = 20.25pF. The entire range for the series combination of load capacitance goes from 4.5pF to 20.25pF in 0.25pF steps. Note that these are typical values. BATTERY MODE ATR SELECTION (BMATR ) Since the accuracy of the crystal oscillator is dependent on the VDD/VBAT operation, the ISL1208 provides the capability to adjust the capacitance between VDD and VBAT when the device switches between power sources. DELTA CAPACITANCE (CBAT TO CVDD) 0pF -0.5pF (≈ +2ppm) +0.5pF (≈ -2ppm) +1pF (≈ -4ppm) Alarm Registers Addresses [0Ch to 11h] The alarm register bytes are set up identical to the RTC register bytes, except that the MSB of each byte functions as an enable bit (enable = “1”). These enable bits specify which alarm registers (seconds, minutes, etc) are used to make the comparison. Note that there is no alarm byte for year. The alarm function works as a comparison between the alarm registers and the RTC registers. As the RTC advances, the alarm will be triggered once a match occurs between the alarm registers and the RTC registers. Any one alarm register, multiple registers, or all registers can be enabled for a match. There are two alarm operation modes: Single Event and periodic Interrupt Mode: • Single Event Mode is enabled by setting the ALME bit to “1”, the IM bit to “0”, and disabling the frequency output. This mode permits a one-time match between the alarm registers and the RTC registers. Once this match occurs, the ALM bit is set to “1” and the IRQ output will be pulled low and will remain low until the ALM bit is reset. This can be done manually or by using the auto-reset feature. • Interrupt Mode is enabled by setting the ALME bit to “1”, the IM bit to “1”, and disabling the frequency output. The IRQ output will now be pulsed each time an alarm occurs. This means that once the interrupt mode alarm is set, it will continue to alarm for each occurring match of the alarm and present time. This mode is convenient for hourly or daily hardware interrupts in microcontroller applications such as security cameras or utility meter reading. To clear an alarm, the ALM bit in the status register must be set to “0” with a write. Note that if the ARST bit is set to 1 (address 07h, bit 7), the ALM bit will automatically be cleared when the status register is read. BMATR1 0 0 1 1 BMATR0 0 1 0 1 DIGITAL TRIMMING REGISTER (DTR ) The digital trimming bits DTR0, DTR1, and DTR2 adjust the average number of counts per second and average the ppm error to achieve better accuracy. • DTR2 is a sign bit. DTR2 = “0” means frequency compensation is >0. DTR2 = “1” means frequency compensation is