ISL14017

® ISL14010, ISL14017 Data Sheet April 16, 2007 FN6407.1 Low Jitter Clock Generators for Set-Top Box The ISL14010 series of devices are general purpose integrated Clock Synthesizers and Generators suited for consumer applications such as Set-top Box, and various other consumer applications. The selectable reference input accepts 30MHz signal either from crystal or an external source. It is specified to operate with a nominal 3.3V supply and is offered in 16 Ld QFN package. Contact Factory for other output frequency options. Features • LVTTL Outputs • Selectable Crystal or Ref. Clock for Inputs • Period Jitter ~50ps RMS • Single Supply; 3.3V nominal • Extended Temperature Range: -40ºC to +85ºC • Available in small foot print package - 16 Ld QFN 3mmx3mm • Pb-Free plus anneal available (RoHS Compliant) Ordering Information PART NUMBER ISL14010IRZ* ISL14017IRZ* PART MARKING 10IZ 17IZ TEMP. RANGE (°C) -40 to +85 -40 to +85 PACKAGE 16 LD QFN 16 LD QFN PKG. DWG. # L16.3x3 L16.3x3 Applications • Set-Top Boxes Pinout ISL14010, ISL14017 (16 LD QFN) TOP VIEW CLK4 13 12 NC 11 CLK3 10 CLK2 9 5 GND 6 NC 7 GND 8 CLK1 NC VCC VCC 14 NC 15 *Add "-T" suffix for tape and reel. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 16 VCC 1 X1 2 Selection Table PART INPUT NUMBER OF OUTPUT OPTIONS FREQUENCY OUTPUTS FREQUENCY PACKAGE ISL14010 ISL14017 30MHz 30MHz 4 LVTTL 4 LVTTL 25, 30, 48, 54 16 LD QFN 25, 30, 40, 50 16 LD QFN X2 3 GND 4 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2006, 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL14010, ISL14017 Functional Block Diagram CLK1 OSC. 30MHz CRYSTAL N1 CLK3 M2 PHASE FREQ DET. VCO2 CLK4 M1 PHASE FREQ DET. VCO1 CLK2 N2 Pin Description 16 LD QFN 1,14,16 2 3 4, 5, 7 8 10 11 13 6, 9, 12, 15 SYMBOLS VCC X1 X2 GND CLK1 CLK2 CLK3 CLK4 NC Supply Voltage The X1 pin is the terminal 1 of an external 30MHz crystal. This pin is grounded for external CK input. The X2 pin is the terminal 2 of external 30MHz crystal, or external clock input. Ground CLK1 Output: 25MHz CLK2 Output: 30MHz CLK3 Output: 48MHz (40MHz for ISL14017) CLK4 Output: 54MHz (50MHz for ISL14017) No Connect PIN DESCRIPTION 2 FN6407.1 April 16, 2007 ISL14010, ISL14017 Absolute Maximum Ratings Voltage on VCC, CLK pins (respect to Gnd) . . . . . . . . -0.3V to 4.0V Voltage on X1, X2 pins (respect to Gnd) . . . . . . . . . . . -0.3V to 2.5V ESD Rating MIL STD-883, Method 3014 . . . . . . . . . . . . . . . . . . . . . . . . .>±5kV Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>500V Thermal Information Thermal Resistance (Typical, Note 1) θJA (°C/W) θJC (°C/W) 16 Ld QFN Package. . . . . . . . . . . . . . . 58 11 Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . -65ºC to +150ºC Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. DC Electrical Specifications SYMBOL Supply Voltage Supply Current VCC = 3.3V ±10%, TA = -40ºC to +85ºC, Typical values are at TA = +25ºC and VCC = 3.3V, Unless otherwise noted SYMBOL VCC ICC CONDITIONS Supply Voltage Supply Current CL = 5pF on all outputs MIN 3.0 TYP 3.3 11 MAX 3.6 15 UNIT V mA CLOCK INPUT X2 (X1 GROUNDED) FOR EXTERNAL CLOCK MODE Input High Level Input Level Low Input Current CLOCK OUTPUTS (CLK) Output High Level VOH IOH = -100µA IOH = -4mA IOH = -6mA Output Low Level VOL IOL = 100µA IOL = 4mA IOL = 6mA Output Short Circuit Current IOSC CLK = VCC or Gnd 6 13 VCC - 0.2 2.4 2.1 0.2 0.4 0.75 30 V V V V V V mA VIH VIL IIL, IIH VX2 to Ground 0.5 1.5 2.4 0.5 V V mA AC Electrical Specifications SYMBOL Crystal Frequency CLOCK OUTPUTS Rise Time Fall Time Duty Cycle Period Jitter Power Up Time CL = 5pF on all outputs SYMBOL fIN CONDITIONS MIN TYP 30 MAX UNIT MHz tR tF 20% to 80% VCC 80% to 20% VCC 40 1.8 1.8 60 50 2 ns ns % ps ms JP tPO RMS VCC >2.7V 3 FN6407.1 April 16, 2007 ISL14010, ISL14017 Typical Performance Curves (Period Jitter) 70 65 PERIOD JITTER SIGMA (ps) 60 55 50 45 40 35 30 25 20 0 2 4 6 8 10 12 14 CK3 CK4 VSUPPLY = 3.3V TEMPERATURE +23ºC CK1 CK2 LOAD CAPACITANCE (pF) FIGURE 1. STANDARD DEVIATION vs LOAD CAPACITANCE All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 4 FN6407.1 April 16, 2007 ISL14010, ISL14017 Package Outline Drawing L16.3x3 16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 2, 4/07 4X 1.5 3.00 A B 6 PIN 1 INDEX AREA 13 12X 0.50 16 6 PIN #1 INDEX AREA 12 1 3.00 1 .50 ± 0 . 15 9 4 (4X) 0.15 8 5 0.10 M C A B + 0.07 4 16X 0.23 - 0.05 16X 0.40 ± 0.10 TOP VIEW BOTTOM VIEW SEE DETAIL "X" 0.10 C 0 . 90 ± 0.1 BASE PLANE ( 2. 80 TYP ) C SEATING PLANE 0.08 C 1. 50 ) ( 12X 0 . 5 ) ( SIDE VIEW ( 16X 0 . 23 ) C ( 16X 0 . 60) 0 . 2 REF 5 0 . 00 MIN. 0 . 05 MAX. TYPICAL RECOMMENDED LAND PATTERN DETAIL "X" NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal ± 0.05 4. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 indentifier may be either a mold or mark feature. 5 FN6407.1 April 16, 2007