ISL22346_09

® ISL22346 Quad Digitally Controlled Potentiometers (XDCP™) Data Sheet September 3, 2009 FN6177.2 Low Noise, Low Power I2C™ Bus, 128 Taps The ISL22346 integrates four digitally controlled potentiometers (DCP) and non-volatile memory on a monolithic CMOS integrated circuit. The digitally controlled potentiometers are implemented with a combination of resistor elements and CMOS switches. The position of the wipers are controlled by the user through the I2C bus interface. Each potentiometer has an associated volatile Wiper Register (WR) and a non-volatile Initial Value Register (IVR) that can be directly written to and read by the user. The contents of the WR controls the position of the wiper. At power-up the device recalls the contents of the two DCP’s IVR to the corresponding WRs. The DCPs can be used as a three-terminal potentiometers or as a two-terminal variable resistors in a wide variety of applications including control, parameter adjustments, and signal processing. Features • Four potentiometers in one package • 128 resistor taps • I2C serial interface - Three address pins, up to eight devices/bus • Non-volatile storage of wiper position • Wiper resistance: 70Ω typical @ VCC = 3.3V • Shutdown mode • Shutdown current 5µA max • Power supply: 2.7V to 5.5V • 50kΩ or 10kΩ total resistance • High reliability - Endurance: 1,000,000 data changes per bit per register - Register data retention: 50 years @ T < +55°C • 20 Ld TSSOP or 20 Ld TQFN package • Pb-free (RoHS compliant) Pinouts ISL22346 (20 LD TSSOP) TOP VIEW RH3 RL3 RW3 A2 SCL SDA GND RW2 RL2 RH2 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 RW0 RL0 RH0 SHDN VCC A1 A0 RH1 RL1 RW1 RL0 RW0 RH3 RL3 RW3 1 2 3 4 5 6 A2 7 SCL 8 SDA 9 GND 10 RW2 15 RH1 14 RL1 13 RW1 12 RH2 11 RL2 O ISL22346 (20 LD TQFN) TOP VIEW SHDN VCC RH0 A1 A0 20 19 18 17 16 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) and XDCP are registered trademarks of Intersil Americas Inc. Copyright Intersil Americas Inc. 2006, 2008, 2009. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL22346 Ordering Information PART NUMBER (Note) ISL22346UFV20Z* ISL22346UFRT20Z* ISL22346WFV20Z* ISL22346WFRT20Z* PART MARKING 22346 UFVZ 223 46UFZ 22346 WFVZ 223 46WFZ RESISTANCE OPTION (kΩ) 50 50 10 10 TEMP. RANGE (°C) -40 to +125 -40 to +125 -40 to +125 -40 to +125 PACKAGE (Pb-free) 20 Ld TSSOP 20 Ld 4x4 TQFN 20 Ld TSSOP 20 Ld 4x4 TQFN PKG. DWG. # M20.173 L20.4x4A M20.173 L20.4x4A *Add “-TK” suffix for tape and reel. Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. Block Diagram VCC RH3 SCL SDA A0 A1 A2 I2C INTERFACE POWER-UP INTERFACE, CONTROL AND STATUS LOGIC WR3 RW3 RL3 RH2 WR2 RW2 RL2 RH1 WR1 NONVOLATILE REGISTERS WR0 RW1 RL1 RH0 RW0 RL0 SHDN GND Pin Descriptions TSSOP PIN NUMBER 1 2 3 4 5 6 7 8 9 10 11 12 13 14 TQFN PIN NUMBER 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PIN NAME RH3 RL3 RW3 A2 SCL SDA GND RW2 RL2 RH2 RW1 RL1 RH1 A0 “High” terminal of DCP3 “Low” terminal of DCP3 “Wiper” terminal of DCP3 Device address input for the I2C interface Open drain I2C interface clock input Open drain Serial data I/O for the I2C interface Device ground pin “Wiper” terminal of DCP2 “Low” terminal of DCP2 “High” terminal of DCP2 “Wiper” terminal of DCP1 “Low” terminal of DCP1 “High” terminal of DCP1 Device address input for the I2C interface DESCRIPTION 2 FN6177.2 September 3, 2009 ISL22346 Pin Descriptions (Continued) TSSOP PIN NUMBER 15 16 17 18 19 20 TQFN PIN NUMBER 17 18 19 20 1 2 EPAD* PIN NAME A1 VCC SHDN RH0 RL0 RW0 DESCRIPTION Device address input for the I2C interface Power supply pin Shutdown active low input “High” terminal of DCP0 “Low” terminal of DCP0 “Wiper” terminal of DCP0 Exposed Die Pad internally connected to GND *Note: PCB thermal land for QFN EPAD should be connected to GND plane or left floating. For more information refer to http://www.intersil.com/data/tb/TB389.pdf 3 FN6177.2 September 3, 2009 ISL22346 Absolute Maximum Ratings Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Voltage at any Digital Interface Pin with Respect to GND . . . . . . . . . . . . . . . . . . . . -0.3V to VCC + 0.3 VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6V Voltage at any DCP Pin with Respect to GND. . . . . . . -0.3V to VCC IW (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA Latchup (Note 4) . . . . . . . . . . . . . . . . . . Class II, Level B @ +125°C ESD Ratings Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5kV Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .350V Thermal Information Thermal Resistance (Typical) θJA (°C/W) θJC (°C/W) 20 Lead TSSOP (Note 1) . . . . . . . . . . . 95 N/A 20 Lead TQFN (Notes 2, 3) . . . . . . . . . 40 3.0 Maximum Junction Temperature (Plastic Package). . . . . . . . +150°C Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Recommended Operating Conditions Temperature Range (Extended Industrial). . . . . . . .-40°C to +125°C VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V Power Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15mW Wiper Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±3.0mA CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 2. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 3. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside. 4. Jedec Class II pulse conditions and failure criterion used. Level B exceptions are: using a max positive pulse of 6.5V on the SHDN pin, and using a max negative pulse of -0.8V for all pins. Analog Specifications SYMBOL RTOTAL Over recommended operating conditions, unless otherwise stated. TEST CONDITIONS W option U option MIN (Note 21) TYP (Note 5) 10 50 -20 ±50 ±80 0 70 10/10/25 Voltage at pin from GND to VCC 0.1 1 VCC 200 +20 MAX (Note 21) UNIT kΩ kΩ % ppm/°C (Note 18) ppm/°C (Note 18) V Ω pF µA PARAMETER RH to RL Resistance RH to RL Resistance Tolerance End-to-End Temperature Coefficient W and U option W option U option VRH, VRL RW CH/CL/CW (Note 20) ILkgDCP VRH and VRL Terminal Voltages Wiper Resistance Potentiometer Capacitance Leakage on DCP Pins VRH and VRL to GND VCC = 3.3V, wiper current = VCC/RTOTAL VOLTAGE DIVIDER MODE (0V @ RLi; VCC @ RHi; measured at RWi, unloaded; i = 0, 1, 2, or 3) INL (Note 10) DNL (Note 9) ZSerror (Note 7) FSerror (Note 8) VMATCH (Note 11) Integral Non-linearity Differential Non-linearity Zero-scale Error Monotonic over all tap positions Monotonic over all tap positions W option U option Full-scale error W option U option DCP to DCP Matching Any two DCPs at same tap position, same voltage at all RH terminals, and same voltage at all RL terminals -1 -0.5 0 0 -5 -2 -2 1 0.5 -1 -1 1 0.5 5 2 0 0 2 LSB (Note 6) LSB (Note 6) LSB (Note 6) LSB (Note 6) LSB (Note 6) 4 FN6177.2 September 3, 2009 ISL22346 Analog Specifications SYMBOL TCV (Note 12) Over recommended operating conditions, unless otherwise stated. (Continued) TEST CONDITIONS DCP register set to 40 hex MIN (Note 21) TYP (Note 5) ±4 MAX (Note 21) UNIT ppm/°C PARAMETER Ratiometric Temperature Coefficient RESISTOR MODE (Measurements between RWi and RLi with RHi not connected, or between RWi and RHi with RLi not connected. i = 0, 1, 2 or 3) RINL (Note 16) RDNL (Note 15) Integral Non-linearity Differential Non-linearity DCP register set between 10h and 7Fh; monotonic over all tap positions DCP register set between 10h and 7Fh; monotonic over all tap positions, W option DCP register set between 10h and 7Fh; monotonic over all tap positions, U option Roffset (Note 14) Offset W option U option RMATCH (Note 17) DCP to DCP Matching Any two DCPs at the same tap position with the same terminal voltages -1 -1 -0.5 0 0 -2 1 0.5 1 1 0.5 5 2 2 MI (Note 13) MI (Note 13) MI (Note 13) MI (Note 13) MI (Note 13) MI (Note 13) Operating Specifications Over the recommended operating conditions, unless otherwise specified. SYMBOL ICC1 ICC2 ISB PARAMETER VCC Supply Current (Volatile Write/Read) VCC Supply Current (Non-volatile Write/Read) VCC Current (Standby) TEST CONDITIONS fSCL = 400kHz; SDA = Open; (for I2C, active, read and write states) fSCL = 400kHz; SDA = Open; (for I2C, active, read and write states) VCC = +5.5V @ +85°C, I2C interface in standby state VCC = +5.5V @ +125°C, I2C interface in standby state VCC = +3.6V @ +85°C, I2C interface in standby state VCC = +3.6V @ +125°C, I2C interface in standby state ISD VCC Current (Shutdown) VCC = +5.5V @ +85°C, I2C interface in standby state VCC = +5.5V @ +125°C, I2C interface in standby state VCC = +3.6V @ +85°C, I2C interface in standby state VCC = +3.6V @ +125°C, I2C interface in standby state ILkgDig tWRT (Note 20) tShdnRec (Note 20) Leakage Current, at Pins A0, A1, A2, SHDN, SDA and SCL DCP Wiper Response Time DCP Recall Time from Shutdown Mode Voltage at pin from GND to VCC SCL falling edge of last bit of DCP data byte to wiper new position From rising edge of SHDN signal to wiper stored position and RH connection SCL falling edge of last bit of ACR data byte to wiper stored position and RH connection Vpor Power-on Recall Voltage Minimum VCC at which memory recall occurs 2.0 -1 1.5 1.5 1.5 2.6 MIN (Note 21) TYP (Note 5) MAX (Note 21) 0.5 3 5 7 3 5 3 5 2 4 1 UNIT mA mA µA µA µA µA µA µA µA µA µA µs µs µs V 5 FN6177.2 September 3, 2009 ISL22346 Operating Specifications Over the recommended operating conditions, unless otherwise specified. (Continued) SYMBOL VCCRamp tD PARAMETER VCC Ramp Rate Power-up Delay VCC above Vpor, to DCP Initial Value Register recall completed, and I2C Interface in standby state TEST CONDITIONS MIN (Note 21) 0.2 3 TYP (Note 5) MAX (Note 21) UNIT V/ms ms EEPROM SPECIFICATION EEPROM Endurance EEPROM Retention tWC (Note 19) Non-volatile Write Cycle Time Temperature T < +55°C 1,000,000 50 12 20 Cycles Years ms SERIAL INTERFACE SPECIFICATIONS VIL VIH Hysteresis VOL Cpin (Note 20) fSCL tsp tAA tBUF A2, A1, A0, SHDN, SDA, and SCL Input Buffer LOW Voltage A2, A1, A0, SHDN, SDA, and SCL Input Buffer HIGH Voltage SDA and SCL Input Buffer Hysteresis SDA Output Buffer LOW Voltage, Sinking 4mA A2, A1, A0, SHDN, SDA, and SCL Pin Capacitance SCL Frequency Pulse Width Suppression Time at SDA and SCL Inputs Any pulse narrower than the max spec is suppressed -0.3 0.7*VCC 0.05*VCC 0 10 400 50 900 1300 0.4 0.3*VCC VCC + 0.3 V V V V pF kHz ns ns ns SCL Falling Edge to SDA Output Data SCL falling edge crossing 30% of VCC, until Valid SDA exits the 30% to 70% of VCC window Time the Bus Must be Free Before the SDA crossing 70% of VCC during a STOP Start of a New Transmission condition, to SDA crossing 70% of VCC during the following START condition Clock LOW Time Clock HIGH Time START Condition Setup Time START Condition Hold Time Input Data Setup Time Measured at the 30% of VCC crossing Measured at the 70% of VCC crossing SCL rising edge to SDA falling edge; both crossing 70% of VCC From SDA falling edge crossing 30% of VCC to SCL falling edge crossing 70% of VCC From SDA exiting the 30% to 70% of VCC window, to SCL rising edge crossing 30% of VCC From SCL rising edge crossing 70% of VCC to SDA entering the 30% to 70% of VCC window From SCL rising edge crossing 70% of VCC, to SDA rising edge crossing 30% of VCC From SDA rising edge to SCL falling edge; both crossing 70% of VCC From SCL falling edge crossing 30% of VCC, until SDA enters the 30% to 70% of VCC window From 30% to 70% of VCC tLOW tHIGH tSU:STA tHD:STA tSU:DAT 1300 600 600 600 100 ns ns ns ns ns tHD:DAT Input Data Hold Time 0 ns tSU:STO tHD:STO tDH STOP Condition Setup Time STOP Condition Hold Time for Read, or Volatile Only Write Output Data Hold Time 600 1300 0 ns ns ns tR SDA and SCL Rise Time 20 + 0.1*Cb 250 ns 6 FN6177.2 September 3, 2009 ISL22346 Operating Specifications Over the recommended operating conditions, unless otherwise specified. (Continued) SYMBOL tF Cb Rpu PARAMETER SDA and SCL Fall Time Capacitive Loading of SDA or SCL SDA and SCL Bus Pull-up Resistor Off-chip A2, A1 and A0 Setup Time A2, A1 and A0 Hold Time TEST CONDITIONS From 70% to 30% of VCC Total on-chip and off-chip Maximum is determined by tR and tF For Cb = 400pF, max is about 2kΩ~2.5kΩ For Cb = 40pF, max is about 15kΩ~20kΩ Before START condition After STOP condition MIN (Note 21) 20 + 0.1*Cb 10 1 TYP (Note 5) MAX (Note 21) 250 400 UNIT ns pF kΩ tSU:A tHD:A NOTES: 600 600 ns ns 5. Typical values are for TA = +25°C and 3.3V supply voltage. 6. LSB: [V(RW)127 – V(RW)0]/127. V(RW)127 and V(RW)0 are V(RW) for the DCP register set to 7F hex and 00 hex respectively. LSB is the incremental voltage when changing from one tap to an adjacent tap. 7. ZS error = V(RW)0/LSB. 8. FS error = [V(RW)127 – VCC]/LSB. 9. DNL = [V(RW)i – V(RW)i-1]/LSB-1, for i = 1 to 127. i is the DCP register setting. 10. INL = [V(RW)i – i • LSB – V(RW)0]/LSB for i = 1 to 127. 11. VMATCH = [V(RWx)i – V(RWy)i]/LSB, for i = 1 to 127, x = 0 to 3 and y = 0 to 3. Max ( V ( RW ) i ) – Min ( V ( RW ) i ) 10 6 12. TC V = --------------------------------------------------------------------------------------------- × -------------------- for i = 16 to 112 decimal, T = -40°C to +125°C. Max( ) is the maximum value of the wiper [ Max ( V ( RW ) i ) + Min ( V ( RW ) i ) ] ⁄ 2 +165°C voltage and Min ( ) is the minimum value of the wiper voltage over the temperature range. 13. MI = |RW127 – RW0|/127. RW127 and RW0 are the measured resistances for the DCP register set to 7F hex and 00 hex respectively. 14. Roffset = RW0/MI, when measuring between RW and RL. Roffset = RW127/MI, when measuring between RW and RH. 15. RDNL = (RWi – RWi-1)/MI - 1, for i = 16 to 127. 16. RINL = [RWi – (MI • i) – RW0]/MI, for i = 16 to 127. 17. RMATCH = (RWi,x – RWi,y)/MI, for i = 1 to 127, x = 0 to 3 and y = 0 to 3. [ Max ( Ri ) – Min ( Ri ) ] 10 18. TC R = --------------------------------------------------------------- × -------------------- for i = 16 to 112, T = -40°C to +125°C. Max( ) is the maximum value of the resistance and Min ( ) is [ Max ( Ri ) + Min ( Ri ) ] ⁄ 2 +165°C the minimum value of the resistance over the temperature range. 19. tWC is the time from a valid STOP condition at the end of a Write sequence of I2C serial interface, to the end of the self-timed internal non-volatile write cycle. 20. Limits should be considered typical and are not production tested. 21. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. 6 7 FN6177.2 September 3, 2009 ISL22346 SDA vs SCL Timing tF tHIGH tLOW tR tsp SCL tSU:STA tHD:STA SDA (INPUT TIMING) tSU:DAT tHD:DAT tSU:STO tAA SDA (OUTPUT TIMING) tDH tBUF A0, A1, and A2 Pin Timing START SCL CLK 1 STOP SDA tSU:A A0, A1, OR A2 tHD:A Typical Performance Curves 100 90 WIPER RESISITANCE (Ω) 80 70 ISB (µA) 60 50 40 30 20 10 0 0 20 40 60 80 100 120 TAP POSITION (DECIMAL) VCC = 3.3V, T = +20°C VCC = 3.3V, T = -40°C 0.2 0 2.7 1.0 0.8 0.6 0.4 T = +25°C T = +125°C VCC = 3.3V, T = +125°C 1.4 1.2 3.2 3.7 4.2 VCC (V) 4.7 5.2 FIGURE 1. WIPER RESISTANCE vs TAP POSITION [ I(RW) = VCC/RTOTAL ] FOR 10kΩ (W) FIGURE 2. STANDBY ICC vs VCC 8 FN6177.2 September 3, 2009 ISL22346 Typical Performance Curves 0.2 T = +25°C VCC = 2.7V 0.1 DNL (LSB) INL (LSB) 0.1 VCC = 2.7V (Continued) 0.2 T = +25°C 0 0 -0.1 VCC = 5.5V -0.2 0 20 40 60 80 100 120 TAP POSITION (DECIMAL) -0.1 VCC = 5.5V -0.2 0 20 40 60 80 100 120 TAP POSITION (DECIMAL) FIGURE 3. DNL vs TAP POSITION IN VOLTAGE DIVIDER MODE FOR 10kΩ (W) FIGURE 4. INL vs TAP POSITION IN VOLTAGE DIVIDER MODE FOR 10kΩ (W) 1.3 10k 1.1 0.9 ZSERROR (LSB) 0.7 0.5 0.3 0.1 -0.1 -0.3 -40 -20 0 20 50k VCC = 2.7V VCC = 5.5V ZSERROR (LSB) 0.0 -0.3 VCC = 2.7V 50k VCC = 5.5V -0.6 -0.9 10k -1.2 40 60 80 100 120 -1.5 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (°C) TEMPERATURE (ºC) FIGURE 5. ZSERROR vs TEMPERATURE FIGURE 6. FSERROR vs TEMPERATURE 0.4 T = +25°C 0.2 DNL (LSB) VCC = 5.5V 0.4 T = +25°C 0.2 INL (LSB) VCC = 5.5V 0 0 -0.2 -0.2 -0.4 VCC = 2.7V -0.6 16 36 56 76 96 116 -0.4 VCC = 2.7V -0.6 16 36 56 76 96 TAP POSITION (DECIMAL) 116 TAP POSITION (DECIMAL) FIGURE 7. DNL vs TAP POSITION IN RHEOSTAT MODE FOR 10kΩ (W) FIGURE 8. INL vs TAP POSITION IN RHEOSTAT MODE FOR 10kΩ (W) 9 FN6177.2 September 3, 2009 ISL22346 Typical Performance Curves 1.0 END TO END RTOTAL CHANGE (%) (Continued) 105 90 0.5 VCC = 2.7V 0.0 VCC = 5.5V 10k -0.5 50k TCv (ppm/°C) 75 60 45 30 15 50k 10k -1.0 -40 0 -20 0 20 40 60 80 100 120 16 36 56 76 96 TEMPERATURE (ºC) TAP POSITION (DECIMAL) FIGURE 9. END TO END RTOTAL % CHANGE vs TEMPERATURE FIGURE 10. TC FOR VOLTAGE DIVIDER MODE IN ppm INPUT 300 250 TCr (ppm/°C) 200 150 50k 100 50 0 16 10k OUTPUT WIPER AT MID POINT (POSITION 40h) RTOTAL = 9.5kΩ 36 56 76 96 TAP POSITION (DECIMAL) FIGURE 11. TC FOR RHEOSTAT MODE IN ppm FIGURE 12. FREQUENCY RESPONSE (2.6MHz) SCL SIGNAL AT WIPER (WIPER UNLOADED) SIGNAL AT WIPER (WIPER UNLOADED MOVEMENT FROM 7Fh TO 00h) WIPER MID POINT MOVEMENT FROM 3Fh TO 40h FIGURE 13. MIDSCALE GLITCH, CODE 3Fh TO 40h FIGURE 14. LARGE SIGNAL SETTLING TIME 10 FN6177.2 September 3, 2009 ISL22346 Pin Descriptions Potentiometers Pins RHI AND RLI (i = 0, 1, 2 OR 3) The high (RHi) and low (RLi) terminals of the ISL22346 are equivalent to the fixed terminals of a mechanical potentiometer. RHi and RLi are referenced to the relative position of the wiper and not the voltage potential on the terminals. With WRi set to 127 decimal, the wiper will be closest to RHi, and with the WRi set to 0, the wiper is closest to RLi. RWI (i = 0, 1, 2 OR 3) RWi is the wiper terminal and is equivalent to the movable terminal of a mechanical potentiometer. The position of the wiper within the array is determined by the WRi register. SHDN The SHDN pin forces the resistor to end-to-end open circuit condition on RHi and shorts RWi to RLi. When SHDN is returned to logic high, the previous latch settings put RWi at the same resistance setting prior to shutdown. This pin is logically ANDed with SHDN bit in ACR register. I2C interface is still available in shutdown mode and all registers are accessible. This pin must remain HIGH for normal operation. RH input pins in order to initiate communication with the ISL22346. A maximum of 8 ISL22346 devices may occupy the I2C serial bus. Principles of Operation The ISL22346 is an integrated circuit incorporating four DCPs with their associated registers, non-volatile memory and an I2C serial interface providing direct communication between a host and the potentiometers and memory. The resistor arrays are comprised of individual resistors connected in series. At either end of the array and between each resistor is an electronic switch that transfers the potential at that point to the wiper. The electronic switches on the device operate in a “make before break” mode when the wiper changes tap positions. When the device is powered down, the last value stored in IVRi will be maintained in the non-volatile memory. When power is restored, the contents of the IVRi are recalled and loaded into the corresponding WRi to set the wipers to the initial value. DCP Description Each DCP is implemented with a combination of resistor elements and CMOS switches. The physical ends of each DCP are equivalent to the fixed terminals of a mechanical potentiometer (RH and RL pins). The RW pin of each DCP is connected to intermediate nodes, and is equivalent to the wiper terminal of a mechanical potentiometer. The position of the wiper terminal within the DCP is controlled by volatile Wiper Register (WR). Each DCP has its own WR. When the WR of a DCP contains all zeroes (WR[6:0]= 00h), its wiper terminal (RW) is closest to its “Low” terminal (RL). When the WR register of a DCP contains all ones (WR[6:0]= 7Fh), its wiper terminal (RW) is closest to its “High” terminal (RH). As the value of the WR increases from all zeroes (0) to all ones (127 decimal), the wiper moves monotonically from the position closest to RL to the closest to RH. At the same time, the resistance between RW and RL increases monotonically, while the resistance between RH and RW decreases monotonically. While the ISL22346 is being powered up, all four WRs are reset to 40h (64 decimal), which locates RW roughly at the center between RL and RH. After the power supply voltage becomes large enough for reliable non-volatile memory reading, all WRs will be reload with the value stored in corresponding non-volatile Initial Value Registers (IVRs). The WRs can be read or written to directly using the I2C serial interface as described in the following sections. The I2C interface Address Byte has to be set to 00h, 01h, 02h or 03h to access the WR of DCP0, DCP1, DCP2 or DCP3 respectively. RW RL FIGURE 15. DCP CONNECTION IN SHUTDOWN MODE Bus Interface Pins SERIAL DATA INPUT/OUTPUT (SDA) The SDA is a bidirectional serial data input/output pin for I2C interface. It receives device address, operation code, wiper address and data from an I2C external master device at the rising edge of the serial clock SCL, and it shifts out data after each falling edge of the serial clock. SDA requires an external pull-up resistor, since it is an open drain input/output. SERIAL CLOCK (SCL) This is the serial clock input of the I2C serial interface. SCL requires an external pull-up resistor, since it is an open drain input. DEVICE ADDRESS (A2 - A0) The address inputs are used to set the least significant 3 bits of the 7-bit I2C interface slave address. A match in the slave address serial data stream must match with the Address 11 FN6177.2 September 3, 2009 ISL22346 Memory Description The ISL22346 contains seven non-volatile and five volatile 8-bit registers. The memory map of ISL22346 is on Table 1. The four non-volatile registers (IVRi) at address 0, 1, 2 and 3 contain initial wiper value and volatile registers (WRi) contain current wiper position. In addition, three non-volatile General Purpose registers from address 4 to address 6 are available. TABLE 1. MEMORY MAP ADDRESS 8 7 6 5 4 3 2 1 0 General Purpose General Purpose General Purpose IVR3 IVR2 IVR1 IVR0 NON-VOLATILE — Reserved Not Available Not Available Not Available WR3 WR2 WR1 WR0 VOLATILE ACR I2C Serial Interface The ISL22346 supports an I2C bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master always initiates data transfers and provides the clock for both transmit and receive operations. Therefore, the ISL22346 operates as a slave device in all applications. All communication over the I2C interface is conducted by sending the MSB of each byte of data first. Protocol Conventions Data states on the SDA line must change only during SCL LOW periods. SDA state changes during SCL HIGH are reserved for indicating START and STOP conditions (see Figure 16). On power-up of the ISL22346, the SDA pin is in the input mode. All I2C interface operations must begin with a START condition, which is a HIGH to LOW transition of SDA while SCL is HIGH. The ISL22346 continuously monitors the SDA and SCL lines for the START condition and does not respond to any command until this condition is met (see Figure 16). A START condition is ignored during the power-up of the device. All I2C interface operations must be terminated by a STOP condition, which is a LOW to HIGH transition of SDA while SCL is HIGH (see Figure 16). A STOP condition at the end of a read operation, or at the end of a write operation places the device in its standby mode. An ACK, Acknowledge, is a software convention used to indicate a successful data transfer. The transmitting device, either master or slave, releases the SDA bus after transmitting eight bits. During the ninth clock cycle, the receiver pulls the SDA line LOW to acknowledge the reception of the eight bits of data (see Figure 17). The ISL22346 responds with an ACK after recognition of a START condition followed by a valid Identification Byte, and once again after successful receipt of an Address Byte. The ISL22346 also responds with an ACK after receiving a Data Byte of a write operation. The master must respond with an ACK after receiving a Data Byte of a read operation. A valid Identification Byte contains 1010 as the four MSBs, and the following three bits matching the logic values present at pins A2, A1, and A0. The LSB is the Read/Write bit. Its value is “1” for a Read operation, and “0” for a Write operation (see Table 4). The non-volatile IVRi and volatile WRi registers are accessible with the same address. The Access Control Register (ACR) contains information and control bits described in Table 2. The VOL bit at access control register (ACR[7]) determines whether the access is to wiper registers WRi or initial value registers IVRi. TABLE 2. ACCESS CONTROL REGISTER (ACR) VOL SHDN WIP 0 0 0 0 0 If VOL bit is 0, the non-volatile IVRi registers are accessible. If VOL bit is 1, only the volatile WRi are accessible. Note, value is written to IVRi register also is written to the corresponding WRi. The default value of this bit is 0. The SHDN bit (ACR[6]) disables or enables Shutdown mode. This bit is logically ANDed with SHDN pin. When this bit is 0, all DCPs are in Shutdown mode. Default value of SHDN bit is 1. The WIP bit (ACR[5]) is read only bit. It indicates that non-volatile write operation is in progress. It is impossible to write to the WRi or ACR while WIP bit is 1. Shutdown Mode The device can be put in Shutdown mode either by pulling the SHDN pin to GND or setting the SHDN bit in the ACR register to 0. The truth table for Shutdown mode is in Table 3. TABLE 3. SHDN pin High Low High Low SHDN bit 1 1 0 0 Mode Normal operation Shutdown Shutdown Shutdown 12 FN6177.2 September 3, 2009 ISL22346 TABLE 4. IDENTIFICATION BYTE FORMAT Logic values at pins A2, A1, and A0 respectively 1 (MSB) 0 1 0 A2 A1 A0 R/W (LSB) SCL SDA START DATA STABLE DATA CHANGE DATA STABLE STOP FIGURE 16. VALID DATA CHANGES, START AND STOP CONDITIONS SCL FROM MASTER 1 8 9 SDA OUTPUT FROM TRANSMITTER HIGH IMPEDANCE SDA OUTPUT FROM RECEIVER HIGH IMPEDANCE START ACK FIGURE 17. ACKNOWLEDGE RESPONSE FROM RECEIVER WRITE SIGNALS FROM THE MASTER S T A R T S T O P IDENTIFICATION BYTE ADDRESS BYTE DATA BYTE SIGNAL AT SDA SIGNALS FROM THE SLAVE 1 0 1 0 A2 A1 A0 0 A C K 0000 A C K A C K FIGURE 18. BYTE WRITE SEQUENCE 13 FN6177.2 September 3, 2009 ISL22346 SIGNALS FROM THE MASTER S T A R T IDENTIFICATION BYTE WITH R/W = 0 ADDRESS BYTE S T A IDENTIFICATION R BYTE WITH T R/W = 1 A C K A C K S AT CO KP SIGNAL AT SDA 1 0 1 0 A2 A1 A0 0 A C K 0000 A C K 1 0 1 0 A2 A1 A0 1 A C K SIGNALS FROM THE SLAVE FIRST READ DATA BYTE LAST READ DATA BYTE FIGURE 19. READ SEQUENCE Write Operation A Write operation requires a START condition, followed by a valid Identification Byte, a valid Address Byte, a Data Byte, and a STOP condition. After each of the three bytes, the ISL22346 responds with an ACK. At this time, the device enters its standby state (see Figure 18). Device can receive more than one byte of data by auto incrementing the address after each received byte. Note after reaching the address 08h, the internal pointer “rolls over” to address 00h. The non-volatile write cycle starts after STOP condition is determined and it requires up to 20ms delay for the next non-volatile write. Thus, non-volatile registers must be written individually. Read Operation A Read operation consist of a three byte instruction followed by one or more Data Bytes (See Figure 19). The master initiates the operation issuing the following sequence: a START, the Identification byte with the R/W bit set to “0”, an Address Byte, a second START, and a second Identification byte with the R/W bit set to “1”. After each of the three bytes, the ISL22346 responds with an ACK. Then the ISL22346 transmits Data Bytes as long as the master responds with an ACK during the SCL cycle following the eighth bit of each byte. The master terminates the read operation (issuing a ACK and a STOP condition) following the last bit of the last Data Byte (see Figure 19). The Data Bytes are from the registers indicated by an internal pointer. This pointer initial value is determined by the Address Byte in the Read operation instruction, and increments by one during transmission of each Data Byte. After reaching the memory location 08h, the pointer “rolls over” to 00h, and the device continues to output data for each ACK received. In order to read back the non-volatile IVR, it is recommended that the application reads the ACR first to verify the WIP bit is 0. If the WIP bit (ACR[5]) is not 0, the host should repeat its reading sequence again. 14 FN6177.2 September 3, 2009 ISL22346 Thin Micro Lead FramePlastic Package (TMLFP) L20.4x4A 20 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220WGGD-1 ISSUE I) MILLIMETERS SYMBOL A A1 A2 A3 b D D1 D2 E E1 E2 e k L N Nd Ne P θ 0.20 0.35 1.95 1.95 0.18 MIN 0.70 NOMINAL 0.75 0.02 0.55 0.20 REF 0.25 4.00 BSC 3.75 BSC 2.10 4.00 BSC 3.75 BSC 2.10 0.50 BSC 0.60 20 5 5 0.60 12 0.75 2.25 2.25 0.30 MAX 0.80 0.05 0.80 NOTES 9 9 5, 8 9 7, 8 9 7, 8 8 2 3 3 9 9 Rev. 0 11/04 NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd and Ne refer to the number of terminals on each D and E. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. 9. Features and dimensions A2, A3, D1, E1, P & θ are present when Anvil singulation method is used and not present for saw singulation. 15 FN6177.2 September 3, 2009 ISL22346 Thin Shrink Small Outline Plastic Packages (TSSOP) N INDEX AREA E E1 -B1 2 3 0.05(0.002) -AD -CSEATING PLANE A 0.25 0.010 L 0.25(0.010) M GAUGE PLANE BM M20.173 20 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A A1 A2 b c MIN 0.002 0.031 0.0075 0.0035 0.252 0.169 0.246 0.0177 20 0o 8o 0o MAX 0.047 0.006 0.051 0.0118 0.0079 0.260 0.177 0.256 0.0295 MILLIMETERS MIN 0.05 0.80 0.19 0.09 6.40 4.30 6.25 0.45 20 8o MAX 1.20 0.15 1.05 0.30 0.20 6.60 4.50 6.50 0.75 NOTES 9 3 4 6 7 Rev. 1 6/98 e b 0.10(0.004) M C AM BS α A1 0.10(0.004) A2 c D E1 e E L N 0.026 BSC 0.65 BSC NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-153-AC, Issue E. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E1” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. (Angles in degrees) α All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 16 FN6177.2 September 3, 2009