ISL23318

Single, 128-taps Low Voltage Digitally Controlled Potentiometer (XDCP™) ISL23318 The ISL23318 is a volatile, low voltage, low noise, low power, I2C Bus™, 128 Taps, single digitally controlled potentiometer (DCP), which integrates DCP core, wiper switches and control logic on a monolithic CMOS integrated circuit. The digitally controlled potentiometer is implemented with a combination of resistor elements and CMOS switches. The position of the wipers are controlled by the user through the I2C bus interface. The potentiometer has an associated volatile Wiper Register (WR) that can be directly written to and read by the user. The contents of the WR controls the position of the wiper. When powered on, the ISL23318’s wiper will always commence at mid-scale (64 tap position). The low voltage, low power consumption, and small package of the ISL23318 make it an ideal choice for use in battery operated equipment. In addition, the ISL23318 has a VLOGIC pin allowing down to 1.2V bus operation, independent from the VCC value. This allows for low logic levels to be connected directly to the ISL23318 without passing through a voltage level shifter. The DCP can be used as a three-terminal potentiometer or as a two-terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing. Features • 128 resistor taps • I2C serial interface - No additional level translator for low bus supply - Two address pins allow up to four devices per bus • Power supply - VCC = 1.7V to 5.5V analog power supply - VLOGIC = 1.2V to 5.5V I2C bus/logic power supply • Wiper resistance: 70Ω typical @ VCC = 3.3V • Shutdown Mode - forces the DCP into an end-to-end open circuit and RW is shorted to RL internally • Power-on preset to mid-scale (64 tap position) • Shutdown and standby current 2V. IOL = 0.5mA, VLOGIC < 2V From 30% to 70% of VLOGIC 1300 ns tDH 0 ns tR SDA and SCL Rise Time 20 + 0.1 x Cb 250 ns 7 FN7887.0 July 26, 2011 ISL23318 Serial Interface Specification SYMBOL tF Cb tSU:A tHD:A NOTES: 8. Typical values are for TA = +25°C and 3.3V supply voltages. 9. LSB = [V(RW)127 – V(RW)0]/127. V(RW)127 and V(RW)0 are V(RW) for the DCP register set to 7F hex and 00 hex respectively. LSB is the incremental voltage when changing from one tap to an adjacent tap. 10. ZS error = V(RW)0/LSB. 11. FS error = [V(RW)127 – VCC]/LSB. 12. DNL = [V(RW)i – V(RW)i-1]/LSB-1, for i = 1 to 127. i is the DCP register setting. 13. INL = [V(RW)i – i • LSB – V(RW)0]/LSB for i = 1 to 127. 14. Max ( V ( RW ) i ) – Min ( V ( RW ) i ) 10 6 TC V = ----------------------------------------------------------------------------- × --------------------V ( RW i ( +25°C ) ) +165°C For i = 16 to 127 decimal, T = -40°C to +125°C. Max( ) is the maximum value of the wiper voltage and Min( ) is the minimum value of the wiper voltage over the temperature range. PARAMETER SDA and SCL Fall Time Capacitive Loading of SDA or SCL A1, A0 Set-up Time A1, A0 Hold Time For SCL, SDA, A0, A1 unless otherwise noted. (Continued) TEST CONDITIONS From 70% to 30% of VLOGIC Total on-chip and off-chip Before START condition After STOP condition MIN (Note 20) 20 + 0.1 x Cb 10 600 600 TYP (Note 8) MAX (Note 20) 250 400 UNITS ns pF ns ns 15. MI = |RW127 – RW0|/127. MI is a minimum increment. RW127 and RW0 are the measured resistances for the DCP register set to 7F hex and 00 hex respectively. 16. Roffset = RW0/MI, when measuring between RW and RL. Roffset = RW127/MI, when measuring between RW and RH. 17. RDNL = (RWi – RWi-1)/MI -1, for i = 8 to 127. 18. RINL = [RWi – (MI • i) – RW0]/MI, for i = 8 to 127. 19. [ Max ( Ri ) – Min ( Ri ) ] 10 TC R = ------------------------------------------------------ × --------------------Ri ( +25°C ) +165°C 6 For i = 8 to 127, T = -40°C to +125°C. Max( ) is the maximum value of the resistance and Min( ) is the minimum value of the resistance over the temperature range. 20. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. 21. It is preferable to ramp up both the VLOGIC and the VCC supplies at the same time. If this is not possible, it is recommended to ramp-up the VLOGIC first followed by the VCC. DCP Macro Model RTOTAL RH CH CW CL 32pF RL 32pF RW 32pF 8 FN7887.0 July 26, 2011 ISL23318 Timing Diagrams SDA vs SCL Timing tF tHIGH tLOW tR tsp SCL tSU:STA SDA (INPUT TIMING) tSU:DAT tHD:DAT tSU:STO tHD:STA tAA SDA (OUTPUT TIMING) tDH tBUF A0 and A1 Pin Timing START SCL CLK 1 STOP SDA tSU:A A0, A1 tHD:A Typical Performance Curves 0.4 0.04 0.2 DNL (LSB) DNL (LSB) 0.02 0 0 -0.2 -0.02 -0.4 0 16 32 48 64 80 96 112 128 -0.04 0 16 32 48 64 80 96 112 128 TAP POSITION (DECIMAL) TAP POSITION (DECIMAL) FIGURE 3. 10k DNL vs TAP POSITION, VCC = 5V FIGURE 4. 50k DNL vs TAP POSITION, VCC = 5V 9 FN7887.0 July 26, 2011 ISL23318 Typical Performance Curves 0.4 (Continued) 0.16 0.2 INL (LSB) 0.08 INL (LSB) 0 0 -0.2 -0.08 -0.4 0 16 32 48 64 80 96 112 128 -0.16 0 16 32 48 64 80 96 112 128 TAP POSITION (DECIMAL) TAP POSITION (DECIMAL) FIGURE 5. 10k INL vs TAP POSITION, VCC = 5V FIGURE 6. 50k INL vs TAP POSITION, VCC = 5V 0.4 0.10 0.2 RDNL (MI) RDNL (MI) 0.05 0 0 -0.2 -0.05 -0.4 -0.10 0 16 32 48 64 80 96 112 128 TAP POSITION (DECIMAL) 0 16 32 48 64 80 96 112 128 TAP POSITION (DECIMAL) FIGURE 7. 10k RDNL vs TAP POSITION, VCC = 5V FIGURE 8. 50k RDNL vs TAP POSITION, VCC = 5V 0.4 0.16 0.2 RINL (MI) 0.08 RINL (MI) 0 0 -0.2 -0.08 -0.4 0 16 32 48 64 80 96 112 128 -0.16 0 16 32 48 64 80 96 112 128 TAP POSITION (DECIMAL) TAP POSITION (DECIMAL) FIGURE 9. 10k RINL vs TAP POSITION, VCC = 5V FIGURE 10. 50k RINL vs TAP POSITION, VCC = 5V 10 FN7887.0 July 26, 2011 ISL23318 Typical Performance Curves 60 50 WIPER RESISTANCE (Ω) (Continued) 50 +125°C +25°C +125°C WIPER RESISTANCE (Ω) +25°C 40 40 30 20 10 0 30 20 -40°C -40°C 10 0 16 32 48 64 80 96 112 128 0 0 16 32 48 64 80 96 112 128 TAP POSITION (DECIMAL) TAP POSITION (DECIMAL) FIGURE 11. 10k WIPER RESISTANCE vs TAP POSITION, VCC = 5V FIGURE 12. 50k WIPER RESISTANCE vs TAP POSITION, VCC = 5V 140 120 100 TCv (ppm/°C) 30 25 20 15 10 5 0 80 60 40 20 0 16 32 48 64 80 96 112 128 TCv (ppm/°C) 16 32 48 64 80 96 112 128 TAP POSITION (DECIMAL) TAP POSITION (DECIMAL) FIGURE 13. 10k TCv vs TAP POSITION FIGURE 14. 50k TCv vs TAP POSITION 350 300 250 TCr (ppm/°C) 100 75 TCr (ppm/°C) 200 150 100 50 0 16 50 25 32 48 64 80 96 112 128 0 16 32 48 64 80 96 112 128 TAP POSITION (DECIMAL) TAP POSITION (DECIMAL) FIGURE 15. 10k TCr vs TAP POSITION FIGURE 16. 50k TCr vs TAP POSITION 11 FN7887.0 July 26, 2011 ISL23318 Typical Performance Curves 20 (Continued) 150 140 15 TCv (ppm/°C) TCr (ppm/°C) 130 10 120 5 110 0 16 32 48 64 80 96 112 128 100 16 32 48 64 80 96 112 128 TAP POSITION (DECIMAL) TAP POSITION (DECIMAL) FIGURE 17. 100k TCv vs TAP POSITION FIGURE 18. 100k TCr vs TAP POSITION SCL CLOCK 1V/DIV RW PIN 10mV/DIV 1µs/DIV 20mV/DIV 5µs/DIV FIGURE 19. WIPER DIGITAL FEED-THROUGH FIGURE 20. WIPER TRANSITION GLITCH 1V/DIV 1µs/DIV WIPER 1V/DIV 0.1s/DIV VRH = VCC VRW SCL 9TH CLOCK OF THE DATA BYTE (ACK) FIGURE 21. WIPER LARGE SIGNAL SETTLING TIME FIGURE 22. POWER-ON START-UP IN VOLTAGE DIVIDER MODE 12 FN7887.0 July 26, 2011 ISL23318 Typical Performance Curves CH1: 0.5V/DIV, 0.2µs/DIV RH PIN CH2: 0.2V/DIV, 0.2µs/DIV RW PIN STANDBY CURRENT ICC (µA) (Continued) 1.2 1.0 0.8 VCC = 5.5V, VLOGIC = 5.5V 0.6 0.4 VCC = 1.7V, VLOGIC = 1.2V 0.2 0 -40 RTOTAL = 10k -3dB FREQUENCY = 1.4MHz AT MIDDLE TAP -15 10 35 60 85 110 TEMPERATURE (°C) FIGURE 23. 10k -3dB CUT OFF FREQUENCY FIGURE 24. STANDBY CURRENT vs TEMPERATURE Functional Pin Descriptions Potentiometers Pins RH AND RL The high (RH) and low (RL) terminals of the ISL23318 are equivalent to the fixed terminals of a mechanical potentiometer. RH and RL are referenced to the relative position of the wiper and not the voltage potential on the terminals. With WR set to 127 decimal, the wiper will be closest to RH, and with the WR set to 0, the wiper is closest to RL. VLOGIC This is an input pin that supplies internal level translator for serial bus operation from 1.2V to 5.5V. Principles of Operation The ISL23318 is an integrated circuit incorporating one DCP with its associated registers and an I2C serial interface providing direct communication between a host and the potentiometer. The resistor array is comprised of individual resistors connected in series. At either end of the array and between each resistor is an electronic switch that transfers the potential at that point to the wiper. The electronic switches on the device operate in a “make-before-break” mode when the wiper changes tap positions. Voltage at any DCP pins, RH, RL or RW, should not exceed VCC level at any conditions during power-up and normal operation. The VLOGIC pin needs to be connected to the I2C bus supply which allows reliable communication with the wide range of microcontrollers and independent of the VCC level. This is extremely important in systems where the master supply has lower levels than DCP analog supply. RW RW is the wiper terminal, and it is equivalent to the movable terminal of a mechanical potentiometer. The position of the wiper within the array is determined by the WR register. Bus Interface Pins SERIAL DATA INPUT/OUTPUT (SDA) The SDA is a bidirectional serial data input/output pin for I2C interface. It receives device address, wiper address and data from an I2C external master device at the rising edge of the serial clock SCL, and it shifts out data after each falling edge of the serial clock. SDA requires an external pull-up resistor, since it is an open drain input/output. DCP Description The DCP is implemented with a combination of resistor elements and CMOS switches. The physical ends of each DCP are equivalent to the fixed terminals of a mechanical potentiometer (RH and RL pins). The RW pin of the DCP is connected to intermediate nodes, and is equivalent to the wiper terminal of a mechanical potentiometer. The position of the wiper terminal within the DCP is controlled by a 7-bit volatile Wiper Register (WR). When the WR of a DCP contains all zeroes (WR[7:0] = 00h), its wiper terminal (RW) is closest to its “Low” terminal (RL). When the WR register of a DCP contains all ones (WR[7:0] = 7Fh), its wiper terminal (RW) is closest to its “High” terminal (RH). As the value of the WR increases from all zeroes (0) to 0111 1111b (127 decimal), the wiper moves FN7887.0 July 26, 2011 SERIAL CLOCK (SCL) This input is the serial clock of the I2C serial interface. SCL requires an external pull-up resistor, since a master is an open drain output. DEVICE ADDRESS (A1, A0) The address inputs are used to set the least significant 2 bits of the 7-bit I2C interface slave address. A match in the slave address serial data stream must match with the Address input pins in order to initiate communication with the ISL23318. A maximum of four ISL23318 devices may occupy the I2C serial bus (see Table 3). 13 ISL23318 monotonically from the position closest to RL to the position closest to RH. At the same time, the resistance between RW and RL increases monotonically, while the resistance between RH and RW decreases monotonically. While the ISL23318 is being powered up, the WR is reset to 40h (64 decimal), which locates RW roughly at the center between RL and RH. The WR can be read or written to directly using the I2C serial interface as described in the following sections. In shutdown mode, if there is a glitch on the power supply which causes it to drop below 1.3V for more than 0.2µs to 0.4µs, the wipers will be RESET to their mid position. This is done to avoid an undefined state at the wiper outputs. WIPER VOLTAGE, VRW (V) POWER-UP MID SCALE = 80H AFTER SHDN Memory Description The ISL23318 contains two volatile 8-bit registers: Wiper Register (WR) and Access Control Register (ACR). The memory map of ISL23318 is shown in Table 1. The Wiper Register (WR) at address 0 contains current wiper position. The Access Control Register (ACR) at address 10h contains information and control bits described in Table 2. TABLE 1. MEMORY MAP ADDRESS (hex) 10 0 VOLATILE REGISTER NAME ACR WR TABLE 2. ACCESS CONTROL REGISTER (ACR) BIT # NAME/ VALUE 7 0 6 SHDN 5 0 4 0 3 0 2 0 1 0 0 0 DEFAULT SETTING (hex) 40 40 USER PROGRAMMED SHDN ACTIVATED SHDN RELEASED WIPER RESTORE TO THE ORIGINAL POSITION SHDN MODE 0 TIME (s) FIGURE 26. SHUTDOWN MODE WIPER RESPONSE I2C Serial Interface The ISL23318 supports an I2C bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master always initiates data transfers and provides the clock for both transmit and receive operations. Therefore, the ISL23318 operates as a slave device in all applications. All communication over the I2C interface is conducted by sending the MSB of each byte of data first. Shutdown Function The SHDN bit (ACR[6]) disables or enables shutdown mode for all DCP channels simultaneously. When this bit is 0, i.e., DCP is forced to end-to-end open circuit and RW is connected to RL through a 2kΩ serial resistor as shown in Figure 25. Default value of the SHDN bit is 1 RH Protocol Conventions Data states on the SDA line must change only during SCL LOW periods. SDA state changes during SCL HIGH are reserved for indicating START and STOP conditions (see Figure 27). On power-up of the ISL23318, the SDA pin is in the input mode. All I2C interface operations must begin with a START condition, which is a HIGH-to-LOW transition of SDA while SCL is HIGH. The ISL23318 continuously monitors the SDA and SCL lines for the START condition and does not respond to any command until this condition is met (see Figure 27). A START condition is ignored during the power-up of the device. All I2C interface operations must be terminated by a STOP condition, which is a LOW to HIGH transition of SDA while SCL is HIGH (see Figure 27). A STOP condition at the end of a read operation or at the end of a write operation places the device in its standby mode. An ACK (Acknowledge) is a software convention used to indicate a successful data transfer. The transmitting device, either master or slave, releases the SDA bus after transmitting eight bits. During the ninth clock cycle, the receiver pulls the SDA line LOW to acknowledge the reception of the eight bits of data (see Figure 28). The ISL23318 responds with an ACK after recognition of a START condition followed by a valid Identification Byte, and once again RW 2kΩ RL FIGURE 25. DCP CONNECTION IN SHUTDOWN MODE In the shutdown mode, the RW terminal is shorted to the RL terminal with around 2kΩ resistance as shown in Figure 25. When the device enters shutdown, all current DCP WR settings are maintained. When the device exits shutdown, the wipers will return to the previous WR settings after a short settling time (see Figure 26). 14 FN7887.0 July 26, 2011 ISL23318 after successful receipt of an Address Byte. The ISL23318 also responds with an ACK after receiving a Data Byte of a write operation. The master must respond with an ACK after receiving a Data Byte of a read operation. A valid Identification Byte contains 10100 as the five MSBs, and the following two bits matching the logic values present at pins A1 and A0. The LSB is the Read/Write bit. Its value is “1” for a Read operation and “0” for a Write operation (see Table 3). 1 (MSB) TABLE 3. IDENTIFICATION BYTE FORMAT LOGIC VALUES AT PINS A1 AND A0, RESPECTIVELY 0 1 0 0 A1 A0 R/W (LSB) SCL SDA START DATA STABLE DATA CHANGE DATA STABLE STOP FIGURE 27. VALID DATA CHANGES, START AND STOP CONDITIONS SCL FROM MASTER 1 8 9 SDA OUTPUT FROM TRANSMITTER HIGH IMPEDANCE SDA OUTPUT FROM RECEIVER START HIGH IMPEDANCE ACK FIGURE 28. ACKNOWLEDGE RESPONSE FROM RECEIVER SIGNALS FROM THE MASTER S T A R T WRITE IDENTIFICATION BYTE ADDRESS BYTE DATA BYTE S T O P SIGNAL AT SDA SIGNALS FROM THE SLAVE 1 0 1 0 0 A1 A0 0 A C K 000 A C K A C K FIGURE 29. BYTE WRITE SEQUENCE 15 FN7887.0 July 26, 2011 ISL23318 SIGNALS FROM THE MASTER S T A R T S T A IDENTIFICATION R BYTE WITH T R/W = 1 READ A C K A C K S AT CO KP IDENTIFICATION BYTE WITH R/W = 0 ADDRESS BYTE SIGNAL AT SDA 1 0 1 0 0 A1 A0 0 A C K 000 A C K 1 0 1 0 0 A1 A0 1 A C K SIGNALS FROM THE SLAVE FIRST READ DATA BYTE LAST READ DATA BYTE FIGURE 30. READ SEQUENCE Write Operation A Write operation requires a START condition, followed by a valid Identification Byte, a valid Address Byte, a Data Byte, and a STOP condition. After each of the three bytes, the ISL23318 responds with an ACK. The data is transferred from I2C block to the corresponding register at the 9th clock of the data byte and device enters its standby state (see Figures 28 and 29). Applications Information VLOGIC Requirements It is recommended to keep VLOGIC powered all the time during normal operation. In a case where turning VLOGIC OFF is necessary, it is recommended to ground the VLOGIC pin of the ISL23318. Grounding the VLOGIC pin or both VLOGIC and VCC does not affect other devices on the same bus. It is good practice to put a 1µF cap in parallel to 0.1µF as close to the VLOGIC pin as possible. Read Operation A Read operation consists of a three byte instruction followed by one or more Data Bytes (see Figure 30). The master initiates the operation issuing the following sequence: a START, the Identification byte with the R/W bit set to “0”, an Address Byte, a second START, and a second Identification byte with the R/W bit set to “1”. After each of the three bytes, the ISL23318 responds with an ACK; then the ISL23318 transmits Data Byte. The master terminates the read operation issuing a NACK (ACK) and a STOP condition following the last bit of the last Data Byte (see Figure 30). VCC Requirements and Placement It is recommended to put a 1µF capacitor in parallel with 0.1µF decoupling capacitor close to the VCC pin. Wiper Transition When stepping up through each tap in voltage divider mode, some tap transition points can result in noticeable voltage transients, or overshoot/undershoot, resulting from the sudden transition from a very low impedance “make” to a much higher impedance “break” within a short period of time (