ISL23348

Quad, 128 Tap, Low Voltage Digitally Controlled Potentiometer (XDCP™) ISL23348 The ISL23348 is a volatile, low voltage, low noise, low power, 128 tap, quad digitally controlled potentiometer (DCP) with an I2C Bus™ interface. It integrates four DCP cores, wiper switches and control logic on a monolithic CMOS integrated circuit. Each digitally controlled potentiometer is implemented with a combination of resistor elements and CMOS switches. The position of the wipers are controlled by the user through the I2C bus interface. Each potentiometer has an associated volatile Wiper Register (WRi, i = 0, 1, 2, 3) that can be directly written to and read by the user. The contents of the WRi controls the position of the wiper. When powered on, the wiper of each DCP will always commence at mid-scale (64 tap position). The low voltage, low power consumption, and small package of the ISL23348 make it an ideal choice for use in battery operated equipment. In addition, the ISL23348 has a VLOGIC pin allowing down to 1.2V bus operation, independent from the VCC value. This allows for low logic levels to be connected directly to the ISL23348 without passing through a voltage level shifter. The DCP can be used as a three-terminal potentiometer or as a two-terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing. Features • Four potentiometers per package • 128 resistor taps • 10kΩ, 50kΩ or 100kΩ total resistance • I2C serial interface - No additional level translator for low bus supply - Three address pins allow up to eight devices per bus • Maximum supply current without serial bus activity (standby) - 5µA @ VCC and VLOGIC = 5V - 2µA @ VCC and VLOGIC = 1.7V • Shutdown mode - Forces the DCP into an end-to-end open circuit and RWi is connected to RLi internally - Reduces power consumption by disconnecting the DCP resistor from the circuit • Power supply - VCC = 1.7V to 5.5V analog power supply - VLOGIC = 1.2V to 5.5V I2C bus/logic power supply • Wiper resistance: 70Ω typical @ VCC = 3.3V • Power-on preset to mid-scale (64 tap position) • Extended industrial temperature range: -40°C to +125°C • 20 Ld TSSOP or 20 QFN packages • Pb-free (RoHS compliant) Applications • Power supply margining • Trimming sensor circuits • Gain adjustment in battery powered instruments • RF power amplifier bias compensation 10000 VREF 8000 RESISTANCE (Ω) 6000 1 DCP OF ISL23348 RH1 VREF_M 4000 RW1 + ISL28114 2000 RL1 0 0 32 64 TAP POSITION (DECIMAL) 96 128 FIGURE 1. FORWARD AND BACKWARD RESISTANCE vs TAP POSITION, 10kΩ DCP FIGURE 2. VREF ADJUSTMENT August 24, 2011 FN7903.1 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2011. All Rights Reserved Intersil (and design) and XDCP are trademarks owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners ISL23348 Block Diagram VLOGIC VCC RH0 WR0 VOLATILE REGISTER WR1 VOLATILE REGISTER WR2 VOLATILE REGISTER WR3 VOLATILE REGISTER SCL SDA A0 A1 A2 I/O BLOCK LEVEL SHIFTER RW0 RL0 RH1 RW1 RL1 RH2 RW2 RL2 RH3 RW3 RL3 POWER UP INTERFACE CONTROL AND STATUS LOGIC GND Pin Configurations ISL23348 (20 LD TSSOP) TOP VIEW RL0 RW0 VCC RH0 1 2 3 4 5 6 7 8 9 20 RL3 19 RW3 18 RH3 17 RL2 16 RW2 15 RH2 14 SCL 13 SDA 12 A2 11 A1 Pin Descriptions TSSOP 1 2 3 4 5 6 7 8 9 10 QFN 19 20 1 2 3 4 5 6 7 8 SYMBOL RL0 RW0 VCC RH0 RL1 RW1 RH1 GND VLOGIC A0 DESCRIPTION DCP0 “low” terminal DCP0 wiper terminal Analog power supply. Range 1.7V to 5.5V DCP0 “high” terminal DCP1 “low” terminal DCP1 wiper terminal DCP1 “high” terminal Ground pin I2C bus /logic supply. Range 1.2V to 5.5V Logic Pin - Hardwire slave address pin for I2C serial bus. Range: VLOGIC or GND Logic Pin - Hardwire slave address pin for I2C serial bus. Range: VLOGIC or GND Logic Pin - Hardwire slave address pin for I2C serial bus. Range: VLOGIC or GND Logic Pin - Serial bus data input/open drain output Logic Pin - Serial bus clock input DCP2 “high” terminal DCP2 wiper terminal DCP2 “low” terminal DCP3 “high” terminal DCP3 wiper terminal DCP3 “low” terminal RL1 RW1 RH1 GND VLOGIC A0 10 ISL23348 (20 LD QFN) TOP VIEW RW0 RL0 RL3 RW3 11 9 A1 20 VCC RH0 19 18 17 6 16 15 14 13 12 11 RH3 RL2 RW2 RH2 SCL 12 10 A2 1 2 3 4 5 6 7 VLOGIC 13 14 15 16 17 18 19 20 11 12 13 14 15 16 17 18 SDA SCL RH2 RW2 RL2 RH3 RW3 RL3 RL1 RW1 RH1 GND SDA 8 A0 9 A1 10 A2 2 FN7903.1 August 24, 2011 ISL23348 Ordering Information PART NUMBER (Notes 1, 2, 3) ISL23348TFVZ ISL23348UFVZ ISL23348WFVZ ISL23348TFRZ ISL23348UFRZ ISL23348WFRZ NOTES: 1. Add “-TK” suffix for 1k unit or “-T7A” suffix for 250 unit Tape and Reel options. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL23348. For more information on MSL please see techbrief TB363. PART MARKING 23348 TFVZ 23348 UFVZ 23348 WFVZ 348T 348U 348W RESISTANCE OPTION (kΩ) 100 50 10 100 50 10 TEMP RANGE (°C) -40 to +125 -40 to +125 -40 to +125 -40 to +125 -40 to +125 -40 to +125 PACKAGE (Pb-free) 20 Ld TSSOP 20 Ld TSSOP 20 Ld TSSOP 20 Ld 3x4 QFN 20 Ld 3x4 QFN 20 Ld 3x4 QFN PKG. DWG. # M20.173 M20.173 M20.173 L20.3x4 L20.3x4 L20.3x4 3 FN7903.1 August 24, 2011 ISL23348 Absolute Maximum Ratings Supply Voltage Range VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V VLOGIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V Voltage on Any DCP Terminal Pin . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V Voltage on Any Digital Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V Wiper Current IW (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA ESD Rating Human Body Model (Tested per JESD22-A114E) . . . . . . . . . . . . . . . . 6kV CDM Model (Tested per JESD22-A114E) . . . . . . . . . . . . . . . . . . . . . . . 1kV Machine Model (Tested per JESD22-A115-A) . . . . . . . . . . . . . . . . . 300V Latch Up (Tested per JESD-78B; Class 2, Level A) . . . . 100mA @ +125°C Thermal Information Thermal Resistance (Typical) θJA (°C/W) θJC (°C/W) 20 Ld TSSOP Package (Notes 4, 6) . . . . . . 85 33 20 Ld QFN Package (Notes 5, 7) . . . . . . . . 40 4 Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . .+150°C Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Recommended Operating Conditions Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C VCC Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.7V to 5.5V VLOGIC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2V to 5.5V DCP Terminal Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0 to VCC Max Wiper Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±3mA CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 4. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 5. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 6. For θJC, the “case temp” location is taken at the package top center. 7. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside. Analog Specifications VCC = 2.7V to 5.5V, VLOGIC = 1.2V to 5.5V over recommended operating conditions unless otherwise stated. Boldface limits apply over the operating temperature range, -40°C to +125°C. SYMBOL RTOTAL PARAMETER RH to RL Resistance W option U option T option RH to RL Resistance Tolerance End-to-End Temperature Coefficient W option U option T option VRH, VRL RW DCP Terminal Voltage Wiper Resistance VRH or VRL to GND RH - floating, VRL = 0V, force IW current to the wiper, IW = (VCC - VRL)/RTOTAL, VCC = 2.7V to 5.5V VCC = 1.7V CH/CL/CW TEST CONDITIONS MIN (Note 20) TYP (Note 8) 10 50 100 MAX (Note 20) UNITS kΩ kΩ kΩ -20 ±2 125 65 45 +20 % ppm/°C ppm/°C ppm/°C 0 70 580 32/32/32 -0.4 2V IOL = 1.5mA, VLOGIC < 2V 0.05 x VLOGIC 0.1 x VLOGIC 0 0.4 0.2 x VLOGIC 10 400 Any pulse narrower than the max spec is suppressed SCL falling edge crossing 30% of VLOGIC, until SDA exits the 30% to 70% of VLOGIC window SDA crossing 70% of VLOGIC during a STOP condition, to SDA crossing 70% of VLOGIC during the following START condition Measured at the 30% of VLOGIC crossing Measured at the 70% of VLOGIC crossing SCL rising edge to SDA falling edge; both crossing 70% of VLOGIC From SDA falling edge crossing 30% of VLOGIC to SCL falling edge crossing 70% of VLOGIC From SDA exiting the 30% to 70% of VLOGIC window, to SCL rising edge crossing 30% of VLOGIC From SCL falling edge crossing 70% of VLOGIC to SDA entering the 30% to 70% of VLOGIC window 1300 50 900 TYP (Note 8) MAX (Note 20) 0.3 x VLOGIC VLOGIC + 0.3 UNITS V V V V V V pF kHz ns ns ns VOL Cpin fSCL tsp tAA tBUF SDA, SCL Pin Capacitance SCL Frequency Pulse Width Suppression Time at SDA and SCL Inputs SCL Falling Edge to SDA Output Data Valid Time the Bus Must be Free Before the Start of a New Transmission Clock LOW Time Clock HIGH Time START Condition Set-up Time START Condition Hold Time Input Data Set-up Time tLOW tHIGH tSU:STA tHD:STA tSU:DAT 1300 600 600 600 100 ns ns ns ns ns tHD:DAT Input Data Hold Time 0 ns 7 FN7903.1 August 24, 2011 ISL23348 Serial Interface Specification SYMBOL tSU:STO tHD:STO tDH PARAMETER STOP Condition Set-up Time For SCL, SDA, A0, A1, A2 unless otherwise noted. (Continued) TEST CONDITIONS From SCL rising edge crossing 70% of VLOGIC, to SDA rising edge crossing 30% of VLOGIC MIN (Note 20) 600 1300 0 TYP (Note 8) MAX (Note 20) UNITS ns ns ns STOP Condition Hold Time for Read From SDA rising edge to SCL falling edge; both or Write crossing 70% of VLOGIC Output Data Hold Time From SCL falling edge crossing 30% of VLOGIC, until SDA enters the 30% to 70% of VLOGIC window. IOL = 3mA, VLOGIC > 2V. IOL = 0.5mA, VLOGIC < 2V From 30% to 70% of VLOGIC From 70% to 30% of VLOGIC Total on-chip and off-chip Before START condition After STOP condition tR tF Cb tSU:A tHD:A NOTES: SDA and SCL Rise Time SDA and SCL Fall Time Capacitive Loading of SDA or SCL A1, A0, A2 Setup Time A1, A0, A2 Hold Time 20 + 0.1 x Cb 20 + 0.1 x Cb 10 600 600 250 250 400 ns ns pF ns ns 8. Typical values are for TA = +25°C and 3.3V supply voltages. 9. LSB = [V(RW)127 – V(RW)0]/127. V(RW)127 and V(RW)0 are V(RW) for the DCP register set to 7f hex and 00 hex respectively. LSB is the incremental voltage when changing from one tap to an adjacent tap. 10. ZS error = V(RW)0/LSB. 11. FS error = [V(RW)127 – VCC]/LSB. 12. DNL = [V(RW)i – V(RW)i-1]/LSB-1, for i = 1 to 127. i is the DCP register setting. 13. INL = [V(RW)i – i • LSB – V(RW)0]/LSB for i = 1 to 127 Max ( V ( RW ) i ) – Min ( V ( RW ) i ) 14. for i = 16 to 127 decimal, T = -40°C to +125°C. Max( ) is the maximum value of the wiper voltage 10 6 TC V = ----------------------------------------------------------------------------- × --------------------V ( RW i ( +25°C ) ) +165°C and Min( ) is the minimum value of the wiper voltage over the temperature range. 15. MI = |RW127 – RW0|/127. MI is a minimum increment. RW127 and RW0 are the measured resistances for the DCP register set to 7f hex and 00 hex respectively. 16. Roffset = RW0/MI, when measuring between RW and RL. Roffset = RW127/MI, when measuring between RW and RH. 17. RDNL = (RWi – RWi-1)/MI -1, for i = 8 to 127. 18. RINL = [RWi – (MI • i) – RW0]/MI, for i = 8 to 127. for i = 8 to 127, T = -40°C to +125°C. Max( ) is the maximum value of the resistance and Min( ) is the [ Max ( Ri ) – Min ( Ri ) ] 10 TC R = ------------------------------------------------------ × --------------------Ri ( +25°C ) +165°C minimum value of the resistance over the temperature range. 20. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. 19. 21. It is preferable to ramp up both the VLOGIC and the VCC supplies at the same time. If this is not possible, it is recommended to ramp-up the VLOGIC first followed by the VCC. 22. VMATCH = [V(RWx)i - V(RWy)i]/LSB, for i = 1 to 127, x = 0 to 3 and y = 0 to 3. 23. RMATCH = (RWi,x - RWi,y)/MI, for i = 1 to 127, x = 0 to 3 and y = 0 to 3. 6 8 FN7903.1 August 24, 2011 ISL23348 DCP Macro Model RTOTAL RH RL CH 32pF CW 32pF RW CL 32pF Timing Diagrams SDA vs SCL Timing tF tHIGH tLOW tR tsp SCL tSU:STA SDA (INPUT TIMING) tSU:DAT tHD:DAT tSU:STO tHD:STA tAA SDA (OUTPUT TIMING) tDH tBUF A0, A1 and A2 Pin Timing START SCL CLK 1 STOP SDA tSU:A A0, A1, A2 tHD:A 9 FN7903.1 August 24, 2011 ISL23348 Typical Performance Curves 0.15 0.10 0.05 0.00 -0.05 -0.10 -0.15 0 32 64 TAP POSITION (DECIMAL) 96 128 DNL (LSB) 0.04 0.02 DNL (LSB) 0.00 -0.02   -0.04 0 32 64 TAP POSITION (DECIMAL) 96 128   FIGURE 3. 10kΩ DNL vs TAP POSITION, VCC = 3.3V, +25°C FIGURE 4. 50kΩ DNL vs TAP POSITION, VCC = 3.3V, +25°C 0.15 0.10 0.16 0.12 0.05 INL (LSB) INL (LSB) 0.00 -0.05 -0.10 -0.15 0 32 64 TAP POSITION (DECIMAL) 96 128 0.08 0.04 0.00   0 32 64 TAP POSITION (DECIMAL) 96 128   FIGURE 5. 10kΩ INL vs TAP POSITION, VCC = 3.3V, +25°C FIGURE 6. 50kΩ INL vs TAP POSITION, VCC = 3.3V, +25°C 0.15 0.10 0.04 0.02 0.05 RDNL (MI) RDNL (MI) 0.00 -0.05 -0.10 -0.15 0 32 64 TAP POSITION (DECIMAL) 96 128 0.00 -0.02 -0.04 0 32 64 TAP POSITION (DECIMAL) 96 128     FIGURE 7. 10kΩ RDNL vs TAP POSITION, VCC = 3.3V, +25°C FIGURE 8. 50kΩ RDNL vs TAP POSITION, VCC = 3.3V, +25°C 10 FN7903.1 August 24, 2011 ISL23348 Typical Performance Curves 0.30 0.25 0.04 0.20 RINL (MI) RINL (MI) (Continued) 0.08 0.15 0.10 0.00 -0.04 0.05 0.00 -0.08 0 32 64 TAP POSITION (DECIMAL) 96 128   0 32 64 TAP POSITION (DECIMAL) 96 128   FIGURE 9. 10kΩ RINL vs TAP POSITION, VCC = 3.3V, +25°C FIGURE 10. 50kΩ RINL vs TAP POSITION, VCC = 3.3V, +25°C 100 +25°C WIPER RESISTANCE (Ω) 120 +125°C WIPER RESISTANCE (Ω) 80 60 40 -40°C 20 0 0 32 64 TAP POSITION (DECIMAL) 96 128 100 80 60 40 20 0 +25°C +125°C -40°C   0 32 64 96 TAP POSITION (DECIMAL) 128   FIGURE 11. 10kΩ WIPER RESISTANCE vs TAP POSITION, VCC = 3.3V FIGURE 12. 50kΩ WIPER RESISTANCE vs TAP POSITION, VCC = 3.3V 200 40 150 TCv (ppm/°C) TCv (ppm/°C) 30 100 20 50 10 0 15 43 71 TAP POSITION (DECIMAL) 99 127 0   15 43 71 TAP POSITION (DECIMAL) 99 127   FIGURE 13. 10kΩ TCv vs TAP POSITION, VCC = 3.3V FIGURE 14. 50kΩ TCv vs TAP POSITION, VCC = 3.3V 11 FN7903.1 August 24, 2011 ISL23348 Typical Performance Curves 400 (Continued) 100 80 300 TCr (ppm/°C) TCr (ppm/°C) 60 40 20 0 200 100 0 15 43 71 99 TAP POSITION (DECIMAL) 127 15 43 71 TAP POSITION (DECIMAL) 99 127     FIGURE 15. 10kΩ TCr vs TAP POSITION FIGURE 16. 50kΩ TCr vs TAP POSITION, VCC = 3.3V 20 100 80 15 TCv (ppm/°C) TCr (ppm/°C) 60 40 20 0 10 5 0 15 43 71 TAP POSITION (DECIMAL) 99 127 15 43 71 TAP POSITION (DECIMAL) 99 127     FIGURE 17. 100kΩ TCv vs TAP POSITION, VCC = 3.3V FIGURE 18. 100kΩ TCr vs TAP POSITION, VCC = 3.3V CH1: 20mV/DIV, 2µs/DIV CH2: 2V/DIV, 2µs/DIV SCL CLOCK WIPER RW PIN SCL 9TH CLK OF THE DATA BYTE (ACK) CH1: 1V/DIV, 1µs/DIV CH2: 10mV/DIV, 1µs/DIV FIGURE 19. WIPER DIGITAL FEED-THROUGH FIGURE 20. WIPER TRANSITION GLITCH 12 FN7903.1 August 24, 2011 ISL23348 Typical Performance Curves 1V/DIV 0.2µs/DIV SCL SCL 9TH CLOCK OF THE DATA BYTE (ACK) (Continued) 0.5V/DIV 20µs/DIV VCC WIPER WIPER FIGURE 21. WIPER LARGE SIGNAL SETTLING TIME FIGURE 22. POWER-ON START-UP IN VOLTAGE DIVIDER MODE STANDBY CURRENT ICC (µA) CH1: RH TERMINAL CH2: RW TERMINAL 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 -40 -15 10 35 60 85 110 VCC = 1.7V, VLOGIC = 1.2V VCC = 5.5V, VLOGIC = 5.5V 0.5V/DIV, 0.2µs/DIV -3dB FREQUENCY = 1.437MHz AT MIDDLE TAP TEMPERATURE (°C) FIGURE 23. 10kΩ -3dB CUT OFF FREQUENCY FIGURE 24. STANDBY CURRENT vs TEMPERATURE Functional Pin Descriptions Potentiometers Pins RHI AND RLI The high (RHi, i = 0, 1, 2, 3) and low (RLi, i = 0, 1, 2, 3) terminals of the ISL23348 are equivalent to the fixed terminals of a mechanical potentiometer. RHi and RLi are referenced to the relative position of the wiper and not the voltage potential on the terminals. With WRi set to 127 decimal, the wiper will be closest to RHi, and with the WRi set to 0, the wiper is closest to RLi. Bus Interface Pins SERIAL DATA INPUT/OUTPUT (SDA) The SDA is a bidirectional serial data input/output pin for I2C interface. It receives device address, wiper address and data from an I2C external master device at the rising edge of the serial clock SCL, and it shifts out data after each falling edge of the serial clock. SDA requires an external pull-up resistor, since it is an open drain input/output. RWI RWi (i = 0, 1, 3) is the wiper terminal, and it is equivalent to the movable terminal of a mechanical potentiometer. The position of the wiper within the array is determined by the WRi register. SERIAL CLOCK (SCL) This input is the serial clock of the I2C serial interface. SCL requires an external pull-up resistor, since a master is an open drain output. VCC Power terminal for the potentiometer section analog power source. Can be any value needed to support the voltage range of the DCP pins, from 1.7V to 5.5V, independent of the VLOGIC voltage. 13 DEVICE ADDRESS (A2, A1, A0) The address inputs are used to set the least significant 3 bits of the 7-bit I2C interface slave address. A match in the slave address serial data stream must match with the Address input FN7903.1 August 24, 2011 ISL23348 pins in order to initiate communication with the ISL23348. A maximum of eight ISL23348 devices may occupy the I2C serial bus (see Table 3). Memory Description The ISL23348 contains five volatile 8-bit registers: Wiper Register WR0, Wiper Register WR1, Wiper Register WR2, Wiper Register WR3 and Access Control Register (ACR). The memory map of ISL23348 is shown in Table 1. The Wiper Register WRi at address i contains current wiper position of DCPi (i = 0, 1, 2, 3). The Access Control Register (ACR) at address 10h contains information and control bits described in Table 2. TABLE 1. MEMORY MAP ADDRESS (hex) 10 3 2 1 0 VOLATILE REGISTER NAME ACR WR3 WR2 WR1 WR0 TABLE 2. ACCESS CONTROL REGISTER (ACR) BIT # NAME/ VALUE 7 0 6 SHDN 5 0 4 0 3 0 2 0 1 0 0 0 DEFAULT SETTING (hex) 40 40 40 40 40 VLOGIC Digital power source for the logic control section. It supplies an internal level translator for 1.2V to 5.5V serial bus operation. Use the same supply as the I2C logic source. Principles of Operation The ISL23348 is an integrated circuit incorporating four DCPs with its associated registers and an I2C serial interface providing direct communication between a host and the potentiometer. The resistor array is comprised of individual resistors connected in series. At either end of the array and between each resistor is an electronic switch that transfers the potential at that point to the wiper. The electronic switches on the device operate in a “make-before-break” mode when the wiper changes tap positions. Voltage at any of the DCP pins, RHi, RLi or RWi, should not exceed VCC level at any conditions during power-up and normal operation. The VLOGIC pin is the terminal for the logic control digital power source. It should use the same supply as the I2C logic source, which allows reliable communication with a wide range of microcontrollers and is independent from the VCC level. This is extremely important in systems where the master supply has lower levels than the DCP analog supply. Shutdown Function The SHDN bit (ACR[6]) disables or enables shutdown mode for all DCP channels simultaneously. When this bit is 0, i.e., DCP is forced to end-to-end open circuit and RW is connected to RL through a 2kΩ serial resistor, as shown in Figure 25. The default value of the SHDN bit is 1. RH DCP Description Each DCP is implemented with a combination of resistor elements and CMOS switches. The physical ends of each DCP are equivalent to the fixed terminals of a mechanical potentiometer (RHi and RLi pins). The RWi pin of the DCP is connected to intermediate nodes, and is equivalent to the wiper terminal of a mechanical potentiometer. The position of the wiper terminal within the DCP is controlled by an 8-bit volatile Wiper Register (WRi). When the WRi of a DCP contains all zeroes (WRi[7:0] = 00h), its wiper terminal (RW) is closest to its “Low” terminal (RLi). When the WRi register of a DCP contains all ones (WRi[7:0] = 7fh), its wiper terminal (RWi) is closest to its “High” terminal (RHi). As the value of the WRi increases from all zeroes (0) to all ones (127 decimal), the wiper moves monotonically from the position closest to RLi to the position closest to RHi. At the same time, the resistance between RWi and RLi increases monotonically, while the resistance between RHi and RWi decreases monotonically. While the ISL23348 is being powered up, all the wipers (WRi) are reset to 40h (64 decimal), which positions RWi at the center between RLi and RHi. The WRi can be read or written to directly using the I2C serial interface as described in the following sections. RW 2kΩ RL FIGURE 25. DCP CONNECTION IN SHUTDOWN MODE When the device enters shutdown, all current DCP WRi settings are maintained. When the device exits shutdown, the wipers will return to the previous WRi settings after a short settling time (see Figure 26). In shutdown mode, if there is a glitch on the power supply which causes it to drop below 1.3V for more than 0.2µs to 0.4µs, the wipers will be RESET to their mid positions. This is done to avoid an undefined state at the wiper outputs. 14 FN7903.1 August 24, 2011 ISL23348 All I2C interface operations must begin with a START condition, which is a HIGH-to-LOW transition of SDA while SCL is HIGH. The ISL23348 continuously monitors the SDA and SCL lines for the START condition and does not respond to any command until this condition is met (see Figure 27). A START condition is ignored during the power-up of the device. All I2C interface operations must be terminated by a STOP condition, which is a LOW to HIGH transition of SDA while SCL is HIGH (see Figure 27). A STOP condition at the end of a read operation or at the end of a write operation places the device in its standby mode. An ACK (Acknowledge) is a software convention used to indicate a successful data transfer. The transmitting device, either master or slave, releases the SDA bus after transmitting eight bits. During the ninth clock cycle, the receiver pulls the SDA line LOW to acknowledge the reception of the eight bits of data (see Figure 28). The ISL23348 responds with an ACK after recognition of a START condition followed by a valid Identification Byte, and once again after successful receipt of an Address Byte. The ISL23348 also responds with an ACK after receiving a Data Byte of a write operation. The master must respond with an ACK after receiving a Data Byte of a read operation. A valid Identification Byte contains 1010 as the four MSBs, and the following three bits are matching the logic values present at pins A2, A1 and A0. The LSB is the Read/Write bit. Its value is “1” for a Read operation and “0” for a Write operation (see Table 3). TABLE 3. IDENTIFICATION BYTE FORMAT LOGIC VALUES AT PINS A2, A1 AND A0 RESPECTIVELY WIPER VOLTAGE, VRW (V) POWER-UP MID SCALE = 80H AFTER SHDN USER PROGRAMMED SHDN ACTIVATED SHDN RELEASED WIPER RESTORE TO THE ORIGINAL POSITION SHDN MODE 0 TIME (s) FIGURE 26. SHUTDOWN MODE WIPER RESPONSE I2C Serial Interface The ISL23348 supports an I2C bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master always initiates data transfers and provides the clock for both transmit and receive operations. Therefore, the ISL23348 operates as a slave device in all applications. All communication over the I2C interface is conducted by sending the MSB of each byte of data first. Protocol Conventions Data states on the SDA line must change only during SCL LOW periods. SDA state changes during SCL HIGH are reserved for indicating START and STOP conditions (see Figure 27). On power-up of the ISL23348, the SDA pin is in the input mode. 1 (MSB) 0 1 0 A2 A1 A0 R/W (LSB) SCL SDA START DATA STABLE DATA CHANGE DATA STABLE STOP FIGURE 27. VALID DATA CHANGES, START AND STOP CONDITIONS 15 FN7903.1 August 24, 2011 ISL23348 SCL FROM MASTER 1 8 9 SDA OUTPUT FROM TRANSMITTER HIGH IMPEDANCE SDA OUTPUT FROM RECEIVER START HIGH IMPEDANCE ACK FIGURE 28. ACKNOWLEDGE RESPONSE FROM RECEIVER SIGNALS FROM THE MASTER S T A R T WRITE IDENTIFICATION BYTE ADDRESS BYTE DATA BYTE S T O P SIGNAL AT SDA SIGNALS FROM THE SLAVE 1 0 1 0 A2 A1 A0 0 A C K 000 A C K A C K FIGURE 29. BYTE WRITE SEQUENCE SIGNALS FROM THE MASTER S T A R T IDENTIFICATION BYTE WITH R/W = 0 ADDRESS BYTE S READ T IDENTIFICATION A BYTE WITH R R/W = 1 T A C K A C K S AT CO KP SIGNAL AT SDA 1 0 1 0 A2 A1 A0 0 A C K 000 A C K 1 0 1 0 A2 A1 A0 1 A C K SIGNALS FROM THE SLAVE FIRST READ DATA BYTE LAST READ DATA BYTE FIGURE 30. READ SEQUENCE Write Operation A Write operation requires a START condition, followed by a valid Identification Byte, a valid Address Byte, a Data Byte, and a STOP condition. After each of the three bytes, the ISL23348 responds with an ACK. The data is transferred from I2C block to the corresponding register at the 9th clock of the data byte and device enters its standby state (see Figures 28 and 29). It is possible to perform a sequential Write to all DCP channels via a single Write operation. The command is initiated by sending an additional Data Byte after the first Data byte instead of sending a STOP condition. Read Operation A Read operation consists of a three byte instruction followed by one or more Data Bytes (see Figure 30). The master initiates the operation issuing the following sequence: a START, the Identification byte with the R/W bit set to “0”, an Address Byte, a second START, and a second Identification byte with the R/W bit set to “1”. After each of the three bytes, the ISL23348 responds with an ACK; then the ISL23348 transmits Data Byte. The master terminates the read operation issuing a NACK (ACK) and a STOP condition following the last bit of the last Data Byte (see Figure 30). 16 FN7903.1 August 24, 2011 ISL23348 Applications Information VLOGIC Requirements VLOGIC should be powered continuously during normal operation. In a case where turning VLOGIC OFF is necessary, it is recommended to ground the VLOGIC pin of the ISL23348. Grounding the VLOGIC pin or both VLOGIC and VCC does not affect other devices on the same bus. It is good practice to put a 1µF cap in parallel to 0.1µF as close to the VLOGIC pin as possible. Wiper Transition When stepping up through each tap in voltage divider mode, some tap transition points can result in noticeable voltage transients, or overshoot/undershoot, resulting from the sudden transition from a very low impedance “make” to a much higher impedance “break” within a short period of time (