ISL23418

Single, 128-Tap, Low Voltage Digitally Controlled Potentiometer (XDCP™) ISL23418 The ISL23418 is a volatile, low voltage, low noise, low power, SPI™ bus, 128 taps, single digitally controlled potentiometer (DCP), which integrates DCP core, wiper switches, and control logic on a monolithic CMOS integrated circuit. The digitally controlled potentiometer is implemented with a combination of resistor elements and CMOS switches. The position of the wiper is controlled by the user through the SPI bus interface. The potentiometer has an associated volatile Wiper Register (WR) that can be directly written to and read by the user. The contents of the WR controls the position of the wiper. When powered on, the ISL23418 wiper always commences at mid-scale (64-tap position). The low voltage, low power consumption, and small package size of the ISL23418 make it an ideal choice for use in battery operated equipment. The ISL23418 has a VLOGIC pin allowing down to 1.2V bus operation, independent from the VCC value. This allows for low logic levels to be connected directly to the ISL23418 without passing through a voltage level shifter. The DCP can be used as a three-terminal potentiometer or as a two-terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing. Features • 128 Resistor Taps • SPI Serial Interface - No Additional Level Translator for Low Bus Supply - Daisy Chaining of Multiple DCP • Wiper Resistance: 70Ω Typical @ VCC = 3.3V • Shutdown Mode: Forces DCP into End-to-end Open Circuit; RW Shorted to RL Internally • Power-on Preset to Mid-scale (64-tap Position) • Shutdown and Standby Current DCP2 --> ... --> DCP(N-1). The write instruction is executed on the rising edge of CS for all N DCPs simultaneously. VLOGIC Requirements Keeping VLOGIC powered all the time during normal operation is recommended. In cases in which turning VLOGIC OFF is necessary, grounding the VLOGIC pin is recommended. Grounding the VLOGIC pin or both VLOGIC and VCC does not affect other devices on the same bus. It is good practice to put a 1µF capacitor in parallel with a 0.1µF decoupling capacitor close to the VLOGIC pin. Daisy Chain Read Operation The read operation consists of two parts. First, the read instructions (N two-byte operations) are sent with a valid address. Second, the requested data is read while sending NOP instructions (N two-byte operations), as shown in Figures 31 and 32. VCC Requirements and Placement Putting a 1µF capacitor in parallel with a 0.1µF decoupling capacitor close to the VCC pin is recommended. N DCP IN A CHAIN CS SCK MOSI MISO µC CS SCK SDI SDO DCP0 CS SCK SDI SDO DCP1 CS SCK SDI SDO DCP2 DCP(N-1) CS SCK SDI SDO FIGURE 29. DAISY CHAIN CONFIGURATION 16 FN7901.0 August 3, 2011 ISL23418 CS SCK 16 CLKLS SDI SDO 0 SDO 1 WR D C P2 16 CLKS WR WR D C P1 D C P2 WR WR WR 16 CLKS D C P0 D C P1 D C P2 SDO 2 FIGURE 30. DAISY CHAIN WRITE SEQUENCE OF N = 3 DCP CS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 SCK SDI INSTRUCTION ADDR DATA IN SDO DATA OUT FIGURE 31. TWO-BYTE READ INSTRUCTION CS SCK 16 CLKS SDI RD DCP2 16 CLKS RD DCP1 16 CLKS RD DCP0 16 CLKS NOP 16 CLKS NOP 16 CLKS NOP SDO DCP2 OUT DCP1 OUT DCP0 OUT FIGURE 32. DAISY CHAIN READ SEQUENCE OF N = 3 DCP 17 FN7901.0 August 3, 2011 ISL23418 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest revision. DATE 8/3/2011 REVISION FN7901.0 Initial Release CHANGE Products Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a complete list of Intersil product families. For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on intersil.com: ISL23418 To report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff FITs are available from our website at: http://rel.intersil.com/reports/search.php For additional products, see www.intersil.com/product_tree Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 18 FN7901.0 August 3, 2011 ISL23418 Mini Small Outline Plastic Packages (MSOP) N M10.118 (JEDEC MO-187BA) 10 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE E1 -BE INCHES SYMBOL MIN 0.037 0.002 0.030 0.007 0.004 0.116 0.116 MAX 0.043 0.006 0.037 0.011 0.008 0.120 0.120 MILLIMETERS MIN 0.94 0.05 0.75 0.18 0.09 2.95 2.95 MAX 1.10 0.15 0.95 0.27 0.20 3.05 3.05 NOTES 9 3 4 6 7 15o 6o Rev. 0 12/02 INDEX AREA A ABC 12 TOP VIEW 0.20 (0.008) A1 A2 4X θ 0.25 (0.010) GAUGE PLANE SEATING PLANE -C- R1 R b c D E1 A A2 4X θ L L1 e E L 0.020 BSC 0.187 0.016 0.199 0.028 0.50 BSC 4.75 0.40 5.05 0.70 A1 -He D b 0.10 (0.004) -A0.20 (0.008) C SEATING PLANE L1 N R 0.037 REF 10 0.003 0.003 5o 0o 15o 6o 0.95 REF 10 0.07 0.07 5o 0o C a C L E1 C R1 θ SIDE VIEW α -B- 0.20 (0.008) CD END VIEW NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-187BA. 2. Dimensioning and tolerancing per ANSI Y14.5M-1994. 3. Dimension “D” does not include mold flash, protrusions or gate burrs and are measured at Datum Plane. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E1” does not include interlead flash or protrusions and are measured at Datum Plane. - H - Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. Formed leads shall be planar with respect to one another within 0.10mm (.004) at seating Plane. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Datums -A -H- . and - B to be determined at Datum plane 11. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only 19 FN7901.0 August 3, 2011 ISL23418 Package Outline Drawing L10.2.1x1.6A 10 LEAD ULTRA THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 5, 3/10 8. PIN 1 INDEX AREA 2.10 B 1 A PIN #1 ID 8. 0.10 MIN. 1.60 10 1 0.05 MIN. 4 4X 0.20 MIN. 5 0.80 0.10 2X TOP VIEW BOTTOM VIEW 9 6X 0.50 6 10 X 0.20 4 0.10 M C A B MC SEE DETAIL "X" PACKAGE OUTLINE MAX. 0.55 0.10 C C (0.10 MIN.) (2.00) SIDE VIEW (1.30) SEATING PLANE 0.08 C 10X 0.40 (10 X 0.20) (0.05 MIN) 1 (10X 0.60) (0.80) C (6X 0.50 ) (2.50) 0 . 125 REF 0-0.05 TYPICAL RECOMMENDED LAND PATTERN DETAIL "X" NOTES: 1. 2. 3. 4. Dimensioning and tolerancing conform to ASME Y14.5M-1994. All Dimensions are in millimeters. Angles are in degrees. Dimensions in ( ) for Reference Only. Unless otherwise specified, tolerance : Decimal ± 0.05 Lead width dimension applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. Maximum package warpage is 0.05mm. Maximum allowable burrs is 0.076mm in all directions. Same as JEDEC MO-255UABD except: No lead-pull-back, MIN. Package thickness = 0.45 not 0.50mm Lead Length dim. = 0.45mm max. not 0.42mm. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 5. 6. 7. 8. 20 FN7901.0 August 3, 2011