ISL24006IRZ-T7

® ISL24006 Data Sheet March 9, 2006 FN6110.1 14-Channel Programmable Switchable I2C TFT-LCD Reference Voltage Generator with Integrated 4-Channel Static Gamma Drivers The ISL24006 is a 14-channel programmable switchable reference voltage generator with four channels of static gamma drivers integrated, for a complete 18-channel total gamma solution for TFT-LCD displays. The 14-channel programmable switchable configuration allows switching between two gamma curves. The ISL24006 is divided into two banks of seven generators: one designed to cover the range from VREFL_L to VREFL_H; the remaining seven channels covering the range from VREFU_L to VREFU_H. Each bank has its own separate high and low reference inputs, with integrated buffers (four static gamma drivers) to drive the column driver internal DAC resistor string to within 0.2V from the top and bottom rails. An output MUX is used to switch between the two curves in less than 1µs. Switching is controlled using an external select pin. ISL24006 includes an I2C interface for programming the offset values. Features • 14-channel programmable switchable • 4-channel static • Fast switch time (< 1µs) • Programmable with 20mV resolution • Digital supply 3.3V to 5V • Supply current of 32mA (without load) • Rail-to-Rail capability • I2C interface • Pb-free plus anneal available (RoHS compliant) Applications • TFT-LCD drive circuits • Reference voltage generators Pinout ISL24006 (38-PIN QFN) TOP VIEW 38 OUT1 37 OUT2 36 OUT3 35 OUT4 34 OUT5 33 OUT6 32 OUT7 31 OUT_REFU_L 30 GND 29 BG 28 GND 27 VREFL_L THERMAL PAD 26 VREFL_H 25 NC 24 NC 23 VREFU_L 22 VREFU_H 21 AVDD 20 OUT_REFL_H OUT14 13 OUT13 14 OUT12 15 OUT11 16 OUT10 17 OUT9 18 OUT8 19 ISL24006 is available in the 38-pin QFN package and is specified for operation over the -40°C to +85°C temperature range. Ordering Information PART NUMBER ISL24006IRZ (See Note) ISL24006IRZ-T7 (See Note) PART MARKING ISL24006IRZ ISL24006IRZ TAPE & REEL PACKAGE 7” 13” PKG. DWG. # OUT_REFU_H 1 AVDD 2 STD_REG 3 A0 4 SDA 5 SCL 6 OSC 7 DVDD 8 BANK_SEL 9 NC 10 GND 11 OUT_REFL_L 12 38-Pin QFN MDP0046 (Pb-Free) 38-Pin QFN MDP0046 (Pb-Free) 38-Pin QFN MDP0046 (Pb-Free) ISL24006IRZ-T13 ISL24006IRZ (See Note) NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2005, 2006. All Rights Reserved. All other trademarks mentioned are the property of their respective owners. ISL24006 Absolute Maximum Ratings (TA = 25°C) Supply Voltage between AVDD and GND . . . . . . . . . . . . . . . . .+18V Supply Voltage between DVDD and GND lesser of VS or +7V (max) Maximum Continuous Output Current [VREFU_H, VREFU_L, VREFL_H, VREFL_L] . . . . . . . . . . . . . 60mA [OUT1 to OUT14] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30mA Total Sourcing/Sink [Upper/Lower] . . . . . . . . . . . . . . . . . . 180mA Operating Temperature . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . +125°C Lead Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +260°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. The device outputs cannot withstand shortcircuit condition for extended periods of time. To avoid damage, do not exceed absolute maximum rating of 20mA/channel. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA Electrical Specifications PARAMETER SUPPLY IAVDD IDVDD ANALOG VOH VOL VOH VOL PSRR VAC IB REG BG SR tS DIGITAL VIH VIL FCLK RSDIN tS tH OUT1 to OUT7 OUT1 to OUT7 OUT8 to OUT14 OUT8 to OUT14 Supply Current AVDD = 15V, DVDD = 5V, VREFU_H = 14V, VREFU_L = 8.5V, VREFL_H = 6.5V, VREFL_L = 1V, RL = 1kΩ and CL = 10pF to 1/2 AVDD, TA = 25°C, unless otherwise specified. CONDITIONS MIN TYP MAX UNIT DESCRIPTION No load 30 2.75 38 4 mA mA Digital Supply Current VREFU_H = 14V, AVDD = 15V VREFU_L = 8.5V, AVDD = 15V VREFL_H = 6.5V, AVDD = 15V VREFL_L = 1.0V, AVDD = 15V AVDD is moved from 14V to 16V 13.94 8.47 6.44 0.96 42 -50 13.98 8.51 6.48 1.00 50 0 2 0.5 14.02 8.55 6.52 1.04 V V V V dB Power Supply Rejection Ratio Accuracy Input Bias Current, VREF(U_H, U_L, L_H, L_L) Load Regulation Band Gap Slew Rate Settling Time +50 50 mV nA mV/mA VREF = 1/2 AVDD IOUT = 5mA step 1.1 8 ±1/2 LSB 1.3 15 1 1.4 V V/µs µs Logic 1 Input Voltage Logic 0 Input Voltage Clock Frequency SDIN Input Resistance Setup Time Hold Time SCL, SDA, STD_REG DVDD20% 20%* DVDD 400 1 40 40 V V kHz GΩ ns ns 2 FN6110.1 March 9, 2006 ISL24006 Block Diagram VREFU_L VREFU_H OSC C3 CONTROL C0 C1 C2 INT/EXT OSCILLATOR DELAY OUT REFU_H 0 1 S/H S/H S/H S/H S/H S/H S/H S/H S/H S/H B S/H S/H BANKA HI DAC HI S/H S/H MUX OUT7 MUX OUT6 MUX OUT5 MUX OUT4 MUX OUT3 MUX OUT2 MUX OUT1 MUX SCL SDA I2C INTERFACE MUX B S/H BANKA LO MUX S/H S/H S/H S/H MUX S/H S/H S/H S/H MUX MUX S/H S/H S/H MUX MUX S/H MUX OUT REFU_L OUT REFL_H STD_REG A0 OUT8 OUT9 OUT10 OUT11 OUT12 OUT13 OUT14 DAC LO AVDD ANALOG POWER DVDD DIGITAL POWER BG REFERENCE GENERATOR S/H OUT REFL_L VREFL_H VREFL_L BANK_SEL 3 FN6110.1 March 9, 2006 ISL24006 Pin Descriptions PIN NUMBER 1 2, 21 3 4 5 6 7 8 9 10, 24, 25 28, 30, 11 12 13, 14, 15, 16, 17, 18, 19 20 22 23 26 27 29 31 32, 33, 34, 35, 36, 37, 38 PIN NAME OUT REFU_H AVDD STD_REG A0 SDA SCL OSC DVDD BANK_SEL NC GND OUT REFL_L OUT8 - OUT14 OUT REFL_H VREFU_H VREFU_L VREFL_H VREFL_L BG OUT REFU_L OUT1 - OUT7 GND Analog Output Analog Output Analog Output Reference Reference Reference Reference Analog Bypass Pin Analog Output Analog Output PIN TYPE Analog Output Analog Power Logic Input Logic Input Input/Output Logic Input Input/Output Digital Power Digital Signal Analog output of VREFU_H Power supply for analog circuit Selects mode, high = standard, low = register I2C device address input, bit 0; when LO, hex address = 74; when HI, hex address = 75 I2C data I2C clock Input clock reference Power supply for digital circuit Select one of two sets of gamma voltages Not connected Ground Analog output of VREFL_L Analog output voltages in lower range Analog output of VREFL_H High reference for upper seven output voltages Low reference for upper seven output voltages High reference for lower seven output voltages Low reference for lower seven output voltages Decoupling capacitor for internal reference generator Analog output of VREFU_L Analog output voltages in upper range PIN FUNCTION Typical Performance Curves JEDEC JESD51-7 - HIGH EFFECTIVE THERMAL CONDUCTIVITY (4-LAYER) TEST BOARD 4.5 4 POWER DISSIPATION (W) 3.5 3 3.33W 2.5 2 1.5 1 0.5 0 0 25 50 75 85 100 AMBIENT TEMPERATURE (°C) 125 150 QFN38 30°C/W POWER DISSIPATION (W) QFN EXPOSED DIEPAD SOLDERED TO PCB PER JESD51-5 JEDEC JESD51-3 (2- LAYER) TEST BOARD 1.2 1 0.8 0.6 0.4 0.2 0 0 QFN38 125°C/W 0.8W 25 50 75 85 100 AMBIENT TEMPERATURE (°C) 125 150 FIGURE 1. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE FIGURE 2. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE 4 FN6110.1 March 9, 2006 STANDARD MODE (STD/REG=HIGH) WRITE MODE I2C DATA Start Device Address W A = don't care Control Byte A Data 1 A Data 2 A Data 3 Data 12 14 A Stop I2C SDA In A6 A5 A4 A3 A2 A1 A0 W A C7 C6 C5 C4 C3 C2 C1 C0 A D7 D6 D5 D4 D3 D2 D1 D0 A D7 D6 D5 D4 D3 D2 D1 D0 A D7 D6 D5 D2 D1 D0 A I2C SDA Out A A A A A 5 I2C CLK In 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 6 7 8 9 STANDARD MODE (STD/REG=HIGH) READ MODE I2C DATA Start Device Address R A Data 1 A Data 2 A Data 3 Data 14 12 NA Stop NA I2C SDA In A6 A5 A4 A3 A2 A1 A0 R A A A I2C SDA Out A D7 D6 D5 D4 D3 D2 D1 D0 A D7 D6 D5 D4 D3 D2 D1 D0 A D7 D6 D5 D2 D1 D0 A ISL24006 I2C CLK In 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 6 7 8 9 REGISTER MODE (STD/REG=LO) WRITE MODE I2C DATA Start Device Address W A Register Address A DATA A STOP I2C SDA In A6 A5 A4 A3 A2 A1 A0 W A X X X X R3 R2 R1 R0 A D7 D6 D5 D4 D3 D2 D1 D0 A I2C SDA Out A A A I2C CLK In 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 REGISTER MODE (STD/REG=LO) READ MODE I2C DATA Start Device Address W A Register Address A Device Address R A DATA A STOP I2C SDA In A6 A5 A4 A3 A2 A1 A0 W A X X X X R3 R2 R1 R0 A A6 A5 A4 A3 A2 A1 A0 R A NA I2C SDA Out A A A D7 D6 D5 D4 D3 D2 D1 D0 A I2C CLK In 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 FIGURE 3. I2C TIMING DIAGRAM 1 FN6110.1 March 9, 2006 ISL24006 General Description The ISL24006 provides a versatile method of providing the reference voltages that are used in setting the transfer characteristics of LCD display panels. The V/T (Voltage/Transmission) curve of the LCD panel requires that a correction is applied to make it linear. However, if the panel is to be used in more than one application, the final curve may differ for different applications. By using the ISL24006, the V/T curve can be changed to optimize its characteristics according to the required application of the display product. Each of the 14 reference voltage outputs can be set with a 8bit resolution. The first half of the output buffers, OUT1 to OUT7 can be operated from VREFU_L to VREFU_H. The second half OUT8 to OUT14 can swing from VREFL_L to VREFL_H. It is also possible to use the ISL24006 for applications other than LCDs where multiple voltage references are required that can be set to 8-bit accuracy. Byte Format Every byte put along the SDA line must be eight bits long. The number of bytes that can be transmitted between a Start and Stop condition is unrestricted. Data is always transferred with the most significant bit (MSB) first. Acknowledge Each byte is followed by an acknowledge bit. When a master device is sending data (WRITE) the master puts a resistive high level on the SDA line during the acknowledge clock pulse. The peripheral that acknowledges, which is the receiver, has to pull down the SDA line during the acknowledge pulse. When a master device is receiving data (READ) the slave puts a resistive high level on the SDA line during the acknowledge clock pulse. The master will acknowledge by pulling down the SDA line during the acknowledge pulse. Not Acknowledge A Not Acknowledge (NA) is when the receiver does not pull down the SDA line during the acknowledge pulse: SDA line remains in the HI or in a high impedance state. A Not Acknowledge is the master device's signal to the slave device to release the SDA line so the master device can generate a Stop signal on the same line. The NA indicates that data just received is the last byte of the data transfer. Digital Interface The ISL24006 uses a simple two-wire I2C interface to program all 14 outputs. The bus line SCLK is the clock signal line and bus SDA is the bi-directional data information signal line. The ISL24006 can support a clock rate up to 400kHz. An external pull up typically 1kΩ resistor is required for each bus line. Start and Stop Condition A Start condition is a high to low transition on the serial data line (SDA) line while the serial clock line (SCLK) holds high. The Stop condition is a low to high transition on the SDA line while SCLK is high. The master device always generates Start and Stop conditions. The bus is considered to be busy after the Start condition and to be free at a certain time interval after the Stop condition. The two bus lines must be high when the buses are not in use. The I2C Timing Diagram 2 (Figure 2) shows the format. Standard Mode When pin #6 (STD_REG) is pulled high, the part operates in Standard Mode, which is more commonly used than the Register Mode. In the Standard Mode, the user can program all outputs in one data stream or transfer frame. For the Standard Mode in a WRITE transfer, a master device sends data to program all the output buffers of the ISL24006. The input data byte (DATA 1) to the first channel (OUT1) is the third byte following the control byte. The second channel (OUT2) is programmed by the fourth byte (DATA 2), and so on. Each byte is followed by an acknowledge bit. Data Validity The data on the SDA line must be stable (clearly defined as HI or LO) during the HI period of the clock signal. SDA transition can only change when the clock signal on the SCLK line is LO. g g Data Clocked in Stop Condition Start, Stop and Timing Details of I2C Interface Start Condition SDA DATA SCL CLOCK tS tH tS tH tR tF FIGURE 4. I2C TIMING DIAGRAM 2 6 FN6110.1 March 9, 2006 ISL24006 TABLE 1. STANDARD MODE WRITE TRANSFER S ISL24006 ADDRESS + W A CONTROL BYTE A DATA 1 A DATA 2 A ... DATA 14 A P S = Start condition P = Stop condition A = Acknowledge bit CONTROL BYTE = multifunction control DATA 1 = 8-bit input to DAC OUT1 DATA 2 = 8-bit input to DAC OUT2 DATA 14 = 8-bit input to DAC OUT14 For the Standard mode in a READ transfer, a master device accepts data from the ISL24006. The output data byte (DATA 1) of the first channel (OUT1) is the second byte of the transfer. OUT2 output data byte is the third byte of the transfer, and so forth and so on. The ISL24006 sends an acknowledge bit after every eighth bit to tell the master device that the ISL24006 is ready to send another byte. Consequently, the master must send a Not Acknowledge, (NA) at the end of the 14th data byte to tell ISL24006 to release the SDA bus. TABLE 2. Standard Mode READ Transfer S ISL24006 ADDRESS + R A DATA 1 A DATA 2 A ... A = Acknowledge NA = Not Acknowledge DATA 1 = 8-bit input to DAC OUT1 DATA 2 = 8-bit input to DAC OUT2 DATA 14 = 8-bit input to DAC OUT14 DATA 14 program a desired reference voltage. A "1" indicates a Read transmission; the master device will receive data from the ISL24006 to read the previous data the voltage reference was set or programmed. Control Byte The multi-function control byte contains information that selects the memory bank (bankA, or bankB), and operation (output, read, or write). It also controls the OSC pin function (external or internal). TABLE 3. Control Byte C7 C6 X C5 X C4 X C3 0 C2 0 C1 0 C0 0 P C0 X S = Start condition P = Stop condition = "0" bypass oscillator = "1" 3.5µs lagging C1 = "0" write data to bankA (default) = "1" write data to bankB C2 = "0" read data from bankA (default) = "1" read data from bankB See Timing Diagram 1 (Figure 1) for detailed formats. Devices Address and W/R Bit Data transfers follow the format shown in Timing Diagram 1. After the Start condition, a first byte is sent which contains the Device Address and write/read bit. This address is a 7-bit long device address and only two device addresses hex (74) and hex (75) in binary, bin (111010) and bin (111011) are allowed for the ISL24006. The first 6 bits (A6 to A1, MSBs) of the device address have been factory programmed and are always 111010. Only the least significant bit (LSB) A0 is allowed to change the logic state. This LSB is controlled externally on the pin #4, A0. When pulled high to DVDD, the LSB of the device address is high and thus the address is hex (75) or in binary bin (1110101). When pulled low to GND, the LSB of the device address low and thus the address is hex (74) or in binary 1110100. Since the device address has to be unique in the I2C bus line, a maximum of two ISL24006 may be used on the same bus at one time. The ISL24006 monitors the bus continuously and waiting for the Start condition followed by the device address. When the device recognizes its device address, it will start to accept data. The eighth bit (W/R) following the device address indicates the data direction. A "0" is a Write transmission; a master device will send data to the ISL24006 to set or 7 C3 = "0" internal oscillator (default) = "1" external oscillator The second bit, C1, selects which bank to write to. A "0" selects bankA. A "1" selects bankB. C1 is a "don't care" on a read mode. The third bit, C2, selects which bank to read from. A "0" selects bankA. A "1" selects bankB. C2 is a "don't care" on a write mode. The fourth bit, C3, selects the function of the OSC pin. A "0" selects the internal oscillator. When the internal oscillator is selected, the OSC pin acts as an output pin. It generates a square wave with a frequency of typically 20kHz where multiple chips can be synchronized. A "1" selects an external oscillator. When the external oscillator is selected, the OSC pin acts an input pin. Multiple chips can be synchronized to an external oscillator. The external frequency or refresh rate can be synchronized up to 200kHz typically. The rest of the bits (C4-C7) in the control byte are "don't cares". FN6110.1 March 9, 2006 ISL24006 Data Byte Data Bytes are the input code data to the 8-bit DACs. Most significant bits are clocked in first. These data bytes determine the output voltages of the ISL24006. TABLE 4. b7 1 b6 0 b5 1 b4 1 b3 1 b2 0 b1 1 b0 0 2 × (1) + 2 × (0) + 2 × (1) + 2 × (1) + 2 × (1) + 2 × (0) + 2 × (1) + 2 × (0) 7 6 5 4 3 2 1 0 Ideal Transfer Function Example Given a typical voltage applied to VREFU_H and VREFU_L: V REF U_H = 14V V REF U_L = 8.5V 14V – 8.5V R = ----------------------------- = 21.5mV 256 V REF L_H = 6.5V V REF L_L = 1V 6.5V – 1V R = ------------------------- = 21.5mV 256 For transient load application, the external clock mode should be used to ensure all functions are synchronized together. The positive edge of the external clock to the OSC pin should be timed to avoid the transient load effect. The Application Drawing shows the LCD H rate signal used, here the positive clock edge is timed to avoid the transient load of the column driver circuits. After power on, the chip will default with the internal oscillator mode. At this time, the OSC pin will be in a high impedance condition to prevent contention. TABLE 5. BINARY INPUT 00000000 00000001 00000011 00000111 00001111 00011111 00111111 01111111 11111111 DECIMAL 0 1 3 7 15 31 63 127 255 VOUT1 (V) 8.5 8.521484 8.564453 8.650391 8.822266 9.166016 9.853516 11.22852 13.97852 VOUT14 (V) 1 1.021484 1.064453 1.150391 1.322266 1.666016 2.353516 3.728516 6.478516 Channel Outputs Each of the channel outputs has a rail-to-rail buffer. This enables all channels to have the capability to drive to within 50mV of the power rails (see Electrical Characteristics for details). When driving large capacitive loads, a series resistor should be placed in series with the output. (Usually between 5Ω and 50Ω). Each of the channels is updated on a continuous cycle. The time for the new data to appear at a specific output will depend on the exact timing relationship of the incoming data to this cycle. Clock Oscillator The ISL24006 require an internal clock or external clock to refresh its outputs. The outputs are refreshed at the falling OSC clock edges. The output refreshed switches open at the rising edges of the OSC clock. The driving load shouldn't be changed at the rising edges of the OSC clock. Otherwise, it will generate a voltage error at the outputs. This clock may be input or output via the clock pin labelled OSC. The internal clock is provided by an internal oscillator running at approximately 21kHz and can be output to the OSC pin. In a two-chip system, if the driving loads are stable, one chip may be programmed to use the internal oscillator; then the OSC pin will output the clock from the internal oscillator. The second chip may have the OSC pin connected to this clock source. Power-On Sequencing At power-on, make sure that AVDD ≥ DVDD - 0.5V to prevent the ESD diode between AVDD and DVDD from driving too much current. If DVDD comes on first, leave AVDD floating. Do not ground AVDD. Power Dissipation With the 30mA maximum continues output drive capability for each channel, it is possible to exceed the 125°C absolute maximum junction temperature. Therefore, it is important to calculate the maximum junction temperature for the application to determine if load conditions need to be modified for the part to remain in the safe operation. 8 FN6110.1 March 9, 2006 ISL24006 The maximum power dissipation allowed in a package is determined according to: T JMAX – T AMAX P DMAX = -------------------------------------------Θ JA where: • TJMAX = Maximum junction temperature • TAMAX = Maximum ambient temperature • θJA = Thermal resistance of the package • PDMAX = Maximum power dissipation in the package The maximum power dissipation actually produced by the IC is the total quiescent supply current times the total power supply voltage and plus the power in the IC due to the loads. P DMAX = A VDD × I AVDD + Σ [ ( A VDD – V OUT i ) × I LOAD i ] when sourcing, and: P DMAX = A VDD × I AVDD + Σ ( V OUT i × I LOAD i ) when sinking. Where: • i = 1 to total 14 • AVDD = Supply voltage • IAVDD = Quiescent current • VOUTi = Output voltage of the i channel • ILOADi = Load current of the i channel By setting the two PDMAX equations equal to each other, we can solve for the RLOADs to avoid the device overheat. The package power dissipation curves provide a convenient way to see if the device will overheat. Power Supply Bypassing and Printed Circuit Board Layout Good printed circuit board layout is necessary for optimum performance. A low impedance and clean analog ground plane should be used for the ISL24006. The traces from the two ground pins to the ground plane must be very short. The thermal pad should be connected to the analog ground plane. Lead length should be as short as possible and all power supply pins must be well bypassed. A 0.1µF ceramic capacitor must be placed very close to the AVDD, VREFU_H, VREFU_L, VREFL_H, VREFL_L, and BG pins. A 4.7µF local bypass ceramic capacitor should be placed to the AVDD, VREFU_H, VREFU_L, VREFL_H, VREFL_L pins. 9 FN6110.1 March 9, 2006 ISL24006 Package Outline Drawing NOTE: The package drawing shown here may not be the latest version. To check the latest revision, please refer to the Intersil website at http://www.intersil.com/design/packages/index.asp All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 10 FN6110.1 March 9, 2006