ISL24010

® ISL24010 Octal Voltage Level Shifter for TFT/LCD Panels Data Sheet November 4, 2005 FN6124.0 High Voltage TFT-LCD Logic Driver The ISL24010 is a high voltage TFT-LCD logic driver with a +40V and -20V (momentary absolute max) output voltage swing capability. It is manufactured using the Intersil’s proprietary monolithic high voltage bipolar process and is capable of driving a 3000pF load in 500ns. The ISL24010 will level shift a digital input signal to an output voltage nearly equal to its output supply voltages. The ISL24010 has 3 supplies. VON1 and VON2 are positive supplies with a voltage range between +10V and +40V (absolute max). VOFF is the negative supply with a voltage range between -5V and -20V (absolute max). Outputs 1 through 6 are connected to VON1 and VOFF. Outputs 7 and 8 are connected to VON2 and VOFF. This configuration enables outputs 1 through 6 to provide slicing to the row drivers to reduce flicker, and outputs 7 and 8 to control possible supply lines. VON2 should remain constant. It is possible to tie VON1 and VON2 supplies together, if independent control as described above is not desired. VON2 is required to be greater than or equal to VON1 at all times. The ISL24010 is available in TSSOP-20 pin package. It is specified for operation over the -40°C to +85°C industrial temperature range. Features • 0V to 5.5V (absolute max) Input Voltage Range • +40V and -20V (momentary absolute max) Output Voltage Range • 10mA Output Continuous Current (all 8 channels) • 25mA Output Peak Current (all 8 channels) • Rise/Fall Times 150ns/210ns • Propagation Delay 250ns • 50kHz Input Logic Frequency • 20 Ld TSSOP Pb-Free Plus Anneal (RoHS Compliant) Applications • TFT-LCD panels Pinout 20 Ld TSSOP TOP VIEW GND IN1 IN2 IN3 IN4 1 2 3 4 5 6 7 8 9 20 VON1 19 OUT1 18 OUT2 17 OUT3 16 OUT4 15 OUT5 14 OUT6 13 OUT7 12 OUT8 11 VON2 Ordering Information PART NUMBER ISL24010IVZ (See Note) PART MARKING 24010IVZ TEMP. RANGE (°C) -40 to +85 -40 to +85 PACKAGE PKG. DWG. # IN5 IN6 IN7 IN8 20 Ld TSSOP M20.173 (Pb-free) 20 Ld TSSOP M20.173 Tape and Reel (Pb-free) VOFF 10 ISL24010IVZ-T 24010IVZ (See Note) NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2005. All Rights Reserved. All other trademarks mentioned are the property of their respective owners. ISL24010 Functional Diagram Connected to VON1 and VOFF CH1 OUT1 OUT2 IN2 IN3 IN4 CH2 OUT3 CH3 OUT4 CH4 OUT5 IN5 IN6 CH5 OUT6 CH6 IN1 IN7 Connected to VON2 and VOFF CH7 CH8 OUT7 OUT8 IN8 2 ISL24010 Absolute Maximum Ratings (TA = 25°C) Driver Positive Supply Voltage Range, (VON) . . . . . . . . +5V to +40V Power Supply Voltage Range, (VON to VOFF) . . . . . . +10V to +60V Negative Supply Voltage Range, (VOFF). . . . . . . . . . . . . -20V to -5V Supply Turn-on Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . 10V/µs Input Voltage Range, All Inputs . . . . . . . . . . . . . . . . . . -0.5V to 5.5V Output Voltage Range, All Outputs . . . . . VOFF -0.5V to VON +0.5V Thermal Information Thermal Resistance (Typical, Note 1) θJA (°C/W) 20 Ld TSSOP Package . . . . . . . . . . . . . . . . . . . . . . 140 IOUT (continuous, all 8 channels) . . . . . . . . . . . . . . . . . . . . . . 80mA TAMBIENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C TJUNCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +150°C TSTORAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on a HIGH effective thermal conductivity test board in free air. See Tech Brief TB379 for details. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA Electrical Specifications PARAMETER Power Supplies I(VON) VON = 22V, VOFF = -5V, TA = -40°C to +85°C Unless Otherwise Specified. Typical values tested at 25°C CONDITION MIN -5 (VOFF) 1.8 TYP MAX 22 (VON) 4.0 UNIT V mA DESCRIPTION Recommended Operating Voltages Supply Current All Inputs low or high No load VON = VON1 + VON2 All Inputs low or high No load Each Input low or high High = 1.8V, Low = 0.8V IOH = -100µA VON = 22V RL = 100pF in parallel with 5kΩ IOH = +100µA VOFF = -5V RL = 100pF in parallel with 5kΩ 1.8 -4.0 -8.0 (VON - 1.5V) I(VOFF) IIN VOH Supply Current Input Leakage High Level Output Voltage -1.8 mA 8.0 µA V ± 2.0 21.2 VOL Low Level Output Voltage -4.3 (VOFF + 1.5V) V VIH VIL tplh High Level Input Voltage Low Level Input Voltage Low to High Prop Delay 50% to 50%, Tested with RL = 100pF in parallel with 5kΩ, f = 50kHz Measured at 50% to 50% f = 50kHz RL = 100pF in parallel with 5kΩ, Measured at 10% to 90% f = 50kHz RL = 100pF in parallel with 5kΩ Measured at 10% to 90% f = 50kHz RL = 100pF in parallel with 5kΩ V 0.8 300 500 V ns tphl High to Low Prop Delay 250 500 ns ttlh Rise Time 150 500 ns tthl Fall Time 210 500 ns 3 ISL24010 Pin Descriptions PIN NUMBER TSSOP-20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 PIN NAME GND IN1 IN2 IN3 IN4 IN5 IN6 IN7 IN8 VOFF VON2 OUT8 OUT7 OUT6 OUT5 OUT4 OUT3 OUT2 OUT1 VON1 EQUIVALENT CIRCUIT 4 1 1 1 1 1 1 1 1 4 4 3 3 2 2 2 2 2 2 4 VON2 IN VOFF CIRCUIT 1. Outputs 1-6 DESCRIPTION Ground pin Level shifter input 1 Level shifter input 2 Level shifter input 3 Level shifter input 4 Level shifter input 5 Level shifter input 6 Level shifter input 7 Level shifter input 8 Negative output supply for all channels Positive output supply for channels 7 and 8. VON2 is required to be greater than or equal to VON1. Lever shifter output 8 Lever shifter output 7 Lever shifter output 6 Lever shifter output 5 Lever shifter output 4 Lever shifter output 3 Lever shifter output 2 Lever shifter output 1 Positive output supply for channels 1 through 6. VON1 is required to be less than or equal to VON2. VON1 OUT VOFF CIRCUIT 2. VON2 OUT VOFF CIRCUIT 3. Outputs 7-8 VON2 VON1 VOFF CIRCUIT 4. ESD CLAMP GND 4 ISL24010 Typical Performance Curves TA = 25°C, Output load parallel RC (RL = 5kΩ, CL = 100pF) unless otherwise specified. 10.0 9.0 8.0 7.0 mA mA 6.0 5.0 4.0 3.0 2.0 1.0 0.0 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 FREQUENCY (kHz) VON2 VON1 & 2 = 22V VOFF = -5V Input 50% Duty Cycle VON1 VOFF 12.0 10.8 9.6 8.4 7.2 6.0 4.8 3.6 2.4 1.2 0.0 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 FREQUENCY (kHz) VON1 & 2 = 22V VOFF = -5V Input 50% Duty Cycle VON2 VON1 VOFF FIGURE 1. SUPPLY CURRENT vs FREQUENCY 1 CHANNEL TOGGELING FIGURE 2. SUPPLY CURRENT vs FREQUENCY 4 CHANNELS TOGGELING 15.0 13.5 12.0 10.5 mA 9.0 7.5 6.0 4.5 3.0 1.5 0.0 VON2 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 FREQUENCY (kHz) VON1 & 2 = 22V VOFF = -5V mA Input 50% Duty Cycle VOFF VON1 15.0 13.5 12.0 10.5 9.0 7.5 6.0 4.5 3.0 1.5 0.0 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 FREQUENCY (kHz) VON1 & 2 = 22V VOFF = -5V Input 50% Duty Cycle VOFF VON2 VON1 FIGURE 3. SUPPLY CURRENT vs FREQUENCY 6 CHANNELS TOGGLING FIGURE 4. SUPPLY CURRENT vs FREQUENCY 8 CHANNELS TOGGLING 350 315 280 245 210 ns Rise Time VON1 & 2 = 20-40V VOFF = -5V Frequency 50kHz 100pF load 20 22 24 26 28 30 32 34 36 38 40 ns 175 140 105 70 35 0 Prop Delay Fall Time 350 315 280 245 210 175 140 105 70 35 0 VON1 & VON2 (V D.C.) 20 VON1 & 2 = 20-40V VOFF = -20V Frequency 50kHz 100pF load 22 24 26 28 30 32 34 36 38 40 Rise Time Prop Delay Fall Time VON1 & VON2 (V D.C.) FIGURE 5. RISE TIME, FALL TIME AND PROP DELAY vs VON1 & VON2 VOLTAGE WITH VOFF = -5V FIGURE 6. RISE TIME, FALL TIME AND PROP DELAY vs VON1 & VON2 VOLTAGE WITH VOFF = -20V 5 ISL24010 Typical Performance Curves TA = 25°C, Output load parallel RC (RL = 5kΩ, CL = 100pF) unless otherwise specified. (Continued) 2000 1800 1600 1400 1200 ns 1800pF ns 1000 800 600 400 200 0 20 22 24 26 28 30 32 34 36 38 40 100pF VON1 & 2 = 20-40V VOFF = -5V 50kHz 50% Duty Cycle 2100 1890 3300pF 1680 1470 1260 1050 840 630 420 210 0 20 22 24 26 28 30 32 34 36 38 40 VON1 & 2 = 20-40V VOFF = -20V 50kHz 50% Duty Cycle 100pF 1800pF 3300pF VON1 & VON2 (V D.C.) VON1 & VON2 (V D.C.) FIGURE 7. RISE TIME vs CAPACITANCE vs SUPPLY VOLTAGE WITH VOFF = -5V FIGURE 8. RISE TIME vs CAPACITANCE vs SUPPLY VOLTAGE WITH VOFF = -20V 2000 1800 1600 1400 1200 ns 1800pF ns 1000 800 600 400 200 0 20 22 24 26 28 30 32 34 36 38 40 100pF VON1 & 2 = 20-40V VOFF = -5V 50kHz 50% Duty Cycle 2200 1980 3300pF 1760 1540 1320 1100 880 660 440 220 0 20 22 24 26 28 30 32 34 36 38 40 VON1 & 2 = 20-40V VOFF = -20V 50kHz 50% Duty Cycle 100pF 1800pF 3300pF VON1 & VON2 (V D.C.) VON1 & VON2 (V D.C.) FIGURE 9. FALL TIME vs CAPACITANCE vs SUPPLY VOLTAGE WITH VOFF = -5V FIGURE 10. FALL TIME vs CAPACITANCE vs SUPPLY VOLTAGE WITH VOFF = -20V 1500 1350 1200 1050 900 ns 1800pF ns 750 600 450 300 150 0 20 22 24 26 28 30 32 34 36 100pF 38 40 VON1 & 2 = 20-40V VOFF = -5V 50kHz 50% Duty Cycle 3300pF 1500 1350 1200 1050 900 750 600 450 300 150 0 20 22 24 26 28 30 32 34 36 100pF 38 40 1800pF VON1 & 2 = 20-40V VOFF = -5V 50kHz 50% Duty Cycle 3300pF VON1 & VON2 (V D.C.) VON1 & VON2 (V D.C.) FIGURE 11. PROP DELAY vs CAPACITANCE vs SUPPLY VOLTAGE WITH VOFF = -5V FIGURE 12. PROP DELAY vs CAPACITANCE vs SUPPLY VOLTAGE WITH VOFF = -20V 6 ISL24010 Typical Performance Curves TA = 25°C, Output load parallel RC (RL = 5kΩ, CL = 100pF) unless otherwise specified. (Continued) 2V/DIV Pulse Input 0 100pF 1500pF 5V/DIV 0 VON1 & 2 = 22V VOFF = -5V 50kHz 50% Duty Cycle 2µs/DIV FIGURE 13. TRANSIENT RESPONSE vs LOAD CAPACITANCE Application Information General The ISL24010 is an Octal voltage level shifter. The part was designed to level shifts a digital input signal to +22V and -5V for TFT-LCD displays. The device is capable of level shifting a CMOS logic signal between +40V and -20V. Input Pin Connections Unused inputs must be tied to ground. Failure to tie unused input pins to ground will result in a rail to rail oscillations on the respective output pins and higher unwanted power dissipation in the part. Under these conditions, the temperature of the part could get very hot. Power Supply Decoupling The ISL24010 requires a 0.1µF decoupling capacitor as close to the VON1, VON2 and VOFF power supply pins for a large load equal to 5kΩ in parallel with 100pF (Figure 16). This will deduce any dv/dt between the different supplies and prevent the internal ESD clamp from turning on and damaging the part. Limiting the Output Current No output short circuit current limit exists on this part. All applications need to limit the output current to less than 80mA. Adequate thermal heat sinking of the parts is also required. Application Diagram (TV) DC/DC CONVERTER 1.0µF 1.0µF Power Supply Sequence The ISL24010 requires that VON2 be greater than or equal to VON1 at all times. Therefore, if VON1 and Von 2 are different supplies, then VON2 needs to be turned on before VON1. The reason for this requirement is shown in Circuit 4 in the Pin Description Table. The ESD protection diode between VON2 and Von 1 will forward bias if VON1 becomes a diode drop greater than VON2. Recommended power supply sequence: VON2, VON1, VOFF then input logic signals. The ESD protection scheme is based on diodes from the pins to the VON2 supply and a dV/dt- triggered clamp. This dV/dt triggered clamp imposes a maximum supply turn-on slew rate of 10V/µs. This clamp will trigger if the supply powers up too fast, causing amps of current to flow. Ground and VON1 are treated as I/O pins with this protection scheme. In applications where the dV/dt supply ramp could exceed 10V/µs, such as hot plugging, additional methods should be employed to ensure the rate of rise is not exceeded. VON1 VON2 VOFF 1.0µF TIMING CONTROLLER ISL24010 LEVEL SHIFTER LCD PANEL FIGURE 14. TYPICAL TV APPLICATION CIRCUIT Latch-up Proof The ISL24010 is manufactured in a high voltage DI process that isolates every transistor in it’s own tub making the part latch-up proof. 7 ISL24010 Application Diagram (Monitor) DC/DC CONVERTER VOFF VON1 VON SLICER CIRCUIT VON2 1.0µF VOFF VON2 VON1 1.0µF 1.0µF TIMING CONTROLLER ISL24010 LEVEL SHIFTER LCD PANEL FIGURE 15. TYPICAL MONITOR APPLICATION CIRCUIT WITH SLICER TO REDUCE FLICKER Test Circuit VON1 VON2 1.0µF C1 1.0µF C2 IN1 OUT1 ISL24010 OUT8 5kΩ 100pF IN8 VOFF 1.0µF C3 If the output load is a series 200Ω resistor and a 3300pF then C1, C2 and C3 can be reduced to 0.47pF. INx tPLH OUTx tPHL tR tF FIGURE 16. TEST LOAD AND TIMING DEFINITIONS 8 ISL24010 Thin Shrink Small Outline Plastic Packages (TSSOP) N INDEX AREA E E1 -B1 2 3 L 0.05(0.002) -AD -CSEATING PLANE A 0.25 0.010 GAUGE PLANE 0.25(0.010) M BM M20.173 20 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A A1 A2 b c D MIN 0.002 0.031 0.0075 0.0035 0.252 0.169 MAX 0.047 0.006 0.051 0.0118 0.0079 0.260 0.177 MILLIMETERS MIN 0.05 0.80 0.19 0.09 6.40 4.30 MAX 1.20 0.15 1.05 0.30 0.20 6.60 4.50 NOTES 9 3 4 6 7 8o Rev. 1 6/98 α A1 0.10(0.004) A2 c e b 0.10(0.004) M C AM BS E1 e E L N 0.026 BSC 0.246 0.0177 20 0o 8o 0.256 0.0295 0.65 BSC 6.25 0.45 20 0o 6.50 0.75 NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-153-AC, Issue E. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E1” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. (Angles in degrees) α All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 9