ISL24202IRTZ

Programmable VCOM Calibrator with EEPROM ISL24202 The ISL24202 is an 8-bit programmable current sink that can be used in conjunction with an external voltage divider to generate a voltage source (VCOM) positioned between the analog supply voltage and ground. The current sink’s full-scale range is controlled by an external resistor, RSET. With the appropriate choice of external resistors R1 and R2, the VCOM voltage range can be controlled between any arbitrary voltage range. The ISL24202 has an 8-bit data register and 8-bit EEPROM for storing both a volatile and a permanent value for its output, accessible through a single up/down counter interface pin (CTL). After the part is programmed with the desired VCOM value, the Counter Enable pin (CE) can be grounded to prevent further changes. On every power-up the EEPROM contents are automatically transferred to the data register, and the pre-programmed output voltage appears at the VOUT pin. The ISL24202 can be used with a high output drive buffer amplifier, which allows it to directly drive the VCOM input of an LCD panel. The ISL24202 is available in an 8 Ld 3mm x 3mm TDFN package. This package has a maximum height of 0.8mm for very low profile designs. The ambient operating temperature range is -40°C to +85°C. Features • Adjustable 8-Bit, 256-Step, Current Sink Output • On-Chip 8-Bit EEPROM • Up/Down Counter Interface • Guaranteed Monotonic Over-Temperature • 4.5V to 19.0V Analog Supply Range for Normal Operation (10.8V Minimum Analog Supply Voltage for Programming) • 2.25V to 3.6V Logic Supply Voltage Operating Range • Pb-free (RoHS-Compliant) • Ultra-Thin 8 Ld TDFN (3 x 3 x 0.8mm Max) Applications • LCD Panel VCOM Generator • Electrophoretic Display VCOM Generator Related Literature • See AN1633 for ISL24202 Evaluation Board Application Note “ISL24202IRTZ-EVALZ Evaluation Board User Guide” (Coming Soon) VDD AVDD 5 2 I/O PIN* MICROCONTROLLER 6 CTL OUT R1 1 LCD PANEL I/O PIN 7 CE ISL24202 R2 VCOM SET 8 EL5411T RSET * 0, 1, TRI-STATE 4 FIGURE 1. TYPICAL ISL24202 APPLICATION March 15, 2011 FN7587.0 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2011. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. ISL24202 Block Diagram VDD 5 VDD RBIAS RBIAS CE 7 8-BIT EEPROM CS 8 SET DIGITAL INTERFACE UP/DOWN COUNTER DAC REGISTERS A1 ANALOG DCP AND CURRENT SINK Q1 1 OUT AVDD 2 3 6 DNC CTL 4 GND FIGURE 2. BLOCK DIAGRAM OF THE ISL24202 Pin Descriptions PIN NAME PIN # OUT 1 FUNCTION Adjustable Sink Current Output Pin. The sink current into the OUT pin is equal to the DAC setting times the maximum adjustable sink current divided by 256. See the “SET” pin function description below (pin 8) for setting the maximum adjustable sink current. High-Voltage Analog Supply. Bypass to GND with 0.1µF capacitor. Do Not Connect to external circuitry. It is acceptable to ground this pin. Ground connection. Digital power supply input. Bypass to GND with 0.1µF de-coupling capacitor. Up/Down Control for internal counter and Internal EEPROM Programming Control Input. When CE is high: A low-to-mid transition increments the 8-bit counter, adding 1 to the DAC setting, increasing the OUT sink current, and lowering the divider voltage at the OUT pin. A high-to-mid transition decrements the 8-bit counter, subtracting 1 from the DAC setting, decreasing the OUT sink current, and increasing the divider voltage at the OUT pin. To program the EEPROM, take this pin to >4.9V (see “CTL EEPROM Programming Signal Time” in the “Electrical Specifications” table on page 5 for details). Float when not in use. Counter Enable Pin. Connect CE to VDD to enable adjustment of the output sink current. Float or connect CE to GND to prevent further adjustment or programming (Note: the CE pin has an internal 500nA pull-down sink current). The EEPROM value will be copied to the register on a VOH to VOL transition. Maximum Sink Current Adjustment Pin. Connect a resistor from SET to GND to set the maximum adjustable sink current of the OUT pin. The maximum adjustable sink current is equal to (AVDD/20) divided by RSET. Thermal pad should be connected to system ground plane to optimize thermal performance. Pin Configuration ISL24202 (8 LD TDFN) TOP VIEW OUT 1 AVDD 2 DNC 3 GND 4 8 SET 7 CE AVDD DNC GND VDD CTL 2 3 4 5 6 PAD 6 CTL 5 VDD (*CONNECT THERMAL PAD TO GND) CE 7 SET 8 PAD - 2 FN7587.0 March 15, 2011 ISL24202 Ordering Information PART NUMBER (Notes 1, 2, 3) ISL24202IRTZ ISL24202IRTZ-EVALZ NOTES: 1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page ISL24202. For more information on MSL please see techbrief TB363. PART MARKING 202Z Evaluation Board INTERFACE COUNTER TEMP RANGE (°C) -40 to +85 8 Ld 3x3 TDFN PACKAGE (Pb-Free) PKG. DWG. # L8.3x3A 3 FN7587.0 March 15, 2011 ISL24202 Absolute Maximum Ratings Supply Voltage AVDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20V VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4V Input Voltage with respect to Ground SET, CTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AVDD+0.3V CE and WP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDD+0.3V Output Voltage with respect to Ground OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AVDD Continuous Output Current OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA ESD Ratings Human Body Model (Tested per JESD22-A114) . . . . . . . . . . . . . . . . . 7kV Machine Model (Tested per JESD22-A115). . . . . . . . . . . . . . . . . . . . 300V Charged Device Model (Tested per JESD22-C101). . . . . . . . . . . . . . . 2kV Latch Up (Tested per JESD 78, Class II, Level A). . . . . . . . . . . . . . . . 100mA Thermal Information Thermal Resistance (Typical) θJA (°C/W) θJC (°C/W) 8 Ld TDFN Package (Notes 4, 5). . . . . . . . . 53 11 Moisture Sensitivity (see Technical Brief TB363) All Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Level 1 Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Recommended Operating Conditions Operating Range AVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5V to 19V VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.25V to 3.6V Ambient Operating Temperature . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 4. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 5. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside. Electrical Specifications Test Conditions: VDD = 3.3V, AVDD = 18V, RSET = 5kΩ, R1 = 10kΩ, R2 = 10kΩ, (See Figure 5). Typicals are at TA = +25°C. Boldface limits apply over the operating temperature range, -40°C to +85°C. SYMBOL PARAMETER TEST CONDITIONS MIN (Note 6) TYP MAX (Note 6) UNITS DC CHARACTERISTICS VDD AVDD AVDD IDD IAVDD SETZSE SETFSE VOUT SET VD IOUT INL DNL VDD Supply Range - Operating AVDD Supply Range Supporting EEPROM Programming AVDD Supply Range for Wide-Supply Operation without EEPROM Programming VDD Supply Current AVDD Supply Current SET Zero-Scale Error SET Full-Scale Error OUT Voltage Range SET Voltage Drift Maximum OUT Sink Current Integral Non-Linearity Differential Non-Linearity VSET + 1 .75 7 4 ±2 ±1 CTL = 0.5*VDD CTL = 0.5*VDD 2.25 10.8 4.5 40 24 3.6 19 19 65 38 ±3 ±8 AVDD V V V µA µA OUT PIN CHARACTERISTICS LSB LSB V µV/°C mA LSB LSB EEPROM CHARACTERISTICS tPROG VIH VIL ICS_PD ICTL tST tREAD EEPROM Programming Time (internal) 100 ms UP/DOWN COUNTER CONTROL INPUTS (SEE FIGURE 11) CE and CTL Input Logic High Threshold CE and CTL Input Logic Low Threshold CE Input Pull Down Current Sink CTL Input Bias Current CTL = GND (sourcing) CTL = VDD (sinking) CE to CTL Start Delay EEPROM Recall Time (after CE de-asserted) 50 10 0.5 7 7 0.7*VDD 0.3*VDD 1.5 15 15 V V µA µA µA µs ms 4 FN7587.0 March 15, 2011 ISL24202 Electrical Specifications Test Conditions: VDD = 3.3V, AVDD = 18V, RSET = 5kΩ, R1 = 10kΩ, R2 = 10kΩ, (See Figure 5). Typicals are at TA = +25°C. Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued) SYMBOL tH_REJ tL_REJ tH_MIN tL_MIN tMTC VPROG tPROG tH_PROP tL_PROP PARAMETER CTL High Pulse Rejection Width CTL Low Pulse Rejection Width CTL High Minimum Valid Pulse Width CTL Low Minimum Valid Pulse Width CTL Minimum Time Between Counts CTL EEPROM Program Voltage (see Figure 9) CTL EEPROM Programming Signal Time CTL High-to-Mid to OUT Propagation Time CTL Low-to-Mid to OUT Propagation Time 200 200 10 4.9 200 65 65 19 TEST CONDITIONS MIN (Note 6) TYP MAX (Note 6) 20 20 UNITS µs µs µs µs µs V µs µs µs NOTE: 6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. 5 FN7587.0 March 15, 2011 ISL24202 Application Information LCD panels have a VCOM (common voltage) that must be precisely set to minimize flicker. Figure 3 shows a typical VCOM adjustment circuit using a mechanical potentiometer, and the equivalent circuit replacement using the ISL24202. Having a digital counter interface enables automatic, digital flicker minimization during production test and alignment. After programming, the counter interface is not needed again - the ISL24202 automatically powers up with the correct VCOM voltage programmed previously. The ISL24202 uses a digitally controllable potentiometer (DCP), with 256 steps of resolution (Figure 4) to change the current drawn at the OUT pin, which then changes the voltage created by the R1 - R2 resistor divider (Figure 5). The OUT voltage can then be buffered by an external amplifier (A2) to generate a buffered output voltage (VCOM) capable of driving the VCOM input of an LCD panel. The amount of current sunk is controlled by the setting of the DCP, which is recalled at power-up from the ISL24202’s internal EEPROM. The EEPROM is typically programmed during panel manufacture. As noted in the “Electrical Specifications” section on page 4, the ISL24202 requires a minimum AVDD voltage of 10.8V for EEPROM programming, but will work in normal operation down to 4.5V after the EEPROM has been programmed, with no additional EEPROM writing. AVDD AVDD REGISTER VALUE 19R AVDD 20 255 254 253 252 R 251 2 1 0 VDCP FIGURE 4. SIMPLIFIED SCHEMATIC OF DCP Output Current Sink Figure 5 shows the schematic of the OUT current sink. The combination of amplifier A1, transistor Q1, and resistor RSET forms a voltage-controlled current source, with the voltage determined by the DCP setting. A VDD A VDD R1 RA RB R1 = RA R2 = RB+RC RSET = RARB + RARC 20RB RC OUT VCOM V DCP Q1 A1 V SAT SET V OUT IOUT R2 V SET = V DCP = IOUT * R SET IOUT R SET VDD ISL24202 AVDD AVDD R1 FIGURE 5. CURRENT SINK CIRCUIT OUT SET RSET IOUT A2 R2 VCOM The external RSET resistor sets the full-scale (maximum) sink current that can be pulled from the OUT node. The relationship between IOUT and Register Value is shown in Equation 2. V DCP RegisterValue + 1 AV DD 1 I OUT = ------------- = ⎛ -------------------------------------------------- ⎞ ⎛ --------------⎞ ⎛ ------------⎞ ⎝ ⎠ ⎝ 20 ⎠ ⎝ R ⎠ R SET 256 SET (EQ. 2) FIGURE 3. MECHANICAL ADJUSTMENT REPLACEMENT The maximum value of IOUT can be calculated by substituting the maximum register value of 255 into Equation 2, resulting in Equation 3: A VDD I OUT ( MAX ) = ------------------20R SET (EQ. 3) DCP (Digitally Controllable Potentiometer) The DCP controls the voltage that ultimately controls the SET current. Figure 4 shows the relationship between the register value and the DCP’s tap position. Note that a register value of 0 selects the first step of the resistor string. The output voltage of the DCP is given in Equation 1: RegisterValue + 1 AV DD V DCP = ⎛ -------------------------------------------------- ⎞ ⎛ --------------⎞ ⎝ ⎠ ⎝ 20 ⎠ 256 (EQ. 1) Equation 2 can also be used to calculate the unit sink current step size per Register Code, resulting in Equation 4: AV DD I STEP = --------------------------------------------( 256 ) ( 20 ) ( R SET ) (EQ. 4) 6 FN7587.0 March 15, 2011 ISL24202 Determination of RSET The ultimate goal for the ISL24202 is to generate an adjustable voltage between two endpoints, VCOM_MIN and VCOM_MAX, with a fixed power supply voltage, AVDD. This is accomplished by choosing the correct values for RSET, R1 and R2. The exact value of RSET is not critical. Values from 1k to more than 100k will work under most conditions. The following expression calculates the minimum RSET value: AV DD ⎛ ⎞ -------------⎜ ⎟ 16 ⎜ ----------------------------------------------------- ⎟ ( k Ω ) R SET ( MIN ) = ⎜ AV DD ⎟ ⎜⎛V – --------------⎞ ⎟ ⎝ ⎝ OUT ( MIN ) 20 ⎠ ⎠ (EQ. 5) Using Equations 6 and 7, calculate the values of R1 and R2: 8.5 – 6.5 R 1 = 5120 ⋅ 7500 ⋅ ⎛ -------------------------------------⎞ = 35.4k Ω ⎝ 256 ⋅ 8.5 – 6.5⎠ 8.5 – 6.5 R 2 = 5120 ⋅ 7500 ⋅ ⎛ ----------------------------------------------------------------- ⎞ = 46.4k Ω ⎝ 255 ⋅ 15 + 6.5 – 256 ⋅ 8.5⎠ (EQ. 10) (EQ. 11) Table 1 shows the resulting VCOM voltage as a function of register value for these conditions. TABLE 1. EXAMPLE VOUT vs REGISTER VALUE REGISTER VALUE 0 20 40 60 80 100 120 VOUT (V) 8.49 8.34 8.18 8.02 7.87 7.71 7.55 7.50 7.40 7.24 7.09 6.93 6.77 6.62 6.50 Note that this is the absolute minimum value for RSET. Larger RSET values reduce quiescent power, since R1 and R2 are proportional to RSET. The ISL24202 is tested with a 5kΩ RSET. Determination of R1 and R2 With AVDD, VCOM(MIN) and VCOM(MAX) known and RSET chosen per the above requirements, R1 and R2 can be determined using Equations 6 and 7: ⎛ V COM ( MAX ) – V COM ( MIN ) ⎞ R 1 = 5120 ⋅ R SET ⎜ --------------------------------------------------------------------------------⎟ ⎝ 256 ⋅ V COM ( MAX ) – V COM ( MIN )⎠ (EQ. 6) 127 140 V COM ( MAX ) – V COM ( MIN ) ⎛ ⎞ R 2 = 5120 ⋅ R SET ⎜ -------------------------------------------------------------------------------------------------------------------- ⎟ 255 ⋅ AV DD + V COM ( MIN ) – 256 ⋅ V COM ( MAX )⎠ ⎝ (EQ. 7) 160 180 200 220 Final Transfer Function The voltage at the OUT pin can be calculated from Equation 8: ⎛ R2 ⎞ ⎛ RegisterValue + 1 ⎛ R 1 ⎞ ⎞ V OUT = AV DD ⎜ ------------------- ⎟ ⎜ 1 – -------------------------------------------------- ⎜ ------------------- ⎟ ⎟ 256 ⎝ 20R SET⎠ ⎠ ⎝ R1 + R2 ⎠ ⎝ (EQ. 8) 240 255 Output Voltage Span Calculation It is also possible to calculate VCOM(MIN) and VCOM(MAX) from the existing resistor values. VCOM_MIN occurs when the greatest current, IOUT(MAX), is drawn from the middle node of the R1/R2 divider. Substituting RegisterValue = 255 into Equation 8 gives the following: ⎛ R1 ⎞ ⎞ ⎛ R2 ⎞ ⎛ V COM ( MIN ) = AV DD ⎜ ------------------- ⎟ ⎜ 1 – ⎜ ------------------- ⎟ ⎟ ⎝ 20R SET⎠ ⎠ ⎝ R1 + R2 ⎠ ⎝ (EQ. 12) With external amplifier A2 in the unity-gain configuration, VOUT = VCOM. Example As an example, suppose the AVDD supply is 15V, the desired VCOM_MIN = 6.5V and the desired VCOM_MAX = 8.5V. RSET is arbitrarily chosen to be 7.5kΩ. First, verify that our chosen RSET meets the minimum requirement described in Equation 5: 15 ⎛ ⎞ ⎛ ⎞ -----⎜ ⎟ ⎜ ⎟ 16 ( 7.5k Ω ) > ⎜ R SET ( MIN ) = ⎜ ------------------------------⎟ = 0.163k Ω⎟ 15⎞ ⎟ ⎜ ⎛ 6.5V – -----⎜ ⎟ ⎝⎝ ⎝ ⎠ 20⎠ ⎠ Similarly, RegisterValue = 0 for VCOM(MAX): ⎛ R2 ⎞ ⎛ 1 ⎛ R1 ⎞ ⎞ V COM ( MAX ) = AV DD ⎜ ------------------- ⎟ ⎜ 1 – --------- ⎜ ------------------- ⎟ ⎟ R1 + R2 ⎠ ⎝ 256 ⎝ 20R SET⎠ ⎠ ⎝ (EQ. 9) (EQ. 13) By finding the difference of Equation 13 and Equation 12, the total span of VCOM can be found: ⎛ R2 ⎞ 1 ⎛ R1 ⎞ V COM SPAN = AV DD ⎜ ------------------- ⎟ ⎛ 1 – --------- ⎞ ⎜ ------------------- ⎟ R1+ R2 ⎠ ⎝ 256⎠ ⎝ 20R SET⎠ ⎝ (EQ. 14) 7 FN7587.0 March 15, 2011 ISL24202 Assuming that the IOUT(MIN) = 0 instead of ISTEP, the expression in Equation 14 simplifies to: ⎛ R 1 ⋅ R 2 ⎞ ⎛ AV DD ⎞ ⎛ R1 ⋅ R2 ⎞ V COM SPAN = ⎜ ------------------- ⎟ ⎜ ------------------- ⎟ = ⎜ ------------------- ⎟ I DVROUT ( MAX ) ⎝ R 1 + R 2⎠ ⎝ 20R SET⎠ ⎝ R 1 + R 2⎠ (EQ. 15) Operating and Programming Supply Voltage and Current To program the EEPROM, AVDD must be ≥10.8V. If further programming is not required, the ISL24202 will operate over an AVDD range of 4.5V to 19V. During EEPROM programming, IDD and IAVDD will temporarily be 4-5x higher for up to 100ms (tPROG). OUT Pin Leakage Current When the voltage on the OUT pin is greater than 10V, an additional leakage current flows into the pin in addition to the ISET current. Figure 6 shows the ISET current and the OUT pin current for OUT pin voltage up to 19V. In applications where the voltage on the OUT pin will be greater than 10V, the actual output voltage will be lower than the voltage calculated by Equation 8 due to this extra current. The graph in Figure 6 was measured with RSET = 4.99kΩ. 0.30 REGISTER = 255 0.25 OUT PIN CURRENT Up/Down Counter Interface The ISL24202 allows the adjustment of the output VCOM voltage and the programming of the non-volatile memory through a single pin (CTL) when the CE (counter enable) pin is high. The CTL pin is biased so that its voltage is set to VDD/2 if the driving circuit is set to Tri-state or High Impedance (Hi-Z), allowing up/down operation using common digital I/O logic. CTL Pin When a mid-high-mid transition is detected on the CTL pin (see Figure 11), the internal register value counts down by one at the trailing (high-mid) edge, and the output VCOM voltage is increased according to Equation 8. Similarly, when a mid-low-mid transition is detected on the CTL pin, the internal register value counts up by one at the trailing (low-mid) edge, and the output VCOM voltage is decreased. Once the maximum or minimum value is reached, the counter saturates and will not overflow or underflow beyond those values. CTL should have a noise filter to reduce bouncing or noise on the input that could cause unwanted counts when the CE pin is high. Figure 8 shows a simple debouncing circuit consisting of a series 1kΩ resistor and a shunt 0.01µF capacitor connected on the CTL pin. To avoid unintentional adjustment, the ISL24202 guarantees to reject CTL pulses shorter than 20µs. AVDD CLOSE TO PROGRAM EEPROM 1kΩ 0.01µF ISL24202 CTL CURRENT (mA) 0.20 SET PIN CURRENT 0.15 0.10 0.05 0.00 0 2 4 6 8 10 12 14 16 18 20 OUT PIN VOLTAGE (V) FIGURE 6. OUT PIN LEAKAGE CURRENT Power Supply Sequence The recommended power supply sequencing is shown in Figure 7. When applying power, VDD should be applied before or at the same time as AVDD. The minimum time for tVS is 0µs. When removing power, the sequence of VDD and AVDD is not important. VDD FIGURE 8. EXTERNAL DEBOUNCER ON CTL PIN AVDD tVS This pin is pulled above 4.9V to program the EEPROM. See “Programming the EEPROM” on page 9 for details. After CE (Counter Enable) is asserted and after programming EEPROM, the very first CTL pulse is ignored (see Figure 11) to avoid the possibility of a false count (since CTL state may be unknown after programming). FIGURE 7. POWER SUPPLY SEQUENCE Do not remove VDD or AVDD within 100ms of the start of the EEPROM programming cycle. Removing power before the EEPROM programming cycle is completed may result in corrupted data in the EEPROM. CE Pin To change the counter controlling the output voltage, the CE (Counter Enable) pin must be pulled high (VDD). When the CE pin is pulled low, the counter value is loaded from EEPROM, which takes 10ms (during which the inputs should remain constant). The CE pin has an internal pull-down to keep it at a logic low 8 FN7587.0 March 15, 2011 ISL24202 when not being driven. CE should be pulled low before powering the device down to ensure that any glitches or transients during power-down will not cause unwanted EEPROM overwriting. The CE pin has a Schmitt trigger on the input to prevent false triggering during slow transitions of the CE pin. The CE pin transition time should be 10µs or less. 1. Power-up the ISL24202. The EEPROM value will be loaded. 2. Set the CE pin to VDD. 3. Change the VOUT voltage using the CTL pin to the desired value, noting that first pulse will be ignored. 4. Pull the CTL pin to 4.9V or higher for at least 200µs. The counter value will be written to EEPROM after 100ms. 5. Change the VOUT value (using the CTL pin) to a different value, noting that first pulse after programming will be ignored. 6. Set the CE pin to 0V. The stored output value will be loaded from EEPROM after 10ms. 7. Verify that the output value is the same value programmed in Step 4. The CTL pin should be left floating after programming. The voltage at the CTL pin will be internally biased to VDD/2 to ensure that no additional pulses will be seen by the Up/Down counter. To prevent further changes, ground the CE pin. Programming the EEPROM To program the non-volatile EEPROM, pull the CTL pin above 4.9V for more than 200µs. The level and timing is shown in Figure 9. It then takes a maximum of 100ms after CTL crosses 4.9V for the programming to be completed inside the device. CTL VOLTAGE >200µs 4.9V 100ms EEPROM OPERATION COMPLETE Typical Application Circuit TIME tPROG FIGURE 9. EEPROM PROGRAMMING When the part is programmed, the data in the counter register is written into the EEPROM. This value will be loaded from the EEPROM during subsequent power-ups as well as when the CE pin is pulled low. The ISL24202 is factory-programmed to mid-scale. As with asserting CE, the first pulse after a program operation is ignored. The EEPROM contents can be written and verified using the following steps: Shown below in Figure 10 is a typical circuit that can be used to program the ISL24202 via the up/down counter interface. Three momentary push-button switches are required. SW1 connected between CTL and AVDD allows the user to bring CTL above VDD for programming the EEPROM, SW2 connected to VDD to pull CTL up, and SW3 connected to GND to pull CTL to down. All the switches should have 1kΩ current-limiting resistors in series. For adjustment and programming to occur, the CE pin has to be set to VDD. This can be achieved by a single-pull double-throw switch (SW4) connected between VDD and GND. Note that pressing the UP button increments the counter, but results in VCOM_OUT decreasing. Similarly, pressing the DOWN button decrements the counter, and results in VCOM_OUT increasing. AVDD AVDD 0.1µF VDD AVDD 1kΩ CLOSE TO PROGRAM EEPROM SW1 VDD 1kΩ SW2 UP DISABLE CE CTL 0.01µF DOWN SW3 1kΩ ENABLE ADJUST / PROGRAM VDD 0.1µF SW4 VDD AVDD OUT R1 ISL24202 GND SET EL5411T R2 VCOM to LCD Panel RSET FIGURE 10. TYPICAL APPLICATION CIRCUIT 9 FN7587.0 March 15, 2011 ISL24202 Up/Down Counter Waveforms The operation modes of the ISL24202 is shown in Table 2. TABLE 2. ISL24202 OPERATION MODES INPUT CTL X X Hi to Mid Lo to Mid Mid to >4.9V >4.9V to Mid X CE Lo Lo to Hi Hi Hi Hi Hi Hi to Lo Counter OUTPUT VCOM_OUT No Change Ignore first CTL pulse Decrement Increment No Change Increase Decrease No Change No Change No Change No Change Write Counter Value to EEPROM No Change No Change EEPROM Ignore next CTL Pulse EEPROM Read Value Programmed Value Figure 11 shows the associated waveforms. NOTE: AFTER COUNTER ENABLE IS ASSERTED, THE FIRST CTL PULSE IS IGNORED VPROG = 4.9V tST tPROG FIRST PULSE AFTER PROGRAMMING IS IGNORED tH_REJ FIRST PULSE AFTER ASSERTING CE IS IGNORED tMTC tREAD CTL HIGH CTL VDD/2 CTL LOW tL_REJ tH_MIN tL_MIN CE tL_PROP ENABLE ADJUSTMENT DISABLE ADJUSTMENT ENABLE ADJUSTMENT tH_PROP AVDD VDD COUNTER OUTPUT 78 ASSUME COUNTER STARTS WITH VALUE 78 79 7A 7B WRITE 7B TO EEPROM 7A 7B DEASSERTING CE RELOADS 7B FROM EEPROM 7A VCOM EXAMPLE POST POWER-UP TIMING FIGURE 11. COUNTER INTERFACE TIMING DIAGRAM 10 FN7587.0 March 15, 2011 ISL24202 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest revision. DATE 3/15/11 REVISION FN7587.0 Initial release. CHANGE Products Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a complete list of Intersil product families. *For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on intersil.com: ISL24202 To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff FITs are available from our website at http://rel.intersil.com/reports/sear For additional products, see www.intersil.com/product_tree Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 11 FN7587.0 March 15, 2011 ISL24202 Package Outline Drawing L8.3x3A 8 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE Rev 4, 2/10 ( 2.30) 3.00 A B ( 1.95) ( 8X 0.50) 3.00 6 PIN 1 INDEX AREA (4X) 0.15 TOP VIEW PIN 1 (6x 0.65) ( 8 X 0.30) TYPICAL RECOMMENDED LAND PATTERN (1.50) ( 2.90 ) SEE DETAIL "X" 2X 1.950 6X 0.65 PIN #1 INDEX AREA 6 1.50 ±0.10 1 SIDE VIEW 0.75 ±0.05 0.10 C C 0.08 C 8 8X 0.30 ± 0.10 2.30 ±0.10 BOTTOM VIEW 8X 0.30 ±0.05 0.10 M C A B 4 C 0 . 2 REF 5 0 . 02 NOM. 0 . 05 MAX. DETAIL "X" NOTES: 1. 2. 3. 4. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. Dimensioning and tolerancing conform to ASME Y14.5m-1994. Unless otherwise specified, tolerance : Decimal ± 0.05 Dimension applies to the metallized terminal and is measured between 0.15mm and 0.20mm from the terminal tip. 5. 6. Tiebar shown (if present) is a non-functional feature. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Compliant to JEDEC MO-229 WEEC-2 except for the foot length. 12 FN7587.0 March 15, 2011