ISL24211IRTZ-EVALZ

Programmable VCOM Calibrator with EEPROM and Output Buffer ISL24211 The ISL24211 is an 8-bit programmable current sink that can be used in conjunction with an external voltage divider to generate a voltage source (VCOM) positioned between the analog supply voltage and ground. The current sink’s full-scale range is controlled by an external resistor, RSET. With the appropriate choice of external resistors R1 and R2, the VCOM voltage range can be controlled between any arbitrary voltage range. The ISL24211 has an 8-bit data register and 8-bit EEPROM for storing both a volatile and a permanent value for its output, with an I2C interface to read and write to the register and EEPROM. After the part is programmed, the I2C interface is no longer needed; on power-up the EEPROM contents are automatically transferred to the data register, and the pre-programmed output voltage appears on the VCOM_OUT pin. The ISL24211 also features an integrated, wide-bandwidth, high output drive buffer amplifier that can directly drive the VCOM input of an LCD panel. The ISL24211 is available in an 10 Ld 3mm x 3mm TDFN package. This package has a maximum height of 0.8mm for very low profile designs. The ambient operating temperature range is -40°C to +85°C. Features • 8-bit, 256-Step, Adjustable Sink Current Output • 60MHz VCOM Buffer/Amplifier • 4.5V to 19.0V Analog Supply Range for Normal Operation (10.8V Minimum Analog Supply Voltage for Programming) • 2.25V to 3.6V Logic Supply Voltage Operating Range • 400kHz, I2C Interface • On-Chip 8-Bit EEPROM • Guaranteed Monotonic Over-Temperature • Compatible with applications using the 7-bit ISL45041 • Pb-free (RoHS-compliant) • Ultra-Thin 10 Ld TDFN (3 x 3 x 0.8mm max) Applications • LCD Panel VCOM Generator • Electrophoretic Display VCOM Generator Related Literature • AN1627 “ISL24211IRTZ-EVALZ Evaluation Board User Guide” Typical Application 3.3V VDD AVDD 6 3 R1 7 MICROCONTROLLER I2C PORT DVR_OUT SDA 1 SCL I/O PIN 4 ISL24211 INN 10 WP VCOM_OUT 2 R2 LCD PANEL 8 VCOM SET 9 RSET 5 FIGURE 1. TYPICAL ISL24211 APPLICATION February 23, 2011 FN7585.0 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2011. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. ISL24211 Block Diagram VDD 6 AVDD 3 SDA SCL 7 8 I2C INTERFACE DAC REGISTERS ANALOG DCP AND CURRENT SINK Q1 A1 8-Bit EEPROM CS VCOM BUFFER AMPLIFER 2 DVR_OUT A2 10 VCOM_OUT WP 4 1 INN 9 SET 5 GND FIGURE 2. BLOCK DIAGRAM OF THE ISL24211 Pin Configuration ISL24211 (10 LD TDFN) TOP VIEW INN 1 DVR_OUT 2 AVDD 3 WP 4 GND 5 EXPOSED THERMAL PAD* Pin Descriptions PIN NAME INN 10 VCOM_OUT 9 SET 8 SCL 7 SDA 6 VDD PIN NUMBER 1 FUNCTION Negative (inverting) input of the VCOM buffer op amp. This pin is used to provide feedback from the end point of the VCOM trace. Adjustable Sink Current Output Pin. The current sunk into the DVR_OUT pin is equal to the DAC setting times the maximum adjustable sink current divided by 256. See the “SET” pin function description below (pin 9) for the maximum adjustable sink current setting. Also tied to the non-inverting input of buffer amp. Analog Power Supply Input. Bypass to GND with 0.1µF capacitor. EEPROM Write Protect. Active Low. 0 = Programming disabled; 1 = Programming allowed. Ground connection. Digital power supply input. Bypass to GND with 0.1µF capacitor. I2C Serial Data Input I2C Clock Input Maximum Sink Current Adjustment Point. Connect a resistor from SET to GND to set the maximum adjustable sink current of the DVR_OUT pin. The maximum adjustable sink current is equal to (AVDD/20) divided by RSET. Output of the buffer amplifier Thermal pad should be connected to system ground plane to optimize thermal performance. DVR_OUT 2 (*THERMAL PAD CONNECTS TO GND) AVDD WP 3 4 GND VDD SDA SCL SET 5 6 7 8 9 VCOM_OUT PAD 10 - 2 FN7585.0 February 23, 2011 ISL24211 Ordering Information PART NUMBER (Notes 1, 2, 3) ISL24211IRTZ ISL24211IRTZ-EVALZ NOTES: 1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page ISL24211. For more information on MSL please see techbrief TB363. PART MARKING 211Z Evaluation Board INTERFACE I2C TEMP RANGE (°C) -40 to +85 PACKAGE (Pb-Free) 10 Ld 3x3 TDFN PKG. DWG. # L10.3x3A 3 FN7585.0 February 23, 2011 ISL24211 Absolute Maximum Ratings Supply Voltage AVDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20V VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4V Input Voltage with respect to Ground SET, INN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4V SCL, SDA and WP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..VDD + 0.3V Output Voltage with respect to Ground DVR_OUT, VCOM_OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AVDD Continuous Output Current DVR_OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA VCOM_OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100mA ESD Ratings Human Body Model (Tested per JESD22-A114) . . . . . . . . . . . . . . . . . 7kV Machine Model (Tested per JESD22-A115). . . . . . . . . . . . . . . . . . . . 300V Charged Device Model (Tested per JESD22-C101). . . . . . . . . . . . . . . 2kV Latch Up (Tested per JESD 78, Class II, Level A). . . . . . . . . . . . . . . . 100mA Thermal Information Thermal Resistance (Typical) θJA (°C/W) θJC (°C/W) 10 Ld TDFN Package (Notes 4, 5) . . . . . . . 53 11 Moisture Sensitivity (see Technical Brief TB363) All Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Level 1 Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Recommended Operating Conditions Operating Range AVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5V to 19V VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.25V to 3.6V Ambient Operating Temperature . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 4. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 5. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside. Electrical Specifications Test Conditions: VDD = 3.3V, AVDD = 18V, RSET = 5kΩ, R1 = 10kΩ, R2 = 10kΩ, (See Figure 5), VCOM_OUT pin connected to INN, unless otherwise specified. Typicals are at TA = +25°C. Boldface limits apply over the operating temperature range, -40°C to +85°C. SYMBOL PARAMETER TEST CONDITIONS MIN (Note 6) TYP MAX (Note 6) UNITS DC CHARACTERISTICS VDD AVDD AVDD IDD IAVDD ZSESET FSESET TCVSET VDVR_OUT IDVR_OUT INL DNL VDD Supply Range - Operating AVDD Supply Range Supporting EEPROM Programming AVDD Supply Range for Wide-Supply Operation (not supporting EEPROM Programming) VDD Supply Current AVDD Supply Current SET Zero-Scale Error SET Full-Scale Error SET Voltage Drift DVR_OUT Voltage Range Maximum DVR_OUT Sink Current Integral Non-Linearity Differential Non-Linearity IDVR_OUT < 0.5mA VSET + 0.4 4 ±2 ±1 7 AVDD WP = SCL = SDA = VDD WP = SCL = SDA = VDD 2.25 10.8 4.5 95 3.8 3.6 19 19 300 6.5 V V V µA mA DVR_OUT CHARACTERISTICS ±3 ±8 LSB LSB µV/°C V mA LSB LSB OUTPUT AMPLIFIER CHARACTERISTICS VOS TCVOS IB CMRR PSRR AVOL VOL Input Offset Voltage Input Offset Voltage Drift Input Bias Current Common-Mode Rejection Ratio Power Supply Rejection Ratio Open Loop Gain Output Swing Low IL = -5mA 55 60 55 ±2 -6.3 0.001 75 82 75 50 150 ±1 ±15 mV µV/°C µA dB dB dB mV 4 FN7585.0 February 23, 2011 ISL24211 Electrical Specifications Test Conditions: VDD = 3.3V, AVDD = 18V, RSET = 5kΩ, R1 = 10kΩ, R2 = 10kΩ, (See Figure 5), VCOM_OUT pin connected to INN, unless otherwise specified. Typicals are at TA = +25°C. Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued) SYMBOL VOH ISC SR Output Swing High Short Circuit Current (Sinking) Short Circuit Current (Sourcing) Slew Rate (Rising) Slew Rate (Falling) tS BW Settling Time to 0.2% -3dB Bandwidth 1kΩ || 8pF Load 1kΩ || 8pF Load PARAMETER TEST CONDITIONS IL = 5mA MIN (Note 6) 17.85 300 450 70 50 TYP 17.9 430 555 116 93 150 60 MAX (Note 6) UNITS V mA mA V/µs V/µs ns MHz I2C INPUTS AND OUTPUT VIH_I2C VIL_I2C VHYS_I2C IL_I2C VOL_I2C VIH_WP VIL_WP VHYS_WP IL_WP SDA, SCL Logic 1 Input Voltage SDA, SCL Logic 0 Input Voltage SDA, SCL Hysteresis SDA, SCL Input Leakage Current SDA Output Logic Low WP Input Logic High WP Input Logic Low WP Input Hysteresis WP Input Leakage Current I2C Clock Frequency I2C Clock High Time I2C Clock Low Time I2C Spike Rejection Filter Pulse Width I2C Data Set Up Time I2C Data Hold Time I2C Time Between Stop and Start I2C Repeated Start Condition Set-up I2C Repeated Start Condition Hold I2C Stop Condition Set-up SDA Pin Capacitance SCL Pin Capacitance EEPROM Write Cycle Time 0.6 1.3 0 250 250 200 0.6 0.6 0.6 10 10 100 50 -0.20 260 -0.5 -1 I = -3mA 0.7VDD 0.3VDD 260 ±1 0.4 1.44 0.55 V V mV µA V V V mV µA I2C TIMING fCLK tSCH tSCL tDSP tSDS tSDH tBUF tSTS tSTH tSPS CSDA CSCL tWR 400 kHz µs µs ns ns ns µs µs µs µs pF pF ms NOTE: 6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. 5 FN7585.0 February 23, 2011 ISL24211 Application Information LCD panels have a VCOM (common voltage) that must be precisely set to minimize flicker. Figure 3 shows a typical VCOM adjustment circuit using a mechanical potentiometer, and the equivalent circuit replacement using the ISL24211. Having a digital I2C interface enables automatic, digital flicker minimization during production test and alignment. After programming, the I2C interface has no further use therefore, the ISL24211 automatically powers up with the correct VCOM voltage programmed previously. The ISL24211 uses a digitally controllable potentiometer (DCP), with 256 steps of resolution (see Figure 4) to change the current drawn at the DVR_OUT pin, which then changes the voltage created by the R1 to R2 resistor divider (see Figure 5). The DVR_OUT voltage is then buffered by A2 to generate a buffered output voltage at the VCOM_OUT pin, capable of directly driving the VCOM input of an LCD panel. The amount of current sunk is controlled by the setting of the DCP, which is recalled at power-up from the ISL24211’s internal EEPROM. The EEPROM is typically programmed during panel manufacture. As noted in the Electrical Specifications on page 4, the ISL24211 requires a minimum AVDD voltage of 10.8V for EEPROM programming, but will work in normal operation (with no EEPROM programming) down to 4.5V. AVDD AVDD 19R AVDD 20 REGISTER VALUE 255 254 253 252 VDCP R 251 2 1 0 FIGURE 4. SIMPLIFIED SCHEMATIC OF DCP Output Current Sink Figure 5 shows the schematic of the DVR_OUT current sink. The combination of amplifier A1, transistor Q1, and resistor RSET forms a voltage-controlled current source, with the voltage determined by the DCP setting. AVDD RA AVDD DVR_ OUT I DVR_OUT R1 RB R1 = RA R2 = RB+RC RSET = RARB + RARC 20RB RC VCOM R2 VDCP Q1 A1 A2 VCOM_OUT VOUT AVDD VDD ISL24211 IOUT AVDD VCOM GND SET IOUT VSAT INN R1 VCOM_OUT DVR_OUT SET RSET INN VSET = VDCP = IOUT * RSET RSET R2 FIGURE 5. CURRENT SINK CIRCUIT FIGURE 3. MECHANICAL ADJUSTMENT REPLACEMENT DCP (Digitally Controllable Potentiometer) The DCP controls the voltage that ultimately controls the SET current. Figure 4 shows the relationship between the register value and the DCP’s tap position. Note that a register value of 0 selects the first step of the resistor string. The output voltage of the DCP is given in Equation 1: RegisterValue + 1 AV DD V DCP = ⎛ -------------------------------------------------- ⎞ ⎛ --------------⎞ ⎝ ⎠ ⎝ 20 ⎠ 256 (EQ. 1) The external RSET resistor sets the full-scale (maximum) sink current that can be pulled from the DVR_OUT node. The relationship between IDVR_OUT and Register Value is shown in Equation 2. V DCP RegisterValue + 1 AV DD 1 I DVROUT = ------------- = ⎛ -------------------------------------------------- ⎞ ⎛ --------------⎞ ⎛ ------------ ⎞ ⎝ ⎠ ⎝ 20 ⎠ ⎝ R ⎠ 256 R SET SET (EQ. 2) 6 FN7585.0 February 23, 2011 ISL24211 The maximum value of IDVR_OUT can be calculated by substituting the maximum register value of 255 into Equation 2, resulting in Equation 3: A VDD I DVROUT ( MAX ) = ------------------20R SET (EQ. 3) First, verify that our chosen RSET meets the minimum requirement described in Equation 5: 15 ⎛ ⎞ ⎛ ⎞ -----⎜ ⎟ ⎜ ⎟ 16 ( 7.5k Ω ) > ⎜ R SET ( MIN ) = ⎜ ------------------------------⎟ = 0.163k Ω⎟ 15⎞ ⎟ ⎜ ⎛ 6.5V – -----⎜ ⎟ ⎝⎝ ⎝ ⎠ 20⎠ ⎠ (EQ. 9) Equation 2 can also be used to calculate the unit sink current step size per Register Code, resulting in Equation 4: AV DD I STEP = --------------------------------------------( 256 ) ( 20 ) ( R SET ) (EQ. 4) Using Equations 6 and 7, calculate the values of R1 and R2: 8.5 – 6.5 R 1 = 5120 ⋅ 7500 ⋅ ⎛ -------------------------------------⎞ = 35.4k Ω ⎝ 256 ⋅ 8.5 – 6.5⎠ 8.5 – 6.5 R 2 = 5120 ⋅ 7500 ⋅ ⎛ ----------------------------------------------------------------- ⎞ = 46.4k Ω ⎝ 255 ⋅ 15 + 6.5 – 256 ⋅ 8.5⎠ (EQ. 10) Determination of RSET The ultimate goal for the ISL24211 is to generate an adjustable voltage between two endpoints, VCOM_MIN and VCOM_MAX, with a fixed power supply voltage, AVDD. This is accomplished by choosing the correct values for RSET, R1 and R2. The exact value of RSET is not critical. Values from 1k to more than 100k will work under most conditions. The following expression calculates the minimum RSET value: AV DD ⎛ ⎞ -------------⎜ ⎟ 16 R SET ( MIN ) = ⎜ ----------------------------------------------------- ⎟ ( k Ω ) ⎜ AV DD ⎟ ⎜⎛V – --------------⎞ ⎟ ⎝ ⎝ OUT ( MIN ) 20 ⎠ ⎠ (EQ. 5) (EQ. 11) Table 1 shows the resulting VCOM voltage as a function of register value for these conditions. TABLE 1. EXAMPLE VDVR_OUT vs REGISTER VALUE REGISTER VALUE 0 20 40 60 80 100 120 127 140 160 180 200 VDVR_OUT (V) 8.49 8.34 8.18 8.02 7.87 7.71 7.55 7.50 7.40 7.24 7.09 6.93 6.77 6.62 6.50 Note that this is the absolute minimum value for RSET. Larger RSET values reduce quiescent power, since R1 and R2 are proportional to RSET. The ISL24211 is tested with a 5kΩ RSET. Determination of R1 and R2 With AVDD, VCOM(MIN) and VCOM(MAX) known and RSET chosen per the above requirements, R1 and R2 can be determined using Equations 6 and 7: ⎛ V COM ( MAX ) – V COM ( MIN ) ⎞ R 1 = 5120 ⋅ R SET ⎜ --------------------------------------------------------------------------------⎟ ⎝ 256 ⋅ V COM ( MAX ) – V COM ( MIN )⎠ (EQ. 6) V COM ( MAX ) – V COM ( MIN ) ⎛ ⎞ R 2 = 5120 ⋅ R SET ⎜ -------------------------------------------------------------------------------------------------------------------- ⎟ 255 ⋅ AV DD + V COM ( MIN ) – 256 ⋅ V COM ( MAX )⎠ ⎝ (EQ. 7) 220 240 255 Final Transfer Function The voltage at DVR_OUT can be calculated from Equation 8: ⎛ R2 ⎞ ⎛ RegisterValue + 1 ⎛ R 1 -⎞ ⎞ V DVROUT = AV DD ⎜ ------------------- ⎟ ⎜ 1 – -------------------------------------------------- ⎜ ------------------- ⎟ ⎟ R1 + R2 ⎠ ⎝ 256 ⎝ 20R SET⎠ ⎠ ⎝ (EQ. 8) Output Voltage Span Calculation It is also possible to calculate VCOM(MIN) and VCOM(MAX) from the existing resistor values. VCOM_MIN occurs when the greatest current, IDVR(MAX), is drawn from the middle node of the R1/R2 divider. Substituting RegisterValue = 255 into Equation 8 gives the following: ⎛ R1 ⎞ ⎞ ⎛ R2 ⎞ ⎛ V COM ( MIN ) = AV DD ⎜ ------------------- ⎟ ⎜ 1 – ⎜ ------------------- ⎟ ⎟ ⎝ 20R SET⎠ ⎠ ⎝ R1+ R2 ⎠ ⎝ (EQ. 12) With amplifier A2 in the unity-gain configuration (VCOM_OUT tied to INN as shown in Figure 5), VDVROUT = VCOM_OUT = VCOM. Example As an example, suppose the AVDD supply is 15V, the desired VCOM_MIN= 6.5V and the desired VCOM_MAX = 8.5V. RSET is arbitrarily chosen to be 7.5kΩ. Similarly, RegisterValue = 0 for VCOM(MAX): ⎛ R2 ⎞ ⎛ 1 ⎛ R1 ⎞ ⎞ V COM ( MAX ) = AV DD ⎜ ------------------- ⎟ ⎜ 1 – --------- ⎜ ------------------- ⎟ ⎟ R1 + R2 ⎠ ⎝ 256 ⎝ 20R SET⎠ ⎠ ⎝ (EQ. 13) 7 FN7585.0 February 23, 2011 ISL24211 By finding the difference of Equation 13 and Equation 12, the total span of VCOM can be found: ⎛ R2 ⎞ 1 ⎛ R1 ⎞ V COM SPAN = AV DD ⎜ ------------------- ⎟ ⎛ 1 – --------- ⎞ ⎜ ------------------- ⎟ R1+ R2 ⎠ ⎝ 256⎠ ⎝ 20R SET⎠ ⎝ (EQ. 14) Power Supply Sequence The recommended power supply sequencing is shown in Figure 7. When applying power, VDD should be applied before or at the same time as AVDD. The minimum time for tVS is 0µs. When removing power, the sequence of VDD and AVDD is not important. Do not remove VDD or AVDD within 100ms of the start of the EEPROM programming cycle. Removing power before the EEPROM programming cycle is completed may result in corrupted data in the EEPROM. Assuming that the IDVROUT(MIN) = 0 instead of ISTEP, the expression in Equation 14 simplifies to: ⎛ R 1 ⋅ R 2 ⎞ ⎛ AV DD ⎞ ⎛ R1 ⋅ R2 ⎞ V COM SPAN = ⎜ ------------------- ⎟ ⎜ ------------------- ⎟ = ⎜ ------------------- ⎟ I DVROUT ( MAX ) ⎝ R 1 + R 2⎠ ⎝ 20R SET⎠ ⎝ R 1 + R 2⎠ (EQ. 15) DVR_OUT Pin Leakage Current When the voltage on the DVR_OUT pin is greater than 10V, an additional leakage current flows into the pin in addition to the ISET current. Figure 6 shows the ISET current and the DVR_OUT pin current for DVR_OUT pin voltage up to 19V. In applications where the voltage on the DVR_OUT pin will be greater than 10V, the actual output voltage will be lower than the voltage calculated by Equation 8. The graph in Figure 6 was measured with RSET = 4.99kΩ. 0.30 0.25 0.20 0.15 0.10 0.05 0.00 0 SET PIN CURRENT REGISTER = 255 OUT PIN CURRENT VDD AVDD tVS FIGURE 7. POWER SUPPLY SEQUENCE Operating and Programming Supply Voltage and Current To program the EEPROM, AVDD must be ≥10.8V. If programming is not required, the ISL24211 will operate over an AVDD range of 4.5V to 19V. During EEPROM programming, IDD and IAVDD will temporarily be higher than their quiescent currents. Figure 8 shows a typical IDD and IAVDD current profile during EEPROM programming. The current pulses are Erase and Write cycles. The EEPROM programming algorithm is shown in Figure 9. The algorithm attempts up to 4 erase cycles and 4 programming cycles, however typical parts only require 1 cycle of each, sometimes 2 when AVDD is near the minimum 10.8V limit. VDD Programming Current CURRENT (mA) 2 4 6 8 10 12 14 16 18 20 2.7mA OUT PIN VOLTAGE (V) FIGURE 6. DVR_OUT PIN LEAKAGE CURRENT 200µA 50µA ~1ms 90µA AVDD Programming Current IP 25µA 100ms Max FIGURE 8. IDD AND IAVDD CURRENT PROFILE DURING EEPROM PROGRAMMING 8 FN7585.0 February 23, 2011 ISL24211 Start EEPROM Programming ISL24211 Programming The ISL24211 accepts I2C bus address and data when the WP pin is high. The ISL24211 ignores the I2C bus when the WP pin is low. Figure 10 shows the serial data format for writing the register and programming the EEPROM. Figure 11 shows the serial data format for reading the DAC register. Table 2 shows the truth table for reading and writing the device. TABLE 2. ISL24211 READ AND WRITE CONTROL No Erase Pulse Are EEPROM Cells Erased? Yes Write Pulse WP PIN 0 0 R/W 1 0 P FUNCTION Read Register. Will acknowledge I2C transactions. Will not write to register. Will acknowledge I2C transactions. Will not write to EEPROM. Read DAC Register. Write DAC Register. Program EEPROM. X 1 0 0 0 Are EEPROM Cells Programmed? No 1 1 1 1 0 0 X 1 0 Yes EEPROM Programming Complete FIGURE 9. EEPROM PROGRAMMING FLOWCHART Programming the EEPROM memory transfers the current DAC register value to the EEPROM and occurs when the control bits select the programming mode and the AVDD voltage is >10.8V. After the EEPROM programming cycle is started, the WP pin can be returned to logic low while the EEPROM write completes, which takes a maximum of 100ms. The ISL24211 uses a 6-bit I2C address, which is “100111yx” for the first transmitted byte. Bit x is the R/W bit, and Bit y is the LSB (D0) of the DCP register code to be written. The complete read and write protocol is shown in Figures 10 and 11. I2C Bus Signals The ISL24211 uses fixed voltages for its I2C thresholds, rather than the percentage of VDD described in the I2C specification (see Table 3). This should not cause a problem in most systems, but the I2C logic levels in a specific design should be checked to ensure they are compatible with the ISL24211. TABLE 3. ISL24211 I2C BUS LOGIC LEVELS SYMBOL VIL_I2C VIH_I2C ISL24211 0.55V 1.44V I2C STANDARD 0.3*VDD 0.7*VDD 9 FN7585.0 February 23, 2011 I2C Read and Write Format ISL24211 I2C Write Byte 1 Start MSB Start 1 0 0 1 1 1 D0 6 b it Address Data R/W LSB LSB 0 ACK ACK MSB D7 D6 D5 D4 D3 D2 D1 Byte 2 Data P LSB P ACK Stop ACK Stop 10 Start Start FN7585.0 February 23, 2011 R/W = 0 = Write R/W = 1 = Read FIGURE 10. I2C WRITE FORMAT When R/W = 0 P = 0: Program EEPROM P = 1: Write Register ISL24211 ISL24211 I2C Read Byte 1 6 bit Address MSB 1 0 0 1 1 1 X X R/W LSB 1 ACK Start ACK Start MSB D7 D6 D5 D4 D3 D2 D1 Byte 2 Data LSB D0 ACK Stop ACK Stop R/W = 0 = Write R/W = 1 = Read FIGURE 11. I2C READ FORMAT ISL24211 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest revision. DATE 2/23/11 REVISION FN7585.0 Initial Release. CHANGE Products Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a complete list of Intersil product families. *For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on intersil.com: ISL24211 To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff FITs are available from our website at http://rel.intersil.com/reports/sear For additional products, see www.intersil.com/product_tree Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 11 FN7585.0 February 23, 2011 ISL24211 Package Outline Drawing L10.3x3A 10 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE Rev 5, 3/10 3.00 A 6 PIN 1 INDEX AREA 6 PIN 1 INDEX AREA 1 2.0 REF 8X 0.50 BSC 5 10X 0 . 30 B 3.00 1.50 0.15 (4X) 10 5 0.10 M C A B 0.05 M C 4 10 X 0.25 TOP VIEW 2.30 ( 2.30 ) BOTTOM VIEW 0 .80 MAX SEE DETAIL "X" 0.10 C C (2.90) (1.50) SIDE VIEW (10 X 0.50) 0 . 2 REF SEATING PLANE 0.08 C 5 ( 8X 0 .50 ) ( 10X 0.25 ) TYPICAL RECOMMENDED LAND PATTERN NOTES: 1. 2. 3. 4. C 0 . 00 MIN. 0 . 05 MAX. DETAIL "X" Dimensions are in millimeters. Dimensions in ( ) for Reference Only. Dimensioning and tolerancing conform to ASME Y14.5m-1994. Unless otherwise specified, tolerance : Decimal ± 0.05 Angular ±2.50° Dimension applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. 6. Tiebar shown (if present) is a non-functional feature. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Compliant to JEDEC MO-229-WEED-3 except exposed pad length (2.30mm). 12 FN7585.0 February 23, 2011