ISL267440

10-Bit and 12-Bit, 1MSPS SAR ADCs ISL267440, ISL267450A The ISL267440 and ISL267450A are 10-bit and 12-bit, 1MSPS sampling SAR-type ADCs featuring excellent linearity over supply and temperature variations, which are drop-in compatible with the AD7440 and AD7450A. The robust, fully-differential input offers high impedance to minimize errors due to leakage currents, and the specified measurement accuracy is maintained with input signals up to the supply rails. The reference accepts inputs from 0.1V to 2.2V for 3V operation and 0.1V to 3.5V for 5V operation, which provides design flexibility in a wide variety of applications. The ISL267440, ISL267450A also feature up to 8kV Human Body Model ESD survivability. The serial digital interface is SPI compatible and is easily interfaced to all popular FPGAs and microcontrollers. Power dissipation is 8.5mW at a sampling rate of 1MSPS, and just 5µW between conversions utilizing Auto Power-Down mode (with a 5V supply), making the ISL267440, ISL267450A excellent solutions for remote industrial sensors and battery-powered instruments. The ISL267440, ISL267450A are available in an 8 lead MSOP package, and are specified for operation over the Industrial temperature range (–40°C to +85°C). Features • Drop-in Compatible with AD7440, AD7450A • Differential Input • Simple SPI-compatible Serial Digital Interface • Guaranteed No Missing Codes • 1MHz Sampling Rate • 3V or 5V Operation • Low Operating Current - 1.25mA at 1MSPS with 3V Supplies - 1.70mA at 1MSPS with 5V Supplies • Power-down Current between Conversions: 1µA • Excellent Differential Non-Linearity • Low THD: -83dB (typ) • Pb-Free (RoHS Compliant) • Available in MSOP Package Applications • Remote Data Acquisition • Battery Operated Systems • Industrial Process Control • Energy Measurement • Data Acquisition Systems • Pressure Sensors • Flow Controllers 1.0 0.8 0.6 VREF DAC VDD 0.4 DNL (LSB) 0.2 0.0 -0.2 -0.4 -0.6 VIN+ VIN– DAC SAR LOGIC SERIAL INTERFACE SCLK SDATA CS VREF -0.8 -1.0 GND 0 1024 2048 CODE 3072 4096 FIGURE 1. BLOCK DIAGRAM FIGURE 2. DIFFERENTIAL LINEARITY ERROR vs CODE December 5, 2011 FN7708.0 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2011. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. ISL267440, ISL267450A Typical Connection Diagram + VREF +3V/5V + 0.1μF + 10μ F SUPPLY VREF REFP-P REFP-P VIN+ VIN– GND VDD SCLK SDATA CS SERIAL INTERFACE μP/μC Pin Configuration ISL267440, ISL267450A (8 LD MSOP) TOP VIEW VREF 1 VIN+ 2 VIN– 3 GND 4 8 VDD 7 SCLK 6 SDATA 5 CS Pin Descriptions ISL267440, ISL267450A PIN NAME VDD SCLK SDATA CS GND VIN– VIN+ VREF PIN NUMBER 8 7 6 5 4 3 2 1 Supply voltage, +2.7V to 5.25V. Serial clock input. Controls digital I/O timing and clocks the conversion. Digital conversion output. Chip select input. Generally controls the start of a conversion though not always the sampling signal. Ground Negative analog input. Positive analog input. Reference voltage. DESCRIPTION 2 FN7708.0 December 5, 2011 ISL267440, ISL267450A Ordering Information PART NUMBER (Note 4) ISL267440IUZ (Note 3) ISL267440IUZ-T (Notes 1, 3) ISL267440IUZ-T7A (Notes 1, 3) ISL267450AIUZ (Note 3) ISL267450AIUZ -T (Notes 1, 3) ISL267450AIUZ -T7A (Notes 1, 3) Coming Soon ISL267440IHZ-T (Notes 1, 2) Coming Soon ISL267440IHZ-T7A (Notes 1, 2) Coming Soon ISL267450AIHZ-T (Notes 1, 2) Coming Soon ISL267450AIHZ-T7A (Notes 1, 2) NOTES: 1. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate -e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 4. For Moisture Sensitivity Level (MSL), please see device information page for ISL267440 or ISL267450A . For more information on MSL please see techbrief TB363. PART MARKING 67440 67440 67440 7450A 7450A 7450A 7440 7440 450A 450A VDD RANGE (V) 2.7 to 5.25 2.7 to 5.25 2.7 to 5.25 2.7 to 5.25 2.7 to 5.25 2.7 to 5.25 2.7 to 5.25 2.7 to 5.25 2.7 to 5.25 2.7 to 5.25 TEMP RANGE (°C) -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C PACKAGE 8 Ld MSOP 8 Ld MSOP 8 Ld MSOP 8 Ld MSOP 8 Ld MSOP 8 Ld MSOP 8 Ld SOT-23 8 Ld SOT-23 8 Ld SOT-23 8 Ld SOT-23 PKG. DWG. # M8.118 M8.118 M8.118 M8.118 M8.118 M8.118 P8.064 P8.064 P8.064 P8.064 3 FN7708.0 December 5, 2011 ISL267440, ISL267450A Table of Contents Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Typical Performance Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 ADC Transfer Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Analog Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Voltage Reference Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Power-Down/Standby Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Dynamic Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Static Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Short Cycling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Power-on Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Power vs Throughput Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Serial Digital Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Adjustable Low-Noise Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Application Hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Grounding and Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Package Outline Drawing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4 FN7708.0 December 5, 2011 ISL267440, ISL267450A Absolute Maximum Ratings Any Pin to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.0V Analog Input to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VDD+0.3V Digital I/O to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VDD+0.3V Digital Input Voltage to GND . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VDD+0.3V Maximum Current In to Any Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA ESD Rating Human Body Model (Tested per JESD22-A114F) . . . . . . . . . . . . . . . . 8kV Machine Model (Tested per JESD22-A115B) . . . . . . . . . . . . . . . . . 400V Charged Device Model (Tested per JESD22-C101E). . . . . . . . . . . . 1.5kV Latch Up (Tested per JESD78C; Class 2, Level A) . . . . . . . . . . . . . . . 100mA Thermal Information Thermal Resistance (Typical) θJA (°C/W) θJC (°C/W) 8 Ld MSOP Package (Notes 5, 6). . . . . . . . . 165 64 8 Ld SOT-23 Package (Notes 5, 6). . . . . . . . 135 99 Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 5. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 6. For θJC, the “case temp” location is taken at the package top center. Electrical Specifications VDD = +3.0V to +3.6V, fSCLK = 18MHz, fS = 1MSPS, VREF = 2.0V; VDD = +4.75V to +5.25V, fSCLK = 18MHz, fS = 1MSPS, VREF = 2.5V; VCM = VREF, unless otherwise noted. Typical values are at TA = +25°C. Boldface limits apply over the operating temperature range, -40°C to +85°C. ISL267440 SYMBOL SINAD PARAMETER TEST CONDITIONS MIN (Note 7) 61.0 60.7 TYP 61.6 61.5 -82 -80 -82 -82 -92 1 15 @ –3dB 10 -0.5 Guaranteed no missed codes to 12 bits (ISL267450A) or 10 bits (ISL267440) Zero Volt Differential Input ± REF input range -0.5 ±0.1 ±0.1 0.5 0.5 15 12 -1 -0.95 ±0.4 ±0.3 1 0.95 -74 -72 -76 -74 MAX MIN (Note 7) (Note 7) 70.0 68.5 ISL267450A TYP 71.4 70.5 -84 -84 -87 -85 -95 1 15 15 -76 -74 -76 -74 dB dB dB dB dB ns ps MHz Bits LSB LSB MAX (Note 7) UNITS dB DYNAMIC PERFORMANCE Signal-to (Noise + Distortion) Ratio fIN = 100kHz VDD = +4.75V to +5.25V fIN = 100kHz VDD = +3.0V to +3.6V THD Total Harmonic Distortion fIN = 100kHz VDD = +4.75V to +5.25V fIN = 100kHz VDD = +3.0V to +3.6V SFDR Spurious Free Dynamic Range fIN = 100kHz VDD = +4.75V to +5.25V fIN = 100kHz VDD = +3.0V to +3.6V IMD tpd Δtpd β3dB N INL DNL Intermodulation Distortion Aperture Delay Aperture Jitter Full Power Bandwidth Resolution Integral Nonlinearity Differential Nonlinearity 2nd and 3rd order, fIN = 90kHz, 110kHz DC ACCURACY OFFSET GAIN Zero-Code Error Positive Gain Error Negative Gain Error Full-Scale Input Span -2.5 -1 -1 ±0.2 ±0.1 ±0.1 VIN+ - VIN– 2.5 1 1 -6 -2 -2 ±0.2 ±0.1 ±0.1 VIN+ - VIN– 6 2 2 LSB LSB ANALOG INPUT (Note 8) |AIN| 2 x VREF V 5 FN7708.0 December 5, 2011 ISL267440, ISL267450A Electrical Specifications VDD = +3.0V to +3.6V, fSCLK = 18MHz, fS = 1MSPS, VREF = 2.0V; VDD = +4.75V to +5.25V, fSCLK = 18MHz, fS = 1MSPS, VREF = 2.5V; VCM = VREF, unless otherwise noted. Typical values are at TA = +25°C. Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued) ISL267440 SYMBOL VIN+, VIN– VIN+ VIN– ILEAK CVIN REF Input DC Leakage Current Input Capacitance REF Input Voltage Range Track/Hold mode VDD = 3V (1% tolerance for specified performance) VDD = 5V (1% tolerance for specified performance) ILEAK CREF VIH VIL ILEAK CIN VOH VOL IOZ COUT DC Leakage Current REF Input Capacitance Input High Voltage Input Low Voltage Input Leakage Current Input Capacitance Output High Voltage Output Low Voltage Floating-State Output Current Floating-State Output Capacitance Output Coding CONVERSION RATE tCONV tACQ fmax VDD IDD Conversion Time Acquisition Time Throughput Rate Positive Supply Voltage Range Positive Supply Input Current Static Dynamic Power Dissipation Static Mode Dynamic NOTES: 7. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. 8. The absolute voltage applied to each analog input must be between GND and VDD to guarantee datasheet performance. VDD = 3V VDD = 5V VDD = 3V, fsmpl = 1MSPS VDD = 5V, fsmpl = 1MSPS 3 5 3.75 8.50 3 5 3.75 8.50 µW µW mW mW 3V 5V 1 1250 1700 1 1250 1700 µA µA µA 2.7 4.75 fSCLK = 18MHz 888 200 1000 3.6 5.25 2.7 4.75 888 200 1000 3.6 5.25 ns ns kSPS V V ISOURCE = 200µA ISINK = 200µA -1 10 Two’s Complement VDD - 0.3 0.4 1 -1 10 -1 10 VDD - 0.3 0.4 1 Track/Hold mode 2.4 0.8 1 -1 10 -1 21/18.5 2.4 0.8 1 -1 13/5 2.0 2.5 1 -1 21/18.5 PARAMETER Absolute Input Voltage Range VCM = VREF VCM ±VREF/2 VCM ±VREF/2 1 -1 13/5 2.0 2.5 1 VCM ±VREF/2 VCM±VREF/2 1 µA pF V V μA pF V V µA pF V V µA pF TEST CONDITIONS MIN (Note 7) TYP MAX MIN (Note 7) (Note 7) ISL267450A TYP MAX (Note 7) UNITS REFERENCE INPUT LOGIC INPUTS LOGIC OUTPUTS POWER REQUIREMENTS 6 FN7708.0 December 5, 2011 ISL267440, ISL267450A Timing Specifications Limits established by characterization and are not production tested. VDD = 3.0V to 3.6V, fSCLK = 18MHz, fS = 1MSPS, VREF = 2.0V; VDD = 4.75V to 5.25V, fSCLK = 18MHz, fS = 1MSPS, VREF = 2.5V; VCM = VREF unless otherwise noted. Boldface limits apply over the operating temperature range, -40°C to +85°C. SYMBOL fSCLK tSCLK tACQ tCONV tCSW tCSS tCDV tCLKDV tSDH tSW tDISABLE tQUIET Clock Frequency Clock Period Acquisition Time Conversion Time CS Pulse Width CS Falling Edge to SCLK Falling Edge Setup Time CS Falling Edge to SDATA Valid SCLK Falling Edge to SDATA Valid SCLK Falling Edge to SDATA Hold SCLK Pulse Width SCLK Falling Edge to SDATA Disable Time (Note 9) Quiet Time Before Sample Extrapolated back to true bus relinquish 10 0.4 x tSCLK 10 60 35 10 10 20 40 PARAMETER TEST CONDITIONS MIN (Note 7) 0.01 55 200 888 TYP MAX (Note 7) 18 UNITS MHz ns ns ns ns ns ns ns ns ns ns ns NOTE: 9. During characterization, tDISABLE is measured from the release point with a 10pF load (see Figure 4) and the equivalent timing using the AD7440/450A loading (25pF) is calculated. 18M Hz = 55.5556ns PERIO D CYCLE CSB SCLK 1 2 D0 3 D0 4 M SB 5 BIT10 6 BIT9 7 BIT8 8 BIT7 9 BIT6 10 BIT5 11 BIT4 1 2 3 4 5 T/H TO HO LD M ODE , DOUT VALID 6 7 8 9 10 11 12 13 14 15 16 17 18 T/H TO SAM PLE M ODE 12 BIT3 13 BIT2 14 DOUT TRISTATE 15 BIT1 BIT0 16 D0 DO UT D0 ISL267450A DATA O UTPUT DO UT D0 D0 D0 D0 M SB BIT8 BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 ISL267440 DATA O UTPUT FIGURE 3. SERIAL INTERFACE TIMING DIAGRAM VDD RL 2.85kΩ OUTPUT PIN CL 10pF FIGURE 4. EQUIVALENT LOAD CIRCUIT 7 FN7708.0 December 5, 2011 ISL267440, ISL267450A Typical Performance Characteristics 75 5.25V -20 70 SINAD (dBc) 2.7V 65 3.6V AMPLITUDE (dBFS) 4.75V -40 -60 -80 -100 -120 55 -140 0 100 200 300 400 500 FREQUENCY (kHz) 0 8192-POINT FFT fSAMPLE = 1MSPS fIN = 95.2kHz SINAD = 72.0dB THD = -91dB SFDR = 93dB 60 10 100 INPUT FREQUENCY (kHz) 1k FIGURE 5. ISL267450A SINAD vs ANALOG INPUT FREQUENCY FOR VARIOUS SUPPLY VOLTAGES FIGURE 6. ISL267450A DYNAMIC PERFORMANCE WITH VDD = 5V 0 -10 -20 -30 CMRR (dB) DNL (LSB) 100k FREQUENCY (Hz) 1k 10k -40 -50 -60 -70 -80 -90 -100 10k 1.0 0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 0 1024 2048 CODE 3072 4096 FIGURE 7. CMRR vs FREQUENCY FOR VDD = 5V FIGURE 8. TYPICAL DNL FOR THE ISL267450A FOR VDD = 5V 0 250mVP-P SINE WAVE ON VDD NO DECOUPLING ON VDD -20 1.0 0.8 0.6 0.4 INL (LSB) 100 200 300 400 500 600 700 800 900 1000 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -40 PSRR (dB) -60 -80 -100 -120 0 -1.0 0 1024 2048 CODE 3072 4096 FREQUENCY (kHz) FIGURE 9. PSRR vs SUPPLY RIPPLE FREQUENCY WITHOUT SUPPLY DECOUPLING FIGURE 10. TYPICAL INL FOR THE ISL267450A FOR VDD = 5V 8 FN7708.0 December 5, 2011 ISL267440, ISL267450A Typical Performance Characteristics 3.0 2.5 2.0 DNL (LSB) 1.5 INL (LSB) 1.0 Pos DNL 0.5 0.0 -0.5 -1.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VREF (V) Neg DNL -1.0 -1.5 -2.0 0.0 0.5 1.0 VREF (V) 1.5 2.0 2.5 (Continued) 2.5 2.0 1.5 1.0 0.5 0.0 -0.5 Neg INL Pos INL FIGURE 11. CHANGE IN DNL vs VREF FOR THE ISL267450A FOR VDD = 5V FIGURE 12. CHANGE IN INL vs VREF FOR THE ISL267450A FOR VDD = 3V 2.5 2.0 ZERO CODE ERROR (LSB) 1.5 DNL (LSB) 1.0 0.5 0.0 -0.5 -1.0 0.0 0.5 1.0 VREF (V) 1.5 2.0 2.5 Neg DNL 6 5 4 3 2 3V VDD 1 0 -1 -2 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VREF (V) 5V VDD Pos DNL FIGURE 13. CHANGE IN DNL VS. VREF FOR THE ISL267450A FOR VDD = 3V 5 4 3 2 INL (LSB) 1 0 -1 Neg INL -2 -3 -4 -5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VREF (V) Pos INL FIGURE 14. CHANGE IN OFFSET ERROR vs REFERENCE VOLTAGE FOR VDD = 5V AND 3V FOR THE ISL267450A 12.0 11.5 11.0 10.5 ENOB (BITS) 10.0 9.5 9.0 8.5 8.0 7.5 7.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VREF (V) 3V VDD 5V VDD FIGURE 15. CHANGE IN INL vs VREF FOR THE ISL267450A FOR VDD = 5V FIGURE 16. CHANGE IN ENOB vs REFERENCE VOLTAGE FOR VDD = 5V AND 3V FOR THE ISL267450A 9 FN7708.0 December 5, 2011 ISL267440, ISL267450A Typical Performance Characteristics 70k 60k 50k 40k 30k 20k 10k 10 CODES 0 2044 2045 2046 2047 CODE 10 CODES 2048 2049 2050 DNL (LSB) 65,516 CODES (Continued) 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 0 256 512 CODE 768 1024 HITS FIGURE 17. HISTOGRAM OF 10,000 CONVERSIONS OF A DC INPUT FOR THE ISL267450A WITH VDD = 5V 0 -20 AMPLITUDE (dBFS) -40 -60 -80 -100 -120 8192-POINT FFT fSAMPLE = 1MSPS fIN = 95.2kHz SINAD = 61.6dB THD = -75dB SFDR = 81dB INL (LSB) 0 100 200 300 400 500 FIGURE 18. TYPICAL DNL FOR THE ISL267440 FOR VDD = 5V 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -140 FREQUENCY (kHz) -0.5 0 256 512 768 1024 CODE FIGURE 19. ISL267440 DYNAMIC PERFORMANCE WITH VDD = 5V FIGURE 20. TYPICAL INL FOR THE ISL267440 FOR VDD = 5V 10 FN7708.0 December 5, 2011 ISL267440, ISL267450A Functional Description The ISL267440, ISL267450A are based on a successive approximation register (SAR) architecture utilizing capacitive charge redistribution digital to analog converters (DACs). Figure 21 shows a simplified representation of the converter. During the acquisition phase (ACQ) the differential input is stored on the sampling capacitors (CS). The comparator is in a balanced state since the switch across its inputs is closed. The signal is fully acquired after tACQ has elapsed, and the switches then transition to the conversion phase (CONV) so the stored voltage may be converted to digital format. The comparator will become unbalanced when the differential switch opens and the input switches transition (assuming that the stored voltage is not exactly at mid-scale). The comparator output reflects whether the stored voltage is above or below mid-scale, which sets the value of the MSB. The SAR logic then forces the capacitive DACs to adjust up or down by one quarter of full-scale by switching in binarily weighted capacitors. Again, the comparator output reflects whether the stored voltage is above or below the new value, setting the value of the next lowest bit. This process repeats until all 12 bits have been resolved. DAC 011...111 011...110 1LSB = 2 x REF/4096 ADC CODE 000...001 000...000 111...111 100...010 100...001 100...000 -REF + 1 LSB 0LSB +REF - 1 LSB ANALOG INPUT (VIN+ – V IN-) FIGURE 22. IDEAL TRANSFER CHARACTERISTICS Analog Input The ISL267440, ISL267450A feature a fully differential input with a nominal full-scale range equal to twice the applied VREF voltage. Each input swings VREF VP-P, 180° out of phase from one another for a total differential input of 2*VREF (refer to Figure 23). Differential signaling offers several benefits over a single-ended input, such as: • Doubling of the full-scale input range (and therefore the dynamic range) • Improved even order harmonic distortion • Better noise immunity due to common mode rejection CONV CS VIN+ VIN– ACQ ACQ CONV ACQ CONV SAR LOGIC CS FIGURE 21. SAR ADC ARCHITECTURAL BLOCK DIAGRAM DAC VREF VREF PP VIN+ ISL267440, ISL267450A An external clock must be applied to the SCLOCK pin to generate a conversion result. The allowable frequency range for SCLOCK is 10kHz to 18MHz (556SPS to 1MSPS). Serial output data is transmitted on the falling edge of SCLOCK. The receiving device (FPGA, DSP or Microcontroller) may latch the data on the rising edge of SCLOCK to maximize set-up and hold times. A stable, low-noise reference voltage must be applied to the VREF pin to set the full-scale input range and common-mode voltage. See “Voltage Reference Input” on page 12 for more details. VCM VREF PP VIN– FIGURE 23. DIFFERENTIAL INPUT SIGNALING Figure 24 shows the relationship between the reference voltage and the full-scale input range for two different values of VREF. ADC Transfer Function The output coding for the ISL267440, ISL267450A is twos complement. The first code transition occurs at successive LSB values (i.e., 1 LSB, 2 LSB, and so on). The LSB size of the ISL267450A is 2*VREF/4096, while the LSB size of the ISL267440 is 2*VREF/1024. The ideal transfer characteristic of the ISL267440, ISL267450A is shown in Figure 22. 11 FN7708.0 December 5, 2011 ISL267440, ISL267450A V VCM 2.5 2.5 2.0 1.5 1.0 t VREF = 2V 5.0 4.0 VIN+ 3.0 2.0VP-P VIN– VCM 2.0V 2.0 1.0 1.0V 0.5 VREF 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 V 5.0 VIN– 4.0 2.5VP-P VIN+ VCM 3.0 FIGURE 26. RELATIONSHIP BETWEEN VREF AND VCM FOR VDD = 3V Voltage Reference Input An external low-noise reference voltage must be applied to the VREF pin to set the full-scale input range of the converter. The reference input accepts voltages ranging from 0.1V to 2.2V for 3V operation and 0.1V to 3.5V for 5V operation. The device is specified with a reference voltage of 2.5V for 5V operation and 2.0V for 3V operation. This pin should be decoupled with a combination of a 1µF electrolytic capacitor and a 0.1µF ceramic capacitor on the PC board. Since the full-scale input range is proportional to the applied VREF, any noise or drift will appear as an error in the conversion result. A low-noise, low-drift reference, such as the ISL2100x family, may be used to maximize system performance, as shown in Figure 27. The VREF pin typically draws 4µA and the current is dependent upon the sampled voltage. This can result in a code-dependent error if there is excessive series resistance or the reference lacks sufficient load regulation; therefore, buffering may be necessary. 2.0 1.0 t VREF = 2.5V FIGURE 24. RELATIONSHIP BETWEEN VREF AND FULL-SCALE RANGE Note that there is a trade-off between VREF and the allowable common mode input voltage (VCM). The full-scale input range is proportional to VREF; therefore the VCM range must be limited for larger values of VREF in order to keep the absolute maximum and minimum voltages on the VIN+ and VIN– pins within specification. Figures 25 and 26 illustrate this relationship for 5V and 3V operation, respectively. The dashed lines show the theoretical VCM range based solely on keeping the VIN+ and VIN– pins within the supply rails. Additional restrictions are imposed due to the required headroom of the input circuitry, resulting in practical limits shown by the shaded area. VCM ISL21009-25 VOUT + ISL267440, ISL267450A VREF 5.0 4.0 3.0 2.0 1.0 VREF 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.25V 3.25V 2.5V FIGURE 27. BUFFERED VOLTAGE REFERENCE Power-Down/Standby Modes 1.75V FIGURE 25. RELATIONSHIP BETWEEN VREF AND VCM FOR VDD = 5V The mode of operation of the ISL267440, ISL267450A is selected by controlling the logic state of the CS signal during a conversion. There are two possible modes of operation: dynamic mode or static mode. When CS is high (deasserted) the ADC will be in static mode. Conversely, when CS is low (asserted) the device will be in dynamic mode. There are no minimum or maximum number of SCLOCK cycles required to enter static mode, which simplifies power management and allows the user to easily optimize power dissipation versus throughput for different application requirements. 12 FN7708.0 December 5, 2011 ISL267440, ISL267450A DYNAMIC MODE This mode is entered when a conversion result is desired by asserting CS. Figure 28 shows the general diagram of operation in this mode. The conversion is initiated on the falling edge of CS, as described in “Serial Digital Interface” on page 13. As soon as CS is brought high, the conversion will be terminated and SDATA will go back into three-state. Sixteen serial clock cycles are required to complete the conversion and access the complete conversion result. CS may idle high until the next conversion or idle low until sometime prior to the next conversion. Once a data transfer is complete, i.e., when SDATA has returned to threestate, another conversion can be initiated by again bringing CS low. CS 100 10 POWER (mW) VDD = 5V 1 0.1 VDD = 3V 0.01 0 50 100 150 200 250 300 350 THROUGHPUT (Ksps) 1 10 16 FIGURE 29. POWER CONSUMPTION vs THROUGHPUT RATE SCLK Serial Digital Interface SDATA NULL BIT AND CONVERSION RESULT FIGURE 28. NORMAL MODE OPERATION STATIC MODE The ISL267440, ISL267450A enter the power-saving static mode automatically any time CS is deasserted. It is not required that the user force a device into this mode following a conversion in order to optimize power consumption. Conversion data is accessed with an SPI-compatible serial interface. The interface consists of the data clock (SCLOCK), serial data output (SDATA), and chip select (CS). A falling edge on the CS signal initiates a conversion by placing the part into the acquisition (ACQ) phase. After tACQ has elapsed, the part enters the conversion (CONV) phase and begins outputting the conversion result starting with a null bit followed by the most significant bit (MSB) and ending with the least significant bit (LSB). The CS pin can be pulled high at this point to put the device into Standby mode and reduce the power consumption. If CS is held low after the LSB bit has been output, the serial output enters a high impedance state. The ISL267440, ISL267450A will remain in this state, dissipating typical dynamic power levels, until CS transitions high then low to initiate the next conversion. SHORT CYCLING In cases where a lower resolution conversion is acceptable, CS can be pulled high before 12 SCLOCK falling edges have elapsed. This is referred to as short cycling, and it can be used to further optimize power dissipation. In this mode a lower resolution result will be acquired, but the ADC will enter static mode sooner and exhibit a lower average power dissipation than if the complete conversion cycle were carried out. The acquisition time (tACQ) requirement must be met for the next conversion to be valid. Data Format Output data is encoded in two’s complement format as shown in Table 1. The voltage levels in the table are idealized and don’t account for any gain/offset errors or noise. TABLE 1. TWO’S COMPLEMENT DATA FORMATTING INPUT –Full Scale –Full Scale + 1LSB Midscale +Full Scale – 1LSB +Full Scale VOLTAGE –VREF –VREF+ 1LSB 0 +VREF– 1LSB +VREF DIGITAL OUTPUT 1000 0000 0000 1000 0000 0001 0000 0000 0000 0111 1111 1110 0111 1111 1111 POWER-ON RESET The ISL267440, ISL267450A performs a power-on reset when the supplies are first activated, which requires approximately 2.5ms to execute. After this is complete, a single dummy cycle must be executed in order to initialize the switched capacitor track and hold. A dummy cycle will take 1μs with an 18MHz SCLOCK. Once the dummy cycle is complete, the ADC mode will be determined by the state of CS. At this point, switching between dynamic and static modes is controlled by CS with no delay required between states. POWER vs THROUGHPUT RATE The ISL267440, ISL267450A provide reduced power consumption at lower conversion rates by automatically switching into a low-power mode after completing a conversion. The average power consumption of the ADC decreases at lower throughput rates. Figure 29 shows the typical power consumption over a wide range of throughput rates. Applications Information Adjustable Low-Noise Reference Figure 30 illustrates how a Digitally Controlled Potentiometer (DCP) can be used in conjunction with a low-noise, low-drift reference to realize an adjustable input range with high system accuracy. The voltage reference output is connected to the high terminal of the DCP and the wiper terminal is buffered and 13 FN7708.0 December 5, 2011 ISL267440, ISL267450A connected to the ADC reference. Buffering is required since the ISL267440, ISL267450A reference input current will cause a voltage drop across the DCP element (100kΩ from RH to RL), impacting accuracy and increasing temperature drift. for which neither m nor n are equal to zero. For example, the second order terms include (fa + fb) and (fa – fb), while the third order terms include (2fa + fb), (2fa – fb), (fa + 2fb), and (fa –2fb). The ISL267440, ISL267450A is tested using the CCIF standard, where two input frequencies near the top end of the input bandwidth are used. In this case, the second order terms are usually distanced in frequency from the original sine waves, while the third order terms are usually at a frequency close to the input frequencies. As a result, the second and third order terms are specified separately. The calculation of the intermodulation distortion is as per the THD specification, where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in dBs. Aperture Delay FIGURE 30. ADJUSTABLE BUFFERED VOLTAGE REFERENCE VOUT RH RL RW 2.5V Terminology Signal-to-(Noise + Distortion) Ratio (SINAD) This is the measured ratio of signal-to-(noise + distortion) at the output of the ADC. The signal is the rms amplitude of the fundamental. Noise is the sum of all nonfundamental signals up to half the sampling frequency (fs/2), excluding DC. The ratio is dependent on the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. The theoretical signal-to-(noise + distortion) ratio for an ideal N-bit converter with a sine wave input is given by: Signal-to-(Noise + Distortion) = ( 6.02 N + 1.76 ) dB (EQ. 1) Thus, for a 12-bit converter this is 74dB, and for a 10-bit this is 62dB. Total Harmonic Distortion Total harmonic distortion (THD) is the ratio of the rms sum of harmonics to the fundamental. For the ISL267440, ISL267450A, it is defined as: V 22 + V 32 + V 42 + V 52 + V 62 THD ( dB ) = 20 log ----------------------------------------------------------------------V 12 (EQ. 2) where V1 is the rms amplitude of the fundamental and V2, V3, V4, V5, and V6 are the rms amplitudes of the second to the sixth harmonics. Peak Harmonic or Spurious Noise (SFDR) Peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the ADC output spectrum (up to fS/2 and excluding DC) to the rms value of the fundamental (also referred to as Spurious Free Dynamic Range (SFDR)). Normally, the value of this specification is determined by the largest harmonic in the spectrum, but for ADCs where the harmonics are buried in the noise floor, it will be a noise peak. Intermodulation Distortion With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities will create distortion products at sum and difference frequencies of mfa ± nfb where m and n = 0, 1, 2 or 3. Intermodulation distortion terms are those 14 + ISL21009-25 X9119 ISL267440, ISL267450A VREF This is the amount of time from the leading edge of the sampling clock until the ADC actually takes the sample. Aperture Jitter This is the sample-to-sample variation in the effective point in time at which the actual sample is taken. Full Power Bandwidth The full power bandwidth of an ADC is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3dB for a full-scale input. Common-Mode Rejection Ratio (CMRR) The common-mode rejection ratio is defined as the ratio of the power in the ADC output at full-scale frequency, f, to the power of a 250mVP-P sine wave applied to the common-mode voltage of VIN+ and VIN– of frequency fs: CMRR ( dB ) = 10 log ( Pfl ⁄ Pfs ) (EQ. 3) Pf is the power at the frequency f in the ADC output; Pfs is the power at frequency fs in the ADC output. Integral Nonlinearity (INL) This is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function. Differential Nonlinearity (DNL) This is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. Zero-Code Error This is the deviation of the midscale code transition (111...111 to 000...000) from the ideal VIN+ – VIN– (i.e., 0 LSB). Positive Gain Error This is the deviation of the last code transition (011...110 to 011...111) from the ideal VIN+ – VIN– (i.e., +REF – 1 LSB), after the zero code error has been adjusted out. Negative Gain Error This is the deviation of the first code transition (100...000 to 100...001) from the ideal VIN+ – VIN– (i.e., – REF + 1 LSB), after the zero code error has been adjusted out. FN7708.0 December 5, 2011 ISL267440, ISL267450A Track and Hold Acquisition Time The track and hold acquisition time is the minimum time required for the track and hold amplifier to remain in track mode for its output to reach and settle to within 0.5 LSB of the applied input signal. Power Supply Rejection Ratio (PSRR) The power supply rejection ratio is defined as the ratio of the power in the ADC output at full-scale frequency, f, to ADC VDD supply of frequency fS. The frequency of this input varies from 1kHz to 1MHz. PSRR ( dB ) = 10 log ( Pf ⁄ Pfs ) (EQ. 4) Application Hints Grounding and Layout The printed circuit board that houses the ISL267440, ISL267450A should be designed so that the analog and digital sections are separated and confined to certain areas of the board. This facilitates the use of ground planes that can be easily separated. A minimum etch technique is generally best for ground planes since it gives the best shielding. Digital and analog ground planes should be joined in only one place, and the connection should be a star ground point established as close to the GND pin on the ISL267440, ISL267450A as possible. Avoid running digital lines under the device, as this will couple noise onto the die. The analog ground plane should be allowed to run under the ISL267440, ISL267450A to avoid noise coupling. The power supply lines to the device should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching signals, such as clocks, should be shielded with digital ground to avoid radiating noise to other sections of the board, and clock signals should never run near the analog inputs. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This reduces the effects of feedthrough through the board. A microstrip technique is by far the best but is not always possible with a double-sided board. In this technique, the component side of the board is dedicated to ground planes, while signals are placed on the solder side. Good decoupling is also important. All analog supplies should be decoupled with μF tantalum capacitors in parallel with 0.1μF capacitors to GND. To achieve the best from these decoupling components, they must be placed as close as possible to the device. Pf is the power at frequency f in the ADC output; Pfs is the power at frequency fs in the ADC output. 15 FN7708.0 December 5, 2011 ISL267440, ISL267450A Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest revision. DATE December 5, 2011 REVISION FN7708.0 Initial release. CHANGE Products Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a complete list of Intersil product families. For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on intersil.com: ISL267440, ISL267450A To report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff FITs are available from our website at: http://rel.intersil.com/reports/search.php For additional products, see www.intersil.com/product_tree Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 16 FN7708.0 December 5, 2011 ISL267440, ISL267450A Package Outline Drawing M8.118 8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE Rev 4, 7/11 5 3.0±0.05 A 8 D DETAIL "X" 1.10 MAX SIDE VIEW 2 4.9±0.15 0.09 - 0.20 3.0±0.05 5 PIN# 1 ID 1 2 B 0.65 BSC TOP VIEW 0.95 REF GAUGE PLANE 0.25 0.55 ± 0.15 H 0.85±010 DETAIL "X" C SEATING PLANE 0.25 - 0.36 0.08 M C A-B D SIDE VIEW 1 0.10 ± 0.05 0.10 C 3°±3° (5.80) (4.40) (3.00) NOTES: 1. Dimensions are in millimeters. 2. Dimensioning and tolerancing conform to JEDEC MO-187-AA and AMSEY14.5m-1994. 3. Plastic or metal protrusions of 0.15mm max per side are not included. 4. Plastic interlead protrusions of 0.15mm max per side are not included. 5. Dimensions are measured at Datum Plane "H". 6. Dimensions in ( ) are for reference only. (0.65) (0.40) (1.40) TYPICAL RECOMMENDED LAND PATTERN 17 FN7708.0 December 5, 2011