40V Precision Single Supply Rail-Rail Output Low Power Operational Amplifiers
ISL28108, ISL28208, ISL28408
The ISL28108, ISL28208 and ISL28408 are single, dual and quad low power precision amplifiers optimized for single supply applications. These devices feature a common mode input voltage range extending to 0.5V below the V- rail, a rail-to-rail differential input voltage range for use as a comparator, and rail-to-rail output voltage swing, which make them ideal for single supply applications where input operation at ground is important. Added features include low offset voltage, and low temperature drift making them the ideal choice for applications requiring high DC accuracy. The output stage is capable of driving large capacitive loads from rail to rail for excellent ADC driving performance. The devices can operate for single or dual supply from 3V (±1.5V) to 40V (±20V) and are fully characterized at ±5V and ±15V. The combination of precision, low power, and small footprint provides the user with outstanding value and flexibility relative to similar competitive parts. Applications for these amplifiers include precision instrumentation, data acquisition, precision power supply control, and industrial control. The ISL28108 single is offered in 8 Ld TDFN, SOIC and MSOP packages. The ISL28208 dual amplifier is offered in 8 Ld TDFN, MSOP, and SOIC packages. The ISL28408 is offered in 14 Ld SOIC package. All devices are offered in standard pin configurations and operate over the extended temperature range to -40°C to +125°C.
Features
• Single or Dual Supply, Rail-to-Rail Output and Below Ground (V-) input capability • Rail-to-rail Input Differential Voltage Range for Comparator Applications • Single Supply Range . . . . . . . . . . . . . . . . . . . . . . . . . 3V to 40V • Low Current Consumption (VS = ±5V) . . . . . . . . . . . . . . 165µA • Low Noise Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 15.8nV/√Hz • Low Noise Current . . . . . . . . . . . . . . . . . . . . . . . . . . . 80fA/√Hz • Low Input Offset Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 230µV • Superb Temperature Drift - Voltage Offset TC . . . . . . . . . . . . . . . . . . . . . . 0.1µV/°C, Typ • Low Input Bias Current . . . . . . . . . . . . . . . . . . . . . . . -13nA Typ • Operating Temperature Range. . . . . . . . . . .-40°C to +125°C • No Phase Reversal
Applications
• Precision Instruments • Medical Instrumentation • Data Acquisition • Power Supply Control • Industrial Process Control
RF LOAD RINRSENSE 10kΩ RIN+ 10kΩ RREF+ 100kΩ VREF IN+ IN100kΩ
V+ ISL28108 V-
+3V to 40V
500 VOUT 400 300 200 VOS (µV) 100 0 -100 -200 -300 -400 -500 -16
VS = ±15V +125°C
+
GAIN = 10
-40°C
+25°C
-15.5
-15
-14.5 -14 13
13.5
14
14.5
15
SINGLE-SUPPLY, LOW-SIDE CURRENT SENSE AMPLIFIER
INPUT COMMON MODE VOLTAGE (V)
FIGURE 1. TYPICAL APPLICATION CIRCUIT
FIGURE 2. INPUT OFFSET VOLTAGE vs INPUT COMMON MODE VOLTAGE, VS = ±15V
July 1, 2011 FN6935.2
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2011. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners.
ISL28108, ISL28208, ISL28408 Ordering Information
PART NUMBER (Notes 1, 2, 3) Coming Soon ISL28108FBZ Coming Soon ISL28108FRTZ Coming Soon ISL28108FUZ ISL28208FBZ ISL28208FRTZ Coming Soon ISL28208FUZ Coming Soon ISL28408FBZ NOTES: 1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL28108, ISL28208, ISL28408. For more information on MSL please see Tech Brief TB363. PART MARKING 28108 FBZ 108Z 8108Z 28208 FBZ 208F 8208Z 28408 FBZ TEMP. RANGE (°C) PACKAGE (Pb-Free) PKG. DWG. # M8.15E L8.3x3A M8.118 M8.15E L8.3x3A M8.118 M14.15
NC 1 -IN 2 -+ PAD
Pin Configurations
ISL28108 (8 LD TDFN) TOP VIEW
8 NC 7 V+ 6 VOUT 5 NC NC -IN +IN V-
ISL28108 (8 LD MSOP, SOIC) TOP VIEW
1 2 3 4 -+ 8 7 6 5 NC V+ VOUT NC
-40 to +125 8 Ld SOIC -40 to +125 8 Ld TDFN -40 to +125 8 Ld MSOP -40 to +125 8 Ld SOIC -40 to +125 8 Ld TDFN -40 to +125 8 Ld MSOP -40 to +125 14 Ld SOIC
+IN 3 V- 4
ISL28208 (8 LD TDFN) TOP VIEW
VOUT_A -IN_A +IN_A V1 2 3 4
ISL28208 (8 LD SOIC, MSOP TOP VIEW
8 V+ 7 VOUT_B
PAD -+ +-
VOUT _A -IN_A +IN_A V-
1 2 3 4 -+ +-
8 V+ 7 VOUT_B 6 -IN_B 5 +IN_B
6 -IN_B 5 +IN_B
ISL28408 (14 LD SOIC) TOP VIEW
VOUT_ A 1 -IN _ A 2 +IN _ A 3 V+ 4 A -+ D +14 V OUT_ D 13 - IN _D 12 +IN _D 11 V 10 +IN _ C -+ B +C 9 -IN _ C 8 V O UT_C
+IN _B 5 - IN _B 6 V OUT_B 7
2
FN6935.2 July 1, 2011
ISL28108, ISL28208, ISL28408 Pin Descriptions
ISL28108 (8 Ld SOIC, MSOP, TDFN) 3 4 2 7 6 1, 5, 8 PAD ISL28208 (8 Ld SOIC, TDFN) 3 5 4 2 6 8 1 7 PAD ISL28408 (14 Ld SOIC, TSSOP) 3 5 10 12 11 2 6 9 13 4 1 7 8 14 PIN NAME +IN +IN_A +IN_B +IN_C +IN_D V-IN -IN_A -IN_B -IN_C -IN_D V+ VOUT VOUT_A VOUT_B VOUT_C VOUT_D NC PAD No internal connection Thermal Pad - TDFN and QFN packages only. Connect thermal pad to ground or most negative potential. Circuit 3 Circuit 2 Positive power supply Amplifier output Circuit 3 Circuit 1 Negative power supply Amplifier inverting input EQUIVALENT CIRCUIT Circuit 1 DESCRIPTION Amplifier non-inverting input
V+ ININ+
V+ OUT VCIRCUIT 2
V+ CAPACITIVELY TRIGGERED ESD CLAMP VCIRCUIT 3
VCIRCUIT 1
3
FN6935.2 July 1, 2011
ISL28108, ISL28208, ISL28408
Absolute Maximum Ratings
Maximum Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42V Maximum Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42V or V- - 0.5V to V+ + 0.5V Min/Max Input Voltage . . . . . . . . . . . . . . . . . . .42V or V- - 0.5V to V+ + 0.5V Max/Min Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20mA Output Short-Circuit Duration (1 output at a time) . . . . . . . . . . . Indefinite ESD Tolerance Human Body Model (Tested per JESD22-A114F) . . . . . . . . . . . . . . . . 6kV Machine Model (Tested per JESD22-A115-C) . . . . . . . . . . . . . . . . . . 400V Charged Device Model (Tested per JESD22-C110D) . . . . . . . . . . . . . 2kV
Thermal Information
Thermal Resistance (Typical) θJA (°C/W) θJC (°C/W) 8 Ld SOIC Package (108, 208, Notes 4, 7) . . 120 55 8 Ld TDFN Package (108, 208, Notes 5, 6). . 47 6 8 Ld MSOP Package (108, 208, Notes 4, 7) . 150 45 14 Ld SOIC Package (408, Notes 4, 7). . . . . . Storage Temperature Range . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Ambient Operating Temperature Range . . . . . . . . . . . . . . -40°C to +125°C Maximum Operating Junction Temperature . . . . . . . . . . . . . . . . . . +150°C Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3V (±1.5V) to 40V (±20V)
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 4. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 5. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 6. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside. 7. For θJC, the “case temp” location is taken at the package top center. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications VS ±15V, VCM = 0, VO = 0V, RL = Open, TA= +25°C, unless otherwise noted. Boldface limits apply over the operating temperature range, -40°C to +125°C. Temperature data established by characterization.
MIN PARAMETER VOS DESCRIPTION Input Offset Voltage CONDITIONS
(Note 8)
-230 -330
TYP 25
MAX (Note 8) 230 330
UNIT µV µV µV/°C µV/°C µV µV nA nA
TCVOS
Input Offset Voltage Temperature Coefficient
ISL28208 SOIC -40°C to +125°C ISL28208 TDFN -40°C to +125°C
0.1 0.2 -300 -400 -43 -63 -13 5
1.1 1.4 300 400
ΔVOS
Input Offset Voltage Match (ISL28208 only) Input Bias Current
IB
TCIB IOS
Input Bias Current Temperature Coefficient Input Offset Current -3 -4
0.07 0 3 4 119 123 102 VCM = V- to V+ -1.8V 105 102 123 115
nA/°C nA nA dB dB dB dB dB
CMRR
Common-Mode Rejection Ratio
VCM = V- -0.5V to V+ -1.8V VCM = V- -0.2V to V+ -1.8V
4
FN6935.2 July 1, 2011
ISL28108, ISL28208, ISL28408
Electrical Specifications VS ±15V, VCM = 0, VO = 0V, RL = Open, TA= +25°C, unless otherwise noted. Boldface limits apply over the operating temperature range, -40°C to +125°C. Temperature data established by characterization. (Continued)
MIN PARAMETER VCMIR DESCRIPTION Common Mode Input Voltage Range Power Supply Rejection Ratio CONDITIONS Guaranteed by CMRR test MAX (Note 8) V+ - 1.8 V+ - 1.8 128 124 126
(Note 8)
V- - 0.5 V-
TYP
UNIT V V dB dB dB dB
PSRR
VS = 3V to 40V, VCMIR = Valid Input Voltage
110 109
AVOL
Open-Loop Gain
VO = -13V to +13V, RL = 10kΩ to ground
117 100
VOL
Output Voltage Low, VOUT to VOutput Voltage High, V+ to VOUT Supply Current/Amplifier
RL = 10kΩ
52
85 145
mV mV mV mV µA µA mA mA
VOH
RL = 10kΩ
70
110 150
IS
RL = Open
185 270
250 350
ISC+ ISCVSUPPLY
Output Short Circuit Source Current Output Short Circuit Sink Current Supply Voltage Range
RL = 10Ω to VRL = 10Ω to V+ Guaranteed by PSRR 3
19 30 40
V
AC SPECIFICATIONS
GBWP enp-p en en en en in THD + N Gain Bandwidth Product Noise Voltage Noise Voltage Density Noise Voltage Density Noise Voltage Density Noise Voltage Density Noise Current Density ACL = 101, VO = 100mVP-P, RL = 2kΩ 0.1Hz to 10Hz; VS = +18V f = 10Hz; VS = +18V f = 100Hz; VS = +18V f = 1kHz; VS = +18V f = 10kHz; VS = +18V f = 10kHz; VS = +18V 1 .2 580 18 16 15.8 15.8 80 0.00042 MHz nVP-P nV/√Hz nV/√Hz nV/√Hz nV/√Hz fA/√Hz %
Total Harmonic Distortion + Noise 1kHz, AV = 1, VO = 3.5VRMS, RL =10kΩ
TRANSIENT RESPONSE
SR tr, tf, Small Signal Slew Rate, VOUT 20% to 80% Rise Time, VOUT 10% to 90% Fall Time, VOUT 90% to 10% ts Settling Time to 0.01% 10V Step; 10% to VOUT AV = 1, RL = 2kΩ, VO = 10VP-P AV = 1, VOUT = 100mVP-P, Rf = 0Ω, RL = 2kΩ to VCM AV = 1, VOUT = 100mVP-P, Rf = 0Ω, RL = 2kΩ to VCM AV = -1, VOUT = 10VP-P, Rg = Rf =10k, RL = 2kΩ to VCM 0.45 264 254 27 V/µs ns ns µs
5
FN6935.2 July 1, 2011
ISL28108, ISL28208, ISL28408
Electrical Specifications VS ±5V, VCM = 0, VO = 0V, TA = +25°C, unless otherwise noted. Boldface limits apply over the operating temperature range, -40°C to +125°C. Temperature data established by characterization.
MIN PARAMETER VOS DESCRIPTION Offset Voltage CONDITIONS MAX (Note 8) 230 330 0.1 0.2 -300 -400 -43 -63 TCIB IOS Input Bias Current Temperature Coefficient Input Offset Current -40°C to +125°C -3 -4 CMRR Common-Mode Rejection Ratio VCM = V- -0.5V to V+ -1.8V VCM = V- -0.2V to V+ -1.8V VCM = V- to V+ -1.8V VCMIR Common Mode Input Voltage Range Power Supply Rejection Ratio Guaranteed by CMRR test 105 100 V- - 0.5 VVS = 3V to 10V, VCMIR = Valid Input Voltage VO = -3V to +3V, RL = 10kΩ to ground 110 109 AVOL Open-Loop Gain 117 99 VOL Output Voltage Low, VOUT to VOutput Voltage High, V+ to VOUT Supply Current/Amplifier RL = 10kΩ 23 38 48 RL = 10kΩ 30 65 70 RL = Open 165 240 ISC+ ISCGBW enp-p en en en en in Output Short Circuit Source Current RL = 10Ω to VOutput Short Circuit Sink Current RL = 10Ω to V+ ACL = 101, VO = 100mVP-P, RL = 2kΩ 0.1Hz to 10Hz f = 10Hz f = 100Hz f = 1kHz f = 10kHz f = 10kHz 14 22 250 350 126 123 124 101 123 89 123 112 V+ - 1.8 V+ - 1.8 -0.067 0 3 4 -15 3 1.1 1.4 300 400
(Note 8)
-230 -330
TYP 25
UNIT µV µV µV/°C µV/°C µV µV nA nA nA/°C nA nA dB dB dB dB dB V V dB dB dB dB mV mV mV mV µA µA mA mA
TCVOS
Input Offset Voltage Temperature Coefficient
ISL28208 SOIC -40°C to +125°C ISL28208 TDFN -40°C to +125°C
ΔVOS
Input Offset Voltage Match (ISL28208 only) Input Bias Current
IB
PSRR
VOH
IS
AC SPECIFICATIONS
Gain Bandwidth Product Noise Voltage Noise Voltage Density Noise Voltage Density Noise Voltage Density Noise Voltage Density Noise Current Density 1.2 600 18 16 15.8 15.8 90 MHz nVP-P nV/√Hz nV/√Hz nV/√Hz nV/√Hz fA/√Hz
6
FN6935.2 July 1, 2011
ISL28108, ISL28208, ISL28408
Electrical Specifications VS ±5V, VCM = 0, VO = 0V, TA = +25°C, unless otherwise noted. Boldface limits apply over the operating temperature range, -40°C to +125°C. Temperature data established by characterization. (Continued)
MIN PARAMETER DESCRIPTION CONDITIONS MAX (Note 8)
(Note 8)
TYP
UNIT
TRANSIENT RESPONSE
SR tr, tf, Small Signal Slew Rate, VOUT 20% to 80% Rise Time, VOUT 10% to 90% Fall Time, VOUT 90% to 10% ts Settling Time to 0.01% 4V Step; 10% to VOUT AV = 1, RL = 2kΩ, VO = 4VP-P AV = 1, VOUT = 100mVP-P, Rf = 0Ω, RL = 2kΩ to VCM AV = 1, VOUT = 100mVP-P, Rf = 0Ω, RL = 2kΩ to VCM AV = -1, VOUT = 4VP-P, Rg = Rf =10k, RL = 2kΩ to VCM 0.4 264 254 14.4 V/µs ns ns µs
NOTE: 8. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
Typical Performance Curves
300 VS = ±15V
NUMBER OF AMPLIFIERS
VS = ±15V, VCM = 0V, RL = Open, unless otherwise specified.
300 VS = ±5V
NUMBER OF AMPLIFIERS
250 200 150 100 50 0
250 200 150 100 50 0
-110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110
VOS (µV)
FIGURE 3. ISL28208 INPUT OFFSET VOLTAGE DISTRIBUTION, VS = ±15V
FIGURE 4. ISL28208 INPUT OFFSET VOLTAGE DISTRIBUTION, VS = ±5V
-1.1 -1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1
TCVOS (µV/C)
FIGURE 5. ISL28208 SOIC TCVOS vs NUMBER OF AMPLIFIERS, VS = ±15V
FIGURE 6. ISL28208 SOIC TCVOS vs NUMBER OF AMPLIFIERS, VS = ±5V
7
-1.1 -1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1
24 22 20 18 16 14 12 10 8 6 4 2 0
VS = ±15V
NUMBER OF AMPLIFIERS
24 22 20 18 16 14 12 10 8 6 4 2 0
NUMBER OF AMPLIFIERS
-110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110
VOS (µV)
VS = ±5V
TCVOS (µV/C)
FN6935.2 July 1, 2011
ISL28108, ISL28208, ISL28408 Typical Performance Curves
24 22 20 18 16 14 12 10 8 6 4 2 0 VS = ±15V
NUMBER OF AMPLIFIERS NUMBER OF AMPLIFIERS
VS = ±15V, VCM = 0V, RL = Open, unless otherwise specified. (Continued)
24 22 20 18 16 14 12 10 8 6 4 2 0 VS = ±5V
-1.1 -1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1
TCVOS (µV/C)
FIGURE 7. ISL28208 TDFN TCVOS vs NUMBER OF AMPLIFIERS, VS = ±15V
FIGURE 8. ISL28208 TDFN TCVOS vs NUMBER OF AMPLIFIERS, VS = ±5V
70 60 50 40 30
VOS (µV)
0 VS = ±2.25V -5 VS = ±5V IBIAS (nA) -10 -15 -20 -25 -40 VS = ±21V VS = ± 15V VS = ±5V
20 10 0 -10 -20 -30 -40 -50 -40 -20 0 20 40 60 80 TEMPERATURE (°C) 100 120 VS = ±20V VS = ±15V
FIGURE 9. VOS vs TEMPERATURE
FIGURE 10. IBIAS vs TEMPERATURE vs SUPPLY
500 400 300 200 VOS (µV) 100 0 -100 -200 -300 -400 -500 -16
VS = ±15V +125°C VOS (µV)
500 400 300 200 100 0 -100 -200 -300 -400 -500 +25°C
-40°C
-15.5
-15
-14.5 -14 13
13.5
14
14.5
15
-6
INPUT COMMON MODE VOLTAGE (V)
FIGURE 11. INPUT OFFSET VOLTAGE vs INPUT COMMON MODE VOLTAGE, VS = ±15V
FIGURE 12. INPUT OFFSET VOLTAGE vs INPUT COMMON MODE VOLTAGE, VS = ±5V
8
-1.1 -1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1
TCVOS (µV/C)
VS = ±2.25V -20 0
VS = ±1.5V 100 120
20 40 60 80 TEMPERATURE (°C)
VS = ±5V +125°C
-40°C
+25°C
-5.5
-5
-4.5
-4 3
3.5
4
4.5
5
INPUT COMMON MODE VOLTAGE (V)
FN6935.2 July 1, 2011
ISL28108, ISL28208, ISL28408 Typical Performance Curves
130 125 120 CHANNEL-A 115 110 105 100 -40 VS = ±15V CHANNEL-B 125 120 CHANNEL-A 115 110 105 100 -40
VS = ±15V, VCM = 0V, RL = Open, unless otherwise specified. (Continued)
130 VS = ±5V CHANNEL-B
CMRR (dB)
-20
0
20 40 60 80 TEMPERATURE (°C)
100
120
CMRR (dB)
-20
0
20 40 60 80 TEMPERATURE (°C)
100
120
FIGURE 13. CMRR vs TEMPERATURE, VS = ±15V
FIGURE 14. CMRR vs TEMPERATURE, VS = ±5V
150 140 130 120 110 100 90 80 70 60 50 40 30 VS = ±15V 20 SIMULATION 10 0 1m 0.01 0.1 1
120 110 100 90
PSRR (dB)
CMRR (dB)
80 70 60 50 VS = ±5V, ±15V 40 AV = 1 30 CL = 4pF 20 RL = 10k
PSRR+
10 100 1k 10k 100k 1M 10M 100M 1G FREQUENCY (Hz)
PSRR10 VSOURCE = 1VP-P 0 10 100 1k 10k 100k FREQUENCY (Hz)
1M
10M
FIGURE 15. CMRR vs FREQUENCY, VS = ±15V
FIGURE 16. PSRR vs FREQUENCY, VS = ±5V & ±15V
140 VS = ±15V 135
PSRR (dB) PSRR (dB)
140 VS = ±5V 135
130
130
125
125
120 -40
-20
0
20
40
60
80
100
120
120 -40
-20
0
TEMPERATURE (°C)
20 40 60 80 TEMPERATURE (°C)
100
120
FIGURE 17. PSRR (DC) vs TEMPERATURE, VS = ±15V
FIGURE 18. PSRR (DC) vs TEMPERATURE, VS = ±5V
9
FN6935.2 July 1, 2011
ISL28108, ISL28208, ISL28408 Typical Performance Curves
1 VS = ±5V and ±15V 125°C 0.1
V+ - VOH (V)
VS = ±15V, VCM = 0V, RL = Open, unless otherwise specified. (Continued)
1 VS = ±5V and ±15V 125°C 0.1
VOL - V- (V)
+25°C
+25°C
0.01 -40°C
0.01 -40°C 0.001 0.001
0.001 0.001
0.01
0.1 1 LOAD CURRENT (mA)
10
0.01
0.1 1 LOAD CURRENT (mA)
10
FIGURE 19. OUTPUT OVERHEAD VOLTAGE HIGH vs LOAD CURRENT, VS = ±5V and ±15V
FIGURE 20. OUTPUT OVERHEAD VOLTAGE LOW vs LOAD CURRENT, VS = ±5V and ±15V
15 14
VOH(V)
5 4 125°C
VOH(V)
+75°C
13 12 11 10 -10 -40°C 0°C VS = ±15V AV = 2 RF = RG = 100k VIN = ±7.5V-DC 0 2 4 6 8 +75°C
3 2 1 -1 -40°C 0°C +25°C
125°C
VOL(V)
-11 -12 -13 -14 -15
VOL(V)
+25°C
-2 VS = ±5V A =2 -3 RV = R = 100k F G -4 VIN = ±2.5V-DC -5 0 2 4 6 8
10
12
14
16
18
20
22
24
10
12
14
16
18
20
22
24
I-FORCE (mA)
I-FORCE (mA)
FIGURE 21. ISL28208 OUTPUT VOLTAGE SWING vs LOAD CURRENT VS = ±15V
FIGURE 22. ISL28208 OUTPUT VOLTAGE SWING vs LOAD CURRENT VS = ±5V
100
VS = ±15V 90 R = 10k L 80 70 60 50 40 30 20 10 0 -40 -20 0
100 VOH (V+ TO VOUT)
VOH AND VOL (mV)
VS = ±5V 90 R = 10k L 80 70 60 50 40 30 20 10 0 -40
VOH (V+ TO VOUT)
VOH AND VOL (mV)
VOL (VOUT TO V-)
VOL (VOUT TO V-)
20 40 60 80 TEMPERATURE (°C)
100
120
-20
0
20 40 60 80 TEMPERATURE (°C)
100
120
FIGURE 23. VOUT HIGH & LOW vs TEMPERATURE, VS = ±15V, RL = 10k
FIGURE 24. VOUT HIGH AND LOW vs TEMPERATURE, VS = ±5V, RL = 10k
10
FN6935.2 July 1, 2011
ISL28108, ISL28208, ISL28408 Typical Performance Curves
50 VS = ±15V 45 R = 10k L 40 35
Isc (mA)
VS = ±15V, VCM = 0V, RL = Open, unless otherwise specified. (Continued)
50 VS = ±5V 45 R = 10k L 40 35
Isc (mA)
ISC-SINK
30 25 20 15 10 5 0 -40 -20 0 ISC-SOURCE 20 40 60 80 100 120
30 25 20 15 10 5 0 -40 -20 0
ISC-SINK
ISC-SOURCE 20 40 60 80 100 120
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 25. SHORT CIRCUIT CURRENT vs TEMPERATURE, VS = ±15V
FIGURE 26. SHORT CIRCUIT CURRENT vs TEMPERATURE, VS = ±5V
30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 0 1k
VS = ±15V AV = 1
INPUT AND OUTPUT (V)
6 5 4 3 2 1 0 -1 -2 -3 -4 -5 -6
VS = ±5V VIN = ±5.9V INPUT
VOUT (VP-P)
OUTPUT
10k 100k FREQUENCY (Hz)
1M
0
2
4
6
8 10 12 TIME (ms)
14
16
18
20
FIGURE 27. MAX OUTPUT VOLTAGE vs FREQUENCY
FIGURE 28. NO PHASE REVERSAL
140 VS = ± 15V 130
AVOL (dB) GAIN (dB), PHASE (°)
120
VS = ±5V
110
100 -60
-40
-20
0
20 40 60 80 100 120 140 160 TEMPERATURE (°C)
200 180 160 140 120 100 80 60 40 20 0 GAIN -20 VS = ±15V -40 -60 RL = 1MΩ -80 SIMULATION -100 1 10 100 0.1
PHASE
1k 10k 100k 1M FREQUENCY (Hz)
10M 100M 1G
FIGURE 29. AVOL vs TEMPERATURE
FIGURE 30. OPEN-LOOP GAIN, PHASE vs FREQUENCY, VS = ±15V
11
FN6935.2 July 1, 2011
ISL28108, ISL28208, ISL28408 Typical Performance Curves
ISUPPLY PER AMPLIFIER (µA)
VS = ±15V, VCM = 0V, RL = Open, unless otherwise specified. (Continued)
70 60 50
GAIN (dB)
210 200 190 180 170 160 150 140 130 120 110 100 90 80 70 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 VSUPPLY (V)
ACL = 1001
RF = 10kΩ, RG = 10Ω RF = 10kΩ, RG = 100Ω
40 30 20 10 0
ACL = 101
ACL = 10 RF = 10kΩ, RG = 1.1kΩ ACL = 1 RF = 0, R G = ∞ 1k 10k 100k
VS = ±5V, ±15V CL = 4pF R L = 2k VOUT = 100mVP-P
-10 100
1M
10M
FREQUENCY (Hz)
FIGURE 31. SUPPLY CURRENT vs SUPPLY VOLTAGE
FIGURE 32. FREQUENCY RESPONSE vs CLOSED LOOP GAIN
1 0 NORMALIZED GAIN (dB) -2 -3 -4 -5 -6 VS = ±15V -7 CL = 4pF AV = +1 -8 VOUT = 100mVP-P -9 1k 100 RL = OPEN, 100k, 10k RL = 1 k RL = 499 RL = 100 RL = 49.9 10k 100k 1M 10M NORMALIZED GAIN (dB) -1
1 0 -1 -2 -3 -4 -5 -6 VS = ±5V -7 CL = 4pF AV = +1 -8 VOUT = 100mVp-p -9 1k 100 RL = OPEN, 100k, 10k RL = 1 k RL = 499 RL = 100 RL = 49.9 10k 100k 1M 10M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 33. GAIN vs FREQUENCY vs RL, VS = ±15V
FIGURE 34. GAIN vs FREQUENCY vs RL, VS = ±5V
1 0 NORMALIZED GAIN (dB) -2 -3 -4 -5 -6 -7 -8 -9 100 VS = ±5V CL = 4pF AV = +1 RL = INF 1k VOUT = 10mVP-P VOUT = 50mVP-P VOUT = 100mVP-P VOUT = 500mVP-P VOUT = 1VP-P 10k 100k 1M 10M FREQUENCY (Hz) NORMALIZED GAIN (dB) -1
1 0 -1 -2 -3 -4 -5 -6 CL = 4pF R = 10k -7 L AV = +1 -8 VOUT = 100mVP-P -9 100 1k VS = ±2.5V VS = ±5V VS = ±15V VS = ±20V
10k 100k FREQUENCY (Hz)
1M
10M
FIGURE 35. GAIN vs FREQUENCY vs OUTPUT VOLTAGE
FIGURE 36. GAIN vs FREQUENCY vs SUPPLY VOLTAGE
12
FN6935.2 July 1, 2011
ISL28108, ISL28208, ISL28408 Typical Performance Curves
100 VS = ±15V 10 G = 100
ZOUT (Ω) ZOUT (Ω)
VS = ±15V, VCM = 0V, RL = Open, unless otherwise specified. (Continued)
100 VS = ±5V
G = 10
10 G = 100 1
G = 10
1
0.10
G=1
0.10
G=1
0.01
1
10
100
1k 10k 100k FREQUENCY (Hz)
1M
10M
0.01 1
10
100
1k 10k 100k FREQUENCY (Hz)
1M
10M
FIGURE 37. OUTPUT IMPEDANCE vs FREQUENCY, VS = ±15V
FIGURE 38. OUTPUT IMPEDANCE vs FREQUENCY, V S = ±5V
100
INPUT NOISE VOLTAGE (nV/√Hz)
100
INPUT NOISE CURRENT (pA/√Hz)
100
INPUT NOISE VOLTAGE (nV/√Hz)
100
INPUT NOISE CURRENT (pA/√Hz)
VS = ±18V 10 INPUT NOISE VOLTAGE 1 INPUT NOISE CURRENT 0.1 0.1 1 10
VS = ±5V 10 10
INPUT NOISE VOLTAGE
1
INPUT NOISE CURRENT
1
0.1
0.1
0.01 0.1
1
10
100
1k
10k
0.01 100k
0.01
0.1
1
10
FREQUENCY (Hz)
100 1k FREQUENCY (Hz)
10k
0.01 100k
FIGURE 39. INPUT NOISE VOLTAGE (en) AND CURRENT (in) vs FREQUENCY, VS = ±18V
FIGURE 40. INPUT NOISE VOLTAGE (en) AND CURRENT (in) vs FREQUENCY, VS = ±5V
1000
INPUT NOISE VOLTAGE (nV)
1000
INPUT NOISE VOLTAGE (nV)
800 600 400 200 0 -200 -400 -600 -800 -1000 0
VS = ±18V AV = 10k
800 600 400 200 0 -200 -400 -600 -800 -1000 0
VS = ±5V AV = 10k
1
2
3
4
5 6 TIME (s)
7
8
9
10
1
2
3
4
5 6 TIME (s)
7
8
9
10
FIGURE 41. INPUT NOISE VOLTAGE 0.1Hz TO 10Hz, VS = ±18V
FIGURE 42. INPUT NOISE VOLTAGE 0.1Hz TO 10Hz, VS = ±5V
13
FN6935.2 July 1, 2011
ISL28108, ISL28208, ISL28408 Typical Performance Curves
160 140
CROSSTALK (dB)
VS = ±15V, VCM = 0V, RL = Open, unless otherwise specified. (Continued)
VS = ±15V CL = 4pF VTX = 1VP-P
120 100 80 60 40 20 0 10 100 RL_TRANSMIT = 2k RL_RECEIVE = 10k 1k 10k 100k FREQUENCY (Hz) RL_TRANSMIT = ∞ RL_RECEIVE = 10k
1M
10M
FIGURE 43. ISL28208 CHANNEL SEPARATION vs FREQUENCY, V S = ±5V, ±15V
200
INPUT
160
INPUT (mV)
VS = ±15V AV = 100 RL = 10k VIN = 100mVP-P OVERDRIVE = 1V
20
0 -40
INPUT (mV)
0 -4 -8 OUTPUT
OUTPUT (V) OUTPUT (V)
16
OUTPUT (V)
120
OUTPUT
12
-80 -120 -160 INPUT -200 0
80 40
8 4
0
0
20
40
60
80 100 120 TIME (µs)
140
160
180
0 200
20
40
60
80 100 120 TIME (µs)
-12 VS = ±15V AV = 100 RL = 10k -16 VIN = 100mVP-P OVERDRIVE = 1V -20 140 160 180 200
FIGURE 44. POSITIVE OUTPUT OVERLOAD RESPONSE TIME, VS = ±15V
FIGURE 45. NEGATIVE OUTPUT OVERLOAD RESPONSE TIME, VS = ±15V
60 50 40 30 20 10 0 OUTPUT INPUT
OUTPUT (V)
INPUT (mV)
INPUT (mV)
6 VS = ±5V AV = 100 5 RL = 10k VIN = 50mVP-P OVERDRIVE = 1V 4 3 2 1 0 200
0 -10 -20 OUTPUT -30 -40 INPUT -50 -60
0 -1 -2 -3 -4 VS = ±5V AV = 100 RL = 10k -5 VIN = 50mVP-P OVERDRIVE = 1V -6 140 160 180 200
0
20
40
60
80 100 120 TIME (µs)
140
160
180
0
20
40
60
80 100 120 TIME (µs)
FIGURE 46. POSITIVE OUTPUT OVERLOAD RESPONSE TIME, VS = ±5V
FIGURE 47. NEGATIVE OUTPUT OVERLOAD RESPONSE TIME, VS = ±5V
14
FN6935.2 July 1, 2011
ISL28108, ISL28208, ISL28408 Typical Performance Curves
60 50
OVERSHOOT (%)
VS = ±15V, VCM = 0V, RL = Open, unless otherwise specified. (Continued)
60 50
OVERSHOOT (%)
VS = ±15V VOUT = 100mVP-P
VS = ±5V VOUT = 100mVP-P
40 AV = -1 30 20 10 0 0.001 AV = 1 AV = 10
40 30 20 10 0 0.001 AV = -1 AV = 10
AV = 1
0.010
0.100
1
10
100
0.010
0.100
1
10
100
LOAD CAPACITANCE (nF)
LOAD CAPACITANCE (nF)
FIGURE 48. OVERSHOOT vs CAPACITIVE LOAD, VS = ±15V
FIGURE 49. OVERSHOOT vs CAPACITIVE LOAD, VS = ±5V
6
VS = ±15V AV = 1 4 R = 2k L CL = 4pF 2
VOUT (V) VOUT (V)
2.4
2.0 VS = ±5V AV = 1 1.6 RL = 2 k 1.2 CL = 4pF 0.8 0.4 0 -0.4 -0.8 -1.2 -1.6 -2.0 -2.4
0 -2 -4 -6
0
100
200 TIME (µs)
300
400
0
100
200 TIME (µs)
300
400
FIGURE 50. LARGE SIGNAL 10V STEP RESPONSE, VS = ±15V
FIGURE 51. LARGE SIGNAL 4V STEP RESPONSE, VS = ±5V
100 80 60 40
VOUT (mV)
20 0 -20 -40 -60 -80 -100 0 0.5 1.0 1.5 2.0 2.5 TIME (µs) 3.0
VS = ±15V AND VS = ±5V AV = 1 RL = 2 k CL = 4pF
3.5
4.0
FIGURE 52. SMALL SIGNAL TRANSIENT RESPONSE VS = ±5V, ±15V
15
FN6935.2 July 1, 2011
ISL28108, ISL28208, ISL28408
Applications Information
Functional Description
The ISL28108, ISL28208, and ISL28408 are single, dual and quad, 1.2MHz, single supply rail-to-rail output amplifiers with a common mode input voltage range extending to a range of 0.5V below the V- rail. Their input stages are optimized for precision sensing of ground referenced signals in low voltage, single supply applications. The input stage has the capability of handling large input differential voltages without phase inversion making them suitable for high voltage comparator applications. Their bipolar design features high open loop gain and excellent DC input and output temperature stability. These op amps feature low quiescent current of 165µA, and a maximum low temperature drift of only 1.1µV/°C for the ISL28208 in the SOIC package and 1.4µV/°C for the ISL28208 in the TDFN package (see Figures 7 and 8). Both devices are fabricated in a new precision 40V complementary bipolar DI process and immune from latch-up.
VINVIN+ RINRIN+ + V+ RF
RL
RG
V-
FIGURE 53. INPUT ESD DIODE CURRENT LIMITING
Output Drive Capability
The bipolar rail-to-rail output stage features low saturation levels that enable an output voltage swing to less than 10mV when the total output load (including feedback resistance) is held below 50µA (Figures 19 and 20). With ±15V supplies this can be achieved by using feedback resistor values >300kΩ. The low input bias and offset currents (-43nA and ±3nA +25°C max respectively) minimize DC offset errors at these high resistance values. For example, a balanced 4 resistor gain circuit (Figure 53) with 1MΩ feedback resistors (RF, RG) generates a worst case input offset error of only ±3mV. Furthermore, the low noise current reduces the added noise associated with high feedback resistance. The output stage is internally current limited. Output current limit over-temperature is shown in Figures 25 and 26. The amplifiers can withstand a short circuit to either rail as long as the power dissipation limits are not exceeded. This applies to only one amplifier at a time for the dual op amp. Continuous operation under these conditions may degrade long-term reliability. The amplifiers perform well driving capacitive loads (Figures 48 and 49). The unity gain, voltage follower (buffer) configuration provides the highest bandwidth, but is also the most sensitive to ringing produced by load capacitance found in BNC cables. Unity gain overshoot is limited to 30% at capacitance values to 0.33nF. At gains of 10 and higher, the device is capable of driving more than 10nF without significant overshoot.
Operating Voltage Range
The devices are designed to operate over the 3V (±1.5V) to 40V (±20V) range and are fully characterized at ±5V and ±15V. Both DC and AC performance remain virtually unchanged over the ±5V to ±15V operating voltage range. Parameter variation with operating voltage is shown in the “Typical Performance Curves” beginning on page 7.
Input Stage Performance
The PNP input stage has a common mode input range extending up to 0.5V below ground at +25°C (see Figures 11 and 12). Full amplifier performance is guaranteed down to ground (V-) over the 40°C to +125°C temperature range. For common mode voltages down to -0.5V the amplifiers are fully functional, but performance degrades slightly over the full temperature range. This feature provides excellent CMRR, AC performance and DC accuracy when amplifying low level ground referenced signals. The input stage has a maximum input differential voltage equal to a diode drop greater than the supply voltage (max 42V) and does not contain the back-to-back input protection diodes found on many similar amplifiers. This feature enables the device to function as a precision comparator by maintaining very high input impedance for high voltage differential input comparator voltages. The high differential input impedance also enables the device to operate reliably in large signal pulse applications without the need for anti-parallel clamp diodes required on MOSFET and most bipolar input stage op amps. Thus, input signal distortion caused by nonlinear clamps under high slew rate conditions are avoided. In applications where one or both amplifier input terminals are at risk of exposure to voltages beyond the supply rails, current limiting resistors may be needed at each input terminal (see Figure 53 RIN+, RIN-) to limit current through the power supply ESD diodes to 20mA.
Output Phase Reversal
Output phase reversal is a change of polarity in the amplifier transfer function when the input voltage exceeds the supply voltage. These devices are immune to output phase reversal, out to 0.5V beyond the rail (VABS MAX) limit (see Figure 28).
16
FN6935.2 July 1, 2011
ISL28108, ISL28208, ISL28408
Using Only One Channel
If the application only requires one channel, the user must configure the unused channel to prevent it from oscillating. The unused channel will oscillate if the input and output pins are floating. This will result in higher than expected supply currents and possible noise injection into the channel being used. The proper way to prevent this oscillation, is to short the output to the inverting input and ground the positive input (as shown in Figure 54).
ISL28108, ISL28208, ISL28408 SPICE Model
Figure 55 shows the SPICE model schematic and Figure 56 shows the net list for the SPICE model. The model is a simplified version of the actual device and simulates important AC and DC parameters. AC parameters incorporated into the model are: 1/f and flatband noise voltage, Slew Rate, CMRR, Gain and Phase. The DC parameters are IOS, total supply current and output voltage swing. The model uses typical parameters given in the “Electrical Specifications” Table beginning on page 4. The AVOL is adjusted for 122dB with the dominant pole at 1Hz. The CMRR is set 128dB, f = 6kHz. The input stage models the actual device to present an accurate AC representation. The model is configured for ambient temperature of +25°C. Figures 57 through 71 show the characterization vs simulation results for the Noise Voltage, Open Loop Gain Phase, Closed Loop Gain vs Frequency, Gain vs Frequency vs RL, CMRR, Large Signal 10V Step Response, Small Signal 0.05V Step and Output Voltage Swing ±15V supplies.
+
FIGURE 54. PREVENTING OSCILLATIONS IN UNUSED CHANNELS
Power Dissipation
It is possible to exceed the +150°C maximum junction temperatures under certain load and power supply conditions. It is therefore important to calculate the maximum junction temperature (TJMAX) for all applications to determine if power supply voltages, load conditions, or package type need to be modified to remain in the safe operating area. These parameters are related using Equation 1:
T JMAX = T MAX + θ JA xPD MAXTOTAL (EQ. 1)
LICENSE STATEMENT
The information in this SPICE model is protected under the United States copyright laws. Intersil Corporation hereby grants users of this macro-model hereto referred to as “Licensee”, a nonexclusive, nontransferable licence to use this model as long as the Licensee abides by the terms of this agreement. Before using this macro-model, the Licensee should read this license. If the Licensee does not accept these terms, permission to use the model is not granted. The Licensee may not sell, loan, rent, or license the macromodel, in whole, in part, or in modified form, to anyone outside the Licensee’s company. The Licensee may modify the macromodel to suit his/her specific applications, and the Licensee may make copies of this macro-model for use within their company only. This macro-model is provided “AS IS, WHERE IS, AND WITH NO WARRANTY OF ANY KIND EITHER EXPRESSED OR IMPLIED, INCLUDING BUY NOT LIMITED TO ANY IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.” In no event will Intersil be liable for special, collateral, incidental, or consequential damages in connection with or arising out of the use of this macro-model. Intersil reserves the right to make changes to the product and the macro-model without prior notice.
where: • PDMAXTOTAL is the sum of the maximum power dissipation of each amplifier in the package (PDMAX) • PDMAX for each amplifier can be calculated using Equation 2:
V OUTMAX PD MAX = V S × I qMAX + ( V S - V OUTMAX ) × -----------------------R
L
(EQ. 2)
where: • TMAX = Maximum ambient temperature • θJA = Thermal resistance of the package • PDMAX = Maximum power dissipation of 1 amplifier • VS = Total supply voltage • IqMAX = Maximum quiescent supply current of 1 amplifier • VOUTMAX = Maximum output voltage swing of the application • RL = Load resistance
17
FN6935.2 July 1, 2011
V++ 12e-6 I2 6E-6 Vin0.1 7 V7 DN 1 D13 DN D14 R1 5e11 0 R2 5 CinDif 1.21e-12 PNP_LATERAL Q7 9 D1 DBREAK Q6 I3 6E-6 DX I1 D3 G1 + R5 13 GAIN = 0.477 V1 14 EOS ++ -E GAIN = 1 -6.76 V2 Vc Vmid
V++
1
-6.74 10 PNP_LATERAL 12
Q8 PNP_input 8 R3 6250
Q9 D2 DBREAK PNP_input 11 R4 6 V--
+ + -
Vin+ GAIN = 0.3 Cin2 4.19e-12 Cin1 4.19e-12
GAIN = 0.477 DX D4 V--
Input Stage
1st Gain Stage
0 DX D5 16 C1 R7 2.31e-11 7.62e9
V+ E2 ++ -GAIN = 1
V++ R19 R13 3.183e3 3.183e3 G15 G9 + + GAIN = 314.15e-6 GAIN = 314.15e-6 C5 10e-12 28 ISY 185e-6 23 DX D10 DX
Vmid GAIN = 261.74e-6 -6.74 V3
G3 + -
GAIN = 12.5e-3 24 V5 -0.4 26 27
D7 C3 DX 10e-12
Vg Vmid
Vc
C6 10e-12
D8 DX
-6.76 G4 + Vmid
V4 17
E4 ++ -GAIN = 0.5 C2 2.31e-11 R8 7.62e9 G6 GAIN = 0.6 + -
25
V6 -0.4 G12 + -
R10 1e-3 20 G8 L2 1.59E-08 GAIN = 0.6 V-+ -
R12 1e-3 22
G16 + -
G10 + -
C4 10e-12 DY
GAIN = 261.74e-6 DX
GAIN = 12.5e-3
GAIN = 12.5e-3
V-VE3 ++ -GAIN = 1 Output Stage Correction Current Sources
2nd Gain Stage
Mid Supply ref V
Common Mode Gain Stage with Zero 0
FIGURE 55. SPICE MODEL SCHEMATIC
+ -
GAIN = 314.15e-6 GAIN = 314.15e-6 L4 R14 1.59E-08 R20 3.183e3 3.183e3
G11 + D9 GAIN = 12.5e-3
DY
D12
G14
+ -
L1 L3 1.59E-08 1.59E-08 G5 G7 + + 18 21 GAIN = 0.6 R9 GAIN = 0.6 1e-3 R11 1e-3 19
+ -
18
FN6935.2 July 1, 2011
0
1150
2
IOS 3e-9
ISL28108, ISL28208, ISL28408
6250
15 G2
R6
1
V++ D11 G13 R15 80
VOUT
R16 80
ISL28108, ISL28208, ISL28408
*ISL28108_208 Macromodel - covers following *products *ISL28108 *ISL28208 *ISL28408 * *Revision History: * Revision A, LaFontaine March 5th 2011 * Model for Noise, supply currents, CMRR *128dB f=6kHz ,AVOL 122dB f=1Hz * SR = 0.45V/us, GBWP 1.2MHz. *Copyright 2011 by Intersil Corporation *Refer to data sheet "LICENSE STATEMENT" *Use of this model indicates your acceptance *with the terms and provisions in the License *Statement. * *Intended use: *This Pspice Macromodel is intended to give *typical DC and AC performance characteristics *under a wide range of external circuit *configurations using compatible simulation *platforms – such as iSim PE. * *Device performance features supported by this *model *Typical, room temp., nominal power supply *voltages used to produce the following *characteristics: *Open and closed loop I/O impedances, *Open loop gain and phase, *Closed loop bandwidth and frequency *response, *Loading effects on closed loop frequency *response, *Input noise terms including 1/f effects, *Slew rate, *Input and Output Headroom limits to I/O *voltage swing, *Supply current at nominal specified supply *voltages. * *Device performance features NOT supported *by this model: *Harmonic distortion effects, *Output current limiting (current will limit at *40mA), *Disable operation (if any), *Thermal effects and/or over temperature *parameter variation, *Limited performance variation vs. supply *voltage is modeled, *Part to part performance variation due to *normal process parameter spread, *Any performance difference arising from *different packaging source, *Load current reflected into the power supply *current. * * Connections: +input * | -input * | | +Vsupply * | | | -Vsupply * | | | | output * |||| .subckt ISL28108_208 Vin+ Vin-V+ V- VOUT * source ISL28118_218_subckt_check_0 * *Voltage Noise E_En VIN+ 6 2 0 0.3 D_D13 1 2 DN D_D14 1 2 DN V_V7 1 0 0.1 R_R17 2 0 1150 * *Input Stage Q_Q6 11 10 9 PNP_input Q_Q7 8 7 9 PNP_input Q_Q8 V-- VIN- 7 PNP_LATERAL Q_Q9 V-- 12 10 PNP_LATERAL I_I1 V++ 9 DC 12e-6 I_I2 V++ 7 DC 6E-6 I_I3 V++ 10 DC 6E-6 I_IOS 6 VIN- DC 3e-9 *D_D1 7 10 DBREAK *D_D2 10 7 DBREAK R_R1 5 6 5e11 R_R2 VIN- 5 5e11 R_R3 V-- 8 6250 R_R4 V-- 11 6250 C_Cin1 V-- VIN- 4.19e-12 C_Cin2 V-- 6 4.19e-12 C_CinDif 6 VIN- 1.21E-12 * *1st Gain Stage G_G1 V++ 14 8 11 0.4779867 G_G2 V-- 14 8 11 0.4779867 V_V1 13 14 -6.74 V_V2 14 15 -6.76 D_D3 13 V++ DX D_D4 V-- 15 DX R_R5 14 V++ 1 R_R6 V-- 14 1 * *2nd Gain Stage G_G3 V++ VG 14 VMID 261.748e-6 G_G4 V-- VG 14 VMID 261.748e-6 V_V3 16 VG -6.74 V_V4 VG 17 -6.76 D_D5 16 V++ DX D_D6 V-- 17 DX R_R7 VG V++ 7.62283e9 R_R8 V-- VG 7.62283e9 C_C1 VG V++ 2.31e-11 C_C2 V-- VG 2.31e-11 * *Mid supply Ref E_E2 V++ 0 V+ 0 1 E_E3 V-- 0 V- 0 1 E_E4 VMID V-- V++ V-- 0.5 I_ISY V+ V- DC 185E-6 * *Common Mode Gain Stage with Zero G_G5 V++ 19 5 VMID 0.6 G_G6 V-- 19 5 VMID 0.6 G_G7 V++ VC 19 VMID 0.6 G_G8 V-- VC 19 VMID 0.6 E_EOS 12 6 VC VMID 1 L_L1 18 V++ 1.59159E-08 L_L2 20 V-- 1.59159E-08 L_L3 21 V++ 1.59159E-08 L_L4 22 V-- 1.59159E-08 R_R9 19 18 1e-3 R_R10 20 19 1e-3 R_R11 VC 21 1e-3 R_R12 22 VC 1e-3 * *Pole Satge G_G15 V++ 28 VG VMID 314.15e-6 G_G16 V-- 28 VG VMID 314.15e-6 R_R19 28 V++ 3.18319e3 R_R20 V-- 28 3.18319e3 C_C5 28 V++ 10e-12 C_C6 V-- 28 10e-12 * G_G9 V++ 23 28 VMID 314.15e-6 G_G10 V-- 23 28 VMID 314.15e-6 R_R13 23 V++ 3.18319e3 R_R14 V-- 23 3.18319e3 C_C3 23 V++ 10e-12 C_C4 V-- 23 10e-12 * *Output Stage with Correction Current Sources G_G11 26 V-- VOUT 23 12.5e-3 G_G12 27 V-- 23 VOUT 12.5e-3 G_G13 VOUT V++ V++ 23 12.5e-3 G_G14 V-- VOUT 23 V-- 12.5e-3 D_D7 23 24 DX D_D8 25 23 DX D_D9 V-- 26 DY D_D10 V++ 26 DX D_D11 V++ 27 DX D_D12 V-- 27 DY V_V5 24 VOUT -0.4 V_V6 VOUT 25 -0.4 R_R15 VOUT V++ 80 R_R16 V-- VOUT 80 .model PNP_LATERAL pnp(is=1e-016 bf=250 va=80 + ik=0.138 rb=0.01 re=0.101 rc=180 kf=0 af=1) .model PNP_input pnp(is=1e-016 bf=100 va=80 + ik=0.138 rb=0.01 re=0.101 rc=180 kf=0 af=1) .model DBREAK D(bv=43 rs=1) .model DN D(KF=6.69e-9 AF=1) .MODEL DX D(IS=1E-12 Rs=0.1) .MODEL DY D(IS=1E-15 BV=50 Rs=1) .ends ISL28108_208
FIGURE 56. SPICE NET LIST
19
FN6935.2 July 1, 2011
ISL28108, ISL28208, ISL28408 Characterization vs Simulation Results
100
INPUT NOISE VOLTAGE (nV/√Hz) INPUT NOISE VOLTAGE (nV/√Hz)
100
10 0.1
1
10
100
1k
10k
100k
10 0.1
1
10
100
1k
10k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 57. CHARACTERIZED INPUT NOISE VOLTAGE
FIGURE 58. SIMULATED INPUT NOISE VOLTAGE
200 180 160 140 120 100 80 60 40 20 0 GAIN -20 VS = ±15V -40 -60 RL = 1MΩ -80 SIMULATION -100 0.1 1 10 100
200 PHASE
GAIN (dB), PHASE (°)
150 100 50 0 -50 -100 GAIN VS = ±15V RL = 1MΩ SIMULATION 0.1 1 10 100
PHASE
GAIN (dB), PHASE (°)
1k 10k 100k 1M FREQUENCY (Hz)
10M 100M 1G
1k 10k 100k 1M FREQUENCY (Hz)
10M 100M 1G
FIGURE 59. CHARACTERIZED OPEN-LOOP GAIN, PHASE vs FREQUENCY
FIGURE 60. SIMULATED OPEN-LOOP GAIN, PHASE vs FREQUENCY
70 60 50
GAIN (dB)
ACL = 1001
RF = 10kΩ, RG = 10Ω RF = 10kΩ, RG = 100Ω
70 60 50
GAIN (dB)
RF = 10kΩ, RG = 10Ω RF = 10kΩ, RG = 100Ω VS = ±5V, ±15V CL = 4pF R L = 2k VOUT = 100mVP-P
40 30 20 10 0
ACL = 101
ACL = 10 RF = 10kΩ, RG = 1.1kΩ ACL = 1 RF = 0, R G = ∞ 1k 10k 100k
VS = ±5V, ±15V CL = 4pF RL = 2 k VOUT = 100mVP-P
40 30 20 10 0 RF = 10kΩ, RG = 1.1kΩ
-10 100
1M
10M
-10 100
RF = 0, R G = ∞ 1k 10k 100k 1M 10M FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 61. CHARACTERIZED CLOSED LOOP GAIN vs FREQUENCY
FIGURE 62. SIMULATED CLOSED LOOP GAIN vs FREQUENCY
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FN6935.2 July 1, 2011
ISL28108, ISL28208, ISL28408 Characterization vs Simulation Results (Continued)
1 0 NORMALIZED GAIN (dB) -2 -3 -4 -5 -6 VS = ±15V -7 CL = 4pF AV = +1 -8 VOUT = 100mVP-P -9 1k 100 RL = OPEN, 100k, 10k RL = 1 k RL = 499 RL = 100 RL = 49.9 10k 100k 1M 10M NORMALIZED GAIN (dB) -1 1 0 -1 -2 -3 -4 -5 -6 VS = ±15V -7 CL = 4pF AV = +1 -8 VOUT = 100mVP-P -9 1k 100 RL = OPEN, 100k, 10k RL = 1 k RL = 499 RL = 100 RL = 49.9 10k 100k 1M 10M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 63. CHARACTERIZED GAIN vs FREQUENCY vs RL
FIGURE 64. SIMULATED GAIN vs FREQUENCY vs RL
150 140 130 120 110 100 90 80 70 60 50 40 30 VS = ±15V 20 SIMULATION 10 0 1m 0.01 0.1 1
150
CMRR (dB)
CMRR (dB)
100
50 VS = ±15V SIMULATION
10 100 1k 10k 100k 1M 10M 100M 1G FREQUENCY (Hz)
0
1m 0.01 0.1
1
10 100 1k 10k 100k 1M 10M 100M 1G FREQUENCY (Hz)
FIGURE 65. CHARACTERIZED CMRR vs FREQUENCY
FIGURE 66. SIMULATED CMRR vs FREQUENCY
6
6 4 2
VOUT (V)
VS = ±15V AV = 1 4 R = 2k L CL = 4pF 2
VOUT (V)
VS = ±15V AV = 1 R L = 2k CL = 4pF
0 -2 -4 -6
0 -2 -4 -6
0
100
200 TIME (µs)
300
400
0
100
200 TIME (µs)
300
400
FIGURE 67. CHARACTERIZED LARGE SIGNAL 10V STEP RESPONSE
FIGURE 68. SIMULATED LARGE SIGNAL 10V STEP RESPONSE
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FN6935.2 July 1, 2011
ISL28108, ISL28208, ISL28408 Characterization vs Simulation Results (Continued)
100 80 60 40
VOUT (mV)
100 VS = ±15V AND VS = ±5V AV = 1 RL = 2k CL = 4pF 80 60 40
VOUT (mV)
20 0 -20 -40 -60 -80 -100 0 0.5 1.0 1.5 2.0 2.5 TIME (µs) 3.0
20 0 -20 -40 -60 -80
VS = ±15V AND VS = ±5V AV = 1 RL = 2k CL = 4pF
3.5
4.0
-100
0
0.5
1.0
1.5
2.0 2.5 TIME (µs)
3.0
3.5
4.0
FIGURE 69. CHARACTERIZED SMALL SIGNAL TRANSIENT RESPONSE
FIGURE 70. SIMULATED SMALL SIGNAL TRANSIENT RESPONSE
20V
OUTPUT VOLTAGE SWING (V)
VOH = 14.93V 10V
0V
-10V VOL = -14.94V -20V 0 0.5 1.0 TIME (m s) 1.5 2.0
FIGURE 71. SIMULATED OUTPUT VOLTAGE SWING
For additional products, see www.intersil.com/product_tree Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com
22
FN6935.2 July 1, 2011
ISL28108, ISL28208, ISL28408 Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest Rev.
DATE 4/20/11 REVISION FN6935.2 CHANGE • Added discussion of ISL28408 throughout datasheet. • On page 2 in “Ordering Information”: Added new part, “ISL28408FBZ”. Corrected part marking for ISL28208FRTZ from 208Z to 208F. Added “ISL28408” to Note 3. Under” Pin Configurations,” added ISL28408 (14 Ld SOIC) pin configuration diagram. • On page 3: in Pin Descriptions table, added column for ISL28408 14Ld SOIC. Corrected schematic for Circuit 2. • On page 4: under “Thermal Information” added "14 Ld SOIC Package (408, Notes 4, 7)" and added ISL28108 to 8 Ld TDFN and 8 Ld MSOP. Changed θJA and θJC for 8 Ld TDFN Package from 48 and 5.5 to 47 and 6. Added Note 6 regarding θJC “case temp” measurement, and applied it to 8 Ld TDFN Package. • On page 4: in Electrical Specifications table, changed TYP spec for TCIB from 70 pA/° C to 0.07nA/° C. On page 6, change TYP spec for TCIB from -67 pA/° C to -0.067nA/° C. These are not spec changes since the values are the same. • On page 10, Figs. 19 and 20: changed y axis units label from (mV) to (V); changed x axis units label from (µA) to (mA). • On page 16, under “Output Drive Capability,” para 2, changed "The output stage can swing at moderate levels of output current (Figures 21 and 22) and the output stage is internally current limited. Output current limit over-termperature..." to "The output stage is internally current limited. Output current limit overtemperature..." • On page 1, in the first paragraph - added the following after V-rail: "a rail-to-rail differential input voltage range for use as a comparator,…" • On page 1 in “Features: - Added bullet - “Rail-to-rail Input Differential Voltage Range for Comparator Applications” - Changed Low Noise Current from "100fA/sq.root Hz" to "80fA/sq.root Hz" • On page 2 in “Ordering Information” - Removed "coming soon" from ISL28208FRTZ part since it is releasing. • On page 4, changed “ESD Tolerance” as follows: - Human Body Model changed from "3kV" to "6kV" - Machine Model changed from "300V" to "400V" - Added JEDEC Test information for all ESD ratings • On page 4 and page 6, added test conditions for SOIC TCVos specs. Added TCVos specs for TDFN. • On page 5 changed “Noise Current Density” Typical from "100" to "80" • On page 16, updated Applications Information Functional Description • On page 16 Updated Input Stage Performance Section • On page 16 Updated Output Drive Capability Section • On page 17 Added ISL28108 AND ISL28208 SPICE MODEL and License Agreement section • On page 18 Added SPICE NET LIST • On page 20 Added Characterization vs Simulation Results curves Initial Release
3/11/11
FN6935.1
2/16/11
FN6935.0
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a complete list of Intersil product families. For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on intersil.com: ISL28108, ISL28208, ISL28408. To report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff FITs are available from our website at: http://rel.intersil.com/reports/search.php
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FN6935.2 July 1, 2011
ISL28108, ISL28208, ISL28408
Package Outline Drawing
M8.15E
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE Rev 0, 08/09
4 4.90 ± 0.10 A DETAIL "A" 0.22 ± 0.03
B
6.0 ± 0.20 3.90 ± 0.10 4 PIN NO.1 ID MARK 5 (0.35) x 45° 1.27 0.43 ± 0.076 0.25 M C A B 4° ± 4°
TOP VIEW
SIDE VIEW “B”
1.75 MAX
1.45 ± 0.1 0.25 0.175 ± 0.075 GAUGE PLANE C SEATING PLANE 0.10 C
SIDE VIEW “A
0.63 ±0.23
DETAIL "A"
(1.27) (0.60)
NOTES: (1.50) 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. Unless otherwise specified, tolerance : Decimal ± 0.05 Dimension does not include interlead flash or protrusions. Interlead flash or protrusions shall not exceed 0.25mm per side. 5. 6. The pin #1 identifier may be either a mold or mark feature. Reference to JEDEC MS-012.
2. (5.40) 3. 4.
TYPICAL RECOMMENDED LAND PATTERN
24
FN6935.2 July 1, 2011
ISL28108, ISL28208, ISL28408
Package Outline Drawing
L8.3x3A
8 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE Rev 4, 2/10
( 2.30) 3.00 A B ( 1.95)
( 8X 0.50) 3.00 6 PIN 1 INDEX AREA (4X) 0.15 TOP VIEW PIN 1 (6x 0.65) ( 8 X 0.30) TYPICAL RECOMMENDED LAND PATTERN (1.50) ( 2.90 )
SEE DETAIL "X" 2X 1.950 6X 0.65 PIN #1 INDEX AREA 6 1.50 ±0.10 1 SIDE VIEW 0.75 ±0.05
0.10 C
C 0.08 C
8 8X 0.30 ± 0.10 2.30 ±0.10 BOTTOM VIEW 8X 0.30 ±0.05 0.10 M C A B
4
C
0 . 2 REF
5
0 . 02 NOM. 0 . 05 MAX. DETAIL "X"
NOTES: 1. 2. 3. 4. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. Dimensioning and tolerancing conform to ASME Y14.5m-1994. Unless otherwise specified, tolerance : Decimal ± 0.05 Dimension applies to the metallized terminal and is measured between 0.15mm and 0.20mm from the terminal tip. 5. 6. Tiebar shown (if present) is a non-functional feature. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Compliant to JEDEC MO-229 WEEC-2 except for the foot length.
25
FN6935.2 July 1, 2011
ISL28108, ISL28208, ISL28408
Package Outline Drawing
M8.118
8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE Rev 3, 3/10
3.0±0.05 A 8 D 1.10 MAX 5
DETAIL "X"
SIDE VIEW 2 3.0±0.05 5 4.9±0.15
0.09 - 0.20
PIN# 1 ID 1 2 B 0.65 BSC TOP VIEW
0.95 REF
GAUGE PLANE
0.25
0.55 ± 0.15 H 0.85±010 DETAIL "X" C SEATING PLANE 0.25 - 0.036 0.08 M C A-B D SIDE VIEW 1 0.10 ± 0.05 0.10 C
3°±3°
(5.80) (4.40) (3.00)
NOTES: 1. Dimensions are in millimeters. 2. Dimensioning and tolerancing conform to JEDEC MO-187-AA and AMSEY14.5m-1994. 3. Plastic or metal protrusions of 0.15mm max per side are not included. 4. Plastic interlead protrusions of 0.15mm max per side are not included. 5. Dimensions are measured at Datum Plane "H". 6. Dimensions in ( ) are for reference only.
(0.65) (0.40) (1.40)
TYPICAL RECOMMENDED LAND PATTERN
26
FN6935.2 July 1, 2011
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