ISL28118M

40V Extended Temperature Range, Precision Single-Supply, Rail-to-Rail Output, Operational Amplifier ISL28118M The ISL28118M is a single, low-power precision amplifier optimized for single-supply applications over the extended temperature range of -55°C to +125°C. This device features a common mode input voltage range extending to 0.5V below the V- rail, a rail-rail differential input voltage range for use as a comparator, and rail-to-rail output voltage swing, which makes it ideal for single-supply applications where input operation at ground is important. The ISL28118M features low power, low offset voltage, and low temperature drift, making it the ideal choice for applications requiring both high DC accuracy and AC performance. The op amp is designed to operate over a single supply range of 3V to 40V or a split supply voltage range of +1.8V/-1.2V to ±20V. The combination of precision and small footprint provides the user with outstanding value and flexibility relative to similar competitive parts. Applications include precision instrumentation, data acquisition, precision power supply controls, and industrial controls. The ISL28118M is offered in the 8 Ld MSOP package and operate over the extended temperature range of -55°C to +125°C. Features • Rail-to-Rail Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300kΩ. The output stage is internally current limited. The amplifiers can withstand a short circuit to either rail as long as the power dissipation limits are not exceeded. Continuous operation under these conditions may degrade long-term reliability. The amplifiers perform well when driving capacitive loads (Figures 45 and 46). The unity gain, voltage follower (buffer) configuration provides the highest bandwidth but is also the most sensitive to ringing produced by load capacitance found in BNC cables. Unity gain overshoot is limited to 35% at capacitance values to 0.33nF. At gains of 10 and higher, the device is capable of driving more than 10nF without significant overshoot. Operating Voltage Range The op amp is designed to operate over a single supply range of 3V to 40V or a split supply voltage range of +1.8V, -1.2V to +/-20V. The device is fully characterized at 10V (±5V) and 30V (±15V). Both DC and AC performance remain virtually unchanged over the complete operating voltage range. Parameter variation with operating voltage is shown in the “Typical Performance Curves” beginning on page 6. The input common mode voltage to the V+ rail (V+ -1.8V over the full temperature range) may limit amplifier operation when operating from split V+ and V- supplies. Figure 6 shows the common mode input voltage range variation over temperature. Input Stage Performance The ISL28118M PNP input stage has a common mode input range extending up to 0.5V below ground at +25°C (Figure 6). Full amplifier performance is guaranteed with input voltage down to ground (V-) over the -55°C to +125°C temperature range. For common mode voltages down to -0.5V below ground (V-), the amplifiers are fully functional, but performance degrades slightly over the full temperature range. This feature provides excellent CMRR, AC performance, and DC accuracy when amplifying low-level, ground-referenced signals. The input stage has a maximum input differential voltage equal to a diode drop greater than the supply voltage (max 42V) and does not contain the back-to-back input protection diodes found on many similar amplifiers. This feature enables the device to function as a precision comparator by maintaining very high input impedance for high-voltage differential input comparator voltages. The high differential input impedance also enables the device to operate reliably in large signal pulse applications, without the need for anti-parallel clamp diodes required on MOSFET and most bipolar input stage op amps. Thus, input signal distortion caused by nonlinear clamps under high slew rate conditions is avoided. In applications where one or both amplifier input terminals are at risk of exposure to voltages beyond the supply rails, current-limiting resistors may be needed at each input terminal (see Figure 52, RIN+, RIN-) to limit current through the power-supply ESD diodes to 20mA. Output Phase Reversal Output phase reversal is a change of polarity in the amplifier transfer function when the input voltage exceeds the supply voltage. The ISL28118M is immune to output phase reversal for input voltage to 0.5V beyond the rail (VABS MAX) limit (Figure 38). Power Dissipation It is possible to exceed the +150°C maximum junction temperatures under certain load and power supply conditions. It is therefore important to calculate the maximum junction temperature (TJMAX) for all applications to determine if power supply voltages, load conditions, or package type need to be modified to remain in the safe operating area. These parameters are related using Equation 1: T JMAX = T MAX + θ JA xPD MAXTOTAL (EQ. 1) where • PDMAXTOTAL is the sum of the maximum power dissipation of each amplifier in the package (PDMAX) • TMAX = Maximum ambient temperature • ΘJA = Thermal resistance of the package 14 FN7858.0 May 11, 2011 ISL28118M PDMAX for each amplifier can be calculated using Equation 2: V OUTMAX PD MAX = V S × I qMAX + ( V S - V OUTMAX ) × -----------------------R L LICENSE STATEMENT The information in the SPICE model is protected under United States copyright laws. Intersil Corporation hereby grants users of this macro-model, hereto referred to as “Licensee”, a nonexclusive, nontransferable licence to use this model, as long as the Licensee abides by the terms of this agreement. Before using this macro-model, the Licensee should read this license. If the Licensee does not accept these terms, permission to use the model is not granted. The Licensee may not sell, loan, rent, or license the macro-model, in whole, in part, or in modified form, to anyone outside the Licensee’s company. The Licensee may modify the macro-model to suit his/her specific applications, and the Licensee may make copies of this macro-model for use within their company only. This macro-model is provided “AS IS, WHERE IS, AND WITH NO WARRANTY OF ANY KIND EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO ANY IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.” In no event will Intersil be liable for special, collateral, incidental, or consequential damages in connection with or arising out of the use of this macro-model. Intersil reserves the right to make changes to the product and the macro-model without prior notice. (EQ. 2) where: • PDMAX = Maximum power dissipation of 1 amplifier • VS = Total supply voltage • IqMAX = Maximum quiescent supply current of one amplifier • VOUTMAX = Maximum output voltage swing of the application • RL = Load resistance ISL28118M SPICE Model Figure 50 shows the SPICE model schematic and Figure 51 shows the net list for the SPICE model. The model is a simplified version of the actual device and simulates important AC and DC parameters. AC parameters incorporated into the model are: 1/f and flatband noise voltage, slew rate, CMRR, and gain and phase. The DC parameters are IOS, total supply current, and output voltage swing. The model uses typical parameters given in the “Electrical Specifications” table beginning on page 3. The AVOL is adjusted for 136dB with the dominant pole at 0.6Hz. The CMRR is set at 120dB, f = 50kHz. The input stage models the actual device to present an accurate AC representation. The model is configured for an ambient temperature of +25°C. Figures 52 through 66 show the characterization vs. simulation results for the noise voltage, open loop gain phase, closed loop gain vs. frequency, gain vs. frequency vs. RL, CMRR, large signal 10V step response, small signal 0.1V step, and output voltage swing ±15V supplies. 15 FN7858.0 May 11, 2011 I1 80e-6 DX D3 G1 + - R5 I2 54E-6 Vin0.1 V7 1 DN D13 2 + ++ -En 0.1 4 V8 D14 0 R1 5e11 DN R2 5e11 5 CinDif 1.33E-12 IOS 4e-9 9 D1 DBREAK PNP_LATERAL Q8 7 Q7 Q6 10 Q9 I3 54E-6 -0.91 PNP_LATERAL 12 13 1 GAIN = 0.65897 V1 PNP_input PNP_input D2 DBREAK 8 11 EOS ++ -GAIN = 1 -0.96 14 Vin+ GAIN = 0.3 Cin2 4.02e-12 Cin1 4.02e-12 6 V-- GAIN = 0.65897 D4 V-- DX E2 ++ -0 DX D5 16 GAIN = 1 L1 3.18319E-09 + GAIN = 1.69138e-3 -0.91 V3 Vg Vmid C1 R7 6.6667E-11 3.7304227e9 V+ Input Stage 1st Gain Stage V++ V++ L3 3.18319E-09 R13 795.7981 D10 DX V++ D11 R15 80 Vout G13 GAIN = 12.5e-3 + DX G5 + + 18 21 GAIN = 1 R9 GAIN = 1 R11 1e-3 1e-3 19 Vc G9 + - GAIN = 1.2566e-3 C3 10e-12 23 ISY D7 DX 24 26 27 2.5E-3 V4 -0.96 G4 GAIN = 1.69138e-3 + + 17 D8 ++ -GAIN = 0.5 C2 6.6667E-11 3.7304227e9 DX D6 G6 + R10 1e-3 20 G8 + L2 3.18319E-09 GAIN = 1 GAIN = 1 V-V2nd Gain Stage Mid Supply ref V Common Mode Gain Stage with Zero 0 E3 + +GAIN = 1 V-R12 1e-3 22 L4 3.18319E-09 DX 25 G10 + + - DY C4 10e-12 DY D9 V-- G14 GAIN = 12.5e-3 Output Stage Correction Current Sources FIGURE 50. SPICE SCHEMATIC + - GAIN = 1.2566e-3 R14 795.7981 G11 G12 D12 + + GAIN = 12.5e-3 GAIN = 12.5e-3 - 16 FN7858.0 May 11, 2011 0 750 R17 V2 3 750 R18 Vcm R3 1k R4 1k 15 G2 R6 1 ISL28118M V5 -0.4 VOUT V6 -0.4 R16 80 ISL28118M *ISL28118_218 Macromodel - covers following *products *ISL28118 *ISL28218 * *Revision History: * Revision A, LaFontaine February 8th 2011 * Model for Noise, supply currents, CMRR *120dB f = 40kHz, AVOL 136dB f = 0.5Hz * SR = 1.2V/us, GBWP 4MHz. *Copyright 2011 by Intersil Corporation *Refer to data sheet “LICENSE STATEMENT” *Use of this model indicates your acceptance *with the terms and provisions in the License *Statement. * *Intended use: *This Pspice Macromodel is intended to give *typical DC and AC performance characteristics *under a wide range of external circuit *configurations using compatible simulation *platforms – such as iSim PE. * *Device performance features supported by this *model: *Typical, room temp., nominal power supply *voltages used to produce the following *characteristics: *Open and closed loop I/O impedances, *Open loop gain and phase, *Closed loop bandwidth and frequency *response, *Loading effects on closed loop frequency *response, *Input noise terms including 1/f effects, *Slew rate, *Input and Output Headroom limits to I/O *voltage swing, *Supply current at nominal specified supply *voltages, * *Device performance features NOT supported *by this model: *Harmonic distortion effects, *Output current limiting (current will limit at *40mA), *Disable operation (if any), *Thermal effects and/or over temperature *parameter variation, *Limited performance variation vs. supply *voltage is modeled, *Part to part performance variation due to *normal process parameter spread, *Any performance difference arising from *different packaging, *Load current reflected into the power supply *current. * source ISL28118_218 SPICEmodel * * Connections: +input * | -input * | | +Vsupply * | | | -Vsupply * | | | | output .subckt ISL28118_218 Vin+ Vin-V+ V- VOUT * source ISL28118_218_presubckt_0 * *Voltage Noise E_En VIN+ 6 2 0 0.3 D_D13 1 2 DN D_D14 1 2 DN V_V7 1 0 0.1 V_V8 4 0 0.1 R_R17 2 0 750 *R_R18 3 0 750 * *Input Stage Q_Q6 11 10 9 PNP_input Q_Q7 8 7 9 PNP_input Q_Q8 V-- VIN- 7 PNP_LATERAL Q_Q9 V-- 12 10 PNP_LATERAL I_I1 V++ 9 DC 80e-6 I_I2 V++ 7 DC 54E-6 I_I3 V++ 10 DC 54E-6 I_IOS 6 VIN- DC 4e-9 *D_D1 7 10 DBREAK *D_D2 10 7 DBREAK R_R1 5 6 5e11 R_R2 VIN- 5 5e11 R_R3 V-- 8 1000 R_R4 V-- 11 1000 C_Cin1 V-- VIN- 4.02e-12 C_Cin2 V-- 6 4.02e-12 C_CinDif 6 VIN- 1.33E-12 * *1st Gain Stage G_G1 V++ 14 8 11 0.65897 G_G2 V-- 14 8 11 0.65897 V_V1 13 14 -0.91 V_V2 14 15 -0.96 D_D3 13 V++ DX D_D4 V-- 15 DX R_R5 14 V++ 1 R_R6 V-- 14 1 * *2nd Gain Stage G_G3 V++ VG 14 VMID 1.69138e-3 G_G4 V-- VG 14 VMID 1.69138e-3 V_V3 16 VG -0.91 V_V4 VG 17 -0.96 D_D5 16 V++ DX D_D6 V-- 17 DX R_R7 VG V++ 3.7304227e9 R_R8 V-- VG 3.7304227e9 C_C1 VG V++ 6.6667E-11 C_C2 V-- VG 6.6667E-11 * *Mid supply Ref E_E2 V++ 0 V+ 0 1 E_E3 V-- 0 V- 0 1 E_E4 VMID V-- V++ V-- 0.5 I_ISY V+ V- DC 0.85E-3 * *Common Mode Gain Stage with Zero G_G5 V++ 19 5 VMID 1 G_G6 V-- 19 5 VMID 1 G_G7 V++ VC 19 VMID 1 G_G8 V-- VC 19 VMID 1 E_EOS 12 6 VC VMID 1 L_L1 18 V++ 3.18319E-09 L_L2 20 V-- 3.18319E-09 L_L3 21 V++ 3.18319E-09 L_L4 22 V-- 3.18319E-09 R_R9 19 18 1e-3 R_R10 20 19 1e-3 R_R11 VC 21 1e-3 R_R12 22 VC 1e-3 * *Pole Stage G_G9 V++ 23 VG VMID 1.2566e-3 G_G10 V-- 23 VG VMID 1.2566e-3 R_R13 23 V++ 795.7981 R_R14 V-- 23 795.7981 C_C3 23 V++ 10e-12 C_C4 V-- 23 10e-12 * *Output Stage with Correction Current Sources G_G11 26 V-- VOUT 23 12.5e-3 G_G12 27 V-- 23 VOUT 12.5e-3 G_G13 VOUT V++ V++ 23 12.5e-3 G_G14 V-- VOUT 23 V-- 12.5e-3 D_D7 23 24 DX D_D8 25 23 DX D_D9 V-- 26 DY D_D10 V++ 26 DX D_D11 V++ 27 DX D_D12 V-- 27 DY V_V5 24 VOUT -0.4 V_V6 VOUT 25 -0.4 R_R15 VOUT V++ 80 R_R16 V-- VOUT 80 .model PNP_LATERAL pnp(is=1e-016 bf=250 va=80 + ik=0.138 rb=0.01 re=0.101 rc=180 kf=0 af=1) .model PNP_input pnp(is=1e-016 bf=100 va=80 + ik=0.138 rb=0.01 re=0.101 rc=180 kf=0 af=1) .model DBREAK D(bv=43 rs=1) .model DN D(KF=6.69e-9 AF=1) .MODEL DX D(IS=1E-12 Rs=0.1) .MODEL DY D(IS=1E-15 BV=50 Rs=1) .ends ISL28118_218 FIGURE 51. SPICE NET LIST 17 FN7858.0 May 11, 2011 ISL28118M Characterization vs Simulation Results 100 INPUT NOISE VOLTAGE (nV/√Hz) 100 INPUT NOISE CURRENT (fA/√Hz) 100 INPUT NOISE VOLTAGE (nV/√Hz) VS = ±18V INPUT NOISE VOLTAGE 10 10 10 1 INPUT NOISE CURRENT 1 1 0.1 0.1 1 10 100 1k FREQUENCY (Hz) 10k 0.1 100k 0.1 0.1 1 10 100 1k FREQUENCY (Hz) 10k 100k FIGURE 52. CHARACTERIZED INPUT NOISE VOLTAGE FIGURE 53. SIMULATED INPUT NOISE VOLTAGE 200 180 160 140 120 100 80 60 40 20 0 -20 -40 -60 VS = ±15V -80 RL = 1MΩ -100 1m 0.01 0.1 PHASE GAIN 1 10 100 1k 10k 100k 1M 10M100M 1G FREQUENCY (Hz) 200 180 160 140 120 100 80 60 40 20 0 -20 -40 -60 VS = ±15V -80 RL = 1MΩ -100 1m 0.01 0.1 PHASE GAIN (dB) GAIN (dB) GAIN 1 10 100 1k 10k 100k 1M 10M100M 1G FREQUENCY (Hz) FIGURE 54. CHARACTERIZED OPEN-LOOP GAIN, PHASE vs FREQUENCY FIGURE 55. SIMULATED OPEN-LOOP GAIN, PHASE vs FREQUENCY 70 60 50 GAIN (dB) ACL = 1000 RF = 10kΩ, RG = 10Ω RF = 10kΩ, RG = 100Ω 70 60 50 GAIN (dB) ACL = 1000 RF = 10kΩ, RG = 10Ω RF = 10kΩ, RG = 100Ω 40 30 20 10 0 ACL = 100 ACL = 10 RF = 10kΩ, RG = 1kΩ ACL = 1 RF = 0, RG = ∞ 1k 10k 100k VS = ±5V & ±15V CL = 4pF RL = 2 k VOUT = 100mVP-P 40 30 20 10 0 ACL = 100 VS = ±5V & ±15V CL = 4pF R L = 2k VOUT = 100mVP-P ACL = 10 RF = 10kΩ, RG = 1kΩ ACL = 1 R F = 0, R G = ∞ 1k 10k 100k 1M 10M FREQUENCY (Hz) -10 100 1M 10M -10 100 FREQUENCY (Hz) FIGURE 56. CHARACTERIZED CLOSED-LOOP GAIN vs FREQUENCY FIGURE 57. SIMULATED CLOSED-LOOP GAIN vs FREQUENCY 18 FN7858.0 May 11, 2011 ISL28118M Characterization vs Simulation Results (Continued) 1 0 NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) -1 -2 -3 -4 -5 -6 VS = ±15V CL = 4pF -7 A = +1 V -8 VOUT = 100mVp-p -9 100 1k 10k RL = OPEN, 100k, 10k RL = 1 k RL = 499k RL = 100k RL = 49.9k 100k 1M 10M 1 0 -1 -2 -3 -4 -5 -6 VS = ±15V CL = 4pF -7 A = +1 V -8 VOUT = 100mVp-p -9 100 1k 10k RL = OPEN, 100k, 10k RL = 1k RL = 499k RL = 100k RL = 49.9k 100k 1M 10M FREQUENCY (Hz) FREQUENCY (Hz) FIGURE 58. CHARACTERIZED GAIN vs FREQUENCY vs RL FIGURE 59. SIMULATED GAIN vs FREQUENCY vs RL 140 130 120 110 100 90 80 70 60 50 40 30 VS = ±15V 20 SIMULATION 10 0 1m 0.01 0.1 1 10 100 1k 10k 100k 1M 10M 100M 1G FREQUENCY (Hz) 140 130 120 110 100 90 80 70 60 50 40 30 VS = ±15V 20 SIMULATION 10 0 1m 0.01 0.1 1 CMRR (dB) CMRR (dB) 10 100 1k 10k 100k 1M 10M 100M 1G FREQUENCY (Hz) FIGURE 60. CHARACTERIZED CMRR vs FREQUENCY FIGURE 61. SIMULATED CMRR vs FREQUENCY 6 VS = ±15V AV = 1 4 RL = 2 k CL = 4pF 2 VOUT (V) 6 4 2 VOUT (V) VS = ±15V AV = 1 RL = 2 k CL = 4pF 0 -2 -4 -6 0 -2 -4 -6 0 10 20 30 40 50 60 TIME (µs) 70 80 90 100 0 10 20 30 40 50 60 TIME (µs) 70 80 90 100 FIGURE 62. CHARACTERIZED LARGE-SIGNAL 10V STEP RESPONSE FIGURE 63. SIMULATED LARGE-SIGNAL 10V STEP RESPONSE 19 FN7858.0 May 11, 2011 ISL28118M Characterization vs Simulation Results (Continued) 100 80 60 40 VOUT (V) 0 -20 -40 -60 -80 -100 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 VOUT (V) 20 VS = ±15V AND VS = ±5V AV = 1 RL = 2 k CL = 4pF 100 80 60 40 20 0 -20 -40 -60 -80 -100 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 VS = ±15V AND VS = ±5V AV = 1 R L = 2k CL = 4pF 1.6 1.8 2.0 TIME (µs) TIME (µs) FIGURE 64. CHARACTERIZED SMALL-SIGNAL TRANSIENT RESPONSE FIGURE 65. SIMULATED SMALL-SIGNAL TRANSIENT RESPONSE 20V OUTPUT VOLTAGE SWING (V) VOH = 14.88V 10V 0V RL = 10kΩ -10V VS = ±15V VOL = -14.93V -20V 0 0.5 1.0 TIME (ms) 1.5 2.0 FIGURE 66. SIMULATED OUTPUT VOLTAGE SWING 20 FN7858.0 May 11, 2011 ISL28118M Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest Rev. DATE 5/11/11 REVISION FN7858.0 Initial Release CHANGE Products Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a complete list of Intersil product families. *For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on intersil.com: ISL28118M. To report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff FITs are available from our website at: http://rel.intersil.com/reports/search.php For additional products, see www.intersil.com/product_tree Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 21 FN7858.0 May 11, 2011 ISL28118M Package Outline Drawing M8.118 8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE Rev 3, 3/10 3.0±0.05 A 8 D 1.10 MAX 5 DETAIL "X" SIDE VIEW 2 3.0±0.05 5 4.9±0.15 0.09 - 0.20 PIN# 1 ID 1 2 B 0.65 BSC TOP VIEW 0.95 REF GAUGE PLANE 0.25 0.55 ± 0.15 H 0.85±010 DETAIL "X" C SEATING PLANE 0.25 - 0.036 0.08 M C A-B D SIDE VIEW 1 0.10 ± 0.05 0.10 C 3°±3° (5.80) (4.40) (3.00) NOTES: 1. Dimensions are in millimeters. 2. Dimensioning and tolerancing conform to JEDEC MO-187-AA and AMSEY14.5m-1994. 3. Plastic or metal protrusions of 0.15mm max per side are not included. 4. Plastic interlead protrusions of 0.15mm max per side are not included. 5. Dimensions are measured at Datum Plane "H". 6. Dimensions in ( ) are for reference only. (0.65) (0.40) (1.40) TYPICAL RECOMMENDED LAND PATTERN 22 FN7858.0 May 11, 2011