ISL28130_10

Single, Dual, and Quad Micropower, Low Drift, RRIO Operational Amplifiers ISL28130, ISL28230, ISL28430 The ISL28130, ISL28230 and ISL28430 are single, dual and quad micropower, low drift operational amplifiers that are optimized for single and dual supply operation from 1.65V to 5.5V and ±0.825V to ±2.75V. Their low supply current of 20µA and wide input range enable the ISL28130, ISL28230, ISL28430 to be an excellent general purpose op amp for a range of applications. The ISL28130, ISL28230 and ISL28430 are ideal for handheld devices that operate off 2 AA or single Li-ion batteries. The ISL28130 is available in industry standard pinouts for 5 Ld SOT-23, 5 Ld SC70 and 8 Ld SOIC packages. The ISL28230 is available in industry standard pinouts for 8 Ld MSOP and 8Ld SOIC packages. The ISL28430 is available in 14 Ld TSSOP and 14 Ld SOIC packages. All devices operate over the temperature range of 0°C to +70°C. ISL28130, ISL28230, ISL28430 Features • Low Input Offset Voltage . . . . . . . . . . . . 40µV, Max. • Low Offset Drift . . . . . . . . . . . . . . . 150nV/°C, Max • Input Bias Current . . . . . . . . . . . . . . 250 pA, Max. • Quiescent Current (Per Amplifier) . . . . . . 20µA, Typ. • Single Supply Range . . . . . . . . . . .+1.65V to +5.5V • Dual Supply Range . . . . . . . . . . ±0.825V to ±2.75V • Low Noise (0.01Hz to 10Hz) . . . . . . . . 1.1µVP-P, Typ. • Rail-to-Rail Inputs and Output • Operating Temperature Range . . . . . . 0°C to +70°C Applications*(see page 11) • Bi-Directional Current Sense • Temperature Measurement • Medical Equipment • Electronic Weigh Scales • Precision/Strain Gauge Sensor • Precision Regulation • Low Ohmic Current Sense • High Gain Analog Front Ends Typical Application I-SENSE+ V+ +1.65V TO +5.5V VREF 4.99k + V+ 0.1 4.99k V499k 499k VSENSE OUT IB vs Temperature 70 INPUT BIAS CURRENT IN- (pA) 60 50 40 30 20 10 0 0 10 20 30 40 50 60 70 VS = ±0.825V VS = ±2.5V I-SENSE- GND BI-DIRECTIONAL CURRENT SENSE AMPLIFIER TEMPERATURE (°C) August 17, 2010 FN7623.0 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2010. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL28130, ISL28230, ISL28430 Ordering Information PART NUMBER (Notes 2, 3) Coming Soon ISL28130CBZ Coming Soon ISL28130CBZ-T7 (Note 1) Coming Soon ISL28130CBZ-T7A (Note 1) ISL28130CHZ-T7 (Note 1) ISL28130CHZ-T7A (Note 1) ISL28130CEZ-T7 (Note 1) ISL28130CEZ-T7A (Note 1) ISL28230CUZ ISL28230CUZ-T7 (Note 1) ISL28230CUZ-T7A (Note 1) ISL28230CBZ ISL28230CBZ-T7 (Note 1) ISL28230CBZ-T7A (Note 1) ISL28430CBZ ISL28430CBZ-T7 (Note 1) ISL28430CBZ-T7A (Note 1) ISL28430CVZ ISL28430CVZ-T7A (Note 1) ISL28430CVZ-T13 (Note 1) NOTES: 1. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL28130, ISL28230, ISL28430. For more information on MSL please see techbrief TB363. PART MARKING 28130 CBZ 28130 CBZ 28130 CBZ PACKAGE (Pb-Free) 8 Ld SOIC 8 Ld SOIC (Tape & Reel) 8 Ld SOIC (Tape & Reel) M8.15E M8.15E M8.15E PKG. DWG. # BDPA (Bottom Brand) 5 Ld SOT-23 (Tape & Reel) P5.064A BDPA (Bottom Brand) 5 Ld SOT-23 (Tape & Reel) P5.064A BLA (Bottom Brand) BLA (Bottom Brand) 8230Z 8230Z 8230Z 28230 CBZ 28230 CBZ 28230 CBZ 28430 CBZ 28430 CBZ 28430 CBZ 28430 CVZ 28430 CVZ 28430 CVZ 5 Ld SC70 (Tape & Reel) 5 Ld SC70 (Tape & Reel) 8 Ld MSOP 8 Ld MSOP (Tape & Reel) 8 Ld MSOP (Tape & Reel) 8 Ld SOIC 8 Ld SOIC (Tape & Reel) 8 Ld SOIC (Tape & Reel) 14 Ld SOIC 14 Ld SOIC (Tape & Reel) 14 Ld SOIC (Tape & Reel) 14 Ld TSSOP P5.049 P5.049 M8.118A M8.118A M8.118A M8.15E M8.15E M8.15E MDP0027 MDP0027 MDP0027 MDP0044 14 Ld TSSOP (Tape & Reel) MDP0044 14 Ld TSSOP (Tape & Reel) MDP0044 Pin Configurations ISL28130 (5 LD SOT-23) TOP VIEW OUT 1 V- 2 IN+ 3 +4 IN5 V+ NC 1 IN- 2 IN+ 3 V- 4 -+ ISL28130 (8 LD SOIC) TOP VIEW 8 NC 7 V+ 6 OUT 5 NC 2 FN7623.0 August 17, 2010 ISL28130, ISL28230, ISL28430 Pin Configurations (Continued) ISL28130 (5 LD SC70) TOP VIEW IN+ 1 V- 2 IN- 3 + 4 OUT 5 V+ ISL28230 (8 LD MSOP, SOIC) TOP VIEW OUT_A 1 IN-_A 2 IN+_A 3 V- 4 -+ +8 V+ 7 OUT_B 6 IN-_B 5 IN+_B ISL28430 (14 LD TSSOP, SOIC) TOP VIEW OUT_A 1 IN-_A 2 IN+_A 3 V+ 4 IN+_B 5 IN-_B 6 OUT_B 7 -+ +-+ +14 OUT_D 13 IN-_D 12 IN+_D 11 V10 IN+_C 9 IN-_C 8 OUT_C Pin Descriptions ISL28130 (5 Ld SOT23) 3 ISL28130 (8 Ld SOIC) 3 ISL28130 (5 LD SC70) 1 PIN NAME IN+ FUNCTION Non-inverting input IN- EQUIVALENT CIRCUIT V+ + IN+ VCircuit 1 2 4 1 4 2 6 2 3 4 VINOUT Negative supply Inverting input Output (See “Circuit 1”) V+ OUT VCircuit 2 5 7 1, 5, 8 5 V+ NC Positive supply Not Connected – This pin is not electrically connected internally. 3 FN7623.0 August 17, 2010 ISL28130, ISL28230, ISL28430 Pin Descriptions ISL28230 ISL28430 (8 Ld MSOP, SOIC) (14 Ld TSSOP, SOIC) 3 5 3 5 10 12 PIN NAME IN+_A IN+_B IN+_C IN+_D IN+ FUNCTION Non-inverting input EQUIVALENT CIRCUIT V+ IN+ VCircuit 1 4 2 6 11 2 6 9 13 VIN-_A IN-_B IN-_C IN-_D OUT_A OUT_B OUT_C OUT_D Negative supply Inverting input (See Circuit 1) 1 7 1 7 8 14 Output V+ OUT VCircuit 2 8 4 V+ Positive supply 4 FN7623.0 August 17, 2010 ISL28130, ISL28230, ISL28430 Absolute Maximum Ratings Max Supply Voltage V+ to V- . . . . . . . Max Voltage VIN to GND . . . . . . (V- Max Input Differential Voltage . . . . . . Max Input Current . . . . . . . . . . . . . . Max Voltage VOUT to GND (10s) . . . . ESD Tolerance (ISL28130) Human Body Model . . . . . . . . . . . . Machine Model . . . . . . . . . . . . . . . Charged Device Model . . . . . . . . . . ESD Tolerance (ISL28230, ISL28430) Human Body Model . . . . . . . . . . . . Machine Model . . . . . . . . . . . . . . . Charged Device Model . . . . . . . . . . Latch-Up Passed Per JESD78B . . . . . . ........... 0.3V) to (V+ + ........... ........... ........... . .6.5V 0.3V)V . 6.5V . 20mA .±3.0V Thermal Information Thermal Resistance (Typical) θJA (°C/W) θJC (°C/W) 5 Ld SOT-23 (Notes 4, 5) . . . . . . . . . 225 110 5 Ld SC70 (Notes 4, 5) . . . . . . . . . . 206 146 8 Ld SOIC (ISL28130CBZ) (Notes 4, 5) 135 95 8 Ld MSOP (Notes 4, 5) . . . . . . . . . . 180 65 8 Ld SOIC (ISL28230CBZ) (Notes 4, 5) 125 90 14 Ld TSSOP (Notes 4, 5) . . . . . . . . 110 40 14 Ld SOIC (Notes 4, 5) . . . . . . . . . 75 47 Maximum Storage Temperature Range-65°C to +150°C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp . . . . . . . . . . . 3000V . . . . . . . . . . . . 200V . . . . . . . . . . . 1500V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4000V . . 400V . 2000V +125°C Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . 0°C to +70°C CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 4. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 5. For θJC, the “case temp” location is taken at the package top center. Electrical Specifications V+ = 5V, V- = 0V, VCM = 2.5V, TA = +25°C, RL = 10kΩ, unless otherwise specified. Boldface limits apply over the operating temperature range, 0°C to +70°C. CONDITIONS MIN (Note 6) TYP MAX (Note 6) UNIT PARAMETER DC SPECIFICATIONS VOS DESCRIPTION Input Offset Voltage Vs = 1.65V to 5.5V -40 -46.8 ±5 20 -60 0.11 - 40 46.8 150 250 5.1 µV µV nV/°C pA pA/°C pA V TCVOS IOS TCIOS IB Common Mode Input Voltage Range CMRR Input Offset Voltage Temperature Coefficient Input Offset Current Input Offset Current Temperature Coefficient Input Bias Current Guaranteed by CMRR -150 -250 -0.1 Common Mode Rejection Ratio VCM = -0.1V to 5.1V 110 105 125 138 4.981 18 150 18 15 50 5.5 25 35 - dB dB dB dB V mV dB V µA µA mA PSRR Power Supply Rejection Ratio Vs = 2.0V to 5.5V 105 105 VOH VOL AOL V+ IS Output Voltage Swing, High Output Voltage Swing, Low Open Loop Gain Supply Voltage Supply Current, Per Amplifier RL = 1MΩ Guaranteed by VOS RL = OPEN 4.950 1.65 - ISC+ Output Source Short Circuit Current RL = Short V- - 5 FN7623.0 August 17, 2010 ISL28130, ISL28230, ISL28430 Electrical Specifications V+ = 5V, V- = 0V, VCM = 2.5V, TA = +25°C, RL = 10kΩ, unless otherwise specified. Boldface limits apply over the operating temperature range, 0°C to +70°C. (Continued) CONDITIONS RL = Short V+ MIN (Note 6) TYP -15 MAX (Note 6) UNIT mA PARAMETER ISC- DESCRIPTION Output Sink Short Circuit Current AC SPECIFICATIONS GBWP eN VP-P eN iN Gain Bandwidth Product Peak-to-Peak Input Noise Voltage Input Noise Voltage Density Input Noise Current Density AV = 100, RF = 100kΩ, RG = 1kΩ, RL = 10kΩ to VCM f = 0.01Hz to 10Hz f = 1kHz f = 1kHz f = 10Hz Cin Differential Input Capacitance Common Mode Input Capacitance TRANSIENT RESPONSE SR Positive Slew Rate Negative Slew Rate tr, tf, Small Signal Rise Time, tr 10% to 90% Fall Time, tf 10% to 90% tr, tf Large Signal Rise Time, tr 10% to 90% Fall Time, tf 10% to 90% ts trecover Settling Time to 0.1%, 2VP-P Step Output Overload Recovery Time, Recovery to 90% of output saturation AV = +1, VOUT = 0.1VP-P, RF = 0Ω, RL = 10kΩ, CL = 1.2pF AV = +1, VOUT = 2VP-P, RF = 0Ω, RL = 10kΩ, CL = 1.2pF AV = +1, RF = 0Ω, RL = 10kΩ, CL = 1.2pF AV = +2, RF = 10kΩ, RL = Open, CL = 3.7pF VOUT = 1V to 4V, RL = 10kΩ 0.2 0.1 1.1 1.1 20 30 35 10.5 V/µs V/µs µs µs µs µs µs µs f = 1MHz 400 1.1 65 72 80 1.6 1.12 kHz µVP-P nV/√(Hz) fA/√(Hz) fA/√(Hz) pF pF NOTE: 6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. Typical Performance Curves n V+ = 5V, V- = 0V, VCM = 2.5V, RL = Open, T = +25°C, unless otherwise specified. 70 INPUT BIAS CURRENT IN- (pA) 60 50 40 30 20 10 0 0 10 20 30 40 50 60 70 VS = ±0.825V VS = ±2.5V 65 INPUT BIAS CURRENT IN+ (pA) 55 45 35 25 15 5 -5 -15 0 10 20 30 40 50 60 70 VS = ±0.825V VS = ±2.5V TEMPERATURE (°C) TEMPERATURE (°C) FIGURE 1. IB+ vs TEMPERATURE FIGURE 2. IB- vs TEMPERATURE 6 FN7623.0 August 17, 2010 ISL28130, ISL28230, ISL28430 Typical Performance Curves 22 21 20 19 18 V+ = 1.6V 17 16 VIN = 0V RL = OPEN 0 10 20 30 40 50 60 V+ = 5V, V- = 0V, VCM = 2.5V, RL = Open, T = +25°C, unless otherwise specified. (Continued) 22 21 20 19 18 17 16 V+ = 5V VIN = 0V RL = OPEN 0 10 20 30 40 50 60 70 SUPPLY CURRENT (µA) 70 TEMPERATURE (°C) SUPPLY CURRENT (µA) TEMPERATURE (°C) FIGURE 3. SUPPLY CURRENT vs TEMPERATURE FIGURE 4. SUPPLY CURRENT vs TEMPERATURE 21 OPEN LOOP GAIN (dB)/PHASE (°) 200 150 100 50 0 -50 RL = 10M CL = 100pF SIMULATION GAIN PHASE SUPPLY CURRENT (µA) 20 19 18 VIN = 0V RL = OPEN 17 16 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 SUPPLY VOLTAGE (V) -100 0.1m 1m 10m 100m 1 10 100 1k 10k 100k 1M 10M FREQUENCY (Hz) FIGURE 5. SUPPLY CURRENT vs SUPPLY VOLTAGE FIGURE 6. FREQUENCY RESPONSE vs OPEN LOOP GAIN, RL = 10MΩ 1 0 NORMALIZED GAIN (dB) -1 -2 -3 -4 -5 -6 -7 -8 -9 100 VS = ±0.8V CL = 3.7pF AV = +1 VOUT = 10mVP-P 1k 10k 100k FREQUENCY (Hz) 1M 10M RL = 1k RL = 10k RL = 49.9k NORMALIZED GAIN (dB) RL = 100k RL = OPEN 1 0 -1 -2 -3 -4 -5 -6 -7 -8 VS = ±2.5V CL = 3.7pF AV = +1 VOUT = 10mVP-P 1k 10k 100k FREQUENCY (Hz) RL = 49.9k RL = 1k RL = 10k RL = 100k RL = OPEN -9 100 1M 10M FIGURE 7. GAIN vs FREQUENCY vs RL, VS = ±0.8V FIGURE 8. GAIN vs FREQUENCY vs RL, VS = ±2.5V 7 FN7623.0 August 17, 2010 ISL28130, ISL28230, ISL28430 Typical Performance Curves 10 9 8 7 GAIN (dB) 6 5 4 3 2 1 VS = ±2.5V RL = 100k CL = 3.7pF AV = +2 VOUT = 10mVP-P 1k 10k 100k FREQUENCY (Hz) V+ = 5V, V- = 0V, VCM = 2.5V, RL = Open, T = +25°C, unless otherwise specified. (Continued) 1 0 NORMALIZED GAIN (dB) Rf = Rg = 1k Rf = Rg = 10k -1 -2 -3 -4 -5 -6 -7 -8 VOUT = 500mV VOUT = 250mV VOUT = 100mV VOUT = 10mV 1k 10k 100k FREQUENCY (Hz) VS = ±2.5V RL = OPEN CL = 3.7pF AV = 1 1M 10M VOUT = 1V Rf = Rg = 100k 0 100 1M 10M -9 100 FIGURE 9. GAIN vs FREQUENCY vs FEEDBACK RESISTOR VALUES Rf/Rg FIGURE 10. GAIN vs FREQUENCY vs VOUT 70 60 50 GAIN (dB) 40 30 20 10 0 AV = 1 Rg = OPEN, Rf = 0 100 1k 10k 100k FREQUENCY (Hz) 1M 10M AV = 10 Rg = 10k, Rf = 100k AV = 100 Rg = 1k, Rf = 100k V+ = 5V CL = 3.7pF RL = 100k VOUT = 10mVP-P AV = 1000 Rg = 100, Rf = 100k NORMALIZED GAIN (dB) 1 0 -1 -2 -3 -4 -5 -6 -7 -8 RL = 100k CL = 3.7pF AV = +1 VOUT = 10mVP-P 1k 10k 100k FREQUENCY (Hz) 1M 10M VS = ±0.7V VS = ±0.8V VS= ±1.5V VS = ±2.75V -10 10 -9 100 FIGURE 11. FREQUENCY RESPONSE vs CLOSED LOOP GAIN FIGURE 12. GAIN vs FREQUENCY vs SUPPLY VOLTAGE 8 6 NORMALIZED GAIN (dB) 4 2 0 -2 -4 CL = 104pF CL = 51pF CL = 3.7pF CL = 824pF CL = 474pF CL = 224pF SIGNAL (V) 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 1M 10M 0 0 50 100 RL = 100k CL = 3.7pF AV = 1 VOUT = 4VP-P 150 200 250 TIME (µs) 300 350 400 VS = ±2.5V -6 R = 100k L -8 AV = +1 VOUT = 10mVP-P -10 100 1k 10k 100k FREQUENCY (Hz) FIGURE 13. GAIN vs FREQUENCY vs CL FIGURE 14. LARGE SIGNAL STEP RESPONSE (4V) 8 FN7623.0 August 17, 2010 ISL28130, ISL28230, ISL28430 Typical Performance Curves 1.2 1.0 SIGNAL (V) 0.8 0.6 0.4 0.2 0 RL = 100k CL = 3.7pF AV = 1 VOUT = 1VP-P V+ = 5V, V- = 0V, VCM = 2.5V, RL = Open, T = +25°C, unless otherwise specified. (Continued) 0.14 0.12 0.10 SIGNAL (V) 0.08 0.06 0.04 0.02 RL = 100k CL = 3.7pF AV = 1 VOUT = 100mVP-P 0 10 20 30 40 50 60 TIME (µs) 70 80 90 100 0 0 5 10 15 20 25 TIME (µs) 30 35 40 FIGURE 15. LARGE SIGNAL STEP RESPONSE (1V) FIGURE 16. SMALL SIGNAL STEP RESPONSE (100mV) 22 VOH BELOW V+ RAIL (mV) 21 20 19 18 17 16 VS = 5V RL = 10kΩ 0 10 20 30 40 50 TEMPERATURE (°C) 60 70 VOL ABOVE V- RAIL (mV) 22 21 20 19 18 17 16 VS = 5V RL = 10kΩ 0 10 20 30 40 50 60 70 TEMPERATURE (°C) FIGURE 17. VOH vs TEMPERATURE FIGURE 18. VOL vs TEMPERATURE -20 -40 CROSSTALK (dB) -60 -80 -100 -120 -140 1k Vs = ±0.8V RL = OPEN CL = 3.7pF AV = 1 VOUT = 1VP-P -20 -40 CROSSTALK (dB) -60 -80 Vs = ±2.5V RL = OPEN CL = 3.7pF AV = 1 VOUT = 1VP-P -100 -120 10k 100k 1M -140 1k 10k 100k 1M FREQUENCY (Hz) FREQUENCY (Hz) FIGURE 19. CROSSTALK vs FREQUENCY, VS = ±0.8V FIGURE 20. CROSSTALK vs FREQUENCY, VS = ±2.5V 9 FN7623.0 August 17, 2010 ISL28130, ISL28230, ISL28430 Applications Information Functional Description The ISL28130, ISL28230 and ISL28430 are low offset low drift operational amplifiers with a very high open loop gain (150dB). The ISL28130, ISL28230 and ISL28430 operate on a single supply range of 1.65V to 5.5V or dual supply range of ±0.825V to ±2.75V while consuming only 20µA of supply current per channel. The ISL28130, ISL28230 and ISL28430 has a 400kHz gain-bandwidth. The high open loop gain, low offset voltage, high bandwidth and low 1/f noise make the ISL28130, ISL28230 and ISL28430 ideal for precision applications. Layout Guidelines for High Impedance Inputs To achieve the maximum performance of the high input impedance and low offset voltage of the ISL28130, ISL28230 and ISL28430 amplifiers, care should be taken in the circuit board layout. The PC board surface must remain clean and free of moisture to avoid leakage currents between adjacent traces. Surface coating of the circuit board will reduce surface moisture and provide a humidity barrier, reducing parasitic resistance on the board. High Gain, Precision DC-Coupled Amplifier The circuit in Figure 22 implements a single-stage DC-coupled amplifier with an input DC sensitivity of under 100nV that is only possible using a low VOS amplifier with high open loop gain. High gain DC amplifiers operating from low voltage supplies are not practical using typical low offset precision op amps. For example, a typical precision amplifier in a gain of 10kV/V with a ±100µV VOS and offset drift 0.5µV/°C of a low offset op amp would produce a DC error of >1V with an additional 5mV/°C of temperature dependent error making it difficult to resolve DC input voltage changes in the mV range. The ±40µV max VOS and 150nV/°C of temperature drift of the ISL28130, ISL28230, ISL28430 produces a temperature stable maximum DC output error of only ±400mV with a maximum output temperature drift of 1.5mV/°C. The additional benefit of a very low 1/f noise corner frequency and some feedback filtering enables DC voltages and voltage fluctuations well below 10µV to be easily detected with a simple single stage amplifier. CF 0.018µF 1MΩ, Rail-to-rail Input and Output (RRIO) The RRIO CMOS amplifier uses parallel input PMOS and NMOS that enable the inputs to swing 100mV beyond either supply rail. The inverting and non-inverting inputs do not have back-to-back input clamp diodes and are capable of maintaining high input impedance at high differential input voltages. This is effective in eliminating output distortion caused by high slew-rate input signals. The output stage uses common source connected PMOS and NMOS devices to achieve rail-to-rail output drive capability with 15mA current limit and the capability to swing to within 50mV of either rail while driving a 10kΩ load. IN+ and IN- Protection All input terminals have internal ESD protection diodes to both positive and negative supply rails, limiting the input voltage to within one diode beyond the supply rails. For applications where either input is expected to exceed the rails by 0.5V, an external series resistor must be used to ensure the input currents never exceed 20mA (see Figure 21). VIN RIN + RL +2.5V VOUT VIN 100Ω 1MΩ + 100Ω -2.5V ACL = 10kV/V RL VOUT FIGURE 21. INPUT CURRENT LIMITING FIGURE 22. HIGH GAIN, PRECISION DC-COUPLED AMPLIFIER 10 FN7623.0 August 17, 2010 ISL28130, ISL28230, ISL28430 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest revision. DATE 8/17/10 REVISION FN7623.0 Initial Release CHANGE Products Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a complete list of Intersil product families. *For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on intersil.com: ISL28130, ISL28230, ISL28430. To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff FITs are available from our website at http://rel.intersil.com/reports/search.php For additional products, see www.intersil.com/product_tree Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 11 FN7623.0 August 17, 2010 ISL28130, ISL28230, ISL28430 Small Outline Transistor Plastic Packages (SC70-5) D P5.049 VIEW C e1 5 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE INCHES MILLIMETERS MIN 0.80 0.00 0.80 0.15 0.15 0.08 0.08 1.85 1.80 1.15 MAX 1.10 0.10 1.00 0.30 0.25 0.22 0.20 2.15 2.40 1.35 6 6 3 3 4 NOTES SYMBOL A MIN 0.031 0.000 0.031 0.006 0.006 0.003 0.003 0.073 0.071 0.045 MAX 0.043 0.004 0.039 0.012 0.010 0.009 0.009 0.085 0.094 0.053 5 E 1 2 3 4 C L C L E1 A1 A2 b e C L 0.20 (0.008) M C L C b b1 c c1 C D E E1 A A2 A1 SEATING PLANE -C- e e1 L L1 0.0256 Ref 0.0512 Ref 0.010 0.018 0.65 Ref 1.30 Ref 0.26 0.46 0.017 Ref. 0.006 BSC 0o 5 0.004 0.004 0.010 8o 0.420 Ref. 0.15 BSC 0o 5 0.10 0.15 0.25 8o 0.10 (0.004) C L2 WITH PLATING c b b1 c1 α N R R1 NOTES: 5 Rev. 3 7/07 BASE METAL 1. Dimensioning and tolerances per ASME Y14.5M-1994. 4X θ1 R1 R GAUGE PLANE SEATING PLANE L C 4X θ1 VIEW C 0.4mm L1 2. Package conforms to EIAJ SC70 and JEDEC MO-203AA. 3. Dimensions D and E1 are exclusive of mold flash, protrusions, or gate burrs. 4. Footlength L measured at reference to gauge plane. 5. “N” is the number of terminal positions. 6. These Dimensions apply to the flat section of the lead between 0.08mm and 0.15mm from the lead tip. 7. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only. α L2 0.75mm 2.1mm 0.65mm TYPICAL RECOMMENDED LAND PATTERN 12 FN7623.0 August 17, 2010 ISL28130, ISL28230, ISL28430 Package Outline Drawing P5.064A 5 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE Rev 0, 2/10 1.90 D A 5 4 0.08-0.20 0-3° PIN 1 INDEX AREA 2.80 3 1.60 3 0.15 C D 2x 2 0.95 SEE DETAIL X B 0.40 ±0.05 3 END VIEW 5 (0.60) 0.20 C 2x 0.20 M C A-B D TOP VIEW 10° TYP (2 PLCS) 2.90 5 0.15 C A-B 2x 1.45 MAX C 1.14 ±0.15 0.10 C SEATING PLANE H (0.25) GAUGE PLANE SIDE VIEW 0.45±0.1 0.05-0.15 DETAIL "X" (0.60) 4 (1.20) NOTES: 1. (2.40) 2. 3. 4. 5. 6. (0.95) (1.90) TYPICAL RECOMMENDED LAND PATTERN Dimensions are in millimeters. Dimensions in ( ) for Reference Only. Dimensioning and tolerancing conform to ASME Y14.5M-1994. Dimension is exclusive of mold flash, protrusions or gate burrs. Foot length is measured at reference to guage plane. This dimension is measured at Datum “H”. Package conforms to JEDEC MO-178AA. 13 FN7623.0 August 17, 2010 ISL28130, ISL28230, ISL28430 Package Outline Drawing M8.118A 8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE (MSOP) Rev 0, 9/09 A 3.0±0.1 8 0.25 CAB 3.0±0.1 4.9±0.15 DETAIL "X" 1.10 Max PIN# 1 ID 1 2 0.65 BSC TOP VIEW B SIDE VIEW 2 0.18 ± 0.05 0.95 BSC 0.86±0.09 H C SEATING PLANE 0.33 +0.07/ -0.08 0.08 C A B SIDE VIEW 1 0.10 ± 0.05 0.10 C GAUGE PLANE 0.25 3°±3° 0.55 ± 0.15 DETAIL "X" 5.80 4.40 3.00 NOTES: 1. 2. 3. Dimensions are in millimeters. Dimensioning and tolerancing conform to JEDEC MO-187-AA and AMSE Y14.5m-1994. Plastic or metal protrusions of 0.15mm max per side are not included. Plastic interlead protrusions of 0.25mm max per side are not included. Dimensions “D” and “E1” are measured at Datum Plane “H”. This replaces existing drawing # MDP0043 MSOP 8L. 0.65 0.40 1.40 TYPICAL RECOMMENDED LAND PATTERN 5. 6. 4. 14 FN7623.0 August 17, 2010 ISL28130, ISL28230, ISL28430 Thin Shrink Small Outline Package Family (TSSOP) 0.25 M C A B D N (N/2)+1 A MDP0044 THIN SHRINK SMALL OUTLINE PACKAGE FAMILY MILLIMETERS SYMBOL 14 LD 16 LD 20 LD 24 LD 28 LD TOLERANCE A A1 A2 0.20 C B A PIN #1 I.D. E E1 1.20 0.10 0.90 0.25 0.15 5.00 6.40 4.40 0.65 0.60 1.00 1.20 0.10 0.90 0.25 0.15 5.00 6.40 4.40 0.65 0.60 1.00 1.20 0.10 0.90 0.25 0.15 6.50 6.40 4.40 0.65 0.60 1.00 1.20 0.10 0.90 0.25 0.15 7.80 6.40 4.40 0.65 0.60 1.00 1.20 0.10 0.90 0.25 0.15 9.70 6.40 4.40 0.65 0.60 1.00 Max ±0.05 ±0.05 +0.05/-0.06 +0.05/-0.06 ±0.10 Basic ±0.10 Basic ±0.15 Reference Rev. F 2/07 1 B TOP VIEW (N/2) 2X N/2 LEAD TIPS b c D E E1 C SEATING PLANE e 0.05 H e L L1 b 0.10 C N LEADS SIDE VIEW 0.10 M C A B NOTES: 1. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15mm per side. 2. Dimension “E1” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm per side. 3. Dimensions “D” and “E1” are measured at dAtum Plane H. 4. Dimensioning and tolerancing per ASME Y14.5M-1994. SEE DETAIL “X” c END VIEW L1 A A2 GAUGE PLANE 0.25 A1 DETAIL X L 0° - 8° 15 FN7623.0 August 17, 2010 ISL28130, ISL28230, ISL28430 Small Outline Package Family (SO) A D N (N/2)+1 h X 45° A E E1 PIN #1 I.D. MARK c SEE DETAIL “X” 1 B (N/2) L1 0.010 M C A B e C H A2 GAUGE PLANE A1 0.004 C 0.010 M C A B b DETAIL X SEATING PLANE L 4° ±4° 0.010 MDP0027 SMALL OUTLINE PACKAGE FAMILY (SO) INCHES SYMBOL A A1 A2 b c D E E1 e L L1 h N NOTES: 1. Plastic or metal protrusions of 0.006” maximum per side are not included. 2. Plastic interlead protrusions of 0.010” maximum per side are not included. 3. Dimensions “D” and “E1” are measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M-1994 SO-8 0.068 0.006 0.057 0.017 0.009 0.193 0.236 0.154 0.050 0.025 0.041 0.013 8 SO-14 0.068 0.006 0.057 0.017 0.009 0.341 0.236 0.154 0.050 0.025 0.041 0.013 14 SO16 (0.150”) 0.068 0.006 0.057 0.017 0.009 0.390 0.236 0.154 0.050 0.025 0.041 0.013 16 SO16 (0.300”) (SOL-16) 0.104 0.007 0.092 0.017 0.011 0.406 0.406 0.295 0.050 0.030 0.056 0.020 16 SO20 (SOL-20) 0.104 0.007 0.092 0.017 0.011 0.504 0.406 0.295 0.050 0.030 0.056 0.020 20 SO24 (SOL-24) 0.104 0.007 0.092 0.017 0.011 0.606 0.406 0.295 0.050 0.030 0.056 0.020 24 SO28 (SOL-28) 0.104 0.007 0.092 0.017 0.011 0.704 0.406 0.295 0.050 0.030 0.056 0.020 28 TOLERANCE MAX ±0.003 ±0.002 ±0.003 ±0.001 ±0.004 ±0.008 ±0.004 Basic ±0.009 Basic Reference Reference NOTES 1, 3 2, 3 Rev. M 2/07 16 FN7623.0 August 17, 2010 ISL28130, ISL28230, ISL28430 Package Outline Drawing M8.15E 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE Rev 0, 08/09 4 4.90 ± 0.10 A DETAIL "A" 0.22 ± 0.03 B 6.0 ± 0.20 3.90 ± 0.10 4 PIN NO.1 ID MARK 5 (0.35) x 45° 1.27 0.43 ± 0.076 0.25 M C A B 4° ± 4° SIDE VIEW “B” TOP VIEW 1.75 MAX 1.45 ± 0.1 0.25 0.175 ± 0.075 GAUGE PLANE C SEATING PLANE 0.10 C SIDE VIEW “A 0.63 ±0.23 DETAIL "A" (1.27) (0.60) NOTES: (1.50) 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. Unless otherwise specified, tolerance : Decimal ± 0.05 Dimension does not include interlead flash or protrusions. Interlead flash or protrusions shall not exceed 0.25mm per side. 5. 6. The pin #1 identifier may be either a mold or mark feature. Reference to JEDEC MS-012. 2. (5.40) 3. 4. TYPICAL RECOMMENDED LAND PATTERN 17 FN7623.0 August 17, 2010