ISL28218FBZ-T7A

DATASHEET ISL28118, ISL28218 FN7532 Rev.8.00 Jan 16, 2020 40V Precision Single-Supply, Rail-to-rail Output, Low-power Operational Amplifiers The ISL28118, ISL28218 are single and dual, low-power precision amplifiers optimized for single-supply applications. These devices feature a common mode input voltage range extending to 0.5V below the V- rail, a rail-to-rail differential input voltage range for use as a comparator and rail-to-rail output voltage swing, which makes them ideal for single-supply applications where input operation at ground is important. Features These op amps feature low power, low offset voltage and low temperature drift, making them the ideal choice for applications requiring both high DC accuracy and AC performance. These amplifiers are designed to operate over a single supply range of 3V to 40V or a split supply voltage range of +1.8V/-1.2V to ±20V. The combination of precision and small footprint provides the user with outstanding value and flexibility relative to similar competitive parts. • Low noise current. . . . . . . . . . . . . . . . . . . . . . . . . . . 355fA/Hz Applications for these amplifiers include precision instrumentation, data acquisition, precision power supply controls and industrial controls. • Rail-to-rail output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300kΩ. The output stage is internally current limited. Output current limit over-temperature is shown in Figures 33 and 34. The amplifiers can withstand a short-circuit to either rail as long as the power dissipation limits are not exceeded. This applies to only one amplifier at a time for the dual op amp. Continuous operation under these conditions may degrade long-term reliability. The amplifiers perform well when driving capacitive loads (Figures 56 and 57). The unity gain, voltage follower (buffer) configuration provides the highest bandwidth but is also the most sensitive to ringing produced by load capacitance found in BNC cables. Unity gain overshoot is limited to 35% at capacitance values to 0.33nF. At gains of 10 and higher, the device is capable of driving more than 10nF without significant overshoot. Output Phase Reversal Output phase reversal is a change of polarity in the amplifier transfer function when the input voltage exceeds the supply voltage. The ISL28118 and ISL28218 are immune to output phase reversal out to 0.5V beyond the rail (VABS MAX) limit (Figure 49). Single Channel Usage The ISL28218 is a dual op amp. If the application requires only one channel, the user must configure the unused channel to prevent it from oscillating. The unused channel oscillates if the input and output pins are floating. This results in higher than expected supply currents and possible noise injection into the channel being used. The proper way to prevent oscillation is to short the output to the inverting input and ground the positive input (Figure 63). + FIGURE 63. PREVENTING OSCILLATIONS IN UNUSED CHANNELS Page 19 of 30 ISL28118, ISL28218 Power Dissipation ISL28118 and ISL28218 SPICE Model It is possible to exceed the +150°C maximum junction temperatures under certain load and power supply conditions. It is therefore important to calculate the maximum junction temperature (TJMAX) for all applications to determine if power supply voltages, load conditions, or package type need to be modified to remain in the safe operating area. These parameters are related using Equation 1: Figure 64 on page 21 shows the SPICE model schematic and Figure 65 on page 22 shows the net list for the SPICE model. The model is a simplified version of the actual device and simulates important AC and DC parameters. AC parameters incorporated into the model are: 1/f and flatband noise voltage, slew rate, CMRR and gain and phase. The DC parameters are IOS, total supply current and output voltage swing. The model uses typical parameters given in the “Electrical Specifications” table beginning on page 5. The AVOL is adjusted for 136dB with the dominant pole at 0.6Hz. The CMRR is set at 120dB, f = 50kHz. The input stage models the actual device to present an accurate AC representation. The model is configured for an ambient temperature of +25°C. T JMAX = T MAX +  JA xPD MAXTOTAL (EQ. 1) Where • PDMAXTOTAL is the sum of the maximum power dissipation of each amplifier in the package (PDMAX) • TMAX = Maximum ambient temperature • JA = Thermal resistance of the package PDMAX for each amplifier can be calculated using Equation 2: V OUTMAX PD MAX = V S  I qMAX +  V S - V OUTMAX   ---------------------------R (EQ. 2) L Where • PDMAX = Maximum power dissipation of 1 amplifier • VS = Total supply voltage • IqMAX = Maximum quiescent supply current of one amplifier • VOUTMAX = Maximum output voltage swing of the application • RL = Load resistance Figures 66 through 80 show the characterization vs simulation results for the noise voltage, open loop gain phase, closed loop gain vs frequency, gain vs frequency vs RL, CMRR, large signal 10V step response, small signal 0.1V step and output voltage swing ±15V supplies. LICENSE STATEMENT The information in the SPICE model is protected under United States copyright laws. Intersil Corporation hereby grants users of this macro-model, hereto referred to as “Licensee”, a nonexclusive, nontransferable licence to use this model, as long as the Licensee abides by the terms of this agreement. Before using this macro-model, the Licensee should read this license. If the Licensee does not accept these terms, permission to use the model is not granted. The Licensee may not sell, loan, rent, or license the macro-model, in whole, in part, or in modified form, to anyone outside the Licensee’s company. The Licensee may modify the macro-model to suit his/her specific applications and the Licensee may make copies of this macro-model for use within their company only. This macro-model is provided “AS IS, WHERE IS AND WITH NO WARRANTY OF ANY KIND EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, ANY IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.” In no event will Intersil be liable for special, collateral, incidental, or consequential damages in connection with, or arising out of, the use of this macro-model. Intersil reserves the right to make changes to the product and the macro-model without prior notice. FN7532 Rev.8.00 Jan 16, 2020 Page 20 of 30 DX I2 54E-6 Vin- 9 Vin+ Q8 CinDif 1.33E-12 5 D14 3 0 750 R1 5e11 DX D5 V3 -0.91 18 +R9 GAIN = 1 1e-3 19 Vg V2 -0.96 15 R4 1k 6 R6 G2 1 GAIN = 0.65897 D4 V-- Input Stage V+ 1st Gain Stage V++ V++ V++ R13 795.7981 L3 3.18319E-09 G9 + GAIN = 1.2566e-3 21 R11 1e-3 Vc 23 D10 D7 DX C3 10e-12 D11 DX G5 + GAIN = 1 GAIN = 1 DX C1 R7 6.6667E-11 3.7304227e9 12 V-- GAIN = 1 L1 3.18319E-09 14 EOS +- + - PNP_LATERAL 11 Cin2 4.02e-12 Cin1 4.02e-12 0 10 PNP_input Q9 PNP_input D2DBREAK R3 1k E2 ++ - - 16 Q6 Q7 8 IOS 4e-9 Vcm En R18 GAIN = 0.3 + GAIN = 1.69138e-3 7 DX R17 2 + - +- 750 DN DN 0 PNP_LATERAL R2 5e11 V8 4 D13 DN V7 -0.91 +- 1 1 GAIN = 0.65897 V1 D1DBREAK 0.1 R5 13 - 0.1 D3 G1 + - I3 54E-6 ISL28118, ISL28218 FN7532 Rev.8.00 Jan 16, 2020 I1 80e-6 V5 24 -0.4 26 R15 80 G13 GAIN = 12.5e-3 Vout VOUT 27 Vmid ISY D8 DX G8 L2 3.18319E-09 GAIN = 1 GAIN = 1 G10 22 L4 3.18319E-09 GAIN = 1.2566e-3 R14 795.7981 V-- Mid Supply ref V D9 V-V- 2nd Gain Stage G11 G12 D12 + + GAIN = 12.5e-3 GAIN = 12.5e-3 DY 20 G6 -0.4 C4 10e-12 DY + - D6 R12 1e-3 + - Page 21 of 30 GAIN = 1.69138e-3 R10 1e-3 + - 17 G4 ++ - GAIN = 0.5 C2 6.6667E-11 3.7304227e9 + - -0.96 V6 25 DX V4 Common Mode Gain Stage with Zero E3 + -+ GAIN = 1 V-- 0 FIGURE 64. SPICE SCHEMATIC Output Stage Correction Current Sources + - 2.5E-3 G14 GAIN = 12.5e-3 R16 80 ISL28118, ISL28218 *ISL28118_218 Macromodel - covers following *products *ISL28118 *ISL28218 * *Revision History: * Revision B, LaFontaine January 22 2014 * Model for Noise, supply currents, CMRR *120dB f = 40kHz, AVOL 136dB f = 0.5Hz * SR = 1.2V/us, GBWP 4MHz. *Copyright 2011 by Intersil Corporation *Refer to data sheet “LICENSE STATEMENT” *Use of this model indicates your acceptance *with the terms and provisions in the License *Statement. * *Intended use: *This Pspice Macromodel is intended to give *typical DC and AC performance characteristics *under a wide range of external circuit *configurations using compatible simulation *platforms – such as iSim PE. * *Device performance features supported by this *model: *Typical, room temp., nominal power supply *voltages used to produce the following *characteristics: *Open and closed loop I/O impedances, *Open loop gain and phase, *Closed loop bandwidth and frequency *response, *Loading effects on closed loop frequency *response, *Input noise terms including 1/f effects, *Slew rate, *Input and Output Headroom limits to I/O *voltage swing, *Supply current at nominal specified supply *voltages, * *Device performance features NOT supported *by this model: *Harmonic distortion effects, *Output current limiting (current will limit at *40mA), *Disable operation (if any), *Thermal effects and/or over-temperature *parameter variation, *Limited performance variation vs. supply *voltage is modeled, *Part to part performance variation due to *normal process parameter spread, *Any performance difference arising from *different packaging, *Load current reflected into the power supply *current. * source ISL28118_218 SPICEmodel * * Connections: +input * | -input * | | +Vsupply * | | | -Vsupply * | | | | output .subckt ISL28118_218 Vin+ Vin-V+ V- VOUT * source ISL28118_218_presubckt_0 * *Voltage Noise E_En VIN+ 6 2 0 0.3 D_D13 1 2 DN D_D14 1 2 DN V_V7 1 0 0.1 V_V8 4 0 0.1 R_R17 2 0 750 *R_R18 3 0 750 * *Input Stage Q_Q6 11 10 9 PNP_input Q_Q7 8 7 9 PNP_input Q_Q8 V-- VIN- 7 PNP_LATERAL Q_Q9 V-- 12 10 PNP_LATERAL I_I1 V++ 9 DC 80e-6 I_I2 V++ 7 DC 54E-6 I_I3 V++ 10 DC 54E-6 I_IOS 6 VIN- DC 4e-9 D_D1 7 10 DBREAK D_D2 10 7 DBREAK R_R1 5 6 5e11 R_R2 VIN- 5 5e11 R_R3 V-- 8 1000 R_R4 V-- 11 1000 C_Cin1 V-- VIN- 4.02e-12 C_Cin2 V-- 6 4.02e-12 C_CinDif 6 VIN- 1.33E-12 * *1st Gain Stage G_G1 V++ 14 8 11 0.65897 G_G2 V-- 14 8 11 0.65897 V_V1 13 14 -0.91 V_V2 14 15 -0.96 D_D3 13 V++ DX D_D4 V-- 15 DX R_R5 14 V++ 1 R_R6 V-- 14 1 * *2nd Gain Stage G_G3 V++ VG 14 VMID 1.69138e-3 G_G4 V-- VG 14 VMID 1.69138e-3 V_V3 16 VG -0.91 V_V4 VG 17 -0.96 D_D5 16 V++ DX D_D6 V-- 17 DX R_R7 VG V++ 3.7304227e9 R_R8 V-- VG 3.7304227e9 C_C1 VG V++ 6.6667E-11 C_C2 V-- VG 6.6667E-11 * *Mid supply Ref E_E2 V++ 0 V+ 0 1 E_E3 V-- 0 V- 0 1 E_E4 VMID V-- V++ V-- 0.5 I_ISY V+ V- DC 0.85E-3 * *Common Mode Gain Stage with Zero G_G5 V++ 19 5 VMID 1 G_G6 V-- 19 5 VMID 1 G_G7 V++ VC 19 VMID 1 G_G8 V-- VC 19 VMID 1 E_EOS 12 6 VC VMID 1 L_L1 18 V++ 3.18319E-09 L_L2 20 V-- 3.18319E-09 L_L3 21 V++ 3.18319E-09 L_L4 22 V-- 3.18319E-09 R_R9 19 18 1e-3 R_R10 20 19 1e-3 R_R11 VC 21 1e-3 R_R12 22 VC 1e-3 * *Pole Stage G_G9 V++ 23 VG VMID 1.2566e-3 G_G10 V-- 23 VG VMID 1.2566e-3 R_R13 23 V++ 795.7981 R_R14 V-- 23 795.7981 C_C3 23 V++ 10e-12 C_C4 V-- 23 10e-12 * *Output Stage with Correction Current Sources G_G11 26 V-- VOUT 23 12.5e-3 G_G12 27 V-- 23 VOUT 12.5e-3 G_G13 VOUT V++ V++ 23 12.5e-3 G_G14 V-- VOUT 23 V-- 12.5e-3 D_D7 23 24 DX D_D8 25 23 DX D_D9 V-- 26 DY D_D10 V++ 26 DX D_D11 V++ 27 DX D_D12 V-- 27 DY V_V5 24 VOUT -0.4 V_V6 VOUT 25 -0.4 R_R15 VOUT V++ 80 R_R16 V-- VOUT 80 .model PNP_LATERAL pnp(is=1e-016 bf=250 va=80 + ik=0.138 rb=0.01 re=0.101 rc=180 kf=0 af=1) .model PNP_input pnp(is=1e-016 bf=100 va=80 + ik=0.138 rb=0.01 re=0.101 rc=180 kf=0 af=1) .model DBREAK D(bv=43 rs=1) .model DN D(KF=6.69e-9 AF=1) .MODEL DX D(IS=1E-12 Rs=0.1) .MODEL DY D(IS=1E-15 BV=50 Rs=1) .ends ISL28118_218 FIGURE 65. SPICE NET LIST FN7532 Rev.8.00 Jan 16, 2020 Page 22 of 30 ISL28118, ISL28218 Characterization vs Simulation Results INPUT NOISE VOLTAGE 10 10 INPUT NOISE CURRENT 1 0.1 0.1 1 10 100 1k FREQUENCY (Hz) 10k 1 100 INPUT NOISE VOLTAGE (nV/√Hz) INPUT NOISE VOLTAGE (nV/√Hz) VS = ±18V INPUT NOISE CURRENT (pA/√Hz) 100 100 0.1 100k 10 1 0.1 0.1 GAIN (dB) GAIN (dB) PHASE GAIN 1 10 100 1k FREQUENCY (Hz) 10 100 1k 10k 100k 1M 10M100M 1G 200 180 160 140 120 100 80 60 40 20 0 -20 -40 -60 VS = ±15V -80 RL = 1MΩ -100 1m 0.01 0.1 FIGURE 68. CHARACTERIZED OPEN-LOOP GAIN, PHASE vs FREQUENCY GAIN (dB) 40 VS = ±5V AND ±15V CL = 4pF RL = 2k VOUT = 100mVP-P 30 20 ACL = 10 10 0 60 Rf = 10kΩ, RG = 100Ω ACL = 100 -10 100 40 30 20 0 Rf = 0, RG = ∞ 1k 10k 100k 1M 10M FREQUENCY (Hz) FIGURE 70. CHARACTERIZED CLOSED-LOOP GAIN vs FREQUENCY FN7532 Rev.8.00 Jan 16, 2020 1 10 100 1k 10k 100k 1M 10M100M 1G Rf = 10kΩ, RG = 10Ω ACL = 1000 Rf = 10kΩ, RG = 100Ω 50 10 Rf = 10kΩ, RG = 1kΩ ACL = 1 GAIN 70 Rf = 10kΩ, RG = 10Ω 50 PHASE FIGURE 69. SIMULATED OPEN-LOOP GAIN, PHASE vs FREQUENCY GAIN (dB) 60 ACL = 1000 100k FREQUENCY (Hz) FREQUENCY (Hz) 70 10k FIGURE 67. SIMULATED INPUT NOISE VOLTAGE FIGURE 66. CHARACTERIZED INPUT NOISE VOLTAGE 200 180 160 140 120 100 80 60 40 20 0 -20 -40 -60 VS = ±15V -80 RL = 1MΩ -100 1m 0.01 0.1 1 VS = ±5V & ±15V CL = 4pF RL = 2k VOUT = 100mVP-P ACL = 100 ACL = 10 RF = 10kΩ, RG = 1kΩ ACL = 1 -10 100 RF = 0, RG = ∞ 1k 10k 100k 1M 10M FREQUENCY (Hz) FIGURE 71. SIMULATED CLOSED-LOOP GAIN vs FREQUENCY Page 23 of 30 ISL28118, ISL28218 (Continued) 1 1 0 0 -1 -1 NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) Characterization vs Simulation Results -2 -3 -4 RL = OPEN, 100k, 10k -5 RL = 1k RL = 499k RL = 100k VS = ±15V -6 CL = 4pF AV = +1 -8 VOUT = 100mVp-p -7 -9 100 1k RL = 49.9k 10k 100k -2 -3 -4 RL = OPEN, 100k, 10k -5 CL = 4pF AV = +1 VOUT = 100mVp-p -7 -8 1M -9 100 10M 1k CMRR (dB) CMRR (dB) 10 100 1k 10k 100k 1M 10M 100M 1G FREQUENCY (Hz) 140 130 120 110 100 90 80 70 60 50 40 30 VS = ±15V 20 SIMULATION 10 0 1m 0.01 0.1 1 6 2 0 0 -2 -2 -4 -4 -6 30 40 50 60 TIME (µs) 70 80 90 100 FIGURE 76. CHARACTERIZED LARGE-SIGNAL 10V STEP RESPONSE FN7532 Rev.8.00 Jan 16, 2020 10 100 1k 10k 100k 1M 10M 100M 1G FREQUENCY (Hz) VS = ±15V AV = 1 RL = 2k CL = 4pF 4 VOUT (V) VOUT (V) VS = ±15V AV = 1 4 RL = 2k CL = 4pF 2 20 10M FIGURE 75. SIMULATED CMRR vs FREQUENCY 6 10 1M FIGURE 73. SIMULATED GAIN vs FREQUENCY vs RL FIGURE 74. CHARACTERIZED CMRR vs FREQUENCY 0 100k FREQUENCY (Hz) FIGURE 72. CHARACTERIZED GAIN vs FREQUENCY vs RL -6 RL = 49.9k 10k FREQUENCY (Hz) 140 130 120 110 100 90 80 70 60 50 40 30 VS = ±15V 20 SIMULATION 10 0 1m 0.01 0.1 1 RL = 1k RL = 499k RL = 100k VS = ±15V -6 0 10 20 30 40 50 60 TIME (µs) 70 80 90 100 FIGURE 77. SIMULATED LARGE-SIGNAL 10V STEP RESPONSE Page 24 of 30 ISL28118, ISL28218 Characterization vs Simulation Results 100 VS = ±15V AND VS = ±5V AV = 1 RL = 2k CL = 4pF 60 VOUT (mV) 40 20 60 40 0 -20 20 0 -20 -40 -40 -60 -60 -80 -80 -100 -100 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 VS = ±15V AND VS = ±5V AV = 1 RL = 2k CL = 4pF 80 VOUT (V) 80 (Continued) 100 2.0 0 0.2 0.4 0.6 TIME (µs) 1.0 1.2 1.4 1.6 1.8 2.0 TIME (µs) FIGURE 78. CHARACTERIZED SMALL-SIGNAL TRANSIENT RESPONSE 20V OUTPUT VOLTAGE SWING (V) 0.8 FIGURE 79. SIMULATED SMALL-SIGNAL TRANSIENT RESPONSE VOH = 14.88V 10V 0V -10V VS = ±15V RL = 10kΩ -20V 0 VOL = -14.93V 0.5 1.0 1.5 2.0 TIME (ms) FIGURE 80. SIMULATED OUTPUT VOLTAGE SWING FN7532 Rev.8.00 Jan 16, 2020 Page 25 of 30 ISL28118, ISL28218 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest Rev. DATE REVISION Jan 16, 2020 FN7532.8 Updated links throughout document. Updated Related Literature section. Updated ordering information table by adding tape and reel information and updating note 1. Updated Figures 38, 39, and 66, changed unit from fA to pA. Removed About Intersil section. Updated disclaimer CHANGE Jul 27, 2015 FN7532.7 Page 1 under Features: Removed bullet 3 (Rail-to-rail input differential voltage range for comparator application). Added to the end of bullet 2 "ground sensing". Jul 15, 2015 FN7532.6 Figures 48 and 78 changed Y-axis from (V) to (mV). May 1, 2014 FN7532.5 Updated Spice model netlist on page 22. Absolute Maximum Ratings table on page 5: Added ESD Tolerance (ISL28118 SOIC package only). Changed POD: FROM M8.118: Corrected lead width dimension in side view 1 from "0.25 - 0.036" to "0.25 - 0.36" To M8.118B: Correct lead dimension in side view 2 from 0.15 - 0.05mm to 0.15+/-0.05mm. Jan 24, 2013 FN7532.4 Added ISL28218 MSOP specifications, and removed references to ISL28118 and ISL28218 TDFN options. page 1: Removed “8 Ld TDFN” from last paragraph of description. page 3: Removed TDFN “Pin Configurations”, and TDFN columns and the “PAD” row from “Pin Descr” table. Moved Ordering Information table from pg 3 to page 2. Removed “Coming Soon” from ISL28218FUZ and added “Note 1” reference, and deleted 2 TDFN offerings in “Ordering Info” table. page 5: Removed TDFN entries from “Thermal Resistance” section, and removed notes 5 and 6. Added delta Vos MSOP row, with limits of ±390µA, and added “ISL28218” to the CMRR MSOP entry. page 6: added “ISL28218” to the existing AVOL MSOP entry. page 7: added new +25°C 28218 MSOP row with 107dB min limit, and added “ISL28218 MSOP” to the existing ISL28118 MSOP full temp row for PSRR. page 7: added “ISL28218” to the existing CMRR SOIC and MSOP rows, and deleted the “ISL28218” rows. page 7: added “ISL28218 MSOP” to the existing ISL28118 MSOP rows for AVOL. page 9: added “+25°C” to “default conditions” info at top of page. Moved “sales Info” from p25 to p23. Removed TDFN package outline drawing. Aug 31, 2011 FN7532.3 Page 7: Electrical Spec Table for Supply Current/Amplifier Change from: 1.4µA Full Temp Max Change to: 1.4mA Full Temp Max Page 28: Updated POD M8.118 to current revision. Corrected lead width dimension in side view 1 from “0.25 - 0.036" to “0.25 - 0.36". May 9, 2011 FN7532.2 Page 2: Added NC pin to Pin Descriptions table. Page 3: Added ISL28218EVAL1Z evaluation board to the Ordering Information table. Page 12: Added new Output Overhead Voltage plots (Figs. 31,32) Pages 19 through 24: Added SPICE model schematic, netlist, description and Figs. 66 through 80. FN7532 Rev.8.00 Jan 16, 2020 Page 26 of 30 ISL28118, ISL28218 The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest Rev. (Continued) DATE REVISION CHANGE Nov 12, 2010 FN7532.1 On page 1: Features Section, added Low input offset voltage and superb offset voltage temperature drift for ISL28118. Updated Intersil trademark statement (bottom of page) On page 4: Removed “coming soon” from ISL28118FBZ. Updated tape & reel note. On page 5: Change ISL28118 Theta JA value from 158 to 165. Added ISL28118 min/max specs to VOS (input offset voltage), TCVOS and min specs to CMRR. On page 6: Added AVOL MIN spec for ISL28118 in dB. Changed existing AVOL spec from V/mV to dB. Added VOL max spec for ISL28118, IS Typ and Max spec for ISL28118. Changed TS from 18µs to 8.5µs. On page 7: Added Min Max VOS spec, TCVOS spec for ISL28118. Changed AVOL specs from V/mV to dB. On page 8: Changed Slew Rate TYP from ±1.2V/µs to ±1V/µs. Added for TS TYP spec = 4µs. Changed min/max note 6 to “Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.” Added Figs 3 & 4 for ISL28118. Figures 5 & 6 moved to page 9. On page 9: Added Figures 7 & 8 On page 11: Added Figures 15 & 16 for ISL28118 On page 11, in Figure 19, changed VS from ±5V to ±15V On page 13 and page 14: Added Figures 27, 28, 31 & 34 for ISL28118 On page 14: Added Figure 35 for ISL28118 On page 15: Figure 41 changed VS from ±18V to ±5V, Figure 42 added RL = 2k, Figure 43 added RL = 10k and corrected "HD+N" to "THD+N" On page 16, Figure 44 added RL = 2k, Figure 45 RL = 10k. On page 18: Added Figure 58 for ISL28118 On page 18, Figure 58 and 59, graph upper left corner changed VS = ±5V to VS = ±15V On page 18, Figure 61, deleted VS = ±5V Sept 16, 2010 FN7532.0 Initial Release FN7532 Rev.8.00 Jan 16, 2020 Page 27 of 30 ISL28118, ISL28218 Package Outline Drawings For the most recent package outline drawing, see M8.15E. M8.15E 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE Rev 0, 08/09 4 4.90 ± 0.10 A DETAIL "A" 0.22 ± 0.03 B 6.0 ± 0.20 3.90 ± 0.10 4 PIN NO.1 ID MARK 5 (0.35) x 45° 4° ± 4° 0.43 ± 0.076 1.27 0.25 M C A B SIDE VIEW “B” TOP VIEW 1.75 MAX 1.45 ± 0.1 0.25 GAUGE PLANE C SEATING PLANE 0.10 C 0.175 ± 0.075 SIDE VIEW “A 0.63 ±0.23 DETAIL "A" (1.27) (0.60) NOTES: (1.50) (5.40) 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal ± 0.05 4. Dimension does not include interlead flash or protrusions. Interlead flash or protrusions shall not exceed 0.25mm per side. 5. The pin #1 identifier may be either a mold or mark feature. 6. Reference to JEDEC MS-012. TYPICAL RECOMMENDED LAND PATTERN FN7532 Rev.8.00 Jan 16, 2020 Page 28 of 30 ISL28118, ISL28218 M8.118B 8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE Rev 1, 3/12 3.0±0.10mm For the most recent package outline drawing, see M8.118B. 5 A D 8 4.9±0.20mm DETAIL "X" 3.0±0.10mm 5 1.10 MAX 0.15±0.05mm PIN# 1 ID SIDE VIEW 2 1 2 B 0.65mm BSC TOP VIEW 0.95 REF 0.86±0.05mm H GAUGE PLANE C 0.25 SEATING PLANE 0.23 - 0.36mm 0.08 M C A-B D 0.10 ± 0.05mm 3°±3° 0.10 C 0.53 ± 0.10mm SIDE VIEW 1 DETAIL "X" (5.80) NOTES: (4.40) (3.00) 1. Dimensions are in millimeters. (0.65) (0.40) (1.40) TYPICAL RECOMMENDED LAND PATTERN FN7532 Rev.8.00 Jan 16, 2020 2. Dimensioning and tolerancing conform to JEDEC MO-187-AA and AMSEY14.5m-1994. 3. Plastic or metal protrusions of 0.15mm max per side are not included. 4. Plastic interlead protrusions of 0.15mm max per side are not included. 5. Dimensions are measured at Datum Plane "H". 6. Dimensions in ( ) are for reference only. Page 29 of 30 1RWLFH  'HVFULSWLRQVRIFLUFXLWVVRIWZDUHDQGRWKHUUHODWHGLQIRUPDWLRQLQWKLVGRFXPHQWDUHSURYLGHGRQO\WRLOOXVWUDWHWKHRSHUDWLRQRIVHPLFRQGXFWRUSURGXFWV DQGDSSOLFDWLRQH[DPSOHV