ISL31480EIRTZ

Fault Protected, Extended CMR, RS-485/RS-422 Transceivers with Cable Invert ISL31480E, ISL31483E, ISL31485E, ISL31486E The ISL3148xE are fault protected, 5V powered differential transceivers that exceed the RS-485 and RS-422 standards for balanced communication. The RS-485 transceiver pins (driver outputs and receiver inputs) are protected against faults up to ±60V. Additionally, the extended common mode range allows these transceivers to operate in environments with common mode voltages up to ±25V (>2X the RS-485 requirement), making this RS-485 family one of the most robust on the market. Transmitters deliver an exceptional 2.5V (typical) differential output voltage into the RS-485 specified 54Ω load. This yields better noise immunity than standard RS-485 ICs, or allows up to six 120Ω terminations in star network topologies. Receiver (Rx) inputs feature a “Full Fail-Safe” design, which ensures a logic high Rx output if Rx inputs are floating, shorted, or on a terminated but undriven (idle) bus. The ISL31483E, ISL31485E and ISL31486E include cable invert functions that reverse the polarity of the Rx and/or Tx bus pins in case the cable is misconnected. Unlike competing devices, Rx full fail-safe operation is maintained even when the Rx input polarity is switched. The ISL31480E and ISL31486E feature a logic supply (VL) pin that sets the VOH of the Rx outputs, and the switching points of the logic input pins, to be compatible with a lower supply voltage (down to 1.8V) in mixed voltage systems. See Table 1 on page 2 for key features and configurations by device number. ISL31480E, ISL31483E, ISL31485E, ISL31486E Features • Fault Protected RS-485 Bus Pins. . . . . . up to ±60V • Extended Common Mode Range . . . . . . . . . . ±25V More Than Twice the Range Required for RS-485 • Cable Invert Pins (Except ISL31480) Corrects for Reversed Cable Connections While Maintaining Rx Full Fail-safe Functionality • Logic Supply (VL) Pin (ISL31480E, ISL31486E) Simplifies Interface to Lower Voltage Logic Devices • Full Fail-safe (Open, Short, Terminated) RS-485 Receivers • 1/4 Unit Load (UL) for up to 128 Devices on the Bus • High Rx IOL for Opto-Couplers in Isolated Designs • Hot Plug Circuitry - Tx and Rx Outputs Remain Three-State During Power-up/Power-down • Slew Rate Limited RS-485 Data Rate . . . . . . 1Mbps • Low Quiescent Supply Current . . . . . . . . . . . 2.3mA Ultra Low Shutdown Supply Current . . . . . . . . 10µA Applications*(see page 19) • Utility Meters/Automated Meter Reading Systems • High Node Count Systems • PROFIBUS® and Field Bus Networks, and Factory Automation • Security Camera Networks • Building Lighting and Environmental Control Systems • Industrial/Process Control Networks Exceptional Rx Operates at 1Mbps Even With ±25V Common Mode Voltage 30 B 25 VOLTAGE (V) 20 15 10 5 RO 0 -5 A VID = ±1V Transceivers Deliver Superior Common Mode Range vs. Standard RS-485 Devices 25 COMMON MODE RANGE 12 0 -7 -12 -20 -25 STANDARD RS-485 CLOSEST TRANSCEIVER COMPETITOR ISL3148XE TIME (400ns/DIV) June 25, 2010 FN7638.0 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2010. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL31480E, ISL31483E, ISL31485E, ISL31486E TABLE 1. SUMMARY OF FEATURES PART NUMBER Coming Soon ISL31480E ISL31483E ISL31485E Coming Soon ISL31486E HALF/FULL DUPLEX Half DATA RATE (Mbps) 1 SLEWRATE LIMITED? Yes EN PINS? Yes HOT PLUG Yes VL PIN? Yes POLARITY LOW REVERSAL QUIESCENT POWER PINS? ICC (mA) SHDN? No 2.3 Yes PIN COUNT 10 Full Half Half 1 1 1 Yes Yes Yes Yes Tx Only Yes Yes Yes Yes No No Yes Yes Yes Yes 2.3 2.3 2.3 Yes No Yes 14 8 10, 12, 14 Ordering Information PART NUMBER (Notes 1, 2, 3) Coming Soon ISL31480EIRTZ Coming Soon ISL31480EIUZ ISL31483EIBZ ISL31485EIBZ Coming Soon ISL31486EIBZ Coming Soon ISL31486EIRTZ Coming Soon ISL31486EIUZ NOTES: 1. Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL31480E, ISL31483E, ISL31485E, and ISL31486E. For more information on MSL please see techbrief TB363. 480E 1480E ISL31483 EIBZ 31485 EIBZ ISL31486 EIBZ 486E 1486E PART MARKING TEMP. RANGE (°C) -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 PACKAGE (Pb-Free) 10 Ld TDFN 10 Ld MSOP 14 Ld SOIC 8 Ld SOIC 14 Ld SOIC 12 Ld TDFN 10 Ld MSOP PKG. DWG. # L10.3x3A M10.118 M14.15 M8.15 M14.15 L12.4x3A M10.118 Pin Configurations ISL31483E (14 LD SOIC) TOP VIEW RINV 1 RO 2 RE 3 DE 4 DI 5 GND 6 GND 7 D R 14 VCC 13 VCC 12 A 11 B 10 Z 9Y 8 DINV RO 1 INV 2 DE 3 DI 4 D ISL31485E (8 LD SOIC) TOP VIEW R 8 VCC 7 B/Z 6 A/Y 5 GND 2 FN7638.0 June 25, 2010 ISL31480E, ISL31483E, ISL31485E, ISL31486E Pin Descriptions PIN ISL31480E ISL31483E ISL31485E NAME PIN # PIN # PIN # RO 2 2 1 ISL31486E ISL31486E ISL31486E (14 LD) (10 LD) (12 LD) PIN # PIN # PIN # 1 1 1 FUNCTION Receiver output. On the ISL31480E, or if INV or RINV is low, then: If A - B ≥ -10mV, RO is high; if A - B ≤ -200mV, RO is low. If INV or RINV is high, then: If B - A ≥ -10mV, RO is high; if B - A ≤ -200mV, RO is low. In all cases, RO = High if A and B are unconnected (floating), or shorted together, or connected to an undriven, terminated bus (i.e., Rx is always failsafe open, shorted, and idle, even if polarity is inverted). Receiver output enable. RO is enabled when RE is low; RO is high impedance when RE is high. Internally pulled low. Driver output enable. The driver outputs, Y and Z, are enabled by bringing DE high, and they are high impedance when DE is low. Internally pulled high (to VL on ISL31480E and ISL31486E; to VCC on other versions). Driver input. On the ISL31480E, or if INV or DINV is low, a low on DI forces output Y low and output Z high, while a high on DI forces output Y high and output Z low. The output states relative to DI invert if INV or DINV is high. Ground connection.This is also the potential of the TDFN EPAD. ±60V Fault Protected RS-485/RS-422 level I/O pin. On the ISL31480E, or if INV is low, A/Y is the non-inverting receiver input and non-inverting driver output. If INV is high, A/Y is the inverting receiver input and the inverting driver output. Pin is an input if DE = 0; pin is an output if DE = 1. ±60V Fault Protected RS-485/RS-422 level I/O pin. On the ISL31480E, or if INV is low, B/Z is the inverting receiver input and inverting driver output. If INV is high, B/Z is the non-inverting receiver input and the noninverting driver output. Pin is an input if DE = 0; pin is an output if DE = 1. ±60V Fault Protected RS-485/RS-422 level input. If RINV is low, then A is the non-inverting receiver input. If RINV is high, then A is the inverting receiver input. RE 4 3 N/A 2 2 2 DE 3 4 3 4 4 4 DI 5 5 4 5 5 6 GND A/Y 6 8 6, 7 N/A 5 6 7, 8 9 6 7 8, 9 11 B/Z 9 N/A 7 10 8 12 A N/A 12 N/A N/A N/A N/A 3 FN7638.0 June 25, 2010 ISL31480E, ISL31483E, ISL31485E, ISL31486E Pin Descriptions (Continued) PIN ISL31480E ISL31483E ISL31485E NAME PIN # PIN # PIN # B N/A 11 N/A ISL31486E ISL31486E ISL31486E (14 LD) (10 LD) (12 LD) PIN # PIN # PIN # N/A N/A N/A FUNCTION ±60V Fault Protected RS-485/RS-422 level input. If RINV is low, then B is the inverting receiver input. If RINV is high, then B is the non-inverting receiver input. ±60V Fault Protected RS-485/RS-422 level output. If DINV is low, then Y is the noninverting driver output. If DINV is high, then Y is the inverting driver output ±60V Fault Protected RS-485/RS-422 level. If DINV is low, then Z is the inverting driver output. If DINV is high, then Z is the non-inverting driver output System power supply input (4.5V to 5.5V). Logic-Level Supply input (1.62V to VCC) which powers all the TTL/CMOS inputs and the RO output (logic pins). VL sets the VIH and VIL levels for logic input pins, and sets the VOH level for the RO pin. Power up this supply after VCC, and keep VL ≤ VCC. To minimize input current, logic input pins that are strapped high externally should connect to VL, but they may be connected to VCC if necessary. Receiver and driver polarity selection input. When driven high this pin swaps the polarity of the driver output and receiver input pins. If unconnected (floating) or connected low, normal RS-485 polarity conventions apply. Internally pulled low. Receiver polarity selection input. When driven high this pin swaps the polarity of the receiver input pins. If unconnected (floating) or connected low, normal RS-485 polarity conventions apply. Internally pulled low. Driver polarity selection input. When driven high this pin swaps the polarity of the driver output pins. If unconnected (floating) or connected low, normal RS-485 polarity conventions apply. Internally pulled low. TDFN exposed thermal pad (EPAD). Connect to GND. No Internal Connection. Y N/A 9 N/A N/A N/A N/A Z N/A 10 N/A N/A N/A N/A VCC VL 10 1 13, 14 N/A 8 N/A 11 12 9 10 13 14 INV N/A N/A 2 3 3 3 RINV N/A 1 N/A N/A N/A N/A DINV N/A 8 N/A N/A N/A N/A PD NC TDFN ONLY 7 N/A N/A N/A N/A EPAD 6 N/A N/A N/A 5, 7, 10 4 FN7638.0 June 25, 2010 ISL31480E, ISL31483E, ISL31485E, ISL31486E Truth Tables TRANSMITTING INPUTS RE X X X X 0 1 DE 1 1 1 1 0 0 DI 1 0 1 0 X X INV or DINV 0 0 1 1 X X OUTPUTS Y 1 0 0 1 High-Z Z 0 1 1 0 High-Z 1 1 0 1 RE 0 0 0 0 0 DE (Half Duplex) 0 0 0 0 0 RECEIVING INPUTS DE (Full Duplex) X X X X X A-B ≥ -0.01V ≤ -0.2V ≤ 0.01V ≥ 0.2V Inputs Open or Shorted X X INV or RINV 0 0 1 1 X OUTPUT RO 1 0 1 0 1 High-Z* High-Z* 0 1 X X High-Z* High-Z NOTE: *Low Power Shutdown Mode (See Note 13), except for ISL31485E. NOTE: *Low Power Shutdown Mode (See Note 13), except for ISL31485E. Typical Operating Circuits ISL31486E HALF DUPLEX EXAMPLE (MSOP PIN NUMBERS SHOWN) +1.8V +5V + 0.1µF 10 VL 3 INV 1 RO 2 RE 4 DE 5 DI D GND 6 THE IC ON THE LEFT HAS THE CABLE CONNECTIONS SWAPPED, SO THE INV PIN IS STRAPPED HIGH TO INVERT ITS RX AND TX POLARITY GND 6 D 9 VCC R A/Y 7 B/Z 8 RT RT + 0.1µF + 0.1µF +5V +1.8V 9 VCC R 10 VL RO 1 RE 2 DE 4 DI 5 3 + 0.1µF 8 B/Z 7 A/Y INV 5 FN7638.0 June 25, 2010 ISL31480E, ISL31483E, ISL31485E, ISL31486E Typical Operating Circuits (Continued) ISL34183E FULL DUPLEX EXAMPLE (SOIC PIN NUMBERS SHOWN) +5V 13, 14 + 0.1µF RT + 0.1µF 9Y 10 Z +5V 13, 14 VCC D DI 5 DE 4 Y9 D GND 6, 7 THE IC ON THE LEFT HAS THE CABLE CONNECTIONS SWAPPED, SO THE INV PINS (1, 8) ARE STRAPPED HIGH TO INVERT ITS RX AND TX POLARITY Z 10 RT RE 3 11 B 12 A GND 6, 7 R RO 2 VCC RINV B 11 2 RO R A 12 3 RE 4 DE 5 DI 8 1 DINV 1 RINV DINV 8 6 FN7638.0 June 25, 2010 ISL31480E, ISL31483E, ISL31485E, ISL31486E Table of Contents Ordering Information ......................................................................................................................... 2 Pin Configuration ................................................................................................................................ 3 Pin Descriptions .................................................................................................................................. 3 Truth Tables ........................................................................................................................................ 6 Typical Operating Circuits.................................................................................................................... 6 Absolute Maximum Ratings ................................................................................................................ 9 Thermal Information .......................................................................................................................... 9 Recommended Operating Conditions .................................................................................................. 9 Electrical Specifications ..................................................................................................................... 9 Test Circuits and Waveforms ............................................................................................................. 12 Application Information .................................................................................................................... 15 Receiver (Rx) Features .................................................................................................................... Driver (Tx) Features ........................................................................................................................ High Overvoltage (Fault) Protection Increases Ruggedness ................................................................... Widest Common Mode Voltage (CMV) Tolerance Improves Operating Range............................................ Cable Invert (Polarity Reversal) Function ............................................................................................ Logic Supply (VL Pin)....................................................................................................................... High VOD Improves Noise Immunity and Flexibility.............................................................................. Hot Plug Function ............................................................................................................................ Data Rate, Cables, and Terminations ................................................................................................. Built-In Driver Overload Protection .................................................................................................... Low Power Shutdown Mode .............................................................................................................. 15 15 15 15 15 16 16 17 17 17 17 Typical Performance Curves ............................................................................................................. 18 Die Characteristics ............................................................................................................................ 19 Revision History ................................................................................................................................ 20 Products ............................................................................................................................................ 20 Package Outline Drawing ................................................................................................................. 21 Package Outline Drawing ................................................................................................................. 22 Package Outline Drawing ................................................................................................................. 23 Package Outline Drawing ................................................................................................................. 24 Package Outline Drawing ................................................................................................................. 25 7 FN7638.0 June 25, 2010 ISL31480E, ISL31483E, ISL31485E, ISL31486E Absolute Maximum Ratings VCC to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V Input Voltages DI, INV, RINV, DINV, DE, RE . . . . . . -0.3V to (VCC + 0.3V) Input/Output Voltages A/Y, B/Z, A, B, Y, Z . . . . . . . . . . . . . . . . . . . . . . . . ±60V A/Y, B/Z, A, B, Y, Z (Transient Pulse Through 100Ω, Note 19) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±80V RO (ISL31480E, ISL31486E) . . . . . . . -0.3V to (VL +0.3V) RO (ISL31483E, ISL31485E) . . . . . . -0.3V to (VCC +0.3V) Short Circuit Duration Y, Z . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Indefinite ESD Rating . . . . . . . . . . . . . . . . . . See Specification Table Latch-up per JESD78, Level 2, Class A . . . . . . . . . . +125°C Thermal Information Thermal Resistance (Typical) θJA (°C/W) θJC (°C/W) 8 Ld SOIC Package (Notes 4, 6) . . 116 47 10 Ld MSOP Package (Notes 4, 6) . 135 50 10 Ld TDFN Package (Notes 5, 7) . 58 7 12 Ld TDFN Package (Notes 5, 7) . 35 3 14 Ld SOIC Package (Notes 4, 6). . 88 38 Maximum Junction Temperature (Plastic Package) . +150°C Maximum Storage Temperature Range . . -65°C to +150°C Pb-free Reflow Profile . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Recommended Operating Conditions Supply Voltage (VCC) . . . . . . . . . . . . Logic Supply Voltage (VL) . . . . . . . . . Temperature Range . . . . . . . . . . . . . . Bus Pin Common Mode Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . 5V . . 1.62V to VCC -40°C to +85°C . -25V to +25V CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTE: 4. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 5. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379 for details. 6. For θJC, the “case temp” location is taken at the package top center. 7. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside. Electrical Specifications Test Conditions: VCC = 4.5V to 5.5V, VL = VCC; Unless Otherwise Specified. Typicals are at TEMP MIN (°C) (Note 16) Full RL = 100Ω (RS-422) RL = 54Ω (RS-485) RL = 54Ω (PROFIBUS, VCC ≥ 5V) RL = 21Ω (Six 120Ω terminations for Star Configurations, VCC ≥ 4.75V) Change in Magnitude of Driver Differential VOUT for Complementary Output States Driver Differential VOUT with Common Mode Load (Figure 1B) ΔVOD RL = 54Ω or 100Ω (Figure 1A) Full Full Full Full Full 2.4 1.5 2.0 0.8 - VCC = 5V, TA = +25°C (Note 8). Boldface limits apply over the operating temperature range, -40°C to +85°C. TEST CONDITIONS TYP 3.2 2.5 2.5 1.3 MAX (Note 16) UNITS VCC VCC 0.2 V V V V V V PARAMETER DC CHARACTERISTICS Driver Differential VOUT (No load) Driver Differential VOUT (Loaded, Figure 1A) SYMBOL VOD1 VOD2 VOD3 RL = 60Ω, -7V ≤ VCM ≤ 12V RL = 60Ω, -25V ≤ VCM ≤ 25V (VCC ≥ 4.75V) RL = 21Ω, -15V ≤ VCM ≤ 15V (VCC ≥ 4.75V) Full Full Full Full Full 1.5 1.7 0.8 -1 -2.5 2.1 2.3 1.1 - VCC V V 3 5 V V V Driver Common-Mode VOUT (Figure 1) VOC RL = 54Ω or 100Ω RL = 60Ω or 100Ω, -20V ≤ VCM ≤ 20V 8 FN7638.0 June 25, 2010 ISL31480E, ISL31483E, ISL31485E, ISL31486E Electrical Specifications Test Conditions: VCC = 4.5V to 5.5V, VL = VCC; Unless Otherwise Specified. Typicals are at TEMP MIN (°C) (Note 16) Full VCC = 5V, TA = +25°C (Note 8). Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued) TEST CONDITIONS RL = 54Ω or 100Ω (Figure 1A) TYP MAX (Note 16) UNITS 0.2 V PARAMETER Change in Magnitude of Driver Common-Mode VOUT for Complementary Output States Driver Short-Circuit Current SYMBOL DVOC IOSD IOSD1 IOSD2 VIH1 VIH2 VIH3 VIH4 DE = VCC, -25V ≤ VO ≤ 25V (Note 10) At First Fold-back, 22V ≤ VO ≤ -22V At Second Fold-back, 35V ≤ VO ≤ -35V DE, DI, RE, INV, RINV, DINV DE, DI, RE, INV, (Only ISL31480E, ISL31486E) DE, DI, RE, INV, RINV, DINV DE, DI, RE, INV, (Only ISL31480E, ISL31486E) DI DE, RE, INV, RINV, DINV DE = 0V, VCC = 0V or 5.5V VIN = 12V VIN = -7V VIN = ±25V VIN = ±60V (Note 20) VL = VCC If Applicable 2.7V ≤ VL ≤ 3V 2.3V ≤ VL < 2.7V 1.6V ≤ VL < 2.3V VL = VCC If Applicable 2.7V ≤ VL ≤ 3V 2.3V ≤ VL < 2.7V 1.6V ≤ VL < 2.3V Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full -250 -83 -13 2.5 2 1.7 0.7*VL -1 -15 -200 -800 -6 -100 -500 -3 -100 -500 -3 -200 - 250 83 13 mA mA mA V V V V V V V V µA µA µA µA µA mA µA µA µA mA µA µA µA mA mV Logic Input High Voltage 6 110 -75 ±240 ±0.7 90 -70 ±200 ±0.5 20 -5 ±40 ±0.15 -100 0.8 0.8 0.65 0.3*VL 1 15 250 800 6 125 500 3 200 500 3 -10 Logic Input Low Voltage VIL1 VIL2 VIL3 VIL4 Logic Input Current Input/Output Current (A/Y, B/Z) IIN1 IIN2 Input Current (A, B) (Full Duplex Versions Only) IIN3 VCC = 0V or 5.5V VIN = 12V VIN = -7V VIN = ±25V VIN = ±60V (Note 20) Output Leakage Current (Y, Z) (Full Duplex Versions Only) IOZD RE = 0V, DE = 0V, VCC = 0V or 5.5V VIN = 12V VIN = -7V VIN = ±25V VIN = ±60V (Note 20) Receiver Differential Threshold Voltage Receiver Input Hysteresis Receiver Output High Voltage VTH A-B for ISL31480E or if INV or RINV = 0; B-A if INV or RINV = 1, -25V ≤ VCM ≤ 25V -25V ≤ VCM ≤ 25V VID = -10mV, VL = VCC If Applicable VID = -10mV, Only ISL31480E, ISL31486E IO = -2mA IO = -8mA VL ≥ 2.7V, IO = -1.5mA VL ≥ 2.3V, IO = -1mA VL ≥ 1.6V, IO = -500mA DVTH VOH1 VOH2 VOH3 VOH4 VOH5 25 Full Full Full Full Full VCC - 0.5 2.8 VL-0.3 VL-0.3 VL-0.25 25 4.75 4.2 - mV V V V V V 9 FN7638.0 June 25, 2010 ISL31480E, ISL31483E, ISL31485E, ISL31486E Electrical Specifications Test Conditions: VCC = 4.5V to 5.5V, VL = VCC; Unless Otherwise Specified. Typicals are at TEMP MIN (°C) (Note 16) Full Full Full 15 -1 VCC = 5V, TA = +25°C (Note 8). Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued) TEST CONDITIONS IO = 6mA, VL ≥ 1.6V, VID = -200mV VO = 1V, VL ≥ 1.6V, VID = -200mV 0V ≤ VO ≤ VL (If Applicable) or VCC (Note 19) 0V ≤ VO ≤ VCC, VL = VCC if applicable TYP 0.27 22 0.01 MAX (Note 16) UNITS 0.4 1 V mA µA PARAMETER Receiver Output Low Voltage Receiver Output Low Current Three-State (High Impedance) Receiver Output Current Receiver Short-Circuit Current SUPPLY CURRENT No-Load Supply Current (Note 9) Shutdown Supply Current ESD PERFORMANCE All Pins SYMBOL VOL IOL IOZR IOSR Full ±12 - ±110 mA ICC ISHDN DE = VCC, RE = 0V or VCC, DI = 0V or VCC DE = 0V, RE = VCC, DI = 0V or VCC (Note 19) Human Body Model (Tested per JESD22-A114E) Machine Model (Tested per JESD22-A115-A) Full Full - 2.3 10 4.5 50 mA µA 25 25 - ±2 ±700 - kV V DRIVER SWITCHING CHARACTERISTICS Driver Differential Output Delay Driver Differential Output Skew Driver Differential Rise or Fall Time Maximum Data Rate Driver Enable to Output High Driver Enable to Output Low Driver Disable from Output Low Driver Disable from Output High Time to Shutdown tPLH, tPHL RD = 54Ω, CD = 50pF (Figure 2) tSKEW R D = 5 4 Ω, CD = 50pF (Figure 2) R D = 5 4 Ω, CD = 50pF (Figure 2) No CM Load -25V ≤ VCM ≤ 25V No CM Load -25V ≤ VCM ≤ 25V No CM Load -25V ≤ VCM ≤ 25V Full Full Full Full Full Full Full Full Full Full Full Full Full Full 70 70 1 60 70 4.5 230 4 160 125 350 15 25 300 400 350 300 120 120 600 2000 2000 ns ns ns ns ns ns Mbps ns ns ns ns ns ns ns tR, tF fMAX tZH tZL tLZ tHZ tSHDN CD = 820pF, VL ≥ 1.6V (Figure 4) SW = GND (Figure 3), (Note 11) SW = VCC (Figure 3), (Note 11) SW = VCC (Figure 3) SW = GND (Figure 3) (Notes 13, 19) Driver Enable from tZH(SHDN) SW = GND (Figure 3), Shutdown to Output High (Notes 13, 14, 19) Driver Enable from Shutdown to Output Low Maximum Data Rate tZL(SHDN) SW = VCC (Figure 3), (Notes 13, 14, 19) fMAX -25V ≤ VCM ≤ 25V (Figure 5) -15V ≤ VCM ≤ 15V, VL ≥ 1.6V (Figure 5) Receiver Input to Output Delay tPLH, tPHL -25V ≤ VCM ≤ 25V (Figure 5) RECEIVER SWITCHING CHARACTERISTICS Full Full Full 1 1 15 12 90 150 Mbps Mbps ns 10 FN7638.0 June 25, 2010 ISL31480E, ISL31483E, ISL31485E, ISL31486E Electrical Specifications Test Conditions: VCC = 4.5V to 5.5V, VL = VCC; Unless Otherwise Specified. Typicals are at TEMP MIN (°C) (Note 16) Full Full Full Full Full Full Full Full 60 VCC = 5V, TA = +25°C (Note 8). Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued) TEST CONDITIONS (Figure 5) RL = 1kΩ, CL = 15pF, SW = VCC (Figure 6), (Notes 12, 19) RL = 1kΩ, CL = 15pF, SW = GND (Figure 6), (Notes 12, 19) RL = 1kΩ, CL = 15pF, SW = VCC (Figure 6) (Note 19) RL = 1kΩ, CL = 15pF, SW = GND (Figure 6) (Note 19) (Notes 13, 19) TYP 4 160 MAX (Note 16) UNITS 10 50 50 50 50 600 2000 2000 ns ns ns ns ns ns ns ns PARAMETER Receiver Skew | tPLH tPHL | Receiver Enable to Output Low Receiver Enable to Output High Receiver Disable from Output Low Receiver Disable from Output High Time to Shutdown SYMBOL tSKD tZL tZH tLZ tHZ tSHDN Receiver Enable from tZH(SHDN) RL = 1kΩ, CL = 15pF, SW = GND (Figure 6), (Notes 13, 15, 19) Shutdown to Output High Receiver Enable from Shutdown to Output Low NOTES: tZL(SHDN) RL = 1kΩ, CL = 15pF, SW = VCC (Figure 6), (Notes 13, 15, 19) 8. All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground unless otherwise specified. 9. Supply current specification is valid for loaded drivers when DE = 0V. 10. Applies to peak current. See “Typical Performance Curves” beginning on page 18 for more information 11. Keep RE = 0 to prevent the device from entering SHDN. 12. The RE signal high time must be short enough (typically 600ns to ensure that the device enters SHDN. 15. Set the RE signal high time >600ns to ensure that the device enters SHDN. 16. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. 17. See Figure 9 for more information, and for performance over-temperature. 18. Tested according to TIA/EIA-485-A, Section 4.2.6 (±80V for 15ms at a 1% duty cycle). 19. Does not apply to the ISL31485E. The ISL31485E has no Rx enable function, and thus no SHDN function. 20. See “Caution” statement in the “Recommended Operating Conditions” section on page 9. Test Circuits and Waveforms RL/2 Z D Y RL/2 VOC VOD RL/2 Z D Y VOD VOC RL/2 375Ω 375Ω VCM VL OR VCC DE DI VL OR VCC DE DI FIGURE 1A. VOD AND VOC FIGURE 1. DC DRIVER TEST CIRCUITS FIGURE 1B. 1B 11 FN7638.0 June 25, 2010 ISL31480E, ISL31483E, ISL31485E, ISL31486E Test Circuits and Waveforms (Continued) DI 50% 50% LOWER OF 3V OR VL 0V tPLH OUT (Z) Z D Y SIGNAL GENERATOR CD RD 375Ω* VCM OUT (Y) VOL tPHL VOH VL OR VCC DE DI 375Ω* *ONLY USED FOR COMMON MODE LOAD TESTS DIFF OUT (Y - Z) 90% 10% tR SKEW = |tPLH - tPHL| 90% 10% tF +VOD -VOD FIGURE 2A. TEST CIRCUIT FIGURE 2B. MEASUREMENT POINTS FIGURE 2. DRIVER PROPAGATION DELAY AND DIFFERENTIAL TRANSITION TIMES DE DI SIGNAL GENERATOR Z D Y CL SW 110Ω VCC GND DE NOTE 13 50% 50% LOWER OF 3V OR VL 0V tZH, tZH(SHDN) NOTE 13 PARAMETER tHZ tLZ tZH tZL tZH(SHDN) tZL(SHDN) OUTPUT Y/Z Y/Z Y/Z Y/Z Y/Z Y/Z RE X X 0 (Note 12) 0 (Note 12) 1 (Note 15) 1 (Note 15) DI 1/0 0/1 1/0 0/1 1/0 0/1 SW GND VCC GND VCC GND VCC CL (pF) 50 50 100 100 100 100 tZL, tZL(SHDN) NOTE 13 OUT (Y, Z) OUT (Y, Z) tHZ OUTPUT HIGH 2.3V VOH - 0.5V VOH 0V tLZ VCC 2.3V OUTPUT LOW VOL + 0.5V V OL FIGURE 3A. TEST CIRCUIT FIGURE 3B. MEASUREMENT POINTS FIGURE 3. DRIVER ENABLE AND DISABLE TIMES LOWER OF 3V OR VL 0V VL OR VCC DE DI D Y Z 54Ω CD + DI VOD - SIGNAL GENERATOR DIFF OUT (Y - Z) +VOD -VOD 0V FIGURE 4A. TEST CIRCUIT FIGURE 4B. MEASUREMENT POINTS FIGURE 4. DRIVER DATA RATE 12 FN7638.0 June 25, 2010 ISL31480E, ISL31483E, ISL31485E, ISL31486E Test Circuits and Waveforms (Continued) RE B A SIGNAL GENERATOR VCM R RO 15pF B VCM A tPLH RO 50% tPHL VCM VCM + 750mV VCM - 750mV SIGNAL GENERATOR VCC OR VL 50% 0V FIGURE 5A. TEST CIRCUIT FIGURE 5B. MEASUREMENT POINTS FIGURE 5. RECEIVER PROPAGATION DELAY AND DATA RATE RE B A SIGNAL GENERATOR R RO 1kΩ 15pF SW VL OR VCC GND RE NOTE 13 50% 50% LOWER OF 3V OR VL 0V PARAMETER tHZ tLZ tZH (Note 12) tZL (Note 12) tZH(SHDN) (Note 16) tZL(SHDN) (Note 16) DE 0 0 0 0 0 0 A +1.5V -1.5V +1.5V -1.5V +1.5V -1.5V SW GND VL / VCC GND VL / VCC GND VL / VCC tZH, tZH(SHDN) NOTE 13 RO tHZ OUTPUT HIGH 1.5V VOH - 0.5V VOH 0V tZL, tZL(SHDN) NOTE 13 RO 1.5V tLZ VL OR VCC VOL + 0.5V VOL OUTPUT LOW FIGURE 6A. TEST CIRCUIT FIGURE 6B. MEASUREMENT POINTS FIGURE 6. RECEIVER ENABLE AND DISABLE TIMES 13 FN7638.0 June 25, 2010 ISL31480E, ISL31483E, ISL31485E, ISL31486E Application Information RS-485 and RS-422 are differential (balanced) data transmission standards used for long haul or noisy environments. RS-422 is a subset of RS-485, so RS-485 transceivers are also RS-422 compliant. RS-422 is a point-to-multipoint (multidrop) standard, which allows only one driver and up to 10 (assuming one unit load devices) receivers on each bus. RS-485 is a true multipoint standard, which allows up to 32 one unit load devices (any combination of drivers and receivers) on each bus. To allow for multipoint operation, the RS-485 specification requires that drivers must handle bus contention without sustaining any damage. Another important advantage of RS-485 is the extended common mode range (CMR), which specifies that the driver outputs and receiver inputs withstand signals that range from +12V to -7V. RS-422 and RS-485 are intended for runs as long as 4000’, so the wide CMR is necessary to handle ground potential differences, as well as voltages induced in the cable by external fields. The ISL3148xE is a family of ruggedized RS-485 transceivers that improves on the RS-485 basic requirements, and therefore increases system reliability. The CMR increases to ±25V, while the RS-485 bus pins (receiver inputs and driver outputs) include fault protection against voltages and transients up to ±60V. Additionally, larger than required differential output voltages (VOD) increase noise immunity. Driver (Tx) Features The RS-485/RS-422 driver is a differential output device that delivers at least 1.5V across a 54Ω load (RS-485), and at least 2.4V across a 100Ω load (RS-422). The drivers feature low propagation delay skew to maximize bit width, and to minimize EMI, and all drivers are threestatable via the active high DE input. The driver outputs are slew rate limited to minimize EMI, and to minimize reflections in unterminated or improperly terminated networks. High Overvoltage (Fault) Protection Increases Ruggedness Note: The available smaller pitch packages (e.g., MSOP and TDFN) may not meet the creepage and clearance (C&C) requirements for ±60V levels. The user is advised to determine his C&C requirements before selecting a package type. The ±60V (referenced to the IC GND) fault protection on the RS-485 pins, makes these transceivers some of the most rugged on the market. This level of protection makes the ISL3148xE perfect for applications where power (e.g., 24V and 48V supplies) must be routed in the conduit with the data lines, or for outdoor applications where large transients are likely to occur. When power is routed with the data lines, even a momentary short between the supply and data lines will destroy an unprotected device. The ±60V fault levels of this family are at least five times higher than the levels specified for standard RS-485 ICs. The ISL3148xE protection is active whether the Tx is enabled or disabled, and even if the IC is powered down. If transients or voltages (including overshoots and ringing) greater then ±60V are possible, then additional external protection is required. Receiver (Rx) Features These devices utilize a differential input receiver for maximum noise immunity and common mode rejection. Input sensitivity is better than ±200mV, as required by the RS-422 and RS-485 specifications. Receiver input (load) current surpasses the RS-422 specification of 3mA, and is four times lower than the RS-485 “Unit Load (UL)” requirement of 1mA maximum. Thus, these products are known as “one-quarter UL” transceivers, and there can be up to 128 of these devices on a network while still complying with the RS-485 loading specification. The Rx functions with common mode voltages as great as ±25V, making them ideal for industrial, or long networks where induced voltages are a realistic concern. All the receivers include a “full fail-safe” function that guarantees a high level receiver output if the receiver inputs are unconnected (floating), shorted together, or connected to a terminated bus with all the transmitters disabled (i.e., an idle bus). Rx outputs feature high drive levels (typically 22mA @ VOL = 1V) to ease the design of optically coupled isolated interfaces. Except for the ISL31485E, Rx outputs are three-statable via the active low RE input. The Rx includes noise filtering circuitry to reject high frequency signals, and typically rejects pulses narrower than 50ns (equivalent to 20Mbps). Widest Common Mode Voltage (CMV) Tolerance Improves Operating Range RS-485 networks operating in industrial complexes, or over long distances, are susceptible to large CMV variations. Either of these operating environments may suffer from large node-to-node ground potential differences, or CMV pickup from external electromagnetic sources, and devices with only the minimum required +12V to -7V CMR may malfunction. The ISL3148xE’s extended ±25V CMR is the widest available, allowing operation in environments that would overwhelm lesser transceivers. Additionally, the Rx will not phase invert (erroneously change state) even with CMVs of ±40V, or differential voltages as large as 40V. Cable Invert (Polarity Reversal) Function With large node count RS-485 networks, it is common for some cable data lines to be wired backwards during installation. When this happens the node is unable to communicate over the network. Once a technician finds the miswired node, he must then rewire the connector which is time consuming. 14 FN7638.0 June 25, 2010 ISL31480E, ISL31483E, ISL31485E, ISL31486E The ISL31483E, ISL31485E, and ISL31486E simplify this task by including cable invert pins (INV, DINV, RINV) that allow the technician to invert the polarity of the Rx input and/or the Tx output pins simply by moving a jumper to change the state of the invert pin(s). When the invert pin(s) is low, the IC operates like any standard RS-485 transceiver and the bus pins have their normal polarity definition of A and Y being noninverting, and B and Z being inverting. With the invert pin high, the corresponding bus pins reverse their polarity, so B and Z are now noninverting and A and Y become inverting. Intersil’s unique cable invert function is superior to that found on competing devices because the Rx full failsafe function is maintained even when the Rx polarity is reversed. Competitor devices implement the Rx invert function simply by inverting the Rx output. This means that with the Rx inputs floating or shorted together, the Rx appropriately delivers a logic 1 in normal polarity, but outputs a logic low when the IC is operated in the inverted mode. Intersil’s innovative Rx design guarantees that with the Rx inputs floating, or shorted together (VID=0V), the Rx output remains high regardless of the state of the invert pins. The full duplex ISL31483E includes two invert pins that allow for separate control of the Rx and Tx polarities. If only the Rx cable is miswired, then only the RINV pin need be driven to a logic 1. If the Tx cable is miswired, then DINV must be connected to a logic high. The two half duplex versions have only one logic pin (INV) that, when high, switches the polarity of both the Tx and the Rx blocks. VCC = +5V VCC = +1.8V RO DI GND VOH = 5V VIH ≥ 2V VOH ≈ 1.8V RXD ESD DIODE TXD GND ISL31483E VCC = +5V UART/PROCESSOR VCC = +1.8V VL RO DI GND VOH = 1.8V VIH = 1.1V VOH ≈ 1.8V RXD TXD ESD DIODE GND ISL31480E UART/PROCESSOR FIGURE 7. USING VL PIN TO ADJUST LOGIC LEVELS TABLE 2. VIH AND VIL vs. VL FOR VCC = 5V VL (V) 1.6 1.8 2.3 2.7 3.3 VIH (V) 1.0 1.1 1.3 1.4 1.6 VIL (V) 0.6 0.7 0.9 1.1 1.3 Logic Supply (VL Pin) Note: Power up VCC before powering up the VL supply, and keep VL ≤ VCC. The ISL31480E and ISL31486E include a VL pin that powers the logic inputs (Tx input and control pins) and the Rx output. These pins interface with “logic” devices such as UARTs, ASICs, and µcontrollers, and today many of these devices use power supplies significantly lower than 5V. Thus, a 5V output level from this transceiver IC might seriously overdrive and damage the logic device input (see Figure 7). Similarly, the logic device’s low VOH might not exceed the VIH of a 5V powered transceiver input. Connecting the VL pin to the power supply of the logic device - as shown in Figure 7 - limits the ISL3148xE’s RO pin VOH to the VL voltage, and reduces the Tx and control input switching points to values compatible with the logic device output levels. Tailoring the logic pin input switching points and output levels to the supply voltage of the UART, ASIC, or µcontroller eliminates the need for a level shifter/translator between the two ICs. VL can be anywhere from VCC down to 1.62V, and the transceivers easily operate at the 1Mbps data rate over this range as long as the VCM doesn’t exceed ±15V. Table 2 indicates typical VIH and VIL values for various VL voltages so the user can ascertain whether or not a particular VL voltage meets his/her needs. The VL supply current (IL) is typically less than 6µA. All of the DC VL current is due to current through the DE input internal pull-up resistor when the pin is driven to the low input state. Transceiver logic inputs that are externally tied high in an application should use the VL supply for the high voltage level to minimize input currents. Except for DI, all logic inputs have 800kΩ pull-up (DE) or pull-down (all other pins) resistors, so connecting an input to the lower voltage VL supply minimizes current. The DE pull-up internally connects to VL, so connecting the DE pin to VCC induces an input current of (VCC - VL)/800kΩ. High VOD Improves Noise Immunity and Flexibility The ISL3148xE driver design delivers larger differential output voltages (VOD) than the RS-485 standard requires, or than most RS-485 transmitters can deliver. The typical ±2.5V VOD provides more noise immunity than networks built using many other transceivers. Another advantage of the large VOD is the ability to drive more than two bus terminations, which allows for 15 FN7638.0 June 25, 2010 ISL31480E, ISL31483E, ISL31485E, ISL31486E utilizing the ISL3148xE in “star” and other multi-terminated, nonstandard network topologies. Figure 9, details the transmitter’s VOD vs IOUT characteristic, and includes load lines for four (30Ω) and six (20Ω) 120Ω terminations. The figure shows that the driver typically delivers ±1.3V into six terminations, and the “Electrical Specification” table guarantees a VOD of ±0.8V at 21Ω over the full temperature range. The RS-485 standard requires a minimum 1.5V VOD into two terminations, but the ISL3148xE deliver RS-485 voltage levels with 2x to 3x the number of terminations. Twisted pair is the cable of choice for RS-485/RS-422 networks. Twisted pair cables tend to pick up noise and other electromagnetically induced voltages as common mode signals, which are effectively rejected by the differential receivers in these ICs. Proper termination is imperative to minimize reflections, and terminations are recommended unless power dissipation is an overriding concern. In point-to-point, or point-tomultipoint (single driver on bus like RS-422) networks, the main cable should be terminated in its characteristic impedance (typically 120Ω) at the end farthest from the driver. In multi-receiver applications, stubs connecting receivers to the main cable should be kept as short as possible. Multipoint (multi-driver) systems require that the main cable be terminated in its characteristic impedance at both ends. Stubs connecting a transceiver to the main cable should be kept as short as possible. Hot Plug Function When a piece of equipment powers up, there is a period of time where the processor or ASIC driving the RS-485 control lines (DE, RE) is unable to ensure that the RS-485 Tx and Rx outputs are kept disabled. If the equipment is connected to the bus, a driver activating prematurely during power-up may crash the bus. To avoid this scenario, the ISL3148xE devices incorporate a “Hot Plug” function. Circuitry monitoring VCC ensures that, during power-up and power-down, the Tx and Rx outputs remain disabled, regardless of the state of DE and RE, if VCC is less than ≈3.5V. This gives the processor/ASIC a chance to stabilize and drive the RS-485 control lines to the proper states. Figure 8 illustrates the power-up and power-down performance of the ISL3148xE compared to an RS-485 IC without the Hot Plug feature. VCC (V) DE, DI = VCC RE = GND 3.5V DRIVER Y OUTPUT (V) VCC 5.0 2.5 0 A/Y ISL3148XE 2.8V Built-In Driver Overload Protection As stated previously, the RS-485 specification requires that drivers survive worst case bus contentions undamaged. These transceivers meet this requirement via driver output short circuit current limits, and on-chip thermal shutdown circuitry. The driver output stages incorporate a double foldback short circuit current limiting scheme which ensures that the output current never exceeds the RS-485 specification, even at the common mode and fault condition voltage range extremes. The first foldback current level (≈70mA) is set to ensure that the driver never folds back when driving loads with common mode voltages up to ±25V. The very low second foldback current setting (≈9mA) minimizes power dissipation if the Tx is enabled when a fault occurs. In the event of a major short circuit condition, devices also include a thermal shutdown feature that disables the drivers whenever the die temperature becomes excessive. This eliminates the power dissipation, allowing the die to cool. The drivers automatically re-enable after the die temperature drops about 15°C. If the contention persists, the thermal shutdown/reenable cycle repeats until the fault is cleared. Receivers stay operational during thermal shutdown. 5.0 2.5 0 RL = 1kΩ RECEIVER OUTPUT (V) RL = 1kΩ RO ISL3148XE 5.0 2.5 0 TIME (40µs/DIV) Low Power Shutdown Mode These CMOS transceivers all use a fraction of the power required by competitive devices, but they also include a shutdown feature (except the ISL31485E) that reduces the already low quiescent ICC to a 10µA trickle. These devices enter shutdown whenever the receiver and driver are simultaneously disabled (RE = VCC and DE = GND) for a period of at least 600ns. Disabling both the driver and the receiver for less than 60ns guarantees that the transceiver will not enter shutdown. Note that receiver and driver enable times increase when the transceiver enables from shutdown. Refer to Notes 11, 12, 13, 14 and 15, at the end of the “Electrical Specification” table on page 11, for more information. FIGURE 8. HOT PLUG PERFORMANCE (ISL3148XE) vs ISL83088E WITHOUT HOT PLUG CIRCUITRY Data Rate, Cables, and Terminations RS-485/RS-422 are intended for network lengths up to 4000’, but the maximum system data rate decreases as the transmission length increases. These 1Mbps versions can operate at full data rates with lengths up to 800’ (244m). Jitter is the limiting parameter at this data rate, so employing encoded data streams (e.g., Manchester coded or Return-to-Zero) may allow increased transmission distances. 16 FN7638.0 June 25, 2010 ISL31480E, ISL31483E, ISL31485E, ISL31486E Typical Performance Curves 90 DRIVER OUTPUT CURRENT (mA) 80 70 60 50 40 30 20 10 0 0 1 2 3 4 DIFFERENTIAL OUTPUT VOLTAGE (V) +85°C RD = 20Ω +25°C RD = 54Ω RD = 30Ω VCC = 5V, TA = +25°C; Unless Otherwise Specified. DIFFERENTIAL OUTPUT VOLTAGE (V) 3.6 3.4 RD = 100Ω 3.2 3.0 2.8 2.6 RD = 54Ω 2.4 2.2 -40 RD = 100Ω 5 -25 0 25 50 TEMPERATURE (°C) 75 85 FIGURE 9. DRIVER OUTPUT CURRENT vs DIFFERENTIAL OUTPUT VOLTAGE FIGURE 10. DRIVER DIFFERENTIAL OUTPUT VOLTAGE vs TEMPERATURE 2.45 2.40 2.35 2.30 ICC (mA) 2.25 2.20 2.15 2.10 2.05 2.00 -40 -25 0 25 50 TEMPERATURE (°C) 75 85 DE = GND, RE = GND DE = VCC, RE = X FIGURE 11. SUPPLY CURRENT vs TEMPERATURE 70 RECEIVER OUTPUT CURRENT (mA) 60 50 40 30 20 10 0 -10 -20 -30 0 1 2 3 4 RECEIVER OUTPUT VOLTAGE (V) 5 VOH, +85°C VOH, +25°C VOL, +25°C VOL, +85°C BUS PIN CURRENT (µA) 800 600 400 200 0 -200 -400 A/Y or B/Z -600 -70 -50 -30 -10 0 10 30 50 70 Y or Z BUS PIN VOLTAGE (V) FIGURE 12. RECEIVER OUTPUT CURRENT vs RECEIVER OUTPUT VOLTAGE FIGURE 13. BUS PIN CURRENT vs BUS PIN VOLTAGE 17 FN7638.0 June 25, 2010 ISL31480E, ISL31483E, ISL31485E, ISL31486E Typical Performance Curves 85 80 75 70 65 tPHL 60 55 RD = 54Ω, CD = 50pF VCC = 5V, TA = +25°C; Unless Otherwise Specified. (Continued) 4.0 RD = 54Ω, CD = 50pF PROPAGATION DELAY (ns) 3.5 tPLH SKEW (ns) 3.0 2.5 |tPLH - tPHL| 50 -40 -25 0 50 25 TEMPERATURE (°C) 75 85 2.0 -40 -25 0 50 25 TEMPERATURE (°C) 75 85 FIGURE 14. DRIVER DIFFERENTIAL PROPAGATION DELAY vs TEMPERATURE A B VID = ±1V FIGURE 15. DRIVER DIFFERENTIAL SKEW vs TEMPERATURE DRIVER OUTPUT (V) RECEIVER OUTPUT (V) DRIVER INPUT (V) VOLTAGE (V) 25 20 15 10 5 0 RD = 54Ω, CD = 50pF DI 5 0 5 0 RO RO 5 0 -5 -10 -15 -20 -25 RO A B TIME (400ns/DIV) 3 2 1 0 -1 -2 -3 A/Y - B/Z TIME (400ns/DIV) FIGURE 16. ±25V RECEIVER PERFORMANCE FIGURE 17. DRIVER AND RECEIVER WAVEFORMS Die Characteristics SUBSTRATE POTENTIAL (POWERED UP) AND TDFN EPAD: GND PROCESS: Si Gate BiCMOS 18 FN7638.0 June 25, 2010 ISL31480E, ISL31483E, ISL31485E, ISL31486E Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest Rev. DATE 06/25/10 REVISION FN7638.0 Initial Release CHANGE Products Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a complete list of Intersil product families. *For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on intersil.com: ISL31480E, ISL31483E, ISL31485E, ISL31486E To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff FITs are available from our website at http://rel.intersil.com/reports/search.php 19 FN7638.0 June 25, 2010 ISL31480E, ISL31483E, ISL31485E, ISL31486E Mini Small Outline Plastic Packages (MSOP) N M10.118 (JEDEC MO-187BA) 10 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE E1 -B12 TOP VIEW 0.25 (0.010) GAUGE PLANE SEATING PLANE -CL L1 4X θ R1 R 0.20 (0.008) ABC E INCHES SYMBOL A A1 A2 b c D 4X θ MILLIMETERS MIN 0.94 0.05 0.75 0.18 0.09 2.95 2.95 MAX 1.10 0.15 0.95 0.27 0.20 3.05 3.05 NOTES 9 3 4 6 7 15o 6o Rev. 0 12/02 MIN 0.037 0.002 0.030 0.007 0.004 0.116 0.116 MAX 0.043 0.006 0.037 0.011 0.008 0.120 0.120 INDEX AREA E1 e E A A2 0.020 BSC 0.187 0.016 0.199 0.028 0.50 BSC 4.75 0.40 5.05 0.70 A1 -He D b 0.10 (0.004) -A0.20 (0.008) C SEATING PLANE L L1 N 0.037 REF 10 0.003 0.003 5o 0o 15o 6o 0.95 REF 10 0.07 0.07 5o 0o C a C L E1 C R R1 θ -B- SIDE VIEW α 0.20 (0.008) CD END VIEW NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-187BA. 2. Dimensioning and tolerancing per ANSI Y14.5M-1994. 3. Dimension “D” does not include mold flash, protrusions or gate burrs and are measured at Datum Plane. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E1” does not include interlead flash or protrusions and are measured at Datum Plane. - H - Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. Formed leads shall be planar with respect to one another within 0.10mm (.004) at seating Plane. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Datums -A -H- . and - B to be determined at Datum plane 11. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only 20 FN7638.0 June 25, 2010 ISL31480E, ISL31483E, ISL31485E, ISL31486E Package Outline Drawing L10.3x3A 10 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE Rev 5, 3/10 3.00 A 6 PIN 1 INDEX AREA 6 PIN 1 INDEX AREA 1 2.0 REF 8X 0.50 BSC 5 10X 0 . 30 B 3.00 1.50 0.15 (4X) 10 5 0.10 M C A B 0.05 M C 4 10 X 0.25 TOP VIEW 2.30 ( 2.30 ) BOTTOM VIEW 0 .80 MAX SEE DETAIL "X" 0.10 C C (2.90) (1.50) SIDE VIEW (10 X 0.50) SEATING PLANE 0.08 C 5 0 . 2 REF ( 8X 0 .50 ) ( 10X 0.25 ) TYPICAL RECOMMENDED LAND PATTERN 0 . 00 MIN. 0 . 05 MAX. DETAIL "X" NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. Dimensioning and tolerancing conform to ASME Y14.5m-1994. Unless otherwise specified, tolerance : Decimal ± 0.05 Angular ±2.50° Dimension applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. 6. Tiebar shown (if present) is a non-functional feature. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Compliant to JEDEC MO-229-WEED-3 except exposed pad length (2.30mm). C 2. 3. 4. 21 FN7638.0 June 25, 2010 ISL31480E, ISL31483E, ISL31485E, ISL31486E Thin Dual Flat No-Lead Plastic Package (TDFN) L12.4x3A 2X 0.15 C A A D 2X 0.15 C B 12 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-229-WGED-4 ISSUE C) MILLIMETERS SYMBOL A A1 MIN 0.70 NOMINAL 0.75 0.20 REF 0.18 0.23 4.00 BSC 3.15 3.30 3.00 BSC 1.55 1.70 0.50 BSC 0.20 0.30 0.40 12 6 0.50 1.80 3.40 0.30 MAX 0.80 0.05 NOTES 5,8 7,8 7,8 8 2 3 Rev. 0 1/06 NOTES: E 6 INDEX AREA TOP VIEW B A3 b D D2 E E2 // 0.10 0.08 C C e k A L N Nd SIDE VIEW C SEATING PLANE D2 (DATUM B) 1 2 D2/2 A3 7 8 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd refers to the number of terminals on D. 4. All dimensions are in millimeters. Angles are in degrees. NX k 6 INDEX AREA (DATUM A) 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. E2 E2/2 NX L N 8 N-1 NX b e (Nd-1)Xe REF. BOTTOM VIEW (A1) L e SECTION "C-C" TERMINAL TIP FOR EVEN TERMINAL/SIDE 5 0.10 M CAB C L NX (b) 5 22 FN7638.0 June 25, 2010 ISL31480E, ISL31483E, ISL31485E, ISL31486E Package Outline Drawing M14.15 14 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE Rev 1, 10/09 4 8.65 A3 14 6 8 0.10 C A-B 2X DETAIL"A" D 0.22±0.03 6.0 3.9 4 0.10 C D 2X PIN NO.1 ID MARK 5 0.31-0.51 0.25 M C A-B D TOP VIEW B3 6 7 0.20 C 2X (0.35) x 45° 4° ± 4° 0.10 C 1.75 MAX 1.25 MIN H 0.25 GAUGE PLANE C SEATING PLANE 0.10 C DETAIL "A" 1.27 SIDE VIEW 0.10-0.25 (1.27) (0.6) NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSEY14.5m-1994. 3. Datums A and B to be determined at Datum H. (5.40) 4. Dimension does not include interlead flash or protrusions. Interlead flash or protrusions shall not exceed 0.25mm per side. 5. The pin #1 indentifier may be either a mold or mark feature. (1.50) 6. Does not include dambar protrusion. Allowable dambar protrusion shall be 0.10mm total in excess of lead width at maximum condition. 7. Reference to JEDEC MS-012-AB. TYPICAL RECOMMENDED LAND PATTERN 23 FN7638.0 June 25, 2010 ISL31480E, ISL31483E, ISL31485E, ISL31486E Small Outline Plastic Packages (SOIC) N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45° H 0.25(0.010) M BM M8.15 (JEDEC MS-012-AA ISSUE C) 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A A1 L MILLIMETERS MIN 1.35 0.10 0.33 0.19 4.80 3.80 MAX 1.75 0.25 0.51 0.25 5.00 4.00 NOTES 9 3 4 5 6 7 8° Rev. 1 6/05 MIN 0.0532 0.0040 0.013 0.0075 0.1890 0.1497 MAX 0.0688 0.0098 0.020 0.0098 0.1968 0.1574 B C D E α A1 0.10(0.004) C e H h L N 0.050 BSC 0.2284 0.0099 0.016 8 0° 8° 0.2440 0.0196 0.050 1.27 BSC 5.80 0.25 0.40 8 0° 6.20 0.50 1.27 e B 0.25(0.010) M C AM BS NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. α For additional products, see www.intersil.com/product_tree Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 24 FN7638.0 June 25, 2010