ISL3284E

® ISL3280E, ISL3281E, ISL3282E, ISL3283E, ISL3284E, ISL3285E Data Sheet October 18, 2007 FN6543.2 ±16.5kV ESD Protected, +125°C, 3.0V to 5.5V, SOT-23/TDFN Packaged, 20Mbps, Full Fail-safe, Low Power, RS-485/RS-422 Receivers The Intersil ISL3280E, ISL3281E, ISL3282E, ISL3283E, ISL3284E, ISL3285E are ±16.5kV IEC61000 ESD Protected, 3.0V to 5.5V powered, single receivers that meet both the RS-485 and RS-422 standards for balanced communication. These receivers have very low bus currents (+125µA/-100µA), so they present a true “1/8 unit load” to the RS-485 bus. This allows up to 256 receivers on the network without violating the RS-485 specification’s 32 unit load maximum and without using repeaters. Receiver inputs feature a “Full Fail-Safe” design, which ensures a logic high Rx output if Rx inputs are floating, shorted, or terminated but undriven. The ISL3280E and ISL3284E feature an always enabled Rx; the ISL3281E and ISL3285E feature an active high Rx enable pin, and the ISL3282E and ISL3283E include an active low enable pin. All versions are offered in Industrial and Extended Industrial (-40°C to +125°C) temperature ranges. A 26% smaller footprint is available with the ISL3282E and ISL3285E TDFN package. These devices, plus the ISL3284E, also feature a logic supply pin (VL) that sets the VOH level of the RO output (and the switching points of the RE / RE input) to be compatible with another supply voltage in mixed voltage systems. For companion single RS-485 transmitters in micro packages, please see the ISL3293E, ISL3294E, ISL3295E, ISL3296E, ISL3297E, ISL3298E data sheet. Features • IEC61000 ESD Protection on RS-485 Inputs . . . ±16.5kV - Class 3 ESD Level on all Other Pins . . . . . . >5kV HBM • Pb-Free (RoHS Compliant) • Wide Supply Range . . . . . . . . . . . . . . . . . . . 3.0V to 5.5V • Specified for +125°C Operation • Logic Supply Pin (VL) Eases Operation in Mixed Supply Systems (ISL3282E, ISL3284E, ISL3285E Only) • Full Fail-safe (Open, Short, Terminated/Undriven) • True 1/8 Unit Load Allows up to 256 Devices on the Bus • High Data Rates . . . . . . . . . . . . . . . . . . . . . up to 20Mbps • Low Quiescent Supply Current . . . . . . . . . . 500µA (Max) - Very Low Shutdown Supply Current . . . . . . 20µA (Max) • -7V to +12V Common Mode Input Voltage Range • Tri-statable Rx Available (Active Low or High EN Input) • 5V Tolerant Logic Inputs When VCC ≤ 5V Applications • Clock Distribution • High Node Count Systems • Space Constrained Systems • Security Camera Networks • Building Environmental Control/Lighting Systems • Industrial/Process Control Networks TABLE 1. SUMMARY OF FEATURES PART NUMBER ISL3280E ISL3281E ISL3282E ISL3283E ISL3284E ISL3285E FUNCTION 1 Rx 1 Rx 1 Rx 1 Rx 1 Rx 1 Rx DATA RATE (Mbps) 20 20 20 20 20 20 # DEVICES ON BUS 256 256 256 256 256 256 RX ENABLE? NO ACTIVE HIGH ACTIVE LOW ACTIVE LOW NO ACTIVE HIGH VL PIN? NO NO YES NO YES YES QUIESCENT ICC (µA) 350 350 350 350 350 350 LOW POWER SHUTDOWN? NO YES YES YES NO YES LEAD COUNT 5-SOT 6-SOT 8-TDFN 6-SOT 6-SOT 8-TDFN 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL3280E, ISL3281E, ISL3282E, ISL3283E, ISL3284E, ISL3285E Pinouts ISL3280E (5 LD SOT-23) TOP VIEW VCC 1 R 4 B 5 A VCC 1 R ISL3281E (6 LD SOT-23) TOP VIEW 6 5 4 A RE B GND 2 RO 3 GND 2 RO 3 ISL3282E (8 LD TDFN) TOP VIEW VCC 1 ISL3283E (6 LD SOT-23) TOP VIEW 6 R 5 4 A RE B RO GND NC VCC 1 2 3 4 R 8 7 6 5 B RE VL A GND 2 RO 3 ISL3284E (6 LD SOT-23) TOP VIEW VCC 1 R 6 5 4 A VL B ISL3285E (8 LD TDFN) TOP VIEW RO GND NC VCC 1 2 3 4 R 8 7 6 5 B RE VL A GND 2 RO 3 2 FN6543.2 October 18, 2007 ISL3280E, ISL3281E, ISL3282E, ISL3283E, ISL3284E, ISL3285E Ordering Information PART NUMBER (Notes 1, 2) ISL3280EFHZ-T ISL3280EIHZ-T ISL3281EFHZ-T ISL3281EIHZ-T ISL3282EFRTZ-T ISL3282EIRTZ-T ISL3283EFHZ-T ISL3283EIHZ-T ISL3284EFHZ-T ISL3284EIHZ-T ISL3285EFRTZ-T ISL3285EIRTZ-T NOTES: 1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 2. Please refer to TB347 for details on reel specifications. 3. SOT-23 “PART MARKING” is branded on the bottom side. PART MARKING (Note 3) 280F 280I 281F 281I 82F 82I 283F 283I 284F 284I 85F 85I TEMP. RANGE (°C) -40 to +125 -40 to +85 -40 to +125 -40 to +85 -40 to +125 -40 to +85 -40 to +125 -40 to +85 -40 to +125 -40 to +85 -40 to +125 -40 to +85 PACKAGE (Tape and Reel) (Pb-Free) 5 Ld SOT-23 5 Ld SOT-23 6 Ld SOT-23 6 Ld SOT-23 8 Ld TDFN 8 Ld TDFN 6 Ld SOT-23 6 Ld SOT-23 6 Ld SOT-23 6 Ld SOT-23 8 Ld TDFN 8 Ld TDFN PKG. DWG. # P5.064 P5.064 P6.064 P6.064 L8.2x3A L8.2x3A P6.064 P6.064 P6.064 P6.064 L8.2x3A L8.2x3A 3 FN6543.2 October 18, 2007 ISL3280E, ISL3281E, ISL3282E, ISL3283E, ISL3284E, ISL3285E Truth Table RECEIVING INPUTS RE, RE 1, 0 1, 0 1, 0 0, 1 A-B ≥ -0.05V ≤ -0.2V Inputs Open/Shorted X OUTPUT RO 1 0 1 High-Z* NOTE: *Shutdown Mode, except for ISL3280E, ISL3284E Pin Descriptions PIN NAME RO RE, RE FUNCTION Receiver output: If A - B ≥ -50mV, RO is high; If A - B ≤ -200mV, RO is low; RO = High if A and B are unconnected (floating) or shorted. Receiver output enable. RO is enabled when RE/RE is high / low; RO is high impedance when RE/RE is low/high. If the Rx enable function isn’t used, connect RE directly to GND, or connect RE through a 1kΩ, or greater, resistor to VCC. RE/RE are internally pulled low/high. Ground connection. This is also the potential of the TDFN thermal pad. ±16.5kV IEC61000 ESD Protected RS-485, RS-422 level, noninverting receiver input. ±16.5kV IEC61000 ESD Protected RS-485, RS-422 level, inverting receiver input. System power supply input (3.0V to 5.5V). On devices with a VL pin, power-up VCC first. Logic-Level Supply which sets the VIL / VIH levels for the RE (ISL3282E only) and RE (ISL3285E only) pins, and sets the VOH level of the RO output (ISL3282E, ISL3284E, ISL3285E only). Power-up this supply after VCC, and keep VL ≤ VCC. No Connection. GND A B VCC VL NC Typical Operating Circuits NETWORK WITH ENABLES +3.3V TO 5V + 1 VCC ISL3281E 3 RO 5 RE A R B 6 4 RT 6 4 Y Z D 0.1µF 0.1µF + 2 VCC ISL329xE DI 1 DE 3 +3.3V GND 2 GND 5 4 FN6543.2 October 18, 2007 ISL3280E, ISL3281E, ISL3282E, ISL3283E, ISL3284E, ISL3285E Typical Operating Circuits (Continued) NETWORK WITHOUT ENABLES +3.3V TO 5V 1 VCC ISL3280E 3 RO A R B 5 4 RT 6 4 Y Z D + 0.1µF 0.1µF + 2 VCC ISL329xE DE DI 1 +3.3V 1kΩ TO 3kΩ 3 GND 2 GND 5 NETWORK WITH VL PIN FOR INTERFACE TO LOWER VOLTAGE LOGIC DEVICES 1.8V 6 VCC VL +3.3V TO 5V + 4 VCC ISL3282E LOGIC DEVICE (µP, ASIC, UART) +3.3V 0.1µF 0.1µF + 8 VCC ISL3298E 2.5V 1 VL VCC 1 RO 7 RE A R B 5 8 RT 6 7 Y Z D DI 3 DE 2 LOGIC DEVICE (μP, ASIC, UART) GND 2 GND 4, 5 5 FN6543.2 October 18, 2007 ISL3280E, ISL3281E, ISL3282E, ISL3283E, ISL3284E, ISL3285E Absolute Maximum Ratings VCC to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 7V VL to GND (ISL3282E, ISL3284E, ISL3285E Only). . -0.3V to (VCC +0.3V) Input Voltages RE, RE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 7V Input/Output Voltages A, B. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -8V to +13V RO (Not ISL3282E, ISL3284E, ISL3285E). . -0.3V to (VCC +0.3V) RO (ISL3282E, ISL3284E, ISL3285E) . . . . . . -0.3V to (VL +0.3V) Short Circuit Duration RO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Indefinite ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . See Specification Table Thermal Information Thermal Resistance (Typical) θJA (°C/W) θJC (°C/W) 5 Ld SOT-23 Package (Note 4) . . . . . . 190 N/A 6 Ld SOT-23 Package (Note 4) . . . . . . 177 N/A 8 Ld TDFN Package (Notes 5, 6). . . . . 65 8 Maximum Junction Temperature (Plastic Package) . . . . . . +150°C Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Operating Conditions Temperature Range F Suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C I Suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTE: 4. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 5. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 6. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside. Electrical Specifications Test Conditions: VCC = 3.0V to 5.5V; VL = VCC (ISL3282E, ISL3284E, ISL3285E only); Typicals are at TA = +25°C (Note 11); Unless Otherwise Specified (Note 7). SYMBOL TEST CONDITIONS VCC ≤ 3.6V VCC ≤ 5.5V ISL3282E and ISL3285E Only TEMP MIN TYP MAX (°C) (Note 10) (Note 11) (Note 10) UNITS PARAMETER DC CHARACTERISTICS Input High Voltage (RE, RE) (Notes 8, 9) VIH1 VIH2 VIH3 VIH4 VIH5 VIH6 VL = VCC if ISL3282E, or ISL3285E 2.7V ≤ VL < 3.0V 2.3V ≤ VL < 2.7V 1.6V ≤ VL < 2.3V 1.35V ≤ VL < 1.6V Full Full Full Full Full 25 Full Full Full Full 25 Full 2 2.4 1.7 1.6 0.72*VL -15 -100 -200 ±7 VCC - 0.4 VL - 0.4 1.2 1.15 VL - 0.1 0.5*VL 0.33*VL ±9 80 -50 -125 15 150 ±30 - 0.7 0.7 0.6 0.25*VL 15 125 -50 ±85 - V V V V V V V V V V V µA µA µA mV mV kΩ mA V V V V V Input Low Voltage (RE, RE) (Notes 8, 9) VIL1 VIL2 VIL3 VIL4 VIL5 VL = VCC if ISL3282E or ISL3285E VL ≥ 2.7V 2.3V ≤ VL < 2.7V 1.6V ≤ VL < 2.3V 1.35V ≤ VL < 1.6V RE = RE = 0V or VCC VCC = 0V, 3.6V, or 5.5V -7V ≤ VCM ≤ 12V VCM = 0V -7V ≤ VCM ≤ 12V 0V ≤ VO ≤ VCC IO = -3.5mA, VID = -50mV (VL = VCC if ISL3282E, ISL3284E, ISL3285E) IO = -1mA, VL ≥ 1.6V IO = -500µA, VL = 1.5V IO = -150µA, VL = 1.35V IO = -100µA, VL ≥ 1.35V ISL3282E, ISL3284E, and ISL3285E Only VIN = 12V VIN = -7V ISL3282E and ISL3285E Only Logic Input Current (Note 8) Input Current (A, B) IIN1 IIN2 VTH ΔVTH RIN IOSR VOH1 VOH2 VOH3 VOH4 VOH5 Full Full Full 25 Full Full Full Full Full Full Full Receiver Differential Threshold Voltage Receiver Input Hysteresis Receiver Input Resistance Receiver Short-Circuit Current Receiver Output High Voltage 6 FN6543.2 October 18, 2007 ISL3280E, ISL3281E, ISL3282E, ISL3283E, ISL3284E, ISL3285E Electrical Specifications Test Conditions: VCC = 3.0V to 5.5V; VL = VCC (ISL3282E, ISL3284E, ISL3285E only); Typicals are at TA = +25°C (Note 11); Unless Otherwise Specified (Note 7). (Continued) SYMBOL VOL1 VOL2 VOL3 VOL4 Three-State (high impedance) Receiver Output Current (Notes 8, 9) SUPPLY CURRENT No-Load Supply Current Shutdown Supply Current (Note 8) ESD PERFORMANCE RS-485 Pins (A, B) IEC61000-4-2, Air-Gap Discharge Method IEC61000-4-2, Contact Discharge Method Human Body Model, From Bus Pins to GND All Pins HBM, per MIL-STD-883 Method 3015 MM RECEIVER SWITCHING CHARACTERISTICS Maximum Data Rate Receiver Input to Output Delay fMAX tPLH, tPHL VID = ±2V, VCM = 0V (Figure 1 and Table 2) (Note 11) VID = ±2V, VCM = 0V (Figure 1) VL ≥ 1.5V (Figure 1) ISL3282E, ISL3284E, and ISL3285E Only Full Full 25 20 20 30, 24 36 44 60 Mbps ns ns 25 25 25 25 25 ±16.5 ±9 ±16.5 ±5 ±250 kV kV kV kV V ICC ISHDN RE/RE = VCC/0V RE/RE = 0V/VCC Full Full 400 500 20 µA µA IOZR TEST CONDITIONS IO = 4mA, VID = -200mV, VL ≥ 2.2V if ISL3282E, ISL3284E, ISL3285E IO = 2mA, VL ≥ 1.5V IO = 1mA, VL ≥ 1.35V IO = 500µA, VL ≥ 1.35V 0V ≤ VO ≤ VCC ISL3282E, ISL3284E, and ISL3285E Only TEMP MIN TYP MAX (°C) (Note 10) (Note 11) (Note 10) UNITS Full Full Full 25 Full -1 0.2 0.2 0.1 0.1 0.015 0.4 0.4 0.4 1 V V V V µA PARAMETER Receiver Output Low Voltage Receiver Skew | tPLH - tPHL | tSK1 tSK2 VCC = 3.3V ±10% (Figure 1) VL = VCC if ISL3282E, VCC = 5V ±10% (Figure 1) ISL3284E, or ISL3285E VL ≥ 1.8V (Figure 1) VL = 1.5V (Figure 1) RL = 1kΩ, CL = 15pF, SW = GND (Figure 2) RL = 1kΩ, CL = 15pF, SW = VCC (Figure 2) RL = 1kΩ, CL = 15pF, SW = GND (Figure 2) RL = 1kΩ, CL = 15pF, SW = VCC (Figure 2) ISL3282E, ISL3284E, and ISL3285E Only Note 11 VL ≥ 1.5V, Note 11 Note 11 VL ≥ 1.5V, Note 11 VL ≥ 1.5V, Note 11 VL ≥ 1.5V, Note 11 Full Full - 1 2 5.5 7.5 ns ns tSK3 tSK4 Receiver Enable to Output High (Note 8) Receiver Enable to Output Low (Note 8) Receiver Disable from Output High (Note 8) Receiver Disable from Output Low (Note 8) NOTES: tZH tZL tHZ tLZ 25 25 Full 25 Full 25 Full 25 Full 25 - 2 4 240, 90 250, 120 240, 90 250, 120 10 24, 20 10 24, 20 500 500 20 20 - ns ns ns ns ns ns ns ns ns ns 7. All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground unless otherwise specified. 8. Does not apply to the ISL3280E or ISL3284E. 9. If the Rx enable function isn’t needed, connect the enable pin to the appropriate supply, as described in the “Pin Descriptions” table. 10. Parts are 100% tested at +25°C. Over-temperature limits established by characterization and are not production tested. 11. Typical values are at 3.3V, 5V. Parameters with a single entry in the “TYP” column apply to 3.3V and 5V. 7 FN6543.2 October 18, 2007 ISL3280E, ISL3281E, ISL3282E, ISL3283E, ISL3284E, ISL3285E Test Circuits and Waveforms VCC GND B A R RE RE RO 15pF B 0V A tPLH SIGNAL GENERATORS RO 50% tPHL VCC OR VL 50% 0V 0V -1V +1V FIGURE 1A. TEST CIRCUIT FIGURE 1B. MEASUREMENT POINTS FIGURE 1. RECEIVER PROPAGATION DELAY AND DATA RATE RE OR RE GND SIGNAL GENERATOR B A R RO 1kΩ VCC OR VL SW 15pF RO GND tZH OUTPUT HIGH 50% tHZ RE (INVERT FOR RE) 1.5V 1.5V 3V 0V V VOH - 0.25V OH 0V PARAMETER tHZ tLZ tZH tZL A +1.5V -1.5V +1.5V -1.5V SW GND VCC OR VL GND VCC OR VL OUTPUT LOW RO tZL 50% tLZ VCC OR VL VOL + 0.25V V OL FIGURE 2A. TEST CIRCUIT FIGURE 2B. MEASUREMENT POINTS FIGURE 2. RECEIVER ENABLE AND DISABLE TIMES (EXCEPT ISL3280E AND ISL3284E) Application Information RS-485 and RS-422 are differential (balanced) data transmission standards for use in long haul or noisy environments. RS-422 is a subset of RS-485, so RS-485 transceivers are also RS-422 compliant. RS-422 is a point-to-multipoint (multidrop) standard, which allows only one driver and up to 10 (assuming one unit load devices) receivers on each bus. RS-485 is a true multipoint standard, which allows up to 32 one unit load devices (any combination of drivers and receivers) on each bus. Another important advantage of RS-485 is the extended common mode range (CMR), which specifies that the driver outputs and receiver inputs withstand signals that range from +12V to -7V. RS-422 and RS-485 are intended for runs as long as 4000’, so the wide CMR is necessary to handle ground potential differences, as well as voltages induced in the cable by external fields. Receiver Features These devices utilize a differential input receiver for maximum noise immunity and common mode rejection. Input sensitivity is better than ±200mV, as required by the RS-422 and RS-485 specifications. Receiver input resistance of 96kΩ surpasses the RS-422 specification of 4kΩ and is eight times the RS-485 “Unit Load (UL)” requirement of 12kΩ minimum. Thus, these products are known as “one-eighth UL” transceivers and there can be up to 256 of these devices on a network while still complying with the RS-485 loading specification. Receiver inputs function with common mode voltages as great as +9V/-7V outside the power supplies (i.e., +12V and -7V), making them ideal for long networks where induced voltages, and ground potential differences are realistic concerns. 8 FN6543.2 October 18, 2007 ISL3280E, ISL3281E, ISL3282E, ISL3283E, ISL3284E, ISL3285E All the receivers include a “full fail-safe” function that guarantees a high level receiver output if the receiver inputs are unconnected (floating), shorted together, or connected to a terminated but undriven bus. Fail-safe with shorted inputs is achieved by setting the Rx upper switching point to -50mV, thereby ensuring that the Rx sees 0V differential as a high input level. All receivers easily support a 20Mbps data rate, and all receiver outputs (except on the ISL3280E and ISL3284E) are tri-statable via the active low RE input or by the active high RE input. TABLE 2. VIH, VIL AND DATA RATE vs VL FOR VCC = 3.3V OR 5V VL (V) 1.35 1.6 1.8 2.3 2.7 3.3 5.5 (i.e., VCC) VIH (V) 0.55 0.7 0.8 1 1.1 1.3 2 VIL (V) 0.5 0.6 0.7 0.9 1 1.2 1.8 DATA RATE (Mbps) 11 16 23 27 30 30 24 Wide Supply Range The ISL3280E, ISL3281E, ISL3282E, ISL3283E, ISL3284E, ISL3285E are designed to operate with a wide range of supply voltages from 3.0V to 5.5V. These devices meet the RS-422 and RS-485 specifications over this full range. Logic Supply (VL Pin, ISL3282E, ISL3284E, ISL3285E Only) Note: Power-up VCC before powering up the VL supply. The ISL3282E, ISL3284E, and ISL3285E include a VL pin that powers the logic input (RE or RE) and / or the Rx output. These pins interface with “logic” devices such as UARTs, ASICs, and microcontrollers and today most of these devices use power supplies significantly lower than 3.3V. Thus, a 3.3V output level from a 3.3V powered RS-485 IC might seriously overdrive and damage the logic device input. Similarly, the logic device’s low VOH might not exceed the VIH of a 3.3V or 5V powered RE input. Connecting the VL pin to the power supply of the logic device (as shown in Figure 3) limits the ISL3282E, ISL3284E, ISL3285E’s Rx output VOH to VL (see Figures 6 through 10), and reduces the RE / RE input switching point to a value compatible with the logic device’s output levels. Tailoring the logic pin input switching point and output levels to the supply voltage of the UART, ASIC, or microcontroller eliminates the need for a level shifter/translator between the two ICs. VL can be anywhere from VCC down to 1.35V, but the input switching points may not provide enough noise margin when VL < 1.6V. Table 2 indicates typical VIH, VIL, and data rate values for various VL settings so the user can ascertain whether or not a particular VL voltage meets his/her needs. The quiescent, RO unloaded, VL supply current (IL) is typically less than 60µA for VL ≤ 3.3V, as shown in Figure 5. VCC = +3.3V VCC = +2V RO VOH = 3.3V RXD ESD DIODE RE GND VIH ≥ 2V VOH ≤ 2V RXEN GND ESD Protection All pins on these devices include class 3 (>4kV) Human Body Model (HBM) ESD protection structures, but the RS-485 pins (receiver inputs) incorporate advanced structures allowing them to survive ESD events in excess of ±16.5kV HBM and ±16.5kV IEC61000. The RS-485 pins are particularly vulnerable to ESD damage because they typically connect to an exposed port on the exterior of the finished product. Simply touching the port pins, or connecting a cable, can cause an ESD event that might destroy unprotected ICs. These new ESD structures protect the device whether or not it is powered up, and without degrading the RS-485 common mode range of -7V to +12V. This built-in ESD protection eliminates the need for board level protection structures (e.g., transient suppression diodes), and the associated, undesirable capacitive load they present. ISL3283E VCC = +3.3V TO 5V UART/PROCESSOR VCC = +2V VL RO VOH = 2V RXD ESD DIODE RE GND VIH = 1V VOH ≤ 2V RXEN GND ISL3282E UART/PROCESSOR FIGURE 3. USING VL PIN TO ADJUST LOGIC LEVELS 9 FN6543.2 October 18, 2007 ISL3280E, ISL3281E, ISL3282E, ISL3283E, ISL3284E, ISL3285E IEC61000-4-2 Testing The IEC61000 test method applies to finished equipment, rather than to an individual IC. Therefore, the pins most likely to suffer an ESD event are those that are exposed to the outside world (the RS-485 pins in this case), and the IC is tested in its typical application configuration (power applied) rather than testing each pin-to-pin combination. The lower current limiting resistor coupled with the larger charge storage capacitor yields a test that is much more severe than the HBM test. The extra ESD protection built into this device’s RS-485 pins allows the design of equipment meeting level 4 criteria without the need for additional board level protection on the RS-485 port. AIR-GAP DISCHARGE TEST METHOD For this test method, a charged probe tip moves toward the IC pin until the voltage arcs to it. The current waveform delivered to the IC pin depends on approach speed, humidity, temperature, etc., so it is difficult to obtain repeatable results. The A and B RS-485 pins withstand ±16.5kV air-gap discharges. CONTACT DISCHARGE TEST METHOD During the contact discharge test, the probe contacts the tested pin before the probe tip is energized, thereby eliminating the variables associated with the air-gap discharge. The result is a more repeatable and predictable test, but equipment limits prevent testing devices at voltages higher than ±9kV. The ISL3280E, ISL3281E, ISL3282E, ISL3283E, ISL3284E, ISL3285E survive ±9kV contact discharges on the RS-485 pins. transmission length increases. Networks operating at 20Mbps are limited to lengths less than 100’, while a 250kbps network that uses slew rate limited transmitters can operate at that data rate over lengths of several thousand feet. Twisted pair is the cable of choice for RS-485, RS-422 networks. Twisted pair cables tend to pick up noise and other electromagnetically induced voltages as common mode signals, which are effectively rejected by the differential receiver in these ICs. To minimize reflections, proper termination is imperative for high data rate networks. Short networks using slew rate limited transmitters need not be terminated, but terminations are recommended unless power dissipation is an overriding concern. In point-to-point, or point-to-multipoint (single driver on bus) networks, the main cable should be terminated in its characteristic impedance (typically 120Ω) at the end farthest from the driver. In multi-receiver applications, stubs connecting receivers to the main cable should be kept as short as possible. Multipoint (multi-driver) systems require that the main cable be terminated in its characteristic impedance at both ends. Stubs connecting a transmitter or receiver to the main cable should be kept as short as possible. Low Power Shutdown Mode These BiCMOS receivers all use a fraction of the power required by their bipolar counterparts, and the versions with output enable functions include a shutdown feature that reduces the already low quiescent ICC to a 20µA trickle. These versions enter shutdown whenever the receiver disables (RE = VCC or RE = GND). Data Rate, Cables, and Terminations RS-485, RS-422 are intended for network lengths up to 4000’, but the maximum system data rate decreases as the Typical Performance Curves 0.50 0.45 0.40 0.35 ICC (mA) VCC = VL = 5V VCC = VL = 3.3V CL = 15pF, TA = +25°C; Unless Otherwise Specified. 250 VCC = 5V OR 3.3V 200 0.25 0.20 0.15 0.10 0.05 0 -40 RE = VCC, RE = 0V -15 10 60 35 TEMPERATURE (°C) 85 110 125 IL (μA) 0.30 150 VL = 5V, VCC = 5V ONLY VL ≤ 1.8V 50 VL = 3.3V 0 VL = 2.5V 0 1 2 3 4 5 6 7 7.5 RE VOLTAGE (V) 100 FIGURE 4. SUPPLY CURRENT vs TEMPERATURE FIGURE 5. VL SUPPLY CURRENT vs ENABLE PIN VOLTAGE 10 FN6543.2 October 18, 2007 ISL3280E, ISL3281E, ISL3282E, ISL3283E, ISL3284E, ISL3285E Typical Performance Curves 60 RECEIVER OUTPUT CURRENT (mA) 50 40 VOH, +125°C 30 20 10 0 VOH, +85°C VCC = VL = 5V VOH, +25°C CL = 15pF, TA = +25°C; Unless Otherwise Specified. (Continued) 30 RECEIVER OUTPUT CURRENT (mA) VOL, +25°C VOL, +85°C VOL, +125°C VOL, +25°C 25 VOH, +25°C 20 15 VOH, +125°C 10 5 VCC = 5V OR 3.3V, VL = 3.3V 0 VOL, +85°C VOL, +125°C VOH, +85°C 0 1 2 3 4 5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.3 RECEIVER OUTPUT VOLTAGE (V) RECEIVER OUTPUT VOLTAGE (V) FIGURE 6. RECEIVER OUTPUT CURRENT vs RECEIVER OUTPUT VOLTAGE FIGURE 7. RECEIVER OUTPUT CURRENT vs RECEIVER OUTPUT VOLTAGE 20 RECEIVER OUTPUT CURRENT (mA) 18 16 14 RECEIVER OUTPUT CURRENT (mA) VCC = 5V OR 3.3V, VL = 2.5V 9 VOL, +25°C VOL, +85°C VOL, +125°C VCC = 5V OR 3.3V, VL = 1.8V 8 7 6 5 4 3 2 1 0 0 0.5 1.0 1.5 1.8 VOH, +125°C VOH, +25°C VOH, +85°C VOL, +25°C VOL, +85°C VOL, +125°C 12 VOH, +25°C 10 8 6 4 2 0 0 0.5 1.0 1.5 VOH, +125°C VOH, +85°C 2.0 2.5 RECEIVER OUTPUT VOLTAGE (V) RECEIVER OUTPUT VOLTAGE (V) FIGURE 8. RECEIVER OUTPUT CURRENT vs RECEIVER OUTPUT VOLTAGE FIGURE 9. RECEIVER OUTPUT CURRENT vs RECEIVER OUTPUT VOLTAGE 5.0 RECEIVER OUTPUT CURRENT (mA) 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.5 RECEIVER OUTPUT VOLTAGE (V) VOH, +125°C VOH, +25°C VOH, +85°C VOL, +125°C VCC = 5V or 3.3V, VL = 1.5V VOL, +85°C VOL, +25°C PROPAGATION DELAY (ns) 55 VCC = 5V 50 VL = 1.5V 45 VL = 1.8V 40 VL = 2.5V 35 30 -40 -15 10 35 60 85 110 125 TEMPERATURE (°C) FIGURE 10. RECEIVER OUTPUT CURRENT vs RECEIVER OUTPUT VOLTAGE FIGURE 11. RECEIVER PROPAGATION DELAY vs TEMPERATURE 11 FN6543.2 October 18, 2007 ISL3280E, ISL3281E, ISL3282E, ISL3283E, ISL3284E, ISL3285E Typical Performance Curves 5.0 4.5 PROPAGATION DELAY (ns) 4.0 3.5 SKEW (ns) 3.0 2.5 2.0 1.5 1.0 0.5 0 -40 -15 10 35 60 85 110 125 30 -40 -15 10 35 60 85 110 125 VL = 2.5V VL = 1.8V VL = 1.5V 50 VL = 1.5V |tPLH - tPHL| CL = 15pF, TA = +25°C; Unless Otherwise Specified. (Continued) VCC = 5V 55 VCC = 3.3V 45 40 VL = 1.8V VL = 2.5V 35 TEMPERATURE (°C) TEMPERATURE (°C) FIGURE 12. RECEIVER SKEW vs TEMPERATURE FIGURE 13. RECEIVER PROPAGATION DELAY vs TEMPERATURE 4.0 3.5 3.0 SKEW (ns) 2.5 2.0 |tPLH - tPHL| VCC = 3.3V RECEIVER INPUT (V) VCC = 5V 2.0 0 A-B -2.0 VL = 1.5V RECEIVER OUTPUT (V) 5.0 4.0 3.0 2.0 1.0 0 VL = 5V 1.5 VL = 1.8V 1.0 0.5 VL = 1.8V 0 -40 -15 10 35 60 85 110 125 VL = 2.5V VL = 1.5V VL = 2.5V TEMPERATURE (°C) TIME (20ns/DIV) FIGURE 14. RECEIVER SKEW vs TEMPERATURE FIGURE 15. RECEIVER WAVEFORMS RECEIVER INPUT (V) VCC = 3.3V 2.0 0 A-B -2.0 Die Characteristics SUBSTRATE AND TDFN THERMAL PAD POTENTIAL (POWERED UP): GND RECEIVER OUTPUT (V) 4.0 3.0 2.0 1.0 0 VL = 3.3V VL = 2.5V VL = 1.5V TRANSISTOR COUNT: 140 PROCESS: Si Gate BiCMOS TIME (20ns/DIV) FIGURE 16. RECEIVER WAVEFORMS 12 FN6543.2 October 18, 2007 ISL3280E, ISL3281E, ISL3282E, ISL3283E, ISL3284E, ISL3285E Small Outline Transistor Plastic Packages (SOT23-5) D P5.064 VIEW C e1 5 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE INCHES MILLIMETERS MIN 0.90 0.00 0.90 0.30 0.30 0.08 0.08 2.80 2.60 1.50 MAX 1.45 0.15 1.30 0.50 0.45 0.22 0.20 3.00 3.00 1.70 6 6 3 3 4 NOTES SYMBOL A MIN 0.036 0.000 0.036 0.012 0.012 0.003 0.003 0.111 0.103 0.060 MAX 0.057 0.0059 0.051 0.020 0.018 0.009 0.008 0.118 0.118 0.067 5 E 1 2 3 4 C L C L E1 A1 A2 b b1 e C L 0.20 (0.008) M C L C b α C c c1 D E E1 A A2 A1 SEATING PLANE -C- e e1 L L1 0.0374 Ref 0.0748 Ref 0.014 0.022 0.024 Ref. 0.010 Ref. 5 0.004 0.004 0o 0.010 8o 0.95 Ref 1.90 Ref 0.35 0.55 0.60 Ref. 0.25 Ref. 5 0.10 0.10 0o 0.25 8o 0.10 (0.004) C L2 N R R1 5 WITH PLATING c b b1 c1 α NOTES: Rev. 2 9/03 BASE METAL 1. Dimensioning and tolerance per ASME Y14.5M-1994. 2. Package conforms to EIAJ SC-74 and JEDEC MO178AA. 3. Dimensions D and E1 are exclusive of mold flash, protrusions, or gate burrs. 4X θ1 R1 R GAUGE PLANE SEATING PLANE L C 4X θ1 VIEW C L1 4. Footlength L measured at reference to gauge plane. 5. “N” is the number of terminal positions. 6. These Dimensions apply to the flat section of the lead between 0.08mm and 0.15mm from the lead tip. 7. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only. α L2 13 FN6543.2 October 18, 2007 ISL3280E, ISL3281E, ISL3282E, ISL3283E, ISL3284E, ISL3285E Small Outline Transistor Plastic Packages (SOT23-6) 0.20 (0.008) M C L b e C VIEW C P6.064 6 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE INCHES SYMBOL MIN 0.036 0.000 0.036 0.012 0.012 0.003 0.003 0.111 0.103 0.060 MAX 0.057 0.0059 0.051 0.020 0.018 0.009 0.008 0.118 0.118 0.068 A MILLIMETERS MIN 0.90 0.00 0.90 0.30 0.30 0.08 0.08 2.80 2.60 1.50 MAX 1.45 0.15 1.30 0.50 0.45 0.22 0.20 3.00 3.00 1.75 6 6 3 3 4 NOTES - 6 C L 1 5 4 C L E E1 A1 A2 b b1 c 2 3 e1 D C L C c1 D E E1 A A2 A1 SEATING PLANE -C- e e1 L L1 L2 N R R1 0.0374 Ref 0.0748 Ref 0.014 0.022 0.024 Ref. 0.010 Ref. 6 0.004 0.004 0o 0.010 8o 0.95 Ref 1.90 Ref 0.35 0.55 0.60 Ref. 0.25 Ref. 6 0.10 0.10 0o 0.25 8o 0.10 (0.004) C WITH PLATING c b b1 c1 5 α NOTES: Rev. 3 9/03 BASE METAL 1. Dimensioning and tolerance per ASME Y14.5M-1994. 4X θ1 R1 R GAUGE PLANE SEATING PLANE L C 4X θ1 VIEW C L1 2. Package conforms to EIAJ SC-74 and JEDEC MO178AB. 3. Dimensions D and E1 are exclusive of mold flash, protrusions, or gate burrs. 4. Footlength L measured at reference to gauge plane. 5. “N” is the number of terminal positions. 6. These Dimensions apply to the flat section of the lead between 0.08mm and 0.15mm from the lead tip. 7. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only α L2 14 FN6543.2 October 18, 2007 ISL3280E, ISL3281E, ISL3282E, ISL3283E, ISL3284E, ISL3285E Thin Dual Flat No-Lead Plastic Package (TDFN) 2X 0.15 C A A D 2X 0.15 C B L8.2x3A 8 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE MILLIMETERS SYMBOL A E MIN 0.70 - NOMINAL 0.75 0.20 REF MAX 0.80 0.05 NOTES - A1 A3 b D 6 INDEX AREA B 0.20 0.25 2.00 BSC 0.32 5,8 - TOP VIEW D2 E // 0.10 C 1.50 1.65 3.00 BSC 1.75 7,8 - E2 A 0.08 C 1.65 1.80 0.50 BSC 1.90 7,8 - e k L N 0.20 0.30 C SEATING PLANE SIDE VIEW A3 0.40 8 4 0.50 8 2 3 Rev. 0 6/04 D2 (DATUM B) 1 2 D2/2 7 8 Nd NOTES: 6 INDEX AREA (DATUM A) NX k 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd refers to the number of terminals on D. E2 E2/2 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.25mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. NX L N N-1 NX b 8 e (Nd-1)Xe REF. BOTTOM VIEW (A1) NX (b) 5 SECTION "C-C" CC e FOR EVEN TERMINAL/SIDE TERMINAL TIP L C L 5 0.10 M C AB 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 15 FN6543.2 October 18, 2007