DATASHEET
ISL33001, ISL33002, ISL33003
FN7560
Rev 6.01
Feb 24, 2022
I2C Bus Buffer with Rise Time Accelerators and Hot Swap Capability
The ISL33001, ISL33002, ISL33003 are 2-Channel Bus Buffers
that provide the buffering necessary to extend the bus
capacitance beyond the 400pF maximum specified by the I2C
specification. In addition, the ISL33001, ISL33002, ISL33003
feature rise time accelerator circuitry to reduce power
consumption from passive bus pull-up resistors and improve
data-rate performance. All devices also include hot swap circuitry
to prevent corruption of the data and clock lines when I2C devices
are plugged into a live backplane, and the ISL33002 and
ISL33003 add level translation for mixed supply voltage
applications. The ISL33001, ISL33002, ISL33003 operate at
supply voltages from +2.3V to +5.5V at a temperature range of
-40°C to +85°C.
Summary of Features
PART
NUMBER
LEVEL
TRANSLATION
Features
• 2 Channel I2C compatible bi-directional buffer
• +2.3VDC to +5.5VDC supply range
• >400kHz operation
• Bus capacitance buffering
• Rise time accelerators
• Hot swapping capability
• ±6kV Class 3 HBM ESD protection on all pins
• ±12kV HBM ESD protection on SDA/SCL pins
• Enable pin (ISL33001 and ISL33003)
• Logic level translation (ISL33002 and ISL33003)
ENABLE READY
PIN
PIN
ACCELERATOR
DISABLE
ISL33001
No
Yes
Yes
No
ISL33002
Yes
No
No
Yes
ISL33003
Yes
Yes
No
No
• READY logic pin (ISL33001)
• Accelerator disable pin (ISL33002)
• Pb-free (RoHS Compliant) 8 Ld SOIC (ISL33001 only),
8 Ld TDFN (3mmx3mm) and 8 Ld MSOP packages
• Low quiescent current . . . . . . . . . . . . . . . . . . . . . . . 2.1mA typ
• Low shutdown current . . . . . . . . . . . . . . . . . . . . . . . . 0.5µA typ
Applications
• I2C bus extender and capacitance buffering
• Server racks for telecom, datacom, and computer servers
• Desktop computers
• Hot-swap board insertion and bus isolation
VCC1
+3.3V
+5.0V
100kHz I2C BUS WITH 2.7kΩ PULL-UP RESISTOR
AND 400pF BUS CAPACITANCE
VCC2
WITHOUT BUFFER
µC
SDA
SDA
ISL33003
SCL
SCL
I2C
DEVICE
A
EN
I2C
DEVICE
B
VOLTAGE (1V/DIV)
BACK
PLANE
WITH BUFFER
GND
TIME (2µs/DIV)
FIGURE 1. TYPICAL OPERATING CIRCUIT
FN7560 Rev 6.01
Feb 24, 2022
FIGURE 2. BUS ACCELERATOR PERFORMANCE
Page 1 of 20
© 2010 Renesas Electronics
ISL33001, ISL33002, ISL33003
Contents
Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin Configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Test Circuits and Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C and SMBUS Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Start-Up Sequencing and Hot Swap Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Connection Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Buffer Output Low and Offset Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Rise Time Accelerators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Enable Pin (ISL33001 and ISL33003) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
READY Logic Pin (ISL33001 Only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ACC Accelerator Pin (ISL33002 Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Propagation Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pull-Up Resistor Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Level Shifting from 3.3V to 1.8V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11
11
11
11
11
11
12
12
12
12
12
12
Typical Performance Curves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Die Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Package Outline Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
FN7560 Rev 6.01
Feb 24, 2022
Page 2 of 20
ISL33001, ISL33002, ISL33003
Ordering Information
PART NUMBER
(Notes 2, 3)
ISL33001IRTZ
PART
MARKING
3001
PACKAGE DESCRIPTION
(RoHS Compliant)
8 Ld TDFN (0.65mm Pitch)
PKG.
DWG. #
CARRIER TYPE
(Note 1)
TEMP. RANGE
L8.3x3A
Tube
-40 to +85°C
ISL33001IRTZ-T
ISL33001IRT2Z
Reel, 6k
01R2
8 Ld TDFN (0.5mm Pitch)
L8.3x3H
ISL33001IRT2Z-T
ISL33001IBZ
ISL33001IBZ-T
ISL33001IUZ
Reel, 6k
33001
IBZ
8 Ld SOIC
33001
8 Ld MSOP
M8.15
M8.118
3002
8 Ld TDFN (0.65mm Pitch)
L8.3x3A
02R2
8 Ld TDFN (0.5mm Pitch)
L8.3x3H
33002
8 Ld MSOP
M8.118
3003
8 Ld TDFN (0.65mm Pitch)
L8.3x3A
Tube
Reel, 6k
03R2
8 Ld TDFN (0.5mm Pitch)
L8.3x3H
ISL33003IRT2Z-T
ISL33003IUZ
Tube
Reel, 2.5k
ISL33003IRTZ-T
ISL33003IRT2Z
Tube
Reel, 6k
ISL33002IUZ-T
ISL33003IRTZ
Tube
Reel, 6k
ISL33002IRT2Z-T
ISL33002IUZ
Tube
Reel, 2.5k
ISL33002IRTZ-T
ISL33002IRT2Z
Tube
Reel, 2.5k
ISL33001IUZ-T
ISL33002IRTZ
Tube
Tube
Reel, 6k
33003
8 Ld MSOP
ISL33003IUZ-T
M8.118
Tube
Reel, 2.5k
ISL33001MSOPEVAL1Z
ISL33001 Evaluation Board
ISL33002MSOPEVAL1Z
ISL33002 Evaluation Board
ISL33003MSOPEVAL1Z
ISL33003 Evaluation Board
NOTES:
1. See TB347 for details about reel specifications.
2. These Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate
plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), see the ISL33001, ISL33002, and ISL33003 product information pages. For more information about MSL, see
TB363.
FN7560 Rev 6.01
Feb 24, 2022
Page 3 of 20
ISL33001, ISL33002, ISL33003
Pin Configurations
ISL33001
(8 LD SOIC, MSOP)
TOP VIEW
ISL33001
(8 LD TDFN)
TOP VIEW
8
VCC1
7
SDA_OUT
SCL_IN 3
6
SDA_IN
GND 4
5
READY
EN 1
SCL_OUT 2
PAD
EN
1
8
VCC1
SCL_OUT
2
7
SDA_OUT
SCL_IN
3
6
SDA_IN
GND
4
5
READY
ISL33002
(8 LD MSOP)
TOP VIEW
ISL33002
(8 LD TDFN)
TOP VIEW
VCC2 1
8
VCC1
7
SDA_OUT
SCL_IN 3
6
SDA_IN
GND 4
5
ACC
SCL_OUT 2
PAD
VCC2
1
8
VCC1
SCL_OUT
2
7
SDA_OUT
SCL_IN
3
6
SDA_IN
GND
4
5
ACC
ISL33003
(8 LD MSOP)
TOP VIEW
ISL33003
(8 LD TDFN)
TOP VIEW
VCC2 1
8
VCC1
7
SDA_OUT
SCL_IN 3
6
SDA_IN
GND 4
5
EN
SCL_OUT 2
VCC2
1
8
VCC1
SCL_OUT
2
7
SDA_OUT
SCL_IN
3
6
SDA_IN
GND
4
5
EN
PAD
FN7560 Rev 6.01
Feb 24, 2022
Page 4 of 20
ISL33001, ISL33002, ISL33003
Pin Descriptions
PIN
PIN NAME NUMBER
FUNCTION
NOTES
VCC1
8
VCC1 power supply, +2.3V to +5.5V. Decouple VCC1 to ground with a high frequency
0.01µF to 0.1µF capacitor.
VCC2
1
VCC2 power supply, +2.3V to +5.5V. Decouple VCC2 to ground with a high frequency ISL33002 (8 LD TDFN, 8 LD MSOP)
0.01µF to 0.1µF capacitor. In level shifting applications, SDA_OUT and SCL_OUT logic ISL33003 (8 LD TDFN, 8 LD MSOP)
thresholds are referenced to VCC2 supply levels. Connect pull-up resistors on these
pins to VCC2.
GND
4
Device Ground Pin
EN
1
Buffer Enable Pin. Logic “0” disables the device. Logic “1” enables the device. Logic ISL33001 (8 LD TDFN, 8 LD SOIC, MSOP)
threshold referenced to VCC1.
ISL33003 (8 LD TDFN, 8 LD MSOP)
5
READY
5
Buffer active ‘Ready’ open drain logic output. When buffer is active, READY is high ISL33001 only
impedance. When buffer is inactive, READY is low impedance to ground. Connect to
10kΩ pull-up resistor to VCC1.
ACC
5
Rise Time Accelerator Enable Pin. Logic “0” disables the accelerator. Logic “1”
enables the accelerator. Logic threshold referenced to VCC1.
SDA_IN
6
Data I/O Pins
SDA_OUT
7
SCL_IN
3
SCL_OUT
2
PAD
FN7560 Rev 6.01
Feb 24, 2022
ISL33002 only
Clock I/O Pins
Thermal pad should be connected to ground or floated.
Thermal Pad; TDFN only
Page 5 of 20
ISL33001, ISL33002, ISL33003
Absolute Maximum Ratings (All voltages referenced to
Thermal Information
GND)
VCC1, VCC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7V
SDA_IN, SCL_IN, SDA_OUT, SCL_OUT, READY . . . . . . . . . . . . -0.3V to +7V
EN, ACC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +(VCC1 + 0.3)V
Maximum Sink Current (SDA and SCL Pins) . . . . . . . . . . . . . . . . . . . . 20mA
Maximum Sink Current (READY pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . 7mA
Latch-Up Tested per JESD78, Level 2, Class A . . . . . . . . . . . . . . . . . . 85°C
ESD Ratings. . . . . . . . . . . . . . . . . . . . . . See “ESD PROTECTION” on page 7
Operating Conditions
Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
VCC1 and VCC2 Supply Voltage Range . . . . . . . . . . . . . . . . . +2.3V to +5.5V
Thermal Resistance
JA (°C/W) JC (°C/W)
47
4
8 Ld TDFN Package (Notes 5, 6). . . . . . . . . .
(0.50mm Pitch)
8 Ld TDFN Package (Notes 5, 6). . . . . . . . . .
48
6
(0.65mm Pitch)
8 Ld MSOP Package (Notes 4, 7) . . . . . . . . .
151
50
8 Ld SOIC Package (Notes 4, 7) . . . . . . . . . .
120
56
Maximum Storage Temperature Range . . . . . . . . . . . . . -65°C to +150°C
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions can adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. JA is measured with the component mounted on a high-effective thermal conductivity test board in free air. See TB379 for details.
5. JA is measured in free air with the component mounted on a high-effective thermal conductivity test board with direct attach features. See TB379.
6. For JC, the case temperature location is the center of the exposed metal pad on the package underside.
7. For JC, the case temperature location is taken at the package top center.
Electrical Specifications
VEN = VCC1, VCC1 = +2.3V to +5.5V, VCC2 = +2.3V to +5.5V, unless otherwise noted (Note 8). Boldface limits apply
over the operating temperature range, -40°C to +85°C.
PARAMETER
SYMBOL
CONDITIONS
TEMP
(°C)
MIN
(Note 9)
TYP
MAX
(Note 9)
UNITS
POWER SUPPLIES
VCC1 Supply Range
VCC1
VCC2 Supply Range
VCC2
Supply Current from VCC1
ICC1
Supply Current from VCC2
ICC2
VCC1 Shutdown Supply
Current
ISHDN1
VCC2 Shutdown Supply
Current
ISHDN2
Full
2.3
-
5.5
V
ISL33002 and ISL33003
Full
2.3
-
5.5
V
VCC1 = 5.5V; ISL33001 only (Note 11)
Full
-
2.1
4.0
mA
VCC1 = VCC2 = 5.5V; ISL33002 and ISL33003
(Note 11)
Full
-
2.0
3.0
mA
VCC2 = VCC1 = 5.5V; ISL33002 and ISL33003
(Note 11)
Full
-
0.22
0.6
mA
VCC1 = 5.5V, VEN = GND; ISL33001 only
Full
-
0.5
-
µA
VCC1 = VCC2 = 5.5V, VEN = GND; ISL33003 only
(Note 13)
Full
-
0.05
-
µA
VCC1 = VCC2 = 5.5V, VEN = GND, ISL33003 only
(Note 13)
Full
-
0.06
-
µA
SDA and SCL pins floating
Full
0.8
1
1.2
V
START-UP CIRCUITRY
Precharge Circuitry
Voltage
VPRE
Enable High Threshold
Voltage
VEN_H
+25
-
0.5*VCC
0.7*VCC
V
Enable Low Threshold
Voltage
VEN_L
+25
0.3*VCC
0.5*VCC
-
V
Enable from 0V to VCC1; ISL33001 and
ISL33003
Full
-1
0.1
1
µA
-
10
-
ns
Enable Pin Input Current
IEN
Enable Delay, On-Off
tEN-HL
ISL33001 and ISL33003 (Note 10)
+25
Enable Delay, Off-On
tEN-LH
ISL33001 and ISL33003 (Figure 3)
+25
-
86
-
µs
Bus Idle Time
tIDLE
(Figure 4, Note 12)
Full
50
83
150
µs
Ready Pin OFF State
Leakage Current
IOFF
ISL33001 only
+25
-1
0.1
1
µA
Ready Delay, On-Off
tREADY-HL
ISL33001 only (Note 10)
+25
-
10
-
ns
FN7560 Rev 6.01
Feb 24, 2022
Page 6 of 20
ISL33001, ISL33002, ISL33003
Electrical Specifications
VEN = VCC1, VCC1 = +2.3V to +5.5V, VCC2 = +2.3V to +5.5V, unless otherwise noted (Note 8). Boldface limits apply
over the operating temperature range, -40°C to +85°C. (Continued)
PARAMETER
SYMBOL
CONDITIONS
TEMP
(°C)
MIN
(Note 9)
TYP
MAX
(Note 9)
UNITS
Ready Delay, Off-On
tREADY-LH
ISL33001 only (Note 10)
+25
-
10
-
ns
Ready Output Low Voltage
VOL_READY
VCC1 = +2.5V, IPULLUP = 3mA; ISL33001 only
Full
-
-
0.4
V
Transient Accelerator
Current
ITRAN_ACC
VCC1 = 2.7V, VCC2 = 2.7V ; (ACC = 0.7*VCC1 for
ISL33002 only) (Figure 8)
+25
-
5
-
mA
Accelerator Pin Enable
Threshold
VACC_EN
ISL33002 only
+25
-
0.5*VCC1
0.7*VCC1
V
Accelerator Pin Disable
Threshold
VACC_DIS
ISL33002 only
+25
0.3*VCC1
0.5*VCC1
-
V
IACC
ISL33002 only
+25
-1
0.1
1
µA
ISL33002 only (Note 10)
+25
-
10
-
ns
SDA, SCL I/O Pins
Human Body Model, SDA and SCL pins to ground
only (JESD22-A114)
+25
-
±12
-
kV
All Pins
Machine Model (JESD22-A115)
+25
-
±400
-
V
Class 3 HBM ESD (JESD22-A114)
+25
±6
-
kV
RISE-TIME ACCELERATORS
Accelerator Pin Input
Current
Accelerator Delay, On-Off
tPDOFF
ESD PROTECTION
INPUT-OUTPUT CONNECTIONS
Input Low Threshold
VIL
VCC1 = VCC2, 10kto VCC1 on SDA and SCL pins
+25
-
-
0.3*VCC1
V
Input-Output Offset
Voltage
VOS
VCC1 = 3.3V, 10kto VCC1 on SDA and SCL pins,
VINPUT = 0.2V; VCC2 = 3.3V, ISL33002 and
ISL33003 (Figure 5)
Full
0
50
150
mV
Output Low Voltage
VOL
VCC1 = 2.7V, VINPUT = 0V, ISINK = 3mA on
SDA/SCL pins; VCC2 = 2.7V, ISL33002 and
ISL33003 (Figure 6)
Full
-
-
0.4
V
Buffer SDA and SCL Pins
Input Capacitance
CIN
(Figure 27)
+25
-
10
-
pF
ILEAK
SDA and SCL pins = VCC1 = 5.5V;
VCC2 = 5.5V, ISL33002 and ISL33003
Full
-5
0.1
5
µA
SCL/SDA Propagation
Delay High-to-Low
tPHL
CLOAD = 100pF, 2.7kto VCC1 on SDA and SCL
pins, VCC1 = 3.3V; VCC2 = 3.3V, ISL33002 and
ISL33003 (Figure 7)
+25
0
27
100
ns
SCL/SDA Propagation
Delay Low-to-High
tPLH
CLOAD = 100pF, 2.7kto VCC1 on SDA and SCL
pins, VCC1 = 3.3V; VCC2 = 3.3V, ISL33002 and
ISL33003 (Figure 7)
+25
0
2
26
ns
Input Leakage Current
TIMING CHARACTERISTICS
NOTES:
8. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
9. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
10. Typical value determined by design simulations. Parameter not tested.
11. Buffer is in the connected state.
12. ISL33002 and ISL33003 limits established by characterization. Not production tested.
13. If the VCC1 and VCC2 voltages diverge, then the shut down ICC increases on the higher voltage supply.
FN7560 Rev 6.01
Feb 24, 2022
Page 7 of 20
ISL33001, ISL33002, ISL33003
Test Circuits and Waveforms
- VSDA_IN = VSDA_OUT = VSCL_OUT = VEN = VCC
- SDA_OUT and SCL pins connected to VCC
- Enable Delay Time Measured on ISL33001 only
- ISL33003 performance inferred from ISL33001
- If tDELAY1 < tEN-LH then tDELAY2 = tEN-LH + tIDLE + tREADY-LH
- If tDELAY1 > tEN-LH then tDELAY2 = tEN-LH + tREADY-LH
- EN Logic Input must be high for t > Enable Delay (tEN_LH)
prior to SCL_IN transition
- Bus Idle Time Measured on ISL33001 only
- ISL33002 and ISL33003 performance inferred from ISL33001
VEN
VCC
VCC
0.5*VCC
0V
VSDA_IN
VREADY
VCC
0.5*VCC
0.5*VCC
0.5VCC
VSCL_IN
0V
VCC
0V
0.5VCC
VREADY
0V
tDELAY1
tREADY-LH
tDELAY2
tIDLE
FIGURE 3. ENABLE DELAY TIME
FIGURE 4. BUS IDLE TIME
+3.3V
10kΩ
10kΩ
VCC1
SCL_OUT
10kΩ
SDA_OUT
0.2V
SCL_IN OR
SDA_IN
10kΩ
SDA_IN
SCL_IN
GND
VIN
0.2V
VO
SCL_OUT OR
SDA_OUT
VIN
0.2V
VOS = VO - 0.2V
FIGURE 5A. TEST CIRCUIT
FIGURE 5B. MEASUREMENT POINTS
FIGURE 5. INPUT TO OUTPUT OFFSET VOLTAGE
+2.7V
900Ω
900Ω
VCC1
SCL_OUT
900Ω
VCC1
SDA_OUT
900Ω
SCL_OUT
SDA_IN
SCL_IN
VOL
VCC1
GND
0V
0V
SDA_OUT
FIGURE 6A. TEST CIRCUIT
VOL
FIGURE 6B. MEASUREMENT POINTS
FIGURE 6. OUTPUT LOW VOLTAGE
FN7560 Rev 6.01
Feb 24, 2022
Page 8 of 20
ISL33001, ISL33002, ISL33003
Test Circuits and Waveforms (Continued)
+3.3V
SCL_IN OR
SDA_IN
2.7kΩ
2.7kΩ
VCC1
SCL_OUT
2.7kΩ
SDA_OUT
2.7kΩ
SCL_OUT OR
SDA_OUT
SDA_IN
SCL_IN
GND
VIN
VIN
100pF
100pF
100pF
*tPLH
100pF
*tPHL
*Propagation delay measured between 50% of VCC1
FIGURE 7A. TEST CIRCUIT
FIGURE 7B. MEASUREMENT POINTS
FIGURE 7. PROPAGATION DELAY
ITRAN_ACC = CV/t
V/t is for only the accelerator
portion of the waveform
*V
VCC1
2.7kΩ
2.7kΩ
SCL_OUT
VCC1
SDA_IN
SCL_IN
2nF
SDA_OUT
GND
*V
VCC1
X
2.7kΩ
10kΩ
100kΩ
X
10kΩ
10kΩ
SCL_OUT
VCC1
10kΩ
SDA_OUT
SDA_IN
SCL_IN
GND
*V < V
X
CC1
(See Figure 24)
FIGURE 8. ACCELERATOR CURRENT TEST CIRCUIT
FN7560 Rev 6.01
Feb 24, 2022
FIGURE 9. ACCELERATOR PULSE WIDTH TEST CIRCUIT
Page 9 of 20
ISL33001, ISL33002, ISL33003
SDA_IN
SDA_OUT
U1
M2
M1
U2
RISE TIME
ACCELERATOR
READY
ISL33001 ONLY
M5
LOGIC CONTROL
START-UP CIRCUITRY
VCC1
VCC2
ISL33002 AND ISL33003
EN
ISL33001 AND ISL33003
SCL_IN
PRECHARGE
CIRCUIT
ACC
ISL33002 ONLY
SCL_OUT
U3
M4
M3
U4
FIGURE 10. CIRCUIT BLOCK DIAGRAM
FN7560 Rev 6.01
Feb 24, 2022
Page 10 of 20
ISL33001, ISL33002, ISL33003
Application Information
The ISL33001, ISL33002, ISL33003 ICs are 2-Wire Bidirectional
Bus Buffers designed to drive heavy capacitive loads in
open-drain/open-collector systems. The ISL33001, ISL33002,
ISL33003 incorporate rise time accelerator circuitry that
improves the rise time for systems that use a passive pull-up
resistor for logic HIGH. These devices also feature hot swapping
circuitry for applications that require hot insertion of boards into
a host system (i.e., servers racks and I/O card modules). The
ISL33001 features a logic output flag (READY) that signals the
status of the buffer and an EN pin to enable or disable the buffer.
The ISL33002 features two separate supply pins for voltage level
shifting on the I/O pins and a logic input to disable the rise time
accelerator circuitry. The ISL33003 features an EN pin and the
level shifting functionality.
I2C and SMBUS Compatibility
The ISL33001, ISL33002, ISL33003 ICs are I2C and SMBUS
compatible devices, designed to work in open-drain/open-collector
bus environments. The ICs support both clock stretching and bus
arbitration on the SDA and SCL pins. They are designed to operate
from DC to more than 400kHz, supporting Fast Mode data rates of
the I2C specification.In addition, the buffer rise time accelerators
are designed to increase the capacitive drive capability of the bus.
With careful choosing of components, driving a bus with the I2C
specified maximum bus capacitance of 400pF at 400kHz data rate
is possible.
Start-Up Sequencing and Hot Swap Circuitry
The ISL33001, ISL33002, ISL33003 buffers contain
undervoltage lock out (UVLO) circuitry that prevents operation of
the buffer until the IC receives the proper supply voltage. For
VCC1 and VCC2, this voltage is approximately 1.8V on the rising
edge of the supply voltage. Externally driven signals at the
SDA/SCL pins are ignored until the device supply voltage is
above 1.8V. This prevents communication errors on the bus until
the device is properly powered up. The UVLO circuitry is also
triggered on the falling edge when the supply voltage drops
below 1.7V.
Once the IC comes out of the UVLO state, the buffer remains
disconnected until it detects a valid connection state. A valid
connection state is either a BUS IDLE condition (see Figure 4) or a
STOP BIT condition (a rising edge on SDA_IN when SCL_IN is high)
along with the SCL_OUT and SDA_OUT pins being logic high.
Note: For the ISL33001 and ISL33003 with EN pins, after coming
out of UVLO, there will be an additional delay from the enable
circuitry if the EN pin voltage is not rising at the same time as the
supply pins (see Figure 3) before a valid connection state can be
established.
Coming out of UVLO but prior to a valid connection state, the SDA
and SCL pins are pre-charged to 1V to allow hot insertion.
Because the bus at any time can be between 0V and VCC,
pre-charging the I/O pins to 1V reduces the maximum
differential voltage from the buffer I/O pin and the active bus.
The pre-charge circuitry reduces system disturbance when the IC
is hot plugged into a live back plane that may have the bus
communicating with other devices.
FN7560 Rev 6.01
Feb 24, 2022
Note: For The ISL33001 and ISL33003 with EN pins, the
pre-charge circuitry is active only after coming out of UVLO and
having the device enabled.
Connection Circuitry
Once a valid connection condition is met, the buffer is active and
the input stage of the SDA/SCL pins is controlled by external
drivers. The output of the buffer will follow the input of the buffer.
The directionality of the IN/OUT pins are not exclusive
(bi-directional operation) and functionally behave identical to
each other. Being a two channel buffer, the SDA and SCL pins
also behave identically. In addition, the SDA and SCL portions of
the buffer are independent from each other. The SDA pins can be
driven in one direction while the SCL pins can be driven opposite.
Refer to Figure 10 for the operation of the bi-directional buffer.
When the input stage of the buffer on one side is driven low by an
external device, the output of the buffer drives an open-drain
transistor to pull the ‘output’ pin low. The ‘output’ pin will
continue to be held low by the transistor until the external driver
on the ‘input’ releases the bus.
To prevent the buffer from entering a latched condition where
both internal transistors are actively pulling the I/O pins low, the
buffer is designed to be active in only one direction. The buffer
logic circuitry senses, which input stage is being externally driven
low and sets that buffer to be the active one. For example,
referring to Figure 10, if SDA_OUT is externally driven low, buffer
U2 will be active and buffer U1 is inactive. M1 is turned on to
drive SDA_IN low, effectively buffering the signal from SDA_OUT
to SDA_IN. The low signal at the input of U1 will not turn M2 on
because U1 remains inactive, preventing a latch condition.
Buffer Output Low and Offset Voltage
By design, when a logic input low voltage is forced on the input of
the buffer, the output of the buffer will have an input to output
offset voltage. The output voltage of the buffer is determined by
Equation 1:
V OUT = V IN + V OS + V CC /R PULL-UP r ON
(EQ. 1)
Where VOS is the buffer internal offset voltage, RPull-Up is the
pull-up resistance on the SDA/SCL pin to VCC and rON is the
ON-resistance of the buffer’s internal NMOS pull-down device.
The last term of the equation is the additional voltage drop
developed by sink current and the internal resistance of the
transistor. The VOS of the buffer can be determined by
Figures 21, 22 and is typically 40mV. Reducing the pull-up
resistor values increases the sink current and increases the
output voltage of the buffer for a given input low voltage
(Figures 19, through 22).
Rise Time Accelerators
The ISL33001, ISL33002, ISL33003 buffer rise time
accelerators on the SDA/SCL pins improve the transient
performance of the system. Heavy load capacitance or weak
pull-up resistors on an Open-Drain bus cause the rise time to be
excessively long, which leads to data errors or reduced data rate
performance. The rise time accelerators are only active on the
low-to-high transitions and provide an active constant current
source to slew the voltage on the pin quickly (Figure 23).
Page 11 of 20
ISL33001, ISL33002, ISL33003
The rise time accelerators are triggered immediately after the
buffer release threshold (approximately 30% of VCC) on both
sides of the buffer is crossed. Once triggered, the accelerators
are active for a defined pulse width (Figure 24) with the current
source turning off as it approaches the supply voltage.
Enable Pin (ISL33001 and ISL33003)
When driven high, the enable pin puts the buffer into its normal
operating state. After power-up, EN high will activate the bus
pre-charge circuitry and wait for a valid connection state to
enable the buffer and the accelerator circuitry.
Driving the EN pin low disables the accelerators, disables the
buffer so that signals on one side of the buffer will be isolated
from the other side, disables the pre-charge circuit and places
the device in a low power shutdown state.
READY Logic Pin (ISL33001 Only)
The READY pin is a digital output flag for signaling the status of
the buffer. The pin is the drain of an Open-Drain NMOS. Connect
a resistor from the READY pin to VCC1 to provide the high pull-up.
The recommended value is 10kΩ.
When the buffer is disabled by having the EN pin low or if the
start-up sequencing is not complete, the READY pin will be pulled
low by the NMOS. When the buffer has the EN pin high and a
valid connection state is made at the SDA/SCL pins, the READY
pin will be pulled high by the pull-up resistor. The READY pin is
capable of sinking 3mA when pulled low while maintaining a
voltage of less than 0.4V.
ACC Accelerator Pin (ISL33002 Only)
The ACC logic pin controls the rise time accelerator circuitry of
the buffer. When ACC is driven high, the accelerators are enabled
and will be triggered when crossing the buffer release threshold.
When ACC is driven low, the accelerators are disabled.
For high-to-low transitions, there is a finite propagation delay
through the buffer from the time an external low on the input
drives the NMOS output low. This propagation delay will always
be positive because the buffer connect threshold on the falling
edge is below the measurement points of the delay. In addition
to the propagation delay of the buffer, there will be additional
delay from the different capacitive loading of the buffer.
Figures 25 and 26 show how the propagation delay from high-tolow, tPHL, is affected by VCC and capacitive loading.
The buffer’s propagation delay times for rising and falling edge
signals must be taken into consideration for the timing
requirements of the system. SETUP and HOLD times may need to
be adjusted to take into account excessively long propagation
delay times caused by heavy bus capacitances.
Pull-Up Resistor Selection
While the ISL33001, ISL33002, ISL33003 2-Channel buffers are
designed to improve the rise time of the bus in passive pull-up
systems, proper selection of the pull-up resistor is critical for
system operation when a buffer is used. For a bus that is
operating normally without active rise time circuitry, using the
ISL33001, ISL33002, ISL33003 buffer allows larger pull-up
resistor values to reduce sink currents when the bus is driving
low. However, choose a pull-up resistor value of no larger than
20kΩ regardless of the bus capacitance seen on the SDA/SCL
lines. The Bus Idle or Stop Bit condition requires valid logic high
voltages to give a valid connection state. Pull-up resistor values
20kΩ or smaller are recommended to overcome the typical
150kΩ impedance of the pre-charge circuitry, delivering valid
high levels.
Level Shifting from 3.3V to 1.8V
For lightly loaded buses, having the accelerators active may
cause ringing or noise on the rising edge transition. Disabling the
accelerators will have the buffers continue to perform level
shifting with the VCC1 and VCC2 supplies and provide
capacitance buffering.
While the ISL3300x level shifters operate down to 2.3V, it is
possible to interface the ISL33002 to 1.8V sensors and micro
controller I/O without causing overshoot on the SCL and SDA
outputs. This is because the ISL33002 is the only device that
allows its accelerators to be disabled. The ISL33001 and
ISL33003, whose accelerators are always active, cause
overshoot on the I2C outputs that trigger the ESD cells of a 1.8V
slave device at the applied clock and data rates.
Propagation Delays
Figure 11 depicts the ISL33002, whose accelerators are disabled
by connecting the ACC pin (Pin 5) to ground.
On a low-to-high transition, the rising edge signal is determined
by the bus pull-up resistor, load capacitance, and the accelerator
current from the ISL33001, ISL33002, ISL33003 buffer. Prior to
the accelerators becoming active, the buffer is connected and
the output voltage will track the input of the buffer. When the
accelerators activate the buffer connection is released and the
signal on each side of the buffer rises independently. The
accelerator current on both sides of the buffer will be equal. If the
pull-up resistance on both sides of the buffer are also equal, then
differences in the rise time will be proportional to the difference
in capacitive loading on the two sides.
Because the signals on each side of the buffer rise
independently, the propagation delay can be positive or negative.
If the input side rises slowly relative to the output (i.e., heavy
capacitive loading on the input and light load on the output) then
the propagation delay tPLH is negative. If the output side rises
slowly relative to the input, tPLH is positive.
FN7560 Rev 6.01
Feb 24, 2022
3.3V
R1
SCL-IN
SDA-IN
R2
8
3
6
5
VCC1
VCC2
SCL_IN
SCL_O UT
SDA_IN
SDA_O UT
ACC
1.8V
D 1 (2.4V)
R3
GND
1
C1
R4
R5
2
SCL-OUT
7
4
ISL33002
SDA-OUT
R 1, R 2 = 10kΩ
R3 = 174 Ω
R 4, R 5 = 1.5kΩ
D1 = CDZV2 .4B
C1 = 0.1µF
FIGURE 11. LEVEL SHIFTING 3.3V I2C SIGNALS AT THE INPUT TO
1.8V SIGNALS AT THE OUTPUT
Page 12 of 20
ISL33001, ISL33002, ISL33003
Figure 12 shows the corresponding input and output signals.
SCL_IN
The supply of the output side (VCC2) is reduced to 2.4V, just 0.1V
above the specified minimum supply level. This ensures reliable
device operation, but also minimizes the distance between VCC2
and the external 1.8V bus voltage, which eases the internal
biasing of the output switches.
SCL_OUT
SDA_IN
VCC2 can be generated either by a separate 2.4V power supply,
or by deriving it from VCC1 using a 2.4V Zener diode and series
resistor, R3. The 100nF buffer capacitance, C1, is needed to
provide sufficient supply current during the switching of the
output stages.
SDA_OUT
2V/Div
With its accelerators disabled, the ISL33002 behaves like a
standard I2C buffer, whose high output steady states are purely
determined by the external 1.8V supply through the pull-up
resistors, R4 and R5. As shown in Figure 12, both I2C outputs are
without overshoot.
20µs/Div
FIGURE 12. 3.3V INPUT AND 1.8V OUTPUT SIGNALS FOR DISABLED
ACCELERATOR
Typical Performance Curves
CIN = COUT = 10pF, VCC1 = VCC2 = VCC, TA = +25°C; Unless Otherwise Specified.
2.4
600
2.3
550
T = -40°C
2.2
2.0
T = +25°C
450
T = +85°C
1.9
ICC1 (nA)
ICC1 (mA)
500
T = +25°C
2.1
1.8
1.7
1.6
T = +85°C
400
350
300
250
1.5
200
1.4
150
1.3
1.2
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
100
6.0
2.0
2.5
3.0
3.5
VCC1 (V)
4.5
5.0
5.5
6.0
FIGURE 14. ICC1 DISABLED CURRENT vs VCC1 (ISL33001)
FIGURE 13. ICC1 ENABLED CURRENT vs VCC1 (ISL33001)
2.4
60
VCC2 = 5.5V
2.3
VCC2 = 5.5V
2.2
50
2.1
T = -40°C
T = +85°C
2.0
40
T = +25°C
1.9
ICC1 (nA)
ICC1 (mA)
4.0
VCC1 (V)
1.8
1.7
1.6
T = +25°C
30
T = +85°C
20
1.5
1.4
10
1.3
1.2
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VCC1 (V)
FIGURE 15. ICC1 ENABLED CURRENT vs VCC1 (ISL33002 AND
ISL33003)
FN7560 Rev 6.01
Feb 24, 2022
6.0
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VCC1 (V)
FIGURE 16. ICC1 DISABLED CURRENT vs VCC1 (ISL33003)
Page 13 of 20
ISL33001, ISL33002, ISL33003
Typical Performance Curves (Continued)
CIN = COUT = 10pF, VCC1 = VCC2 = VCC, TA = +25°C; Unless Otherwise
60
0.24
T = +25°C
VCC1 = 5.5V
VCC1 = 5.5V
0.22
50
T = -40°C
40
T = +85°C
ICC2 (nA)
ICC2 (mA)
0.20
0.18
0.16
30
T = +25°C
T = +85°C
20
0.14
10
0.12
0.10
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
0
2.0
6.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VCC2 (V)
VCC2 (V)
FIGURE 17. ICC2 ENABLED CURRENT vs VCC2 (ISL33002 AND
ISL33003)
FIGURE 18. ICC2 DISABLED CURRENT vs VCC2 (ISL33003)
120
120
VCC = 2.3V
100
100
80
80
T = -40°C
T = +25°C
60
VOL (mV)
VOL (mV)
T = +85°C
VCC = 2.7V
40
40
VCC = 4.5V
VIN = 0V
0
1
2
3
4
5
6
7
VCC = 3.3V
VIN = 0V
20
20
0
60
8
9
10
0
0
11
1
2
3
4
IOL (mA)
FIGURE 19. SDA/SCL OUTPUT LOW VOLTAGE vs SINK CURRENT vs VCC
8
9
10
11
100
90
90
VCC = 5.5V
80
80
70
70
60
60
50
VCC = 3.3V
VCC = 2.3V
40
VOS (mV)
VOS (mV)
7
FIGURE 20. SDA/SCL OUTPUT LOW VOLTAGE vs SINK CURRENT vs
TEMPERATURE
100
30
20
10
10
0
1
2
3
4
5
6
IOL (mA)
7
8
9
10
11
FIGURE 21. INPUT TO OUTPUT OFFSET VOLTAGE vs SINK CURRENT
vs VCC
FN7560 Rev 6.01
Feb 24, 2022
T = +85°C
40
20
VIN = 0.2V
T = -40°C
T = +25°C
50
30
0
6
5
IOL (mA)
0
VCC = 3.3V
VIN = 0.2V
0
1
2
3
4
5
6
7
8
9
10
11
IOL (mA)
FIGURE 22. INPUT TO OUTPUT OFFSET VOLTAGE vs SINK CURRENT
vs TEMPERATURE
Page 14 of 20
ISL33001, ISL33002, ISL33003
Typical Performance Curves (Continued)
CIN = COUT = 10pF, VCC1 = VCC2 = VCC, TA = +25°C; Unless Otherwise
800
11
ACCELERATOR PULSE WIDTH (ns)
ACCELERATOR CURRENT (mA)
12
T = -40°C
10
9
8
T = +85°C
7
6
5
T = +25°C
4
3
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
700
T = +25°C
600
T = -40°C
T = +85°C
500
400
300
200
2.0
6.0
See Figure 9
2.5
3.0
3.5
VCC (V)
FIGURE 23. ACCELERATOR PULL-UP CURRENT vs VCC
50
T = +25°C
T = -40°C
10
0
2.0
2.5
3.0
3.5
4.0
4.5
VCC (V)
5.0
5.5
6.0
T = +85°C
30
20
5.5
50
PROPAGATION DELAY (ns)
PROPAGATION DELAY (ns)
40
5.0
FIGURE 24. ACCELERATOR PULSE WIDTH vs VCC
RPULL-UP = 2.7kΩ
CIN = 10pF
COUT = 100pF
T = +85°C
4.0
4.5
VCC (V)
40
30
T = +25°C
20
T = -40°C
VCC = 3.3V
RPULL-UP = 10kΩ
CIN = 50pF
10
0
0
6.0
FIGURE 25. PROPAGATION DELAY H-L vs VCC
100
200
300
400 500 600
COUT (pF)
700
800
900
FIGURE 26. PROPAGATION DELAY H-L vs COUT
Die Characteristics
12
11
SUBSTRATE AND TDFN THERMAL PAD POTENTIAL
(POWERED UP):
VCC = 2.3V
CAPACITANCE (pF)
VCC = 3.3V
GND
VCC = 5.5V
10
PROCESS:
0.25µm CMOS
9
8
7
6
-30
-10
10
30
50
70
90
TEMPERATURE (°C)
FIGURE 27. SDA/SCL PIN CAPACITANCE vs TEMPERATURE vs VCC
FN7560 Rev 6.01
Feb 24, 2022
Page 15 of 20
ISL33001, ISL33002, ISL33003
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest revision.
DATE
REVISION
CHANGE
Feb 24, 2022
6.01
Removed Related Literature and About Intersil sections.
Added TOC.
Updated Ordering Information Table by applying new formatting, updating notes, and adding parts.
Added Level Shifting from 3.3V to 1.8V section.
Updated PODs L8.6x6H and L8.3x3A to the latest version, changes are as follows:
- Tiebar Note updated
Updated POD M8.118 to the latest version, changes are as follows:
-Corrected typo in the side view 1 updating package thickness tolerance from ±010 to ±0.10.
Updated POD M8.15 to the latest version, changes are as follows:
-Added the coplanarity spec into the drawing.
July 11, 2014
6.00
In “Features” on page 1, changed “Low quiescent Current” from “2.2mA” to “2.1mA”.
On page 6, added “Pb-Free Reflow Profile” entry to “Thermal Info” section.
In “Electrical Spec” table on page 6, changed “VCC” to “VCC1” in the “Supply Current from VCC2” row.
In “Electrical Spec” table on page 7, for parameter “Input Low Threshold”, moved the “TYP” column
entry to the “MAX” column.
On page 8, Figure 4, clarified the associated notes.
On page 9, Figure 8, changed “IACC” to ITRAN_ACC”, and noted that the V/t is for the accelerator
portion of the waveform.
December 19, 2013
5.00
Added Note 13 at the end of the "Elec Spec" table on page 7 as follows:
“13. If the Vcc1 and Vcc2 voltages diverge, then the shut-down Icc increases on the higher voltage
supply."
Added reference "(Note 13)" after "ISL33003 only" in rows for Vcc1 and Vcc2 "Shut-down Supply
current" parameters (last 2 rows of "Power Supplies" section) on page 6.
October 12, 2012
4.00
Changed “SDA_IN, SCL_IN...0.3V to +(VCC1 + 0.3)V, SDA_OUT, SCL_OUT...0.3V to +(VCC2 + 0.3)V,
ENABLE, READY, ACC...0.3V to +(VCC1 + 0.3)V” to “SDA_IN, SCL_IN, SDA_OUT, SCL_OUT, READY...0.3V
to +7V; ENABLE, ACC...0.3V to +(VCC1 + 0.3)V”, in the Absolute Maximum Ratings section at the top of
page 6.
Removed “Pb-free Reflow Profile” and link from “Thermal Information” section at the top of page 6.
Added “open drain” and “Connect to 10kΩ pull-up resistor to VCC1.”, in Pin Descriptions in the READY
section on page 3.
October 11, 2011
3.00
Converted to new datasheet template.
Changed Title of datasheet from: “2-Wire Bus Buffer With Rise Time Accelerators and Hot Swap
Capability”
to: I2C Bus Buffer with Rise Time Accelerators and Hot Swap Capability
Pg 1, added to Related Literature: AN1637, “Level Shifting Between 1.8V and 3.3V Using I2C Buffers”
Replaced POD M8.118 Rev 3 with Rev 4 due to the following changes:
Corrected lead width dimension in side view 1 from "0.25 - 0.036" to "0.25 - 0.36"
Replaced POD M8.15 Rev 1 with Rev 3 due to the following changes:
Changed in Typical Recommended Land Pattern the following:
2.41(0.095) to 2.20(0.087)
0.76 (0.030) to 0.60(0.023)
0.200 to 5.20(0.205)
Figure 3 (was Fig1) - Added:
- If tDELAY1 < tEN-LH then tDELAY2 = tEN-LH + tIDLE + tREADY-LH
- If tDELAY1 > tEN-LH then tDELAY2 = tEN-LH + tREADY-LH
and replaced graph
September 13, 2010
2.00
Added SOIC package information to datasheet for ISL33001.
April 30, 2010
1.00
Changed typical value of “Supply Current from VCC1” on page 6 for ISL33001 only from 2.2mA to
2.1mA.
Changed typical value of “Input-Output Offset Voltage” on page 7 from 100mV to 50mV.
March 18, 2010
0.00
Initial Release.
FN7560 Rev 6.01
Feb 24, 2022
Page 16 of 20
ISL33001, ISL33002, ISL33003
Package Outline Drawings
For the most recent package outline drawing, see L8.3x3H.
L8.3x3H
8 Lead Thin Dual Flat No-Lead Plastic Package (TDFN)
Rev 1, 5/15
2.38
1.50 REF
3.00
A
PIN #1 INDEX AREA
6
PIN 1
INDEX AREA
6 X 0.50
6
B
1
8 X 0.40
4
2.20
3.00
(4X)
1.64
0.15
5
8
0.10 M C A B
TOP VIEW
8 X 0.25
BOTTOM VIEW
( 2.38 )
SEE DETAIL "X"
0 .80 MAX
0.10 C
C
BASE PLANE
SEATING PLANE
0.08 C
2 . 80
( 2 .20 )
SIDE VIEW
( 1.64 )
C
0.2 REF
8X 0.60
0 . 00 MIN.
0 . 05 MAX.
( 8X 0.25 )
DETAIL “X”
( 6X 0 . 5 )
NOTES:
TYPICAL RECOMMENDED LAND PATTERN
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Lead width dimension applies to the metallized terminal and is
measured between 0.15mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature and may be
located on any of the 4 sides (or ends).
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
FN7560 Rev 6.01
Feb 24, 2022
Page 17 of 20
ISL33001, ISL33002, ISL33003
For the most recent package outline drawing, see L8.3x3A.
L8.3x3A
8 Lead Thin Dual Flat No-Lead Plastic Package
Rev 5, 5/15
( 2.30)
3.00
( 1.95)
A
B
3.00
( 8X 0.50)
6
PIN 1
INDEX AREA
(4X)
(1.50)
( 2.90 )
0.15
PIN 1
TOP VIEW
(6x 0.65)
( 8 X 0.30)
TYPICAL RECOMMENDED LAND PATTERN
SEE DETAIL "X"
2X 1.950
6X 0.65
PIN #1
INDEX AREA
0.10 C
0.75 ±0.05
C
0.08 C
1
SIDE VIEW
6
1.50 ±0.10
8
8X 0.30 ±0.05
8X 0.30 ± 0.10
2.30 ±0.10
C
4
0.10 M C A B
0 . 2 REF
5
0 . 02 NOM.
0 . 05 MAX.
DETAIL "X"
BOTTOM VIEW
NOTES:
FN7560 Rev 6.01
Feb 24, 2022
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to ASME Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4.
Dimension applies to the metallized terminal and is measured
between 0.15mm and 0.20mm from the terminal tip.
5.
Tiebar shown (if present) is a non-functional feature and may be
located on any of the 4 sides (or ends).
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7.
Compliant to JEDEC MO-229 WEEC-2 except for the foot length.
Page 18 of 20
ISL33001, ISL33002, ISL33003
For the most recent package outline drawing, see M8.118.
M8.118
8 Lead Mini Small Outline Plastic Package
Rev 5, 5/2021
3.0 ±0.05
5
A
DETAIL "X"
D
8
1.10 MAX
SIDE VIEW 2
0.09 - 0.20
4.9 ±0.15
3.0 ±0.05
5
0.95 REF
PIN# 1 ID
1
2
B
0.65 BSC
GAUGE
PLANE
TOP VIEW
0.55 ±0.15
0.25
3°±3°
0.85 ±0.10
H
DETAIL “X”
C
SEATING PLANE
0.25 - 0.36
0.08 M C A-B D
0.10 ±0.05
0.10 C
SIDE VIEW 1
(5.80)
NOTES:
(4.40)
(3.00)
1. Dimensions are in millimeters.
(0.65)
(0.40)
(1.40)
TYPICAL RECOMMENDED LAND PATTERN
FN7560 Rev 6.01
Feb 24, 2022
2. Dimensioning and tolerancing conform to JEDEC MO-187-AA
and AMSEY14.5m-1994.
3. Plastic or metal protrusions of 0.15mm max per side are not
included.
4. Plastic interlead protrusions of 0.15mm max per side are not
included.
5. Dimensions are measured at Datum Plane “H”.
6. Dimensions in ( ) are for reference only.
Page 19 of 20
ISL33001, ISL33002, ISL33003
For the most recent package outline drawing, see M8.15.
M8.15
8 Lead Narrow Body Small Outline Plastic Package
Rev 5, 4/2021
FN7560 Rev 6.01
Feb 24, 2022
Page 20 of 20
IMPORTANT NOTICE AND DISCLAIMER
RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL
SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING
REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND
OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED,
INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for developers skilled in the art designing with Renesas products. You are solely responsible
for (1) selecting the appropriate products for your application, (2) designing, validating, and testing your application, and (3)
ensuring your application meets applicable standards, and any other safety, security, or other requirements. These
resources are subject to change without notice. Renesas grants you permission to use these resources only for
development of an application that uses Renesas products. Other reproduction or use of these resources is strictly
prohibited. No license is granted to any other Renesas intellectual property or to any third party intellectual property.
Renesas disclaims responsibility for, and you will fully indemnify Renesas and its representatives against, any claims,
damages, costs, losses, or liabilities arising out of your use of these resources. Renesas' products are provided only subject
to Renesas' Terms and Conditions of Sale or other applicable terms agreed to in writing. No use of any Renesas resources
expands or otherwise alters any applicable warranties or warranty disclaimers for these products.
(Rev.1.0 Mar 2020)
Corporate Headquarters
Contact Information
TOYOSU FORESIA, 3-2-24 Toyosu,
Koto-ku, Tokyo 135-0061, Japan
www.renesas.com
For further information on a product, technology, the most
up-to-date version of a document, or your nearest sales
office, please visit:
www.renesas.com/contact/
Trademarks
Renesas and the Renesas logo are trademarks of Renesas
Electronics Corporation. All trademarks and registered
trademarks are the property of their respective owners.
工商网监
湘ICP备2023018690号
