ISL34321INZ

16-Bit Long-Reach Video SERDES with Bi-directional Side-Channel ISL34321 The ISL34321 is a serializer/deserializer of LVCMOS parallel video data. The video data presented to the serializer on the parallel LVCMOS bus is serialized into a high-speed differential signal. This differential signal is converted back to parallel video at the remote end by the deserializer. It also transports auxiliary data bidirectionally over the same link during the video vertical retrace interval. I2C bus mastering allows the placement of external slave devices on the remote side of the link. An I2C controller can be place on either side of the link allowing bidirectional I2C communication through the link to the external devices on the other side. Both chips can be fully configured from a single controller or independently by local controllers. ISL34321 Features • 16-bit RGB transport over single differential pair • 6MHz to 45MHz pixel clock rates • Bi-directional auxiliary data transport without extra bandwidth and over the same differential pair • Hot plugging with automatic resynchronization every HSYNC. • I2C Bus Mastering to the remote side of the link with a controller on either the serializer or deserializer • Selectable clock edge for parallel data output • DC balanced with industry standard 8b/10b line code allows AC-coupling - Provides immunity against ground shifts • 16 programmable settings each for transmitter amplitude boost and pre-emphasis and receiver equalization allow for longer cable lengths and higher data rates • Same device for serializer and deserializer simplifies inventory Applications*(see page 12) • Video entertainment systems • Industrial computing terminals • Remote cameras Related Literature*(see page 12) • See ISL34341 datasheet FN6827 “WSVGA 24-Bit Long-Reach Video SERDES with Bi-directional SideChannel” Typical Application 3.3V 1.8V VDD_IO 3.3V 1.8V VDD_IO VDD_P VDD_TX RSTB/PDB VDD_TX VDD_P 16 RSTB/PDB VDD_AN VDD_CR VDD_AN VDD_CDR VDD_CR VDD_CDR VDD_IO VDD_IO 16 RGBA/C 27nF 10m DIFFERENTIAL CABLE SERIOP 27nF SERION REF_CLK VIDEO_TX REF_RES 27nF SERIOP 27nF SERION PCLK_IN GND_CR GND_AN GND_P GND_TX GND_CDR GND_IO REF_RES RGBA/C VIDEO SOURCE VSYNC HSYNC DATAEN PCLK_IN ISL34321 ISL34321 VSYNC HSYNC DATAEN PCLK_OUT VIDEO_TX VIDEO TARGET GND_CR GND_AN GND_P GND_TX GND_CDR GND_IO I2CA0 3.16 KΩ 3.16 KΩ VDD_IO VDD_IO September 23, 2010 FN6870.1 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2009, 2010. All Rights Reserved All other trademarks mentioned are the property of their respective owners. I2CA0 ISL34321 Block Diagram SCL SDA I2C VCM GENERATOR RAM PREEMPHASIS 3 V/H/DE TDM RGB 16 RX EQ 8b/10b MUX DEMUX SERION TX SERIOP VIDEO_TX (HI) CDR PCLK_IN (REF_CLK WHEN VIDEO_TX IS LO) PCLK_OUT x20 x20 Pin Configuration ISL34321 (48 LD EPTQFP) TOP VIEW GND_CDR VDD_CDR REF_RES MASTER GND_AN VDD_AN GND_TX VDD_TX SERION SERIOP I2CA0 36 35 34 33 32 31 30 29 28 27 26 25 GND_IO VDD_IO PCLK_OP RGBA0 RGBA1 RGBA2 RGBA3 RGBA4 RGBA5 RGBA6 RGBA7 GND_IO 37 38 39 40 41 42 43 44 45 46 47 48 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 16 15 14 13 9 10 11 12 SDA SCL VDD_P GND_P PCLK_IN VIDEO_TX VHSYNCPOL VSYNC HSYNC DATAEN VDDCR GNDCR RGBC0 RGBC1 RGBC2 RGBC3 RGBC4 RGBC5 RGBC6 RGBC7 STATUS VDD_IO 2 RSTB/PDB TEST_EN I2CA1 FN6870.1 September 23, 2010 ISL34321 Pin Descriptions DESCRIPTION PIN NUMBER 47, 45, 43, 41, 9, 7, 5, 3, 46 44 42 40 8 6 4 2 PIN NAME RGBA7, RGBA5, RGBA3, RGBA1, RGBC7, RGBC5, RGBC3, RGBC1, RGBA6 RGBA4 RGBA2 RGBA0 RGBC6 RGBC4 RGBC2 RGBC0 SERIALIZER Parallel video data LVCMOS inputs with Hysteresis DESERIALIZER Parallel video data LVCMOS outputs 16 17 15 20 39 33, 32 18 HSYNC VSYNC DATAEN PCLK_IN PCLK_OUT SERIOP, SERION VHSYNCPOL Horizontal (line) Sync LVCMOS input with Hysteresis Vertical (frame) Sync LVCMOS input with Hysteresis Video Data Enable LVCMOS input with Hysteresis Pixel clock LVCMOS input Default; not used High-speed differential serial I/O CMOS input for HSYNC and VSYNC Polarity 1: HSYNC & VSYNC active low 0: HSYNC & VSYNC active high CMOS input for video flow direction 1: video serializer 0: video deserializer I2C Interface Pins (I2C DATA, I2C CLK) Horizontal (line) Sync LVCMOS output Vertical (frame) Sync LVCMOS output Video Data Enable LVCMOS output PLL reference clock LVCMOS input Recovered clock LVCMOS output High speed differential serial I/O 19 VIDEO_TX 24, 23 25, 26 27 SDA, SCL (Note 1) I2CA[1:0] (Note 1) I2C Device Address MASTER I2C Master Mode 1: Master 0: Slave CMOS input for Reset and Power-down. For normal operation, this pin must be forced high. When this pin is forced low, the device will be reset. If this pin stays low, the device will be in PD mode. CMOS output for Receiver Status: 1: Valid 8b/10b data received 0: otherwise Note: serializer and deserializer switch roles during side-channel reverse traffic Analog bias setting resistor connection; use 3.16kΩ ±1% to ground PLL Ground Digital (Parallel and Control) Ground 12 RSTB/PDB 10 STATUS 28 21 37, 48 35 31 29 13 14 34 30 REF_RES GND_P (Note 2) GND_IO (Note 2) GND_CDR (Note 2) Analog (Serial) Data Recovery Ground GND_TX (Note 2) GND_AN (Note 2) GND_CR (Note 2) VDD_CR VDD_TX VDD_AN Analog (Serial) Output Ground Analog Bias Ground Core Logic Ground Core Logic VDD Analog (Serial) Output VDD Analog Bias VDD 3 FN6870.1 September 23, 2010 ISL34321 Pin Descriptions (Continued) DESCRIPTION PIN NUMBER 36 1, 38 22 11 Exposed Pad NOTES: 1. Pins with the same name are internally connected together. However, this connection must NOT be used for connecting together external components or features. 2. The various differently-named Ground pins are internally weakly connected. They must be tied together externally. The different names are provided to assist in minimizing the current loops involved in bypassing the associated supply VDD pins. In particular, for ESD testing, they should be considered a common connection PIN NAME VDD_CDR VDD_IO (Note 1) VDD_P TEST_EN PD SERIALIZER Analog (Serial) Data Recovery VDD Digital (Parallel and Control) VDD PLL VDD Must be connected to ground Must be connected to ground DESERIALIZER Ordering Information PART NUMBER (Notes 3, 4, 5) ISL34321INZ PART MARKING ISL34321 INZ TEMP. RANGE (°C) -40 to +85 PACKAGE (Pb-free) 48 Ld EPTQFP PKG. DWG. # Q48.7x7B 3. Add “-T13” suffix for tape and reel. Please refer to TB347 for details on reel specifications. 4. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 5. For Moisture Sensitivity Level (MSL), please see device information page for ISL34321. For more information on MSL please see techbrief TB363. 4 FN6870.1 September 23, 2010 ISL34321 Absolute Maximum Ratings Supply Voltage VDD_P to GND_P, VDD_TX to GND_TX, VDD_IO to GND_IO . . . . . . . . . . . . . . . . -0.5V to 4.6V VDD_CDR to GND_CDR, VDD_CR to GND_CR -0.5V to 2.5V Between any pair of GND_P, GND_TX, GND_IO, GND_CDR, GND_CR . . . . . . . . . . -0.1V to 0.1V 3.3V Tolerant LVTTL/LVCMOS Input Voltage . . . . . . . . . . . . . . . .-0.3V to VDD_IO+0.3V Differential Input Voltage . . . . . . . .-0.3V to VDD_IO + 0.3V Differential Output Current . . . . . . . . Short Circuit Protected LVTTL/LVCMOS Outputs . . . . . . . . . . Short Circuit Protected ESD Rating Human Body Model All pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4kV SERIOP/N (all VDD Connected, all GND Connected) . 8kV Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . 200V Latch Up (Tested per JESD-78B; Class2, Level A). . . .100mA Thermal Information Thermal Resistance (Typical) θJA θJC (°C/W) EPTQFP (Notes 6, 7) . . . . . . . . . . . 38 12 Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . 327mW Maximum Junction Temperature . . . . . . . . . . . . . . +125°C Maximum Storage Temperature Range . . . -65°C to +150°C Operating Temperature Range . . . . . . . . . . -40°C to +85°C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 6. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 7. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside. Electrical Specifications Unless otherwise indicated, all data is for: VDD_CDR = VDD_CR = 1.8V, VDD_IO = 3.3V, VDD_TX = VDD_P = VDD_AN = 3.3V, TA = +25°C, Ref_Res = 3.16kΩ, High-speed AC-coupling capacitor = 27nF. SYMBOL CONDITIONS MIN TYP MAX UNITS PARAMETER POWER SUPPLY VOLTAGE VDD_CDR, VDD_CR VDD_TX, VDD_P, VDD_AN, VDD_IO 1.7 3.0 1.8 3.3 1.9 3.6 V V SERIALIZER POWER SUPPLY CURRENTS Total 1.8V Supply Current Total 3.3V Supply Current DESERIALIZER POWER SUPPLY CURRENTS Total 1.8V Supply Current Total 3.3V Supply Current POWER-DOWN SUPPLY CURRENT Total 1.8V Power-Down Supply Current Total 3.3V Power-Down Supply Current PARALLEL INTERFACE High Level Input Voltage Low Level Input Voltage Input Leakage Current High Level Output Voltage Low Level Output Voltage Output Short Circuit Current VIH VIL IIN VOH VOL IOSC IOH = -4.0mA, VDD_IO = 3.0V IOL = 4.0mA, VDD_IO = 3.6V -1 2.6 0.4 35 ±0.01 2.0 0.8 1 V V µA V V mA RSTB = GND 10 0.5 mA mA PCLK_IN = 45MHz (Note 8) 66 50 76 63 mA mA PCLK_IN = 45MHz (Note 8) 62 40 80 52 mA mA 5 FN6870.1 September 23, 2010 ISL34321 Electrical Specifications Unless otherwise indicated, all data is for: VDD_CDR = VDD_CR = 1.8V, VDD_IO = 3.3V, VDD_TX = VDD_P = VDD_AN = 3.3V, TA = +25°C, Ref_Res = 3.16kΩ, High-speed AC-coupling capacitor = 27nF. (Continued) SYMBOL tOR/tOF CONDITIONS Slew rate control set to min CL = 8pF Slew rate control set to max, CL = 8pF SERIALIZER PARALLEL INTERFACE PCLK_IN Frequency PCLK_IN Duty Cycle Parallel Input Setup Time Parallel Input Hold Time DESERIALIZER PARALLEL INTERFACE PCLK_OUT Frequency PCLK_OUT Duty Cycle PCLK_OUT Period Jitter (rms) PCLK_OUT Spread Width PCLK_OUT to Parallel Data Outputs (includes Sync and DE pins) Deserializer Output Latency fOUT tODC tOJ tOSPRD tDV tCPD Clock randomizer off Clock randomizer on Relative to PCLK_OUT, (Note 9) Inherent in the design -1.0 4 9 6 50 0.5 ±20 5.5 14 45 MHz % %tPCLK %tPCLK ns PCLK fIN tIDC tIS tIH 6 40 3.5 1.0 50 45 60 MHz % ns ns MIN TYP 1 4 MAX UNITS ns ns PARAMETER Output Rise and Fall Times DESERIALIZER REFERENCE CLOCK (REF_CLK IS FED INTO PCLK_IN) REF_CLK Lock Time REF_CLK to PCLK_OUT Maximum Frequency Offset HIGH-SPEED TRANSMITTER HS Differential Output Voltage, Transition Bit VODTR TXCN = 0x00 TXCN = 0x0F TXCN = 0xF0 TXCN = 0xFF HS Differential Output Voltage, NonTransition Bit VODNTR TXCN = 0x00 TXCN = 0x0F TXCN = 0xF0 TXCN = 0xFF HS Generated Output Common Mode Voltage HS Common Mode SerializerDeserializer Voltage Difference HS Differential Output Impedance HS Output Latency HS Output Rise and Fall Times HS Differential Skew HS Output Random Jitter HS Output Deterministic Jitter VOCM ΔVCM ROUT tLPD tR/tF tSKEW tRJ tDJ PCLK_IN = 45MHz PCLK_IN = 45MHz Inherent in the design 20% to 80% 80 4 650 650 800 900 1100 1300 800 900 430 600 2.35 10 100 7 150