ISL34340_0806

IGNS D ES T EW R T PA OR N ED F A C EM E N ND MME EPL Data Sheet ECO NDED R 341 TR NO L3 4 ME IS OM R EC ® ISL34340 June 23, 2008 FN6255.1 WSVGA 24-Bit Long-Reach Video SERDES with Bidirectional Side-Channel The ISL34340 is a serializer/deserializer of LVCMOS parallel video data. The video data presented to the serializer on the parallel LVCMOS bus is serialized into a high-speed differential signal. This differential signal is converted back to parallel video at the remote end by the deserializer. It also transports auxiliary data bidirectionally over the same link during the video vertical retrace interval. Features • 24-bit RGB transport over single differential pair • Bidirectional auxiliary data transport without extra bandwidth and over the same differential pair • 40MHz PCLK transports - SVGA 800x600 @ 70fps, 16% blanking - WSVGA 1024x600 @ 60fps, 8% blanking • Internal 100Ω termination on high-speed serial lines • DC balanced 8b/10b line code allows AC-coupling - Provides immunity against ground shifts Ordering Information PART NUMBER (Note) PART MARKING TEMP. RANGE (°C) PACKAGE (Pb-free) PKG. DWG. # • Transmitter amplitude boost and pre-emphasis and receiver equalization allow for longer cable lengths and higher data rates • Same device for serializer and deserializer simplifies inventory • I2C interface • High-speed serial lines meet 8kV ESD rating • Pb-free (RoHS compliant) ISL34340INZ* ISL34340INZ -40 to +85 64 Ld EPTQFP Q64.10x10B *Add “-T13” suffix for tape and reel. Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. Applications • Navigation and display systems • Video entertainment systems • Industrial computing terminals • Remote cameras 3.3V 1.8V VDD_IO 3.3V 1.8V VDD_IO VDD_AN VDD_CR VDD_AN VDD_CDR VDD_CR RSTB/PDB VDD_CDR VDD_TX VDD_TX VDD_IO VDD_IO VDD_P VDD_P 24 RSTB/PDB 24 RGBA/B/C 27nF 10m DIFFERENTIAL CABLE 27nF SERIOP SERIOP 27nF 27nF RGBA/B/C VIDEO SOURCE VSYNC HSYNC DATAEN PCLK_IN ISL34340 SERION REF_CLK VIDEO_TX SERION PCLK_IN ISL34340 VSYNC HSYNC DATAEN PCLK_OUT VIDEO_TX VIDEO SINK GND_CR GND_AN GND_P GND_TX GND_CDR GND_IO GND_CR GND_AN GND_P GND_TX GND_CDR GND_IO REF_RES REF_RES I2CA0 3.16 KΩ VDD_IO 3.16 KΩ VDD_IO 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2008. All Rights Reserved All other trademarks mentioned are the property of their respective owners. I2CA0 ISL34340 Pinout ISL34340 (64 LD EPTQFP) TOP VIEW GND_IO VDD_CDR VDD_CDR GND_CDR GND_CDR VDD_TX GND_TX SERIOP SERION GND_TX VDD_AN GND_AN REF_RES TEST I2CA0 I2CA1 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 Block Diagram SCL SDA I2C VCM GENERATOR RAM PREEMPHASIS 3 V/H/DE TDM RGB 24 RX EQ 8b/10b MUX DEMUX SERION TX SERIOP VIDEO_TX (HI) CDR PCLK_IN (REF_CLK WHEN VIDEO_TX IS LO) PCLK_OUT x30 ÷30 2 VDD_IO RGBB4 RGBB5 RGBB6 RGBB7 RGBC0 RGBC1 RGBC2 RGBC3 RGBC4 RGBC5 RGBC6 RGBC7 STATUS TEST_EN RSTB/PDB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 VIDEO_TX VDD_IO PCLK_OUT RGBA0 RGBA1 RGBA2 RGBA3 RGBA4 RGBA5 RGBA6 RGBA7 RGBB0 RGBB1 RGBB2 RGBB3 GND_IO 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 I2CA2 I2CA3 SDA SCL VDD_P GND_P PCLK_IN VSYNCPOL HSYNCPOL VSYNC HSYNC DATAEN VDD_CR VDD_CR GND_CR GND_CR FN6255.1 June 23, 2008 ISL34340 Absolute Maximum Ratings Supply Voltage VDD_P to GND_P, VDD_TX to GND_TX, VDD_IO to GND_IO . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 4.6V VDD_CDR to GND_CDR, VDD_CR to GND_CR . . -0.5V to 2.5V Between any pair of GND_P, GND_TX, GND_IO, GND_CDR, GND_CR . . . . . . . . . . . . . -0.1V to 0.1V 3.3V Tolerant LVTTL/LVCMOS Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to VDD_IO + 0.3V Differential Input Voltage . . . . . . . . . . . . . . .-0.3V to VDD_IO + 0.3V Differential Output Current . . . . . . . . . . . . . . Short Circuit Protected LVTTL/LVCMOS Outputs . . . . . . . . . . . . . . . . Short Circuit Protected ESD Rating Human Body Model All pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4kV SERIOP/N (all VDD Connected, all GND Connected) . . . . .8kV Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200V Thermal Information Thermal Resistance (Typical, Notes 1, 2) θJA θJC (°C/W) EPTQFP. . . . . . . . . . . . . . . . . . . . . . . . 33 4.5 Maximum Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . 327mW Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +125°C Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C Operating Temperature Range . . . . . . . . . . . . . . . . .-40°C to +85°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 2. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside. Electrical Specifications Unless otherwise indicated, all data is for: VDD_CDR = VDD_CR = 1.8V, VDD_IO = 3.3V, VDD_TX = VDD_P = VDD_AN = 3.3V, TA = +25°C, Ref_Res = 3.16kΩ, High-speed AC-coupling capacitor = 27nF. SYMBOL CONDITIONS MIN TYP MAX UNITS PARAMETER POWER SUPPLY VOLTAGE VDD_CDR, VDD_CR VDD_TX, VDD_P, VDD_AN, VDD_IO SERIALIZER POWER SUPPLY CURRENTS Analog TX Supply Current Analog CDR Supply Current Digital I/O Supply Current Digital Supply Current PLL/VCO Supply Current Analog Bias Supply Current Total 1.8V Supply Current Total 3.3V Supply Current DESERIALIZER POWER SUPPLY CURRENTS Analog TX Supply Current Analog CDR Supply Current Digital I/O Supply Current Digital Supply Current PLL/VCO Supply Current Analog Bias Supply Current Total 1.8V Supply Current Total 3.3V Supply Current 1.7 3.0 1.8 3.3 1.9 3.6 V V IDDTX IDDCDR IDDIO IDDCR IDDP IDDAN VIDEO_TX = 1 PCLK_IN = 40MHz 17 57 1 20 17 5.5 77 40 90 46 2 mA mA mA mA mA mA mA mA IDDTX IDDCDR IDDIO IDDCR IDDP IDDAN VIDEO_TX = 0 REF_CLK = 40MHz 24 45 17 32 17 5.4 77 64 90 80 25 mA mA mA mA mA mA mA mA 3 FN6255.1 June 23, 2008 ISL34340 Electrical Specifications Unless otherwise indicated, all data is for: VDD_CDR = VDD_CR = 1.8V, VDD_IO = 3.3V, VDD_TX = VDD_P = VDD_AN = 3.3V, TA = +25°C, Ref_Res = 3.16kΩ, High-speed AC-coupling capacitor = 27nF. (Continued) SYMBOL CONDITIONS MIN TYP MAX UNITS PARAMETER POWER-DOWN SUPPLY CURRENT Total 1.8V Power-Down Supply Current Total 3.3V Power-Down Supply Current PARALLEL INTERFACE High Level Input Voltage Low Level Input Voltage Input Leakage Current High Level Output Voltage Low Level Output Voltage Output Short Circuit Current Output Rise and Fall Times RSTB = GND; spec is per device 0.5 1 mA mA VIH VIL IIN VOH VOL IOSC tOR/tOF Slew rate control set to min, CL = 8pF Slew rate control set to max, CL = 8pF IOH = -2.0mA, VDD_IO = 3V IOL = 2.0mA, VDD_IO = 3V 2.0 0.8 -10 0.8*VDD_IO 0.2*VDD_IO 50 1 4 ±0.01 10 V V µA V V mA ns ns SERIALIZER PARALLEL INTERFACE PCLK_IN Frequency PCLK_IN Duty Cycle Parallel Input Setup Time Parallel Input Hold Time DESERIALIZER PARALLEL INTERFACE PCLK_OUT Frequency PCLK_OUT Duty Cycle PCLK_OUT Period Jitter (RMS) PCLK_OUT Spread Width Time to Parallel Output Data Valid Deserializer Output Latency fOUT tODC tOJ tOSPRD tDV tCPD Clock randomizer off Clock randomizer on Relative to PCLK_OUT Part-to-part, side-channel disabled -4.7 4 9 6 50 0.5 ±20 5.5 14 40 MHz % %tPCLK %tPCLK ns PCLK fIN tIDC tIS tIH 6 40 3.6 1.6 50 40 60 MHz % ns ns DESERIALIZER REFERENCE CLOCK (REF_CLK IS FED INTO PCLK_IN) REF_CLK Lock Time REF_CLK to PCLK_OUT Clock Maximum Frequency Offset HIGH-SPEED TRANSMITTER HS Differential Output Voltage, Transition Bit VODTR TXCN = 0x00 TXCN = 0x0F TXCN = 0xF0 TXCN = 0xFF HS Differential Output Voltage, Non-Transition Bit VODNTR TXCN = 0x00 TXCN = 0x0F TXCN = 0xF0 TXCN = 0xFF 600 600 825 1170 975 1300 825 460 975 600 990 990 mVP-P mVP-P mVP-P mVP-P mVP-P mVP-P mVP-P mVP-P tPLL PCLK_OUT is the recovered clock 1500 100 5000 µs ppm 4 FN6255.1 June 23, 2008 ISL34340 Electrical Specifications Unless otherwise indicated, all data is for: VDD_CDR = VDD_CR = 1.8V, VDD_IO = 3.3V, VDD_TX = VDD_P = VDD_AN = 3.3V, TA = +25°C, Ref_Res = 3.16kΩ, High-speed AC-coupling capacitor = 27nF. (Continued) SYMBOL VOCM ΔVCM ROUT tLPD tR/tF tSKEW tRJ tDJ Part-to-part 20% to 80% 80 4 CONDITIONS MIN TYP 2.35 20 100 7 150