ISL54103
DDC Accelerator (DDCA)
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The ISL54103 DDC Accelerator (DDCA) is a dual active pull-up
bus terminator designed to improve data transmission speed
on the DDC 2-wire serial bus interfaces.
The DDCA detects rising input transitions with two internal
voltage references and two comparators per channel. After
the voltage on a data line crosses the first threshold
(VTRIPL), the boost pull-up current source is activated to
speed transition. After the voltage crosses the second
threshold (VTRIPH), the boost pull-up current source is
de-activated, leaving an active pull-up current of 275µA on
the line. When both channels are HIGH, the pull-up current
for both lines is reduced to 100µA to save power. Internal
logic ensures that the active and boost pull-up current
sources are not activated during downward transitions.
The level for VTRIPH is controlled by a bandgap voltage
referred to VDD. This feature makes the switching behavior
invariant for all power supply voltages between 2.7V and 5.5V.
A noise filter on each channel prevents the circuit from
responding to input transitions that do not exceed a
voltage-time threshold. To activate the boost circuit, the input
must exceed VTRIPL by 100Vns (typical) (See Figure 10).
The DDCA permits operation of the bus at frequencies up to
100kHz, despite the capacitive loads of multiple devices
and/or long PC board traces. Enhanced ESD protection on
the accelerator pins are guaranteed to withstand 8kV ESD
(HBM) events.
The DDC Accelerator provides an essential function in DDC
applications because of distributed capacitance of the DDC
wires in long video cables. By incorporating DDCA, systems
using DDC can reliably increase their bus load, allowing
longer cables, without the risk of data corruption.
FN6303 Rev 2.00
October 14, 2011
DATASHEET
FN6303
Rev 2.00
October 14, 2011
Features
• Active Termination for DDC Lines
• Enhances System Bus Signal Rise Time
• More Reliable HDCP Performance In Video Multiplexers
and Cable Extenders
• Increases Maximum Cable Length While Guaranteeing
Data Integrity
• 2.2mA Current Boost on Low to High Transitions
• 8kV ESD Protection on SDA and SCL Pins
• Wide Operating Voltage Range: 2.7V to 5.5V
• Small Package - 5 Ld SOT-23
• Pb-free (RoHS Compliant)
Target Applications
• Video Multiplexers
• Video Cable Extenders
• Video Distribution Amplifiers
• Televisions
• Computer Monitors
• Projectors
Pinout
ISL54103
(5 LD SOT-23)
TOP VIEW
VDD
1
GND
2
N.C.
3
5
DDC1
4
DDC2
Page 1 of 9
ISL54103
Pin Descriptions
SOT-23
SYMBOL
DESCRIPTION
1
VDD
Supply Voltage
2
GND
Ground
3
N.C.
No Connect
4
DDC1
Active Pull-Up for DDC Signal
5
DDC2
Active Pull-Up for DDC Signal
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART MARKING
(Note 4)
TEMP
RANGE (°C)
PACKAGE
(Pb-free)
PKG.
DWG. #
ISL54103IHZ-T7
103Z
-40 to +85
5 Ld SOT-23
P5.064
ISL54103IHZ-T7A
103Z
-40 to +85
5 Ld SOT-23
P5.064
NOTES:
1. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J
STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL54103. For more information on MSL please see techbrief
TB363.
4. The part marking is located on the bottom of the part.
FN6303 Rev 2.00
October 14, 2011
Page 2 of 9
ISL54103
System Diagram
ISL54103
VDD
Video Source
Display Device
DDC1
PC, DVD, Set Top
Box, etc.
TV, Monitor, A/V
Receiver, etc.
DDC2
GND
VGA,
DVI,
HDMI
SDA
SCL
BUS SIGNALS
VGA,
DVI,
HDMI
IC Block Diagram
VDD
1.825mA 175A 100A
VTRIPH=
VDD-0.5V
DDC1
+
Control
VTRIPL=
0.75V
VTRIPH=
VDD-0.5V
+
+
DDC2
Control
8kV ESD
Protection
0.75V
8kV ESD
Protection
VTRIPL=
+
1.825mA 175A 100A
VDD
FN6303 Rev 2.00
October 14, 2011
GND
Page 3 of 9
ISL54103
Absolute Maximum Ratings
Thermal Information
Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to 6.5V
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +135°C
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C
Voltage on Pins . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VDD+0.3V
ESD Min Other Pins (HBM) . . . . . . . . . . . . . . . . . . . . . . . . . . . .>2kV
ESD DDC1 and DDC2 Pins (HBM) . . . . . . . . . . . . . . . . . . . . . .>8kV
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
Electrical Specifications
SYMBOL
Over all operating conditions unless otherwise specified, Typical values are measured at VDD = 3.3V and
TA = +25°C
PARAMETER
CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6)
UNIT
5.5
V
ANALOG PARAMETERS
VDD
Supply Voltage Range
2.7
VDD RAMP VDD Ramp Rate
0.05
50
V/ms
80
100
µA
80
125
µA
275
350
µA
IDD
Supply Current
DDC1 = DDC2 = Open
IOUT_SB
Standby Pull-Up Current
DDC1 = DDC2 = VDD - 1.0V
IOUT_A1
Active Pull-Up Current
DDC1 = GND; DDC2 = Open
125
DDC1 = Open; DDC2 = GND
125
275
350
1.6
2.2
IOUT_A2
IOUT_B1
Boost Pull-Up Current (Figure 2) VTRIPL < DDC1 < VTRIPH, DDC2 = Open
VTRIPL < DDC2 < VTRIPH, DDC1 = Open
µA
mA
1.6
2.2
VTRIPL
Input Voltage Threshold Low
0.65
0.75
0.85
VTRIPH
Input Voltage Threshold High
VDD - 0.60
VDD - 0.50
VDD - 0.40
V
fMAX
DDC Max Frequency
100
kHz
NSS
Noise Spike Suppression
(Note 5) (Figure 10)
IOUT_B2
20
mA
V
V-ns
NOTES:
5. Measured as area under triangular waveform above VTRIPL, with time as base and VIN as height (See Figure 10).
6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
FN6303 Rev 2.00
October 14, 2011
Page 4 of 9
ISL54103
370
3.75
350
2.60
BOOST PULL-UP CURRENT, IOUT_B (µA)
ACTIVE PULL-UP CURRENT, IOUT_A (µA)
Typical Performance Curves
330
310
290
VDD = 5.5V
270
250
VDD = 2.7V
230
210
-60
-40
-20
0
20
40
60
80
2.45
2.15
2.00
VDD = 2.7V
1.85
1.70
1.55
-60
100
VDD = 5.5V
2.30
-40
-20
TEMPERATURE (°C)
120
0.95
110
0.90
100
90
VDD = 5.5V
80
VDD = 2.7V
60
50
40
-60
-40
-20
0
20
40
60
80
100
TEMPERATURE (°C)
FIGURE 3. STANDBY PULL-UP CURRENT, DDC1, 2 =
VDD - 0.5V
FN6303 Rev 2.00
October 14, 2011
20
40
60
80
100
FIGURE 2. BOOST PULL-UP CURRENT, DDC PIN = VDD/2
INPUT THRESHOLD LOW, VTRIPL (V)
STANDBY PULL-UP CURRENT, IOUT_SB (µA)
FIGURE 1. ACTIVE PULL-UP CURRENT, DDC PIN = 0V
70
0
TEMPERATURE (°C)
0.85
0.80
VDD = 5.5V
0.75
VDD = 2.7V
0.70
0.65
0.60
0.55
-60
-40
-20
0
20
40
60
80
100
TEMPERATURE (°C)
FIGURE 4. VTRIPL VOLTAGE
Page 5 of 9
ISL54103
(Continued)
0.70
95
0.65
90
0.60
85
SUPPLY CURRENT, IDD (µA)
INPUT THRESHOLD HIGH, VTRIPH (VDD-V)
Typical Performance Curves
0.55
VDD = 5.5V
0.50
VDD = 2.7V
0.45
0.40
75
VDD = 2.7V
70
65
60
0.35
0.30
-60
VDD = 5.5V
80
-40
-20
0
20
40
60
80
55
-60
100
-40
-20
0
20
40
60
80
100
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 5. VTRIPH VOLTAGE
FIGURE 6. IDD CURRENT, DDC1 = DDC2 = OPEN
BOOST PULL-UP CURRENT, IOUT_B (mA)
3.5
3.0
2.5
VDD = 5.0V
2.0
1.5
VDD = 2.7V
1.0
0.5
0
0
1
2
3
4
5
6
DDC VOLTAGE (V)
FIGURE 7. BOOST PULL-UP CURRENT vs DDC VOLTAGE
Functional Description
DDC Overview
DDC is a 2-wire serial communication standard based on the
I2C standard. Devices communicate to each other using one
clock (SCL) and one data (SDA) line. These are both
bidirectional.
Each signal is connected to a positive supply voltage via a
current-source or pull-up resistor (see “System Diagram” on
page 3). When the bus is free, both lines are HIGH. The output
stages of all devices connected to the bus must have an opendrain or open-collector to perform the wired-AND function.
Simple pull-up resistors on the clock and data lines work well
unless there are long signal lines. The combined capacitance
of long cables increases the rise time on the signal to such an
FN6303 Rev 2.00
October 14, 2011
extent that the communication becomes unreliable or fails to
meet the bus timing specifications. Smaller value resistors can
sometimes compensate for the extra capacitance, but this
increases the current consumption when the signal lines are
pulled LOW.
ISL54103 Operation
To improve the operation of the DDC where larger bus
capacitance exists, the ISL54103 provides active pull-up using
switched current sources. When the bus is idle and both lines
are HIGH, a standby pull-up current of 100µA is used to
maintain the signal level while minimizing power consumption.
When either of the two signals is pulled LOW, an active pull-up
current of 275µA maintains a good VOL noise margin.
When the bus line is released, it is pulled high by the ISL54103
active current until the voltage exceeds the VTRIPL level for a
Page 6 of 9
ISL54103
period of time. This voltage-time combination filters out noise
on the signal line. Once the ISL54103 detects a valid rising
edge, a 2.2mA boost current pulls the bus line high very
quickly (see Figure 8). This boost current turns off when the
input level reaches the VTRIPH threshold and the pull-up
current returns to the active level. If both inputs are HIGH, the
pull-up current drops to the standby level of 100µA.
VDD
VTRIPH
With DDCA
Without DDCA
With ISL54103 DDCA
VTRIPH
VTRIPL
With RC
Pull-up
VTRIPL
Gnd
DDC1
DDC2
>20Vns
(Typical)
t
FIGURE 10. NOISE SUPPRESSION. BOOST CURRENT APPLIED
WHEN INPUT SIGNAL EXCEEDS 20Vns (TYPICAL)
R = 15.8k
C = 200pF
FIGURE 8. ISL54103 DDC SYSTEM BOOST PULL-UP
COMPARED TO RESISTOR PULL-UP (VDD = 5.5V)
With ISL54103 DDCA
VTRIPH
With RC
Pull-up
VTRIPL
R = 15.8k
C = 200pF
FIGURE 9. ISL54103 DDC SYSTEM BOOST PULL-UP
COMPARED TO RESISTOR PULL-UP (VDD = 2.7V)
FN6303 Rev 2.00
October 14, 2011
Page 7 of 9
ISL54103
Package Outline Drawing
P5.064
5 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE
Rev 3, 4/11
8°
0°
3.00 3
2.80
(1.90)
5
0.22
0.08 5
4
3.00
2.60
1.70
1.50
3
2
(0.95)
SEE DETAIL X
0.50
0.30
0.20 (0.008) M C
TOP VIEW
END VIEW
0.25
0.10
0.10 MIN
1.30
0.90
1.45 SEATING
0.90 PLANE
C
GAUGE PLANE
SEATING
PLANE
4
0.55
0.35
C
0.15
0.00
0.10 (0.004) C
(0.60)
SIDE VIEW
8°
0°
(0.25)
DETAIL "X"
5x (0.60)
5x (1.2)
5
4
(2.4)
NOTES:
1. Dimensioning and tolerance per ASME Y14.5M-1994.
3
2. Package conforms to EIAJ SC-74 and JEDEC MO178AA.
3. Package length and width are exclusive of mold flash, protrusions,
or gate burrs.
4. Footlength measured at reference to gauge plane.
5. Lead thickness applies to the flat section of the lead between
0.08mm and 0.15mm from the lead tip.
(2x 0.95)
6. Controlling dimension: MILLIMETER.
Dimensions in ( ) for reference only.
(1.90)
TYPICAL RECOMMENDED LAND PATTERN
FN6303 Rev 2.00
October 14, 2011
Page 8 of 9
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