ISL5416

® ISL5416 Data Sheet August 2004 FN6006.3 Four-Channel Wideband Programmable DownConverter The ISL5416 Four-Channel Wideband Programmable Digital DownConverter (WPDC) is designed for high dynamic range applications such as cellular basestations where the processing of multiple channels is required in a small physical space. The WPDC combines four channels in a single package, each including: an NCO, a digital mixer, digital filters, an AGC and a resampling filter. All channels are independently programmable and may be updated in real time. Each of the four channels can select any of the four digital input buses. Each of the tuners can process a W-CDMA channel. Channels may be cascaded or polyphased for increased bandwidth. Selectable outputs include I samples, Q samples, and AGC gain. Outputs from the part are available over the parallel, serial or uP interfaces. Features • Up to 95MSPS Input • Four Parallel 16-bit Fixed or 17-bit Floating Point Inputs • Programmable RF Attenuator/VGA Control • 32-Bit Programmable Carrier NCO with > 110dB SFDR • 20-bit Internal Data Path • Filter Functions - Multi-Stage Cascaded-Integrator-Comb (CIC) Filter - Two programmable FIR Filters (first up to 32-taps, second up to 64-taps) - Half Band Interpolation Filter - Resampling FIR Filter • Overall decimation from 1 to >4096 • Digital AGC with up to 96dB of Gain Range • Up to Four Independent 16-bit Parallel Outputs • Serial Output Option • 16-bit Parallel µP Interface • 1.8V core, 3.3V I/O Operation • Evaluation Board and Configuration Software available • Pb-free available Ordering Information PART NUMBER ISL5416KI ISL5416KIZ (See Note) ISL5416EVAL1 TEMP RANGE (oC) -40 to 85 -40 to 85 25 PACKAGE 256 BGA 256 BGA (Pb-free) PKG. DWG. # V256.17x17 V256.17x17 EVALUATION KIT NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which is compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J Std-020B. Applications • Basestation Receivers: GSM/EDGE, CDMA2000, UMTS. Block Diagram TEST REGISTER OUTPUT RANGE CONTROL AOUT(15:8) INPUT CHANNEL ROUTING NCO MIXER CIC Q I I FIR1 FILTER Q FIR2 FILTER I AGC Q Q I IHBF Q I RESAMPLER Q I OUTPUT ROUTING & FORMATTING AOUT(7:0) FSYNCA OEA AIN(16:0) ENIA CLKA INPUT SELECT CLOCK & FORMAT INPUT A INPUT B INPUT C INPUT D CHANNEL O CHANNEL 1 CHANNEL 2 CHANNEL 3 CLKO1 CLKO2 /INTRPT EOUT(15:0) RF ATTENUATOR VGA CONTROL JTAG SYNCHRONIZATION SYNCO SYNCIN1 SYNCIN2 µP INTERFACE ADD(2:0) uP MODE CE RD or RD/WR RESET 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002-2004. All Rights Reserved All other trademarks mentioned are the property of their respective owners. P(15:0) WR or DSTRB TYPICAL CHANNEL x1, 2, 4, 8 ROUND SATURATE NCO 32-BIT CONTROL >110 db SFDR x1, 2, 4, 8 ROUND SATURATE CHANNEL 0 INPUT A AIN(16:0) ENIA CLKA INPUT FORMAT RANGE CONTROL TEST REGISTER MUX CASCADE IN DIGITAL TUNER OUTPUT FORMAT SLOT CONTROL CH 0, 1 MUXING AOUT(15:0) FSYNCA OEA EXT AGC CNTRL CASCADE OUT INPUT B BIN(16:0) ENIB CLKB INPUT FORMAT RANGE CONTROL CHANNEL 1 AGC GAIN BOUT(15:0) OUTPUT MULTIPLEXING MUX DIGITAL TUNER OUTPUT FORMAT SLOT CONTROL CH 0, 1 MUXING FSYNCB OEB MUX 0 - 96 dB BYPASS AIN(16:0) BIN(16:0) CIN(16:0) DIN(16:0) TEST INPUT DIGITAL 24 16 TUNING / / MIXER 24 / CIC 24 FILTER / 24 / 24 20 / GAIN / FIR 24 20 1 / / 24 / 24 / 24 20 GAIN / FIR / 20 2 24 / / 1-64 TAPS R=1-8 BYPASS AGC 24 / 24 / R O 16 / U 16 N/ D F I F O 16 16 16 / IHBF / RESAMPLING / 16 16 16 FILTER / / / MUX MUX 1-5 STAGES R=2-64K BYPASS 1-32 TAPS R=1-8 BYPASS SELECT FORMAT CASCADE INPUTS FILTER CASCADE OUTPUT 24 / / 24 MUX TO SERIAL TO PARALLEL TO uP SEQUENCING INTERFACE ROUTING AND ROUTING MUX MUX 2 CIN(16:0) ENIC CLKC DIN(16:0) ENID CLKD EOUT(15:0) RESET ISL5416 CHANNEL 2 INPUT C INPUT FORMAT RANGE CONTROL COUT(15:0) FSYNCC OEC DIGITAL TUNER OUTPUT FORMAT SLOT CONTROL CH 2, 3 MUXING INPUT D INPUT FORMAT RANGE CONTROL CHANNEL 3 AGC GAIN DOUT(15:0) DIGITAL TUNER OUTPUT FORMAT FSYNCD SLOT CONTROL CH 2, 3 MUXING SERIAL OUTPUTS SEQUENCED uP READ DATA JTAG SYNCHRONIZATION uP INTERFACE P(15:0), uPMODE, RD (RD/WR), WR (DSTRB), CE, ADD(2:0) SYNCO SYNCIN1 SYNCIN2 OED CLKO1 CLKO2/ INTRPT MUX TRST TMS TCLK TDI TDO ISL5416 256-LEAD BGA TOP VIEW 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A Ain9 B Ain8 C Ain7 D Ain6 E Ain5 F Ain3 G Ain2 H Ain0 J CLKC K GND L Cin14 M Cin12 N Cin10 P Cin9 R GND T Din8 Din7 Din5 ENIC Cin2 CE Eout0 Cout0 Cout2 OEC Cout4 VccIO FSYNCD Dout8 Cout9 Din9 Vcc Din6 ENID Din2 Din1 Eout1 Dout1 Dout2 Vcc Dout5 Dout6 Dout7 Dout9 GND Cin11 Din10 Din11 Din4 Din3 Vcc Din0 Dout0 P1 OED Dout4 GND VccIO Dout10 Cout10 Cin13 Din12 Din13 GND GND WR RD Vcc P0 Dout3 Add0 Dout11 Dout12 Cout12 Cout11 Cin15 Eout3 Din15 Din14 TRST Add2 GND Add1 GND P2 Vcc Cin16 Din16 Eout4 Eout5 Eout2 P3 P4 Dout15 CLKO2/ CLKO1 Cout15 INTRPT Dout13 Dout14 Cout14 Cout13 VccIO CLKD Eout6 Eout7 GND GND P5 P6 Bout0 VccIO Aout0 Bin0 Vcc Eout8 Eout9 GND P7 Bout1 Bout2 Aout1 Aout2 Ain1 Bin1 Bin2 TMS TDI P8 GND Bout3 Aout3 Vcc RESET Vcc Bin3 GND GND GND uPmode GND P10 P9 Bout5 Bout4 VccIO Aout4 Aout5 Ain4 Bin4 Bin5 Eout10 Bin13 Eout11 Vcc P13 P11 TDO GND Bout6 Bout7 Aout6 Aout7 Bin6 Bin7 GND Bin14 Bin15 Eout12 Eout14 P14 P12 Bout15 Bout14 Bout8 Bout9 Aout8 Aout9 Bin8 ENIB Bin11 Bin12 Ain13 Bin16 CLKB P15 VccIO OEB VccIO FSYNCB VccIO Bout10 Aout10 Bin9 Bin10 Vcc Vcc Ain15 Ain16 Eout15 GND SYNCIn2 OEA Vcc Bout13 Bout12 Bout11 FSYNCA ENIA Ain10 Ain11 Ain12 Ain14 Eout13 CLKA SYNCIn1 SYNCO Aout15 Aout14 Aout13 GND Aout12 Aout11 Cin8 Cin7 Cin6 Cin5 Cin4 Cin3 Cin1 Cin0 Cout1 TCLK Cout3 Cout5 Cout6 FSYNCC Cout7 Cout8 POWER PIN GROUND PIN SIGNAL PIN THERMAL BALL NC (NO CONNECTION) Vcc = +1.8V CORE SUPPLY VOLTAGE VccIO = +3.3V I/O SUPPLY VOLTAGE NOTE: Thermal Balls should be connected to the ground plane Unused Input Balls should be connected to ground or VccIO as appropriate 3 ISL5416 Pin Descriptions NAME TYPE INTERNAL PULL-UP/DOWN DESCRIPTION POWER SUPPLY Vcc VccIO GND INPUTS Ain(16:0) I PULL DOWN Parallel Data Input bus A. Sampled on the rising or falling edge (programmable) of clock when ENIA is active (low). The bus order can be programmed (See IWA = 0*00h, bit 4). Parallel Data Input bus B. Sampled on the rising or falling edge (programmable) of clock when ENIB is active (low). The bus order can be programmed (See IWA = 0*00h, bit 4). Parallel Data Input bus C. Sampled on the rising or falling edge (programmable) of clock when ENIC is active (low). The bus order can be programmed (See IWA = 0*00h, bit 4). Parallel Data Input bus D. Sampled on the rising or falling edge (programmable) of clock when ENID is active (low). The bus order can be programmed (See IWA = 0*00h, bit 4). Input enable for Parallel Data Input bus A. Active low. This pin enables the input to the part in one of two modes, gated or interpolated. In gated mode, one sample is taken per CLK when ENIx is asserted. Input enable for Parallel Data Input bus B. Active low. This pin enables the input to the part in one of two modes, gated or interpolated. In gated mode, one sample is taken per CLK when ENIx is asserted. Input enable for Parallel Data Input bus C. Active low. This pin enables the input to the part in one of two modes, gated or interpolated. In gated mode, one sample is taken per CLK when ENIx is asserted. Input enable for Parallel Data Input bus D. Active low. This pin enables the input to the part in one of two modes, gated or interpolated. In gated mode, one sample is taken per CLK when ENIx is asserted. Positive Power Supply Voltage (core), 1.8V ±0.09 Positive Power Supply Voltage (I/O), 3.3V ±0.165 Ground, 0V. Bin(16:0) I PULL DOWN Cin(16:0) I PULL DOWN Din(16:0) I PULL DOWN ENIA I PULL DOWN ENIB I PULL DOWN ENIC I PULL DOWN ENID I PULL DOWN CONTROL CLKA CLKB CLKC CLKD SYNCIn1 I I I I I PULL DOWN PULL DOWN PULL DOWN PULL DOWN Input clock for data bus A. CLKA or CLKC may be used for Ain(16:0). Input clock for data bus B. CLKB or CLKC may be used for Bin(16:0). Input clock for data bus C. CLKC is also the master clock for all channels of ISL5416 Input clock for data bus D. CLKD or CLKC may be used for Din(16:0). Global synchronization input signal 1. SYNCIn1 can update the carrier NCOs, reset decimation counters, restart the filter, and restart the output section among other functions. For most of the functional blocks, the response to SYNCIn1 is programmable and can be enabled or disabled. Global synchronization input signal 2. SYNCIn2 can update the carrier NCOs, reset decimation counters, restart the filter, and restart the output section among other functions. For most of the functional blocks, the response to SYNCIn2 is programmable and can be enabled or disabled. Synchronization Output Signal. The processing of multiple ISL5416 devices can be synchronized by tying the SYNCO from one ISL5416 device (the master) to the SYNCIn of all the ISL5416 devices (the master and slaves). An optional internal SYNCO to SYNCInX connection is provided. PULL UP Reset Signal. Active low. Asserting reset will halt all processing and set certain registers to default values. SYNCIn2 I PULL DOWN SYNCO O RESET I 4 ISL5416 Pin Descriptions NAME JTAG TDO TDI TMS TCLK TRST O I I I I PULL UP PULL UP PULL DOWN PULL UP Test data out Test data in. Test mode select. Test clock. Test reset. Active low. If JTAG not used, tie this pin low. If there is a trace connected to the pin and there is enough board noise, the JTAG port might get into an unexpected state and stop communications with the part TYPE (Continued) INTERNAL PULL-UP/DOWN DESCRIPTION OUTPUTS Aout(15:0) O Parallel Data Output bus A. A 16-bit parallel data output which can be programmed to consist of I, Q, AGC. Data from Channels 0, 1, 2 and 3 can be multiplexed into a common parallel output data bus. Information can be sequenced in a programmable order. Can be ones complemented. Can be divided into two 8-bit busses. See Data Output Formatter Section and Microprocessor Interface Section. See Table 24. Parallel Data Output bus B. A 16-bit parallel data output which can be programmed to consist of I, Q, AGC. Data from Channels 0, 1, 2 and 3 can be multiplexed into a common parallel output data bus. Information can be sequenced in a programmable order. Can be ones complemented. Can be divided into two 8-bit busses. See Data Output Formatter Section and Microprocessor Interface Section. Parallel Data Output bus C. A 16-bit parallel data output which can be programmed to consist of I, Q, AGC. Data from Channels 0, 1, 2 and 3 can be multiplexed into a common parallel output data bus. Information can be sequenced in a programmable order. Can be ones complemented. Can be divided into two 8-bit busses. See Data Output Formatter Section and Microprocessor Interface Section. Parallel Data Output bus D. A 16-bit parallel data output which can be programmed to consist of I, Q, AGC. Data from Channels 0, 1, 2 and 3 can be multiplexed into a common parallel output data bus. Information can be sequenced in a programmable order. Can be ones complemented. Can be divided into two 8-bit busses. See Data Output Formatter Section and Microprocessor Interface Section. Below is the table of the serial output bits allocation for DOUT. SERIAL OUTPUT BITS ALLOCATION SER. OUTPUT A SER. OUTPUT B SER. OUTPUT C SER. OUTPUT D SCLKX * SSYNCX * SD1X * SD2X * DOUT0 DOUT1 DOUT2 DOUT3 DOUT4 DOUT5 DOUT6 DOUT7 DOUT8 DOUT9 DOUT10 DOUT11 DOUT12 DOUT13 DOUT14 DOUT15 Bout(15:0) O Cout(15:0) O Dout(15:0) O * X denotes A, B, C, D as appropriate Eout(15:0) CLKO1 O O A 16-bit parallel VGA/Attenuator control output. Partitionable into separate 4 or 8-bit busses. Output Clock 1. Can be programmed to be at CLKC/N for N = 1 to 16. The polarity of CLKO1 is programmable. Available ONLY on Rev B (final) version of the part. Provides a complementary output or a second clock to simplify board routing. Polarity is programmable. It can also be programmed as an interrupt from one or more channels for a sequenced read (FIFO-like) mode. See register GWA = 0000h, bit 13. CLKO2/ INTRPT O 5 ISL5416 Pin Descriptions NAME FSYNCA FSYNCB FSYNCC FSYNCD OEA OEB OEC OED TYPE O O O O I I I I PULL UP PULL UP PULL UP PULL UP (Continued) INTERNAL PULL-UP/DOWN DESCRIPTION Frame Synchronization output signal for bus Aout(15:0). Frame Synchronization output signal for bus Bout(15:0). Frame Synchronization output signal for bus Cout(15:0). Frame Synchronization output signal for bus Dout(15:0). Output three-state enable for Parallel Data Output bus A. Active low. Output three-state enable for Parallel Data Output bus B. Active low. Output three-state enable for Parallel Data Output bus C. Active low. Output three-state enable for Parallel Data Output bus D. Active low. MICROPROCESSOR INTERFACE P(15:0) ADD(2:0) WR or DSTRB I/O I I Microprocessor Interface Data bus. See Microprocessor Interface Section. P15 is the MSB. Microprocessor Interface Address bus. ADD2 is the MSB. See Microprocessor Interface Section. Microprocessor Interface Write or Data Strobe Signal. When the Microprocessor Interface Mode Control (µP MODE) is low, data transfers (from P(15:0) to the internal write holding register) occur on the low to high transition of WR when CE is asserted (low). When the µP MODE control is high this input functions as a data strobe DSTRB control. In this mode with RD/WR low, data transfers (from P(15:0) to the internal write holding register) occur on the low to high transition of DSTRB. With RD/WR high the data from the address specified is placed on P(15:0) when DSTRB is low. See the Microprocessor Interface Section. Microprocessor Interface Read or Read/Write Signal. When the Microprocessor Interface Mode Control (µP MODE) is low, the data from the address specified is placed on P(15:0) when RD is asserted (low) and CE is asserted (low). When the µP MODE control is high this input functions as a Read/Write control input. Data is read from P(15:0) when RD/WR high or written to the appropriate register when low. See the Microprocessor Interface Section. PULL DOWN Microprocessor Interface Mode Control. This pin is used to select the Read/Write mode for the Microprocessor Interface. When 0, RD and WR, when 1, DSTROBE and RD/WR. When µP MODE is 0, the microprocessor interface consists of separate RD and WR strobes; when µP MODE is 1, the interface consists of a RD/WR control and a single data strobe. See the Microprocessor Interface Section. Microprocessor Interface Chip Select. Active low. This pin has the same timing requirements as the address pins. RD or RD/WR I µP MODE I CE I 6 ISL5416 Functional Description The ISL5416 is a four channel digital receiver integrated circuit offering exceptional dynamic range and flexibility. Each of the four channels consists of a front-end NCO, digital mixer, CIC-filter, two FIR filters, AGC, Interpolation Half Band Filter and Re-sampling Filter. The parameters for the four channels are independently programmable. There are four 17-bit parallel data input busses (Ain(16:0), Bin(16:0), Cin(16:0) and Din(16:0)). The ISL5416 supports both fixed and floating point parallel data input modes. The floating point modes support gain ranging A/D converters or A/D converter and RF/IF Attenuators or VGAs. Gated or interpolated data input modes are supported. Each input can be connected to any or all of the internal signal processing channels, Channels 0, 1, 2 and 3. The four channels share a common processing clock (CLKC). Four input clocks are provided to allow for clock skew between input sources. Each input has a Range Control circuits to monitor the signal level on the parallel data busses and to control the gain prior to the A/D converters. A 16-bit bus (Eout(15:0)) is provided to control the external VGA/RF Attenuators. Each front end NCO/digital mixer/CIC filter section includes a quadrature numerically controlled oscillator (NCO), digital mixer, barrel shifter and a cascaded-integrator-comb filter (CIC). The NCO has a 32-bit frequency control word. The SFDR of the NCO is >110dB. The barrel shifter provides a gain of between 2-45 and 4 to compensate for the gain in the CIC. The CIC filter order is programmable from 1 to 5 and the CIC decimation factor can be programmed from 2 to 512 for 5th order, 2048 for 4th order, 32768 for 3rd order, or 65536 for 1st or 2nd order filters. The CIC filter can also be bypassed. Each channel back end section includes two FIR filters, an AGC, Interpolation Half Band Filter and Resampler. The first FIR filter can have up to 32 taps and the second can have up to 64 taps. The 32-tap filter calculates 4 taps per clock, while the 64-tap filter calculates 8 taps per clock. The coefficients for the programmable digital filters are 20 bits wide. Each FIR filter can be bypassed. The AGC section can provide up to 96dB of either fixed or automatic gain control. For automatic gain control, two settling modes and two sets of loop gains are provided. Separate attack and decay slew rates are provided for each loop gain. Programmable limits allow the user to specify a gain range less than 96dB. A fixed coefficient interpolate-by-2 Half Band Filter and a non-integer resampling filter follow the AGC. Coefficients for the resampling filter are provided in ROM. Four 16-bit parallel data outputs (Aout(15:0), Bout(15:0), Cout(15:0) and Dout(15:0)) are provided. The output of each channel can be routed to any of the output buses. Outputs from more than one channel can be multiplexed through a common output if the channels are synchronized. Dout(15:0)) can alternately be used as four serial output pairs. A common output clock (CLKO1) is used for the 7 parallel output buses. A second clock output pin (CLKO2/INTRPT) is provided to simplify board routing or to allow a complementary output clocks. The ISL5416 is programmed through a 16-bit microprocessor interface. The output data can also be read via the microprocessor interface. The ISL5416 is specified to operate to a maximum clock rate of 95 MSPS over the industrial temperature range (-40oC to 85oC). The I/O power supply voltage range is 3.3V ± 0.165V while the core power supply voltage is 1.8V ± 0.09V. Input Select/Format Block CLOCKING The channel processing and output timing is clocked with the rising edge of CLKC. Each input bus can be clocked with the rising or falling edge of its own clock or with the rising or falling edge of CLKC. The frequency of all the clocks must be the same, but providing separate clocks allows the inputs from multiple A/D converters to have a small amount of skew. INPUT FORMAT The inputs can be fixed point or floating point with mantissa/exponents sizes of 14/3, 15/2, or 16/1. The exponent inputs are added to the exponent from the internal range control circuits, so if the range control circuits are used, the exponent pins are typically grounded and/or disabled via software in IWA = 0*10h, bit 3. The input format may be twos complement or offset binary format in either fixed or floating point modes (IWA = 0*00h). GATED/INTERPOLATED MODES For input sample rates at sub-multiples of the clock rate, gated and interpolated input modes are provided. Each input channel has an input enable (ENIx, x = A, B, C or D). In the gated mode, one input sample is processed per clock that the ENIx signal is asserted (low). Processing is disabled when ENIx is high. The ENIx signal is pipelined through the part to minimize delay (latency). In the interpolated mode, the input is zeroed when the ENIx signal is high, but processing inside the part continues. This mode inserts zeros between the data samples, interpolating the input data stream up to the clock rate. The spacing between ENIx signals must be constant in the interpolated mode. MULTIPLEXED INPUT MODE Each input section can select one channel from a multiplexed data stream of up to 8 channels. The input enable is delayed by 0 to 7 clock cycles to enable a selection register. The register following the selection register is enabled by the non-delayed input enable to realign the processing of the channels. The one-clock-wide input enable must align with the data for the first channel. The desired channel is then selected by programming the delay. A delay of zero selects the first channel, a delay of 1 selects the second, etc. Each input section selects only one channel of the multiplexed stream, so a separate input bus must be used for each channel of the multiplexed data stream. ISL5416 CLKC CLKX R1 CLKC CLKX R1 R2 R3 R4 R2 R3 R4 INTERPOLATE BUS REVERSE OBIN FLOAT/FIX SLOT# ENIX XIN(16:0) R1 R R E G R2 R E G R3 R E G R4 R E G (16:0) M U (0:16) X F M T R M A P MANTISSA EXPONENT PROCESSING ENABLE ^ CLK/CLK ^ ^ ^ D M U X R E G TO CHANNELS AND RANGE CONTROL ^ MUX CLKX/CLKC CLKX MUX DIN (ONLY) TO SERIAL FREQUENCY OFFSET CLK CLKC NOTE: To simplify the board routing, each of the four input data busses can be reversed, MSB for LSB (see IWA = 0*00h, bit 4) FIGURE 1. INPUT SECTION SYNCInX Use SYNCInX main purpose is as a processing start-up signal after a reset to align the start of processing of multiple channels or chips. This assures that the carrier phases have a known relationship and that the output timing aligns for multiplexing outputs. It can also be used after start-up as a system timing synchronization signal. Two SYNCInX signals are provided so that one can be used as a regularly occurring signal (such as at time slot boundaries) and one as an infrequent signal (such as at start up or at 1 pps). If more than one air interface standard is processing in one part, one SYNCInX signal could be used for the slot timing for each standard. Register updates from a processor write are synchronized to the clock, so that the register updates in multiple channels of the same part are time aligned. However, when synchronizing multiple parts the processor will need knowledge of the SYNCInX timing so that enabling the SYNCInX in multiple parts occurs between SYNCInX pulses. Alternatively, SYNCIn1 could be used as a regularly occurring SYNCI signal and SYNCIn2 could be a gated version. The channel processing control register might only be updated on SYNCIn2 and the other SYNCI functions would respond to SYNCIn1. 8 ISL5416 VGA/RF Attenuator (A/D Range Control) The range control section monitors the output of the A/D and adjusts the RF/IF gain to maintain a desired A/D output range. The gain adjustments are in 6 dB steps. The levels, adjustment rates, and gain to bit mapping are programmable. The range control section uses three programmable thresholds. Two thresholds, an upper and a lower threshold, are compared against the average magnitude of the A/D output. The range control adjusts the gain to keep the average A/D output between the upper and lower thresholds. If the average is above the upper threshold, an internal attenuator control register is increased by a programmable amount. If the average is below the lower threshold, the gain attenuator control register is decreased by a separate programmed amount. The number of samples averaged for each decision is programmable. The adjustments to the attenuator control register can be less than 6 dB to further filter the inputs. Only the three MSBs of the attenuator control register are used to control the RF/IF gain, and these are weighted as 6, 12, 24 dB steps. The third threshold, an immediate threshold, is compared against the magnitude of each A/D sample. If the magnitude of any A/D sample exceeds the threshold, the attenuator control register is immediately increased by the amount programmed for the immediate threshold. Because there will be some time delay from a register change until the effect of the change is seen at the A/D, the immediate threshold is disabled for a programmable number of clock cycles after it has been triggered. To maximize the input sensitivity the range control also includes a programmable bias. If the average signal is between the upper and lower threshold, the bias value is added from the attenuator control register. This bias removes attenuation when it is no longer needed to avoid missing small signals due to high input noise figure. Four counters control the amount of time that the input is averaged and align the adjustments to time slot boundaries. One counts out the time slot period. If desired, this counter can be reset by a SYNCInX signal to align its count to the system timing. A second counter provides a programmable delay from the start of the first counter's period to the start of the integration period. This compensates for system delays or allows the adjustments to be made over a certain portion of the time slot. The third counter sets the integration period for averaging the input samples for the upper and lower threshold decisions. The fourth counter controls the number of integration periods per time slot. See Figure 2 for a block diagram. Note that the counters are ignored for the immediate threshold decisions. The user can program a separate code for output on the EOUT bus for each of the eight possible states of the three MSBs of the attenuator control register. These codes can be up to 8 bits, but if four gain control sections are used, only four bits are available for each gain control section. The mapping of the gain control bits to EOUT bits is done in GWA = 0001h and the codes are programmed in IWA = 0*17h and 0*18h. The three MSBs of the attenuator control register can be routed internally to the channels to be used as the floatingpoint exponents. This adds gain in 6 dB steps to compensate for the 6 dB steps of RF attenuator. The MSBs can be added to the input exponent bits if desired. There is a programmable delay from the attenuator control register to the channel input to compensate for RF/IF filter group delay and A/D and ISL5416 pipeline delays. 9 ISL5416 SYNC ENABLE COUNTERS FROM INPUT SECTION MANTISSA EXPONENT INTERVAL (SLOT PERIOD) LD DOWN COUNTER =0 |X| BYPASS BW SELECT EN HPF EN INPUT EXP |X| (SYNC TO START OF INTEGRATION) REG INTEGRATION TIME EN LD B IMMEDIATE A TH2 B ∆ 2(-1 TO -16) BARREL SHIFT 1-256 CLOCKS TH3 A B ∆ A PROG DELAY A>B UPPER A4096. A block diagram is provided below in Figure 8. The re-sampling filter (HOIF) can accept inputs at any rate up to its maximum output rate of one half the clock rate. Preceding the resampler is an interpolation halfband filter. This filter can be used to provide a fixed interpolation by 2 when the resampler is bypassed or, when used with the resampler, to increase the image-free dynamic range of the output. The IHBF can output at up to the clock rate if the resampling filter is bypassed and up to one half the clock rate if the resampling filter is enabled. Frequency response plots are provided below for the half-band and resampling filters. An example frequency response for a FIR2 response together with the half-band and resampling filters is also provided. The resampling process produces images of the signal at multiples of the input sample rate. Large interfering signals must be removed from the spectrum with the CIC, FIR1, and FIR2 filters or the images created from them in the resampling process may cause problems. The level of the images created by resampling process has a fixed dBc level for a given set of filters and sampling ratio. As the signal level in the channel increases and decrease, the images levels will increase and decrease by the same amount. As the ratio of the FIR2 output sample rate to the band edge increases, the level, in dBc, of the images decreases. 0 -20 -40 -60 -80 - 100 0 5 10 15 x 10 6 FIGURE 7A. INTERPOLATION HALF BAND RESPONSE 10 0 -10 -20 -30 -40 -50 -60 -70 -80 0 0.5 1 1.5 2 2. 5 3 x 10 7 FIGURE 7B. IHBF (INTERPOLATE BY 2) AND RESAMPLER (INTERPOLATE BY 2) 10 0 -10 -20 -30 -40 -50 -60 -70 -80 0 5 10 15 x 10 6 FIGURE 7C. INDIVIDUAL AND COMPOSITE RESPONSES (FIR2 OUTPUT AT 7.68 MHz WITH IHBF, INTERPOLATE BY 2) 19 ISL5416 Two NCOs and two counters set the sample rates through the rate change section. NCO1 sets the output sample rate of the resampling filter. NCO1 is 48 bits and is updated at the clock rate, so its output frequency is: Fout1 = Fclk * N1 / 248, where N1 is the 48-bit programming word. The carry output of the phase accumulator is used as the output clock, so there can be one clock period of jitter. NCO2 is programmed for the input sample rate to the resampler (equals the halfband filter output rate). NCO2 is updated at the NCO1 output rate. NCO2 controls the phase of the resampling filter. This NCO also has a 48-bit phase accumulator. The equation for programming the output frequency of NCO2 is: Fout2 = Fout1 * N2 / 248 = Fclk * (N1 / 248) * (N2 / 248) when the resampling filter is enabled and Fout2 = Fclk * N2 / 248 10 0 -10 -20 -30 -40 -50 -60 -70 -80 0 5 10 15 x 10 6 10 0 -10 -20 -30 -40 -50 -60 -70 -80 0 0. 5 1 1. 5 2 2. 5 3 x 10 7 FIGURE 7D. INDIVIDUAL AND COMPOSITE RESPONSES (FIR2 OUTPUT AT 7.68 MHz WITH IHBF, INTERPOLATE BY 2 AND RE-SAMPLER, INTERPOLATE BY 2 when the resampling filter is bypassed. NCO2 can have one output sample period (Fout1 period) of jitter (one clock period when the HOIF is bypassed). A static phase offset can be programmed for NCO2. The range of the phase offset is 0 to 2 NCO2 output sample periods (0 - 2 resampling filter input sample periods). The programming resolution is 1/256 of a resampling filter input sample period. This programmable offset allows the user vary the group delay of one channel relative to another in very fine increments to compensate for differences in system delays. If the resampler is not needed for rate change, it can be used for phase shifting by setting bit 22 in IWA *001h. While the 48-bit phase accumulators provide very good frequency programming resolution, at some input/output sample rate ratios, there will be a slow phase drift due to the finite word length. To correct for this, a “leap” counter is provided to reset the phase of the NCOs after a programmed interval to remove any accumulated error. The leap counter is 32 bits. If properly programmed, this phase correction will not be seen in the output of the part. The input rate to the IHBF/RS section must match the output sample rate of FIR2, i.e. the output rate of NCO2 must equal the input sample rate of the part divided by the decimation factors in the CIC, FIR1, and FIR2. The leap counter can guarantees this over the long term, but due to the jitter of the phase accumulator outputs, a FIFO is provided to guarantee that there are no dropped samples. The FIFO is filled at the output sample rate of the AGC and is emptied by Fout2 (or Fout2/2 if the IHBF is enabled). After reset, the FIFO is filled to a depth of two before the NCOs are enabled. This minimum fill depth guarantees that there are enough samples in the FIFO that the FIFO never empties or overflows due to NCO jitter if the NCOs and leap counter are properly programmed. FIFO reads are enabled after an FIGURE 7E. FIR2 AND IHBF COMPOSITE RESPONSE 10 0 -10 -20 -30 -40 -50 -60 -70 -80 0 0.5 1 1.5 2 2.5 3 x 10 7 FIGURE 7F. FIR2, IHBF AND RESAMPLER COMPOSITE RESPONSE 20 ISL5416 additional 0 to 3 input samples as programmed by the user. This additional depth provides for additional programmable group delay. The additional FIFO depth can only be programmed at reset. Because the NCOs are enabled after a depth of 2 is reached, the data into the IHBF/Resampler is zeroed until the programmed fill depth is reached. If both the half-band and resampling filters are enabled, the programmable FIFO depth, together with the NCO2 phase offset, provides from 0 to 4 FIR2 output sample periods of programmable group delay in 1/512 increments. Because the IHBF and RS combination can only interpolate, for resampling ratios