ISL54220IRTZ

High-Speed USB 2.0 (480Mbps) Multiplexer ISL54220 The Intersil ISL54220 is a single supply dual 2:1 multiplexer that can operate from a single 2.7V to 5.5V supply. It contains two SPDT (Single Pole/Double Throw) switches configured as a DPDT. The part was designed for switching or routing of USB High-Speed signals and/or USB Full-speed signals in portable battery powered products. The 6Ω switches can swing rail-to-rail and were specifically designed to pass USB full speed data signals that range from 0V to 3.3V and USB high speed data signals that range from 0V to 400mV. They have high bandwidth and low capacitance to pass USB high-speed data signals with minimal distortion. The digital logic inputs are 1.8V logic compatible when operated with a 2.7V to 3.6V supply. The ISL54220 has an output enable pin to open all the switches. The ISL54220 is available in 10 Ld 1.8mmx1.4mm µTQFN, 10 Ld TDFN and 10 Ld MSOP packages. It operates over a temperature range of -40 to +85°C. ISL54220 Features • High-Speed (480Mbps) and Full-Speed (12Mbps) Signaling Capability per USB 2.0 • 1.8V Logic Compatible (2.7V to +3.6V supply) • Enable Pin to Open all Switches • Power OFF Protection • D-/D+ Pins Overvoltage Tolerant to 5.5V • -3dB Frequency . . . . . . . . . . . . . . . . . . 742MHz • Low ON Capacitance @ 240MHz . . . . . . . . . 4.2pF • Low ON-Resistance @ VDD = 5.5V . . . . . . . 4.5Ω • Low ON-Resistance @ VDD = 3.3V . . . . . . . 6.0Ω • Single Supply Operation (VDD) . . . . . 2.7V to 5.5V • Available in µTQFN, TDFN, and MSOP Packages • Pb-Free (RoHS Compliant) • Compliant with USB 2.0 Short Circuit and Overvoltage Requirements Without Additional External Components Related Literature • Technical Brief TB363 “Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs)” • Application Note AN1449 “ISL54220IRUEVAL1Z Evaluation Board User’s Manual” Applications*(see page 15) • MP3 and other Personal Media Players • Cellular/Mobile Phones • PDA’s • Digital Cameras and Camcorders • USB Switching Application Block Diagram USB 2.0 HS Eye Pattern With Switches In The Signal Path µCONTROLLER SEL VBUS DD- ISL54220 LOGIC OE USB HIGH-SPEED OR FULL-SPEED TRANSCEIVER USB HIGH_SPEED OR FULL-SPEED TRANSCEIVER HSD1HSD1+ D+ GND D+ HSD2HSD2+ GND VOLTAGE SCALE (0.1V/DIV) VDD USB CONNECTOR PORTABLE MEDIA DEVICE TIME SCALE (0.2ns/DIV) February 4, 2010 FN6819.1 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2008, 2010. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL54220 Pin Configurations ISL54220 (10 LD 3.0X3.0 TDFN) TOP VIEW PD SEL HSD1+ HSD2+ D+ GND 1 2 3 4 5 LOGIC CONTROL ISL54220 (10 LD MSOP) TOP VIEW 10 VDD 9 8 OE HSD1- SEL HSD1+ HSD2+ D+ GND 1 2 3 4 5 LOGIC CONTROL 10 VDD 9 8 OE HSD1- 7 HSD26 D- 7 HSD26 D- ISL54220 (10 LD 1.8X1.4 µTQFN) TOP VIEW HSD17 OE 8 LOGIC CONTROL VDD 9 SEL 10 HSD26 5 4 3 1 2 DGND D+ HSD1+ HSD2+ NOTE: 1. Switches Shown for SEL = Logic “1” and OE = Logic “0”. Truth Table OE 0 0 1 SEL 0 1 X HSD1-, HSD1+ ON OFF OFF HSD2-, HSD2+ OFF ON OFF Pin Descriptions TDFN 10 1 2 3 4 5 6 7 8 9 PD MSOP 10 1 2 3 4 5 6 7 8 9 µTQFN 9 10 1 2 3 4 5 6 7 8 NAME VDD SEL FUNCTION Power Supply (2.7V to 5.5V) Select Logic Control Input Logic “0” when ≤ 0.5V, Logic “1” when ≥ 1.4V with a 2.7V to 3.6V Supply. HSD1+ USB Data Port (Channel 1 Positive Input) HSD2+ USB Data Port (Channel 2 Positive Input) D+ GND DUSB Data Common Positive Port Ground Connection USB Data Common Negative Port HSD2- USB Data Port (Channel 2 Negative Input) HSD1- USB Data Port (Channel 1 Negative Input) OE PD Bus Switch Enable Thermal Pad. Tie to Ground or Float 2 FN6819.1 February 4, 2010 ISL54220 Ordering Information PART NUMBER (Note 5) ISL54220IRUZ-T (Notes 2, 4) ISL54220IRTZ (Note 3) ISL54220IRTZ-T (Notes 2, 3) ISL54220IUZ (Note 3) ISL54220IUZ-T (Notes 2, 3) ISL54220IRUEVAL1Z NOTES: 2. Please refer to TB347 for details on reel specifications. 3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 4. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 5. For Moisture Sensitivity Level (MSL), please see device information page for ISL54220. For more information on MSL please see techbrief TB363. PART MARKING H 4220 4220 54220 54220 Evaluation Board TEMP. RANGE (°C) -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 PACKAGE (Pb-Free) 10 Ld 1.8mmx1.4mm µTQFN (Tape and Reel) 10 Ld 3x3 TDFN 10 Ld 3x3 TDFN (Tape and Reel) 10 Ld MSOP 10 Ld MSOP (Tape and Reel) PKG. DWG. # L10.1.8x1.4A L10.3x3A L10.3x3A M10.118 M10.118 3 FN6819.1 February 4, 2010 ISL54220 Absolute Maximum Ratings VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 6.5V Input Voltages HSD2x, HSD1x (Note 6) . . . . . . . . . . . . . . - 0.3V to 6.5V SEL, OE (Note 6) . . . . . . . . . . . . . -0.3 to ((VDD) + 0.3V) Output Voltages D+, D- (Note 6) . . . . . . . . . . . . . . . . . . . . -0.3V to 6.5V Continuous Current (HSD2x, HSD1x) . . . . . . . . . . . ±40mA Peak Current (HSD2x, HSD1x) (Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . ±100mA ESD Rating Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . >6kV Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . >500V Charged Device Model . . . . . . . . . . . . . . . . . . . . . . >2kV Latch-up Tested per JEDEC; Class II Level A . . . . . at +85°C Thermal Information Thermal Resistance (Typical) θJA (°C/W) θJC (°C/W) 10 Ld µTQFN (Notes 8, 10) . . . . . . 160 105 10 Ld TDFN (Notes 8, 9) . . . . . . . . 55 18 10 Ld MSOP (Note 7, 10) . . . . . . . 165 65 Maximum Junction Temperature (Plastic Package). . +150°C Maximum Storage Temperature Range. . . . . -65°C to +150°C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Operating Conditions Temperature Range . . . . . . VDD Supply Voltage Range . Logic Control Input Voltage Analog Signal Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C . . 2.7V to 5.5V . . . . 0V to VDD . . . . 0V to VDD CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 6. Signals on HSD1x, HSD2x, D+,D- exceeding GND by specified amount are clamped. Signals on OE and SEL exceeding VDD or GND by specified amount are clamped. Limit current to maximum current ratings. 7. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 8. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 9. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside. 10. For θJC, the “case temp” location is the center of the package top. Electrical Specifications - 2.7V to 5.5V Supply Test Conditions: VDD = +3.3V, GND = 0V, VSELH = 1.4V, VSELL = 0.5V, VOEH = 1.4V, VOEL = 0.5V, (Note 11), Unless Otherwise Specified. Boldface limits apply over the operating temperature range, -40°C to +85°C. TEMP MIN (°C) (Notes 12, 13) TYP MAX (Notes 12, 13) UNITS PARAMETER ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG ON-Resistance, rON (High-Speed) TEST CONDITIONS VDD = VDD, SEL = 0V or VDD , OE = 0V VDD = 2.7V, SEL = 0.5V or 1.4V, OE = 0.5V, IDx = 40mA, VHSD1x or VHSD2 x = 0V to 400mV (see Figure 3, Note 16) VDD = 2.7V, SEL = 0.5V or 1.4V, OE = 0.5V, IDx = 40mA, V VHSD1x or VHSD2 x = Voltage at max rON, (Notes 15, 16) VDD = 2.7V, SEL = 0.5V or 1.4V, OE = 0.5V, IDx = 40mA, VHSD1x or VHSD2 x = 0V to 400mV, (Notes 14, 16) Full 25 Full 0 - 6.7 - VDD 8 10 V Ω Ω rON Matching Between Channels, ΔrON (High-Speed) 25 Full - 0.117 - 0.45 0.55 Ω Ω rON Flatness, RFLAT(ON) (High-Speed) 25 Full 25 Full 25 Full 25 Full -15 -20 -20 -25 -15 -20 0.94 0.31 2.2 0.26 - 1.2 1.3 15 20 20 25 15 20 Ω Ω nA nA nA nA nA nA OFF Leakage Current, IHSD1x(OFF) VDD = 5.5V, SEL = VDD and OE = 0V or OE = VDD, VDx = 0.3V, 3.3V, VHSD1X = 3.3V, 0.3V, VHSD2x = 0.3V, 3.3V ON Leakage Current, IHSD1x(ON) VDD = 5.5V, SEL = OE = 0V, VDx = 0.3V, 3.3V, VHSD1X = 0.3V, 3.3V, VHSD2x = 3.3V, 0.3V OFF Leakage Current, IHSD2x(OFF) VDD = 5.5V, SEL = OE = 0V or OE = VDD, VDx = 3.3V, 0.3V, VHSD2x = 0.3V, 3.3V, VHSD1X = 3.3V, 0.3V 4 FN6819.1 February 4, 2010 ISL54220 Electrical Specifications - 2.7V to 5.5V Supply Test Conditions: VDD = +3.3V, GND = 0V, VSELH = 1.4V, VSELL = 0.5V, VOEH = 1.4V, VOEL = 0.5V, (Note 11), Unless Otherwise Specified. Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued) TEMP MIN (°C) (Notes 12, 13) 25 Full 25 Full -20 -25 TYP 2.1 0.0047 MAX (Notes 12, 13) UNITS 20 25 0.025 0.40 nA nA µA µA PARAMETER ON Leakage Current, IHSD2x(ON) TEST CONDITIONS VDD = 5.5V, SEL = VDD, OE = 0V, VDx= 0.3V, 3.3V, VHSD2x = 0.3V, 3.3V, VHSD1X = 3.3V, 0.3V VDD = 0V, VD+ = 0V to 5.25V, VD-= 0V to 5.25V, SEL = OE = VDD Power OFF Leakage Current, ID+, IDDYNAMIC CHARACTERISTICS Turn-ON Time, tON Turn-OFF Time, tOFF Break-Before-Make Time Delay, tD Skew, (tSKEWOUT - tSKEWIN) VDD = 3.3V, RL = 50Ω, CL = 10pF (see Figure 1) VDD = 3.3V, RL = 50Ω, CL = 10pF (see Figure 1) VDD = 3.3V, RL = 50Ω , CL = 10pF (see Figure 2) VDD = 3.3V, SEL = 0V or 3.3V, OE = 0V, RL = 45Ω, CL = 10pF, tR = tF = 500ps at 480Mbps, (Duty Cycle = 50%) (see Figure 6) 25 25 25 25 - 35 27 10 50 - ns ns ns ps Rise/Fall Degradation (Propagation VDD = 3.3V, SEL = 0V or 3.3V, OE = 0V, Delay), tPD RL = 45Ω, CL = 10pF, (see Figure 6) Crosstalk OFF-Isolation -3dB Bandwidth OFF Capacitance, CHSxOFF VDD = 3.3V, RL = 50Ω, f = 240MHz (see Figure 5) VDD = 3.3V, OE = 3.3V, RL = 50Ω, f = 240MHz Signal = 0dBm, 0.2VDC offset, RL = 50Ω f = 1MHz, VDD = 3.3V, SEL = 0V, OE = 3.3V, VHSD1x or VHSD2x = VDx = 0V (see Figure 4) f = 1MHz, VDD = 3.3V, SEL = 0V or 3.3V, OE = 0V, VHSD1x or VHSD2x = VDx = 0V (see Figure 4) f = 240MHz, VDD = 3.3V, SEL = 0V or 3.3V, OE = 0V, VHSD1x or VHSD2x = VDx = 0V (see Figure 4) 25 25 25 25 25 - 250 -36 -32 742 2.8 - ps dB dB MHz pF COM ON Capacitance, CDX(ON) 25 - 7.4 - pF COM ON Capacitance, CDX(ON) 25 - 4.2 - pF POWER SUPPLY CHARACTERISTICS Power Supply Range, VDD Positive Supply Current, IDD VDD = 5.5V, SEL = 0V or VDD, OE = 0V or VDD VDD = 4.3V, SEL = 2.6V, OE = 0V or 2.6V Full 25 Full 25 Full Positive Supply Current, IDD VDD = 3.6V, SEL = 1.4V, OE = 0V or 1.4V 25 Full DIGITAL INPUT CHARACTERISTICS Input Voltage Low, VSELL, VOEL Input Voltage High, VSELH, VOEH Input Voltage Low, VSELL, VOEL VDD = 2.7V to 3.6V VDD = 2.7V to 3.6V VDD = 4.3V to 5.5V Full Full Full 1.4 0.5 0.8 V V V 2.7 0.009 0.159 6.6 5.5 0.03 1 0.6 1.6 10 12 V µA µA µA µA µA µA Positive Supply Current, IDD 5 FN6819.1 February 4, 2010 ISL54220 Electrical Specifications - 2.7V to 5.5V Supply Test Conditions: VDD = +3.3V, GND = 0V, VSELH = 1.4V, VSELL = 0.5V, VOEH = 1.4V, VOEL = 0.5V, (Note 11), Unless Otherwise Specified. Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued) TEMP MIN (°C) (Notes 12, 13) Full Full Full Full 2.0 TYP 3.3 -3.6 -8.2 MAX (Notes 12, 13) UNITS V nA nA nA PARAMETER Input Voltage High, VSELH, VOEH Input Current, ISELL, IOEL Input Current, ISELH Input Current, IOEH NOTES: TEST CONDITIONS VDD = 4.3V to 5.5V VDD = 5.5V, SEL = 0V, OE = 0V VDD = 5.5V, SEL = 5.5V VDD = 5.5V, OE = 5.5V 11. VLOGIC = Input voltage to perform proper function. 12. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. 13. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. 14. Flatness is defined as the difference between maximum and minimum value of ON-resistance over the specified analog signal range. 15. rON matching between channels is calculated by subtracting the channel with the highest max rON value from the channel with lowest max rON value, between HSD2+ and HSD2- or between HSD1+ and HSD1-. 16. Limits established by characterization and are not production tested. Test Circuits and Waveforms VDD LOGIC INPUT 50% 0V tOFF SWITCH INPUT VINPUT 90% SWITCH OUTPUT 0V tON VOUT 90% VIN VINPUT SWITCH INPUT HSDxx Dx SEL GND OE RL 50Ω CL 10pF VOUT tr < 20ns tf < 20ns VDD C Logic input waveform is inverted for switches that have the opposite logic sense. Repeat test for all switches. CL includes fixture and stray capacitance. RL V OUT = V (INPUT) ----------------------R L + r ON FIGURE 1B. TEST CIRCUIT FIGURE 1A. MEASUREMENT POINTS FIGURE 1. SWITCHING TIMES 6 FN6819.1 February 4, 2010 ISL54220 Test Circuits and Waveforms (Continued) VDD C VDD LOGIC INPUT 0V VINPUT HSD2x HSD1x SEL SWITCH OUTPUT VOUT 90% VIN 0V tD GND OE Dx RL 50Ω VOUT CL 10pF Repeat test for all switches. CL includes fixture and stray capacitance. FIGURE 2A. MEASUREMENT POINTS FIGURE 2B. TEST CIRCUIT FIGURE 2. BREAK-BEFORE-MAKE TIME VDD C rON = V1/40mA HSDx VHSDX V1 40mA SEL OV OR VDD Dx GND OE Repeat test for all switches. FIGURE 3. rON TEST CIRCUIT 7 FN6819.1 February 4, 2010 ISL54220 Test Circuits and Waveforms (Continued) VDD C VDD C HSDxx SIGNAL GENERATOR SEL HSD1x Dx 50Ω IMPEDANCE ANALYZER Dx GND OE SEL 0V OR VDD VIN ANALYZER RL Repeat test for all switches. Dx GND HSD2x OE NC Signal direction through switch is reversed, worst case values are recorded. Repeat test for all switches. FIGURE 4. CAPACITANCE TEST CIRCUIT FIGURE 5. CROSSTALK TEST CIRCUIT VDD C tri 90% DIN+ DIN10% 50% tskew_i 90% 50% 10% tfi tro 90% OUT+ OUT10% 50% tskew_o 90% tf0 50% 10% GND |tro - tri| Delay Due to Switch for Rising Input and Rising Output Signals. |tfo - tfi| Delay Due to Switch for Falling Input and Falling Output Signals. |tskew_0| Change in Skew through the Switch for Output Signals. |tskew_i| Change in Skew through the Switch for Input Signals. DINDIN+ 143Ω 15.8Ω 143Ω COMD1 OE D1 CL VIN 15.8Ω SEL COMD2 D2 CL OUT+ 45Ω OUT45Ω FIGURE 6A. MEASUREMENT POINTS FIGURE 6. SKEW TEST FIGURE 6B. TEST CIRCUIT 8 FN6819.1 February 4, 2010 ISL54220 Application Block Diagram µCONTROLLER VDD SEL ISL54220 LOGIC CIRCUITRY OE VBUS USB CONNECTOR D- D- HSD1HSD1+ USB HIGH-SPEED OR FULL-SPEED TRANSCEIVER #1 USB HIGH_SPEED OR FULL-SPEED TRANSCEIVER #2 PORTABLE MEDIA DEVICE D+ GND D+ HSD2HSD2+ GND Detailed Description The ISL54220 device is a dual single pole/double throw (SPDT) analog switch configured as a DPDT that operates from a single DC power supply in the range of 2.7V to 5.5V. It was designed to function as a dual 2-to-1 multiplexer to select between two USB high-speed differential data signals in portable battery powered products. It is offered in a TDFN, MSOP, and a small µTQFN packages for use in MP3 players, cameras, PDAs, cell phones, and other personal media players. The device has an enable pin to open all switches. The part consists of four 6Ω high speed (HSx) switches. These switches have high bandwidth and low capacitance to pass USB high-speed (480Mbps) differential data signals with minimal edge and phase distortion. They can also swing from 0V to VDD to pass USB full speed (12Mbps) differential data signals with minimal distortion. The ISL54220 was designed for MP3 players, cameras, cell phones, and other personal media player applications that have multiple high-speed or full-speed transceivers sections and need to multiplex between these USB sources to a single USB host (computer). A typical application block diagram of this is shown on page 9. A detailed description of the HS switches is provided in the following section. the HSD1 and HSD2 switches over this signal range is only 0.12Ω, ensuring minimal impact by the switches to USB high speed signal transitions. As the signal level increases, the rON switch resistance increases. At signal level of 3.3V, the switch resistance is nominally 129Ω. See Figures 7, 8, 9, 10 in the “Typical Performance Curves” beginning on page 11. The HSx switches were specifically designed to pass USB 2.0 high-speed (480Mbps) differential signals in the range of 0V to 400mV. They have low capacitance and high bandwidth to pass the USB high-speed signals with minimum edge and phase distortion to meet USB 2.0 high speed signal quality specifications. See Figure 11 in the “Typical Performance Curves” on page 12 for USB High-speed Eye Pattern taken with switch in the signal path. The HSx switches can also pass USB full-speed signals (12Mbps) with minimal distortion and meet all the USB requirements for USB 2.0 full-speed signaling. See Figure 12 in the “Typical Performance Curves” on page 13 for USB Full-speed Eye Pattern taken with switch in the signal path. The maximum normal operating signal range for the HSx switches is from 0V to VDD. The signal voltage should not be allow to exceed the VDD voltage rail or go below ground by more than -0.3V for normal operation. However, in the event that the USB 5.25V VBUS voltage gets shorted to one or both of the D-/D+ pins, the ISL54220 has special fault protection circuitry to prevent damage to the ISL54220 part. The fault circuitry allows the signal pins (D-, D+, HS1D-, HS1D+, HS2D-, HS2D+) to be driven up to 5.5V while the VDD supply voltage is in the range of 0V to 5.5V. In this condition the part draws < 500µA of current and causes no stress to the IC. In addition when VDD is at 0V (ground) all switches are OFF FN6819.1 February 4, 2010 High-Speed (HSx) Switches The HSx switches (HSD1-, HSD1+, HSD2-, HSD2+) are bi-directional switches that can pass rail-to-rail signals. When powered with a 3.3V supply, these switches have a nominal rON of 6Ω over the signal range of 0V to 400mV with a rON flatness of 0.94Ω. The rON matching between 9 ISL54220 and the fault voltage is isolated from the other side of the switch. When VDD is in the range of 2.7V to 5.5V the fault voltage will pass through to the output of an active switch channel. The HS1 channel switches are active (turned ON) whenever the SEL voltage is logic “0” (Low) and the OE voltage is logic “0” (Low). The HS2 channel switches are active (turned ON) whenever the SEL voltage is logic “1” (High) and the OE voltage is logic “0” (Low). With VDD supply voltage in the range of 4.3V to 5.5V the logic levels are: OE = Logic “0” (Low) when VOE ≤ 0.8V OE = Logic “1” (High) when VOE ≥ 2.0V SEL = Logic “0” (Low) when VSEL ≤ 0.8V SEL = Logic “1” (High) when VSEL ≥ 2.0V HSD1 USB Channel If the SEL pin = Logic “0” and the OE pin = Logic “0”, high-speed Channel 1 will be ON. The HSD1- and HSD1+ switches are ON and the HSD2- and HSD2+ switches are OFF (high impedance). When a computer or USB hub is plugged into the common USB connector and channel one is active, a link will be established between the USB 1 driver section of the media player and the computer. The device will be able to transmit and receive data from the computer at a data rate of 480Mbps. HSD2 USB Channel If the SEL pin = Logic “1” and the OE pin = Logic “0”, high-speed Channel 2 will be ON. The HSD2- and HSD2+ switches are ON and the HSD1- and HSD1+ switches are OFF (high impedance). When a USB cable from a computer or USB hub is connected at the common USB connector and the part has Channel 2 active, a link will be established between the USB 2 driver section of the media player and the computer. The device will be able to transmit and receive data from the computer at a data rate of 480Mbps. All Switches OFF Mode If the SEL pin = Logic “0” or Logic “1” and the OE pin = Logic “1”, all of the switches will turn OFF (high impedance). The all OFF state can be used to switch between the two USB sections of the media player. When disconnecting from one USB device to the other USB device, you can momentarily put the ISL54220 switch in the “all off” state in order to get the computer to disconnect from the one device so it can properly connect to the other USB device when that channel is turned ON. ISL54220 Operation The following will discuss using the ISL54220 shown in the “Application Block Diagram” on page 9. POWER The power supply connected at the VDD pin provides the DC bias voltage required by the ISL54220 part for proper operation. The ISL54220 can be operated with a VDD voltage in the range of 2.7V to 5.5V. When used in a USB application, the VDD voltage should be kept in the range of 3.0V to 5.5V to ensure you get the proper signal levels for good signal quality. A 0.01µF or 0.1µF decoupling capacitor should be connected from the VDD pin to ground to filter out any power supply noise from entering the part. The capacitor should be located as close to the VDD pin as possible. In a typical application, VDD will be in the range of 2.8V to 4.3V and will be connected to the battery or LDO of the portable media device. LOGIC CONTROL The state of the ISL54220 device is determined by the voltage at the SEL pin and the OE pin. SEL is only active when the OE pin is logic “0” (Low). Refer to “Truth Table” on page 2. The ISL54220 logic pins are designed to minimize current consumption when the logic control voltage is lower than the VDD supply voltage. With VDD = 3.6V and logic pins at 1.4V the part typically draws only 6.6µA. With VDD = 4.3V and logic pins at 2.6V, the part typically draws only 0.2µA. Driving the logic pins to the VDD supply rail minimizes power consumption. The logic pins must be held High or Low and must not float. Logic Control Voltage Levels With VDD supply voltage in the range of 2.7V to 3.6V the logic levels are: OE = Logic “0” (Low) when VOE ≤ 0.5V OE = Logic “1” (High) when VOE ≥ 1.4V SEL = Logic “0” (Low) when VSEL ≤ 0.5V SEL = Logic “1” (High) when VSEL ≥ 1.4V USB 2.0 VBUS Short Requirements The USB specification in section 7.1.1 states a USB device must be able to withstand a VBUS short to the D+ or D- signal lines when the device is either powered off or powered on for at least 24 hours. The ISL54220 part has special fault protection circuitry to meet these short circuit requirements. The fault protection circuitry allows the signal pins (D-, D+, HS1D-, HS1D+, HS2D-, HS2D+) to be driven up to 5.5V while the VDD supply voltage is in the range of 0V to 5.5V. In this overvoltage condition the part draws