ISL54225IRTZEVAL1Z

High-Speed USB 2.0 (480Mbps) Multiplexer with Overvoltage Protection (OVP) ISL54225 The Intersil ISL54225 is a single supply dual 2:1 multiplexer that can operate from a single 2.7V to 5.25V supply. It contains two SPDT (Single Pole/Double Throw) switches configured as a DPDT. The part was designed for switching or routing of USB High-Speed signals and/or USB Full-speed signals in portable battery powered products. The 6.5Ω switches were specifically designed to pass USB high speed/full speed data signals. They have high bandwidth and low capacitance to pass USB high speed data signals with minimal DISTORTION. The ISL54225 has OVP circuitry on the D-/D+ COM pins that opens the USB in-line switches when the voltage at these pins exceeds 3.8V (typ) or goes negative by -0.5V (typ). It isolates fault voltages up to +5.25V or down to -5V from getting passed to the other-side of the switch, thereby protecting the USB transceivers. The digital logic inputs are 1.8V logic compatible when operated with a 2.7V to 3.6V supply. The ISL54225 has an output enable pin to open all the switches. It can be used to facilitate proper bus disconnect and connection when switching between the USB sources. The ISL54225 is available in 10 Ld 1.8mmx1.4mm µTQFN and 10 Ld TDFN packages. It operates over a temperature range of -40°C to +85°C. ISL54225 Features • High-Speed (480Mbps) and Full-Speed (12Mbps) Signaling Capability per USB 2.0 • 1.8V Logic Compatible (2.7V to +3.6V Supply) • Enable Pin to Open all Switches • Low Power Mode • Power OFF Protection • D-/D+ Pins Overvoltage Protection for +5.25V and -5V Fault Voltages • -3dB Frequency . . . . . . . . . . . . . . . . . . . . 780MHz • Low ON Capacitance @ 240MHz . . . . . . . . . . 3.3pF • Low ON-Resistance . . . . . . . . . . . . . . . . . . . . 6.5Ω • Single Supply Operation (VDD) . . . . . 2.7V to 5.25V • Available in µTQFN and TDFN Packages • Pb-Free (RoHS Compliant) • Compliant with USB 2.0 Short Circuit and Overvoltage Requirements Without Additional External Components Applications*(see page 16) • MP3 and other Personal Media Players • Cellular/Mobile Phones • PDA’s • Digital Cameras and Camcorders • USB Switching Typical Application 3.3V 500Ω USB 2.0 HS Eye Pattern With Switches in the Signal Path VOLTAGE SCALE (0.1V/DIV) VDD LOGIC USB CONNECTOR VBUS DDOVP D+ ISL54225 GND CONTROL OE SEL HSD1HSD1+ µP USB TRANSCEIVER USB TRANSCEIVER D+ GND HSD2HSD2+ TIME SCALE (0.2ns/DIV) July 2, 2010 FN7627.0 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2010. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL54225 Pin Configuration ISL54225 (10 LD 1.8X1.4 µTQFN) TOP VIEW HSD1+ HSD17 OE 8 LOGIC CONTROL VDD 9 SEL 10 6 5 4 3 1 2 DGND D+ SEL 1 HSD2- 2 HSD2+ 3 D+ 4 GND 5 OVP PD LOGIC CONTROL 10 VDD 9 8 7 6 OE HSD1+ HSD1D- ISL54225 (10 LD 3X3 TDFN) TOP VIEW OVP HSD2- HSD2+ NOTE: 1. Switches Shown for SEL = Logic “1” and OE = Logic “0”. Pin Descriptions µTQFN 1 2 3 4 5 6 7 8 9 10 TDFN 2 3 4 5 6 7 8 9 10 1 PD PIN NAME DESCRIPTION HSD2- USB Data Port Channel 2 HSD2+ USB Data Port Channel 2 D+ GND DUSB Data COM Port Ground Connection USB Data COM Port Truth Table OE 0 0 1 1 SEL 0 1 0 1 HSD1-, HSD1+ ON OFF OFF OFF HSD2-, HSD2+ OFF ON OFF OFF STATE Normal Normal Low Power Normal HSD1- USB Data Port Channel 1 HSD1+ USB Data Port Channel 1 OE VDD SEL PD Bus Switch Enable Power Supply Select Logic Control Input Thermal Pad. Tie to Ground or Float Logic “0” when ≤ 0.5V, Logic “1” when ≥ 1.4V with a 2.7V to 3.6V Supply. Note: In Low Power mode there is no persistence checking when in OVP condition. TABLE 1. USB - OVP POSSIBLE SITUATIONS AND TRIP POINT VOLTAGE TRIP POINT CODEC SUPPLY 2.7V to 3.3V 2.7V to 3.3V SWITCH SUPPLY (VDD) 2.7V to 5.25V 2.7V to 5.25V COMs SHORTED TO VBUS -5V PROTECTED Yes Yes MIN 3.63V -0.76V MAX 3.95V -0.29V 2 FN7627.0 July 2, 2010 ISL54225 Ordering Information PART NUMBER ISL54225IRUZ-T (Notes 2, 3) ISL54225IRUZ-T7A (Notes 2, 3) ISL54225IRTZ (Note 4) ISL54225IRTZ-T (Notes 2, 4) ISL54225IRTZEVAL1Z NOTES: 2. Please refer to TB347 for details on reel specifications. 3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 4. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 5. For Moisture Sensitivity Level (MSL), please see device information page for ISL54225. For more information on MSL please see techbrief TB363. PART MARKING U0 U0 4225 4225 Evaluation Board TEMP. RANGE (°C) -40 to +85 -40 to +85 -40 to +85 -40 to +85 PACKAGE (Pb-Free) 10 Ld 1.8x1.4mm µTQFN (Tape and Reel) 10 Ld 1.8x1.4mm µTQFN (Tape and Reel) 10 Ld 3x3 TDFN 10 Ld 3x3 TDFN (Tape and Reel) PKG. DWG. # L10.1.8x1.4A L10.1.8x1.4A L10.3x3A L10.3x3A 3 FN7627.0 July 2, 2010 ISL54225 Absolute Maximum Ratings VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.5V VDD to Dx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.5V Dx to HSD1x, HSD2x . . . . . . . . . . . . . . . . . . . . . . . . . 8.6V Input Voltages HSD2x, HSD1x . . . . . . . . . . . . . . . . . . . . . - 0.3V to 6.5V SEL, OE . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.5V Output Voltages D+, D- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -5V to 6.5V Continuous Current (HSD2x, HSD1x) . . . . . . . . . . . .±40mA Peak Current (HSD2x, HSD1x) (Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . ±100mA ESD Rating: Human Body Model (Tested per JESD22-A114-F) . . . >5.5kV Machine Model (Tested per JESD22-A115-A). . . . . . . >250V Charged Device Model (Tested per JESD22-C101-D) . . >2kV Latch-up Tested per JEDEC; Class II Level A . . . . . at +85°C Thermal Information Thermal Resistance (Typical) θJA (°C/W) θJC (°C/W) 10 Ld µTQFN Package (Note 6, 7) . 210 165 10 Ld TDFN Package (Notes 8, 9). . 58 22 Maximum Junction Temperature (Plastic Package). . +150°C Maximum Storage Temperature Range . . . -65°C to +150°C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Recommended Operating Conditions Temperature Range . . . . . . VDD Supply Voltage Range . Logic Control Input Voltage Analog Signal Range VDD = 2.7V to 5.25V . . . . . . . . . . . . . . . -40°C to +85°C . . . . . . . . . . . . . 2.7V to 5.25V . . . . . . . . . . . . . . . 0V to 5.25V . . . . . . . . . . . . . . . . 0V to 3.6V CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 6. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 7. For θJC, the “case temp” location is taken at the package top center. 8. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 9. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside. Electrical Specifications - 2.7V to 5.25V Supply Test Conditions: VDD = +3.3V, GND = 0V, VSELH = 1.4V, VSELL = 0.5V, VOEH = 1.4V, VOEL = 0.5V, (Note 10), Unless Otherwise Specified. Boldface limits apply over the operating temperature range, -40°C to +85°C. TEMP MIN MAX (°C) (Notes 11, 12) TYP (Notes 11, 12) UNITS PARAMETER ANALOG SWITCH CHARACTERISTICS ON-Resistance, rON (High-Speed) rON Matching Between Channels, ΔrON (High-Speed) rON Flatness, RFLAT(ON) (High-Speed) ON-Resistance, rON TEST CONDITIONS VDD = 2.7V, SEL = 0.5V or 1.4V, OE = 0.5V, IDx = 17mA, VHSD1x or VHSD2x = 0V to 400mV (see Figure 3, Note 15) VDD = 2.7V, SEL = 0.5V or 1.4V, OE = 0.5V, IDx = 17mA, VHSD1x or VHSD2x = Voltage at max rON, (Notes 14, 15) VDD = 2.7V, SEL = 0.5V or 1.4V, OE = 0.5V, IDx = 17mA, VHSD1x or VHSD2x = 0V to 400mV, (Notes 13, 15) VDD = 3.3V, SEL = 0.5V or 1.4V, OE = 0.5V, ICOMx = 17mA, VD+ or VD-= 3.3V (See Figure 4, Note 15) VDD = 5.25V, SEL = VDD and OE = VDD or OE = 0V, VDx = 0.3V, 3.3V, VHSD1x = 3.3V, 0.3V, VHSD2x = 0.3V, 3.3V VDD = 5.25V, SEL = OE = 0V, VDx = 0.3V, 3.3V, VHSD1X = 0.3V, 3.3V, VHSD2x = 3.3V, 0.3V VDD = 5.25V, SEL = OE = 0V or OE = VDD, VDx = 3.3V, 0.3V, VHSD2x = 0.3V, 3.3V, VHSD1X = 3.3V, 0.3V 25 Full 25 Full 25 Full 25 Full 25 Full 25 Full 25 Full -20 -20 - 6.5 0.2 0.3 12 1 30 2 1 30 8 10 0.45 0.5 0.5 1 20 25 20 3 4 20 - Ω Ω Ω Ω Ω Ω Ω Ω nA nA µA µA nA nA OFF Leakage Current, IHSD1x(OFF) ON Leakage Current, IHSD1x(ON) OFF Leakage Current, IHSD2x(OFF) 4 FN7627.0 July 2, 2010 ISL54225 Electrical Specifications - 2.7V to 5.25V Supply Test Conditions: VDD = +3.3V, GND = 0V, VSELH = 1.4V, VSELL = 0.5V, VOEH = 1.4V, VOEL = 0.5V, (Note 10), Unless Otherwise Specified. Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued) TEMP MIN MAX (°C) (Notes 11, 12) TYP (Notes 11, 12) UNITS 25 Full 25 25 25 2 5 19 0.05 3 4 13 26 1 µA µA µA µA µA PARAMETER ON Leakage Current, IHSD2x(ON) Power OFF Leakage Current, ID+, IDPower OFF Logic Current, ISEL, IOE TEST CONDITIONS VDD = 5.25V, SEL = VDD, OE = 0V, VDx = 0.3V, 3.3V, VHSD2x = 0.3V, 3.3V, VHSD1x = 3.3V, 0.3V VDD = 0V, VD+ = 5.25V, VD-= 5.25V, SEL = OE = VDD VDD = 0V, SEL = OE = 5.25V Power OFF D+/D- Current, VDD = 0V, SEL = OE = VDD, IHSDX+, IHSDXVHSDX+ = VHSDX- = 5.25V OVERVOLTAGE PROTECTION DETECTION Positive Fault-Protection Trip Threshold, VPFP Negative Fault-Protection Trip Threshold, VNFP OFF Persistence Time Fault Protection Response Time VDD = 2.7V to 5.25V, SEL = 0V or VDD, OE = 0V See Table 1 on page 2 VDD = 2.7V to 5.25V, SEL = 0V or VDD, OE = 0V See Table 1 on page 2 Negative OVP Response: VDD = 2.7V, SEL = 0V or VDD, OE = 0V, VDx = 0V to -5V, RL = 15kΩ Positive OVP Response: VDD = 2.7V, SEL = 0V or VDD, OE = 0V, VDx = 0V to 5.25V, RL = 15kΩ VDD = 2.7V, SEL = 0V or VDD, OE = 0V, VDx = 0V to 5.25V or 0V to -5V, RL = 15kΩ 25 25 25 25 25 3.63 -0.76 - 3.8 -0.5 1 2 40 3.95 -0.29 - V V µs µs µs ON Persistence Time Fault Protection Recovery Time DYNAMIC CHARACTERISTICS Turn-ON Time, tON Turn-OFF Time, tOFF Break-Before-Make Time Delay, tD Turn-ON Enable Time, tENABLE Turn-OFF Disable Time, tDISABLE VDD = 3.3V, VINPUT = 3V, RL = 50Ω, CL = 50pF (see Figure 1) VDD = 3.3V, VINPUT = 3V, RL = 50Ω, CL = 50pF (see Figure 1) VDD = 3.3V, RL = 50Ω, CL = 50pF (see Figure 2) VDD = 3.3V, VINPUT = 3V, RL = 15kΩ, CL = 50pF, Time out of All-Off state VDD = 3.3V, VINPUT = 3V, RL = 15kΩ, CL = 50pF, Time into All-Off state, Time is highly dependent on the load (RL , CL) time constant. 25 25 25 25 25 110 70 40 90 120 ns ns ns ns ns Skew, (tSKEWOUT - tSKEWIN) VDD = 3.3V, SEL = 0V or 3.3V, OE = 0V, RL = 45Ω, CL = 10pF, tR = tF = 500ps at 480Mbps, (Duty Cycle = 50%) (see Figure 6) Rise/Fall Degradation (Propagation Delay), tPD Crosstalk OFF-Isolation -3dB Bandwidth VDD = 3.3V, SEL = 0V or 3.3V, OE = 0V, RL = 45Ω, CL = 10pF (see Figure 6) VDD = 3.3V, RL = 50Ω, f = 240MHz (see Figure 5) VDD = 3.3V, OE = 3.3V, RL = 50Ω, f = 240MHz Signal = 0dBm, 0.2VDC offset, RL = 50Ω 25 - 50 - ps 25 25 25 25 25 25 - 250 -32 -30 780 2.5 5.4 - ps dB dB MHz pF pF OFF Capacitance, CHSxOFF f = 1MHz, VDD = 3.3V, SEL = 0V or 3.3V, OE = VDD (see Figure 4) COM ON Capacitance, CDX(ON) f = 1MHz, VDD = 3.3V, SEL = 0V or 3.3V, OE = 0V (see Figure 4) 5 FN7627.0 July 2, 2010 ISL54225 Electrical Specifications - 2.7V to 5.25V Supply Test Conditions: VDD = +3.3V, GND = 0V, VSELH = 1.4V, VSELL = 0.5V, VOEH = 1.4V, VOEL = 0.5V, (Note 10), Unless Otherwise Specified. Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued) TEMP MIN MAX (°C) (Notes 11, 12) TYP (Notes 11, 12) UNITS 25 3.3 pF PARAMETER COM ON Capacitance, CDX(ON) TEST CONDITIONS f = 240MHz, VDD = 3.3V, SEL = 0V or 3.3V, OE = 0V (see Figure 4) POWER SUPPLY CHARACTERISTICS Power Supply Range, VDD Positive Supply Current, IDD VDD = 5.25V, SEL = 0V or VDD, OE = 0V Full 25 Full Positive Supply Current, IDD VDD = 3.6V, SEL = 0V or VDD, OE = 0V 25 Full Positive Supply Current, IDD (Low Power State) VDD = 3.6V, SEL = 0V, OE = VDD 25 Full 25 Full Positive Supply Current, IDD VDD = 3.6V, SEL = 1.4V, OE = 0V or 1.4V 25 Full DIGITAL INPUT CHARACTERISTICS Input Voltage Low, VSELL, VOEL VDD = 2.7V to 3.6V Full Full Full Full Full Full Full Full Full 1.4 1.7 2.0 3.3 1.4 1.4 0.5 5.25 0.7 5.25 0.8 5.25 V V V V V V nA µA µA 2.7 45 23 5 35 25 5.25 58 66 30 35 6 10 45 52 32 38 V µA µA µA µA µA µA µA µA µA µA Positive Supply Current, IDD VDD = 4.3V, SEL = 2.6V, OE = 0V or 2.6V Input Voltage High, VSELH, VDD = 2.7V to 3.6V VOEH Input Voltage Low, VSELL, VOEL VDD = 3.7V to 4.2V Input Voltage High, VSELH, VDD = 3.7V to 4.2 VOEH Input Voltage Low, VSELL, VOEL VDD = 4.3V to 5.25V Input Voltage High, VSELH, VDD = 4.3V to 5.25V VOEH Input Current, ISELL, IOEH VDD = 5.25V, SEL = 0V, OE = 5.25V Input Current, ISELH Input Current, IOEL NOTES: 10. VLOGIC = Input voltage to perform proper function. VDD = 5.25V, SEL = 5.25V, 4MΩ pull-down resistor VDD = 5.25V, OE = 0V, 4MΩ pull-up resistor 11. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. 12. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. 13. Flatness is defined as the difference between maximum and minimum value of ON-resistance over the specified analog signal range. 14. rON matching between channels is calculated by subtracting the channel with the highest max rON value from the channel with lowest max rON value, between HSD2+ and HSD2- or between HSD1+ and HSD1-. 15. Limits established by characterization and are not production tested. 6 FN7627.0 July 2, 2010 ISL54225 Test Circuits and Waveforms VDD LOGIC INPUT 50% 0V tOFF SWITCH INPUT VINPUT 90% SWITCH OUTPUT 0V tON VOUT 90% VIN VINPUT SWITCH INPUT HSDxx Dx SEL GND OE RL CL VOUT tr < 20ns tf < 20ns VDD C Logic input waveform is inverted for switches that have the opposite logic sense. Repeat test for all switches. CL includes fixture and stray capacitance. RL ----------------------V OUT = V (INPUT) R + r L ON FIGURE 1B. TEST CIRCUIT FIGURE 1A. MEASUREMENT POINTS FIGURE 1. SWITCHING TIMES VDD C VDD LOGIC INPUT 0V VINPUT HSD2x HSD1x SEL SWITCH OUTPUT VOUT 90% VIN 0V tD GND OE Dx RL 50Ω VOUT CL 10pF Repeat test for all switches. CL includes fixture and stray capacitance. FIGURE 2A. MEASUREMENT POINTS FIGURE 2B. TEST CIRCUIT FIGURE 2. BREAK-BEFORE-MAKE TIME VDD C rON = V1/17mA HSDx VHSDx V1 17mA SEL 0V OR VDD Dx GND OE Repeat test for all switches. FIGURE 3. rON TEST CIRCUIT 7 FN7627.0 July 2, 2010 ISL54225 Test Circuits and Waveforms (Continued) VDD C VDD C HSDxx SIGNAL GENERATOR SEL HSD1x Dx 50Ω IMPEDANCE ANALYZER Dx GND OE SEL 0V OR VDD VIN ANALYZER RL Repeat test for all switches. Dx GND HSD2x OE NC Signal direction through switch is reversed, worst case values are recorded. Repeat test for all switches. FIGURE 4. CAPACITANCE TEST CIRCUIT FIGURE 5. CROSSTALK TEST CIRCUIT VDD C tri 90% DIN+ DIN10% 50% tskew_i 90% 50% 10% tfi tro 90% OUT+ OUT10% 50% tskew_o 90% tf0 50% 10% GND |tro - tri| Delay Due to Switch for Rising Input and Rising Output Signals. |tfo - tfi| Delay Due to Switch for Falling Input and Falling Output Signals. |tskew_0| Change in Skew through the Switch for Output Signals. |tskew_i| Change in Skew through the Switch for Input Signals. DINDIN+ 143Ω 15.8Ω 143Ω COMD1 D1 OE CL VIN 15.8Ω SEL COMD2 D2 CL OUT+ 45Ω OUT45Ω FIGURE 6A. MEASUREMENT POINTS FIGURE 6. SKEW TEST FIGURE 6B. TEST CIRCUIT 8 FN7627.0 July 2, 2010 ISL54225 Application Block Diagram 500Ω ISL54225 SEL VBUS USB CONNECTOR DDOVP D+ GND GND D+ 4MΩ HSD1HSD1+ HSD2HSD2+ VDD VDD 4MΩ LOGIC CIRCUITRY OE µCONTROLLER USB HIGH-SPEED OR FULL-SPEED TRANSCEIVER #1 USB HIGH_SPEED OR FULL-SPEED TRANSCEIVER #2 PORTABLE MEDIA DEVICE Detailed Description The ISL54225 device is a dual single pole/double throw (SPDT) analog switch configured as a DPDT that operates from a single DC power supply in the range of 2.7V to 5.25V. It was designed to function as a dual 2-to-1 multiplexer to select between two USB high-speed differential data signals in portable battery powered products. It is offered in a TDFN, and a small µTQFN packages for use in MP3 players, cameras, PDAs, cellphones, and other personal media players. The device has an enable pin to open all switches and put the part in a low power state. The part contains special overvoltage detection and protection (OVP) circuitry on the D-/D+ COM pins. This circuitry acts to open the USB in-line switches when the part senses a voltage on the COM pins that is >3.8V (typ) or < -0.5V (typ). It isolates voltages up to 5.25V and down to -5V from getting through to the other side of the switch to protect the USB transceivers connected at the signal pins (HSD1-, HSD1+, HSD2-, HSD2+). The part consists of four 6.5Ω high speed (HSx) switches. These switches have high bandwidth and low capacitance to pass USB high-speed (480Mbps) differential data signals with minimal edge and phase distortion. They can also swing from 0V to 3.6V to pass USB full speed (12Mbps) differential data signals with minimal distortion. The ISL54225 was designed for MP3 players, cameras, cellphones, and other personal media player applications that have multiple high-speed or full-speed transceivers sections and need to multiplex between these USB sources to a single USB host (computer). A typical application block diagram of this functionality is previously shown. A detailed description of the HS switches is provided in the following section. High-Speed (HSx) Data Switches The HSx switches (HSD1-, HSD1+, HSD2-, HSD2+) are bi-directional switches that can pass USB high-speed and USB full-speed signals when VDD is in the range of 2.7V to 5.25V. When powered with a 2.7V supply, these switches have a nominal rON of 6.5Ω over the signal range of 0V to 400mV with a rON flatness of 0.3Ω. The rON matching between the HSD1x switches and HSD2x switches over this signal range is only 0.2Ω, ensuring minimal impact by the switches to USB high-speed signal transitions. As the signal level increases, the rON switch resistance increases. At signal level of 3.3V, the switch resistance is nominally 12Ω. See Figures 9, 10, 11, 12, 13, 14, 15 and 16 in the “Typical Performance Curves” beginning on page 12. The HSx switches were specifically designed to pass USB 2.0 high-speed (480Mbps) differential signals in the range of 0V to 400mV. They have low capacitance and high bandwidth to pass the USB high-speed signals with minimum edge and phase distortion to meet USB 2.0 high speed signal quality specifications. See Figure 21 in the “Typical Performance Curves” on page 14 for USB High-speed Eye Pattern taken with switch in the signal path. The HSx switches can also pass USB full-speed signals (12Mbps) with minimal distortion and meet all the USB requirements for USB 2.0 full-speed signaling. See Figure 22 in the “Typical Performance Curves” on page 14 for USB Full-speed Eye Pattern taken with switch in the signal path. 9 FN7627.0 July 2, 2010 ISL54225 The HS1 channel switches are active (turned ON) whenever the SEL voltage is logic “0”(Low) and the OE voltage is logic “0”(Low). The HS2 channel switches are active (turned ON) whenever the SEL voltage is logic “1” (High) and the OE voltage is logic “0” (Low). OVERVOLTAGE PROTECTION (OVP) The maximum normal operating signal range for the HSx switches is from 0V to 3.6V. For normal operation, the signal voltage should not be allowed to exceed these voltage levels or go below ground by more than -0.3V. However, in the event that a positive voltage > 3.8V (typ) to 5.25V, such as the USB 5V VBUS voltage, gets shorted to one or both of the COM+ and COM- pins or a negative voltage < -0.5V (typ) to -5V gets shorted to one or both of the COM pins, the ISL54225 has OVP circuitry to detect the overvoltage condition and open the SPDT switches to prevent damage to the USB down-stream transceivers connected at the signal pins (HS1D-, HS1D+, HS2D-, HS2D+). The OVP and power-off protection circuitry allows the COM pins (D-, D+) to be driven up to 5.25V while the VDD supply voltage is in the range of 0V to 5.25V. In this condition, the part draws < 100µA of ICOMx and IDD current and causes no stress to the IC. In addition, the SPDT switches are OFF and the fault voltage is isolated from the other side of the switch. External VDD Series Resistor to Limit IDD Current during Negative OVP Condition A 100Ω to 1kΩ resistor in series with the VDD pin (see Figure 7) is required to limit the IDD current draw from the system power supply rail during a negative OVP fault event. With a negative -5V fault voltage at both COM pins, the graph in Figure 8 shows the IDD current draw for different external resistor values for supply voltages of 2.7V, 3.6V, and 5.25V. With a 500Ω resistor, the current draw is limited to around 5mA. When the negative fault voltage is removed, the IDD current will return to it’s normal operation current of 25µA to 45µA. The series resistor also provides improved ESD and latch-up immunity. During an overvoltage transient event (such as occurs during system level IEC 61000 ESD testing), substrate currents can be generated in the IC that can trigger parasitic SCR structures to turn ON, creating a low impedance path from the VDD power supply to ground. This will result in a significant amount of current flow in the IC, which can potentially create a latch-up state or permanently damage the IC. The external VDD resistor limits the current during this over-stress situation and has been found to prevent latch-up or destructive damage for many overvoltage transient events. Under normal operation, the low microamp IDD current of the IC produces an insignificant voltage drop across the series resistor resulting in no impact to switch operation or performance. 10 -5V FAULT VOLTAGE VSUPPLY PROTECTION RESISTOR 100Ω to 1kΩ VDD D+ DOVP HSD1+ HSD2+ HSD1HSD2OE C IDD SEL LOGIC GND FIGURE 7. VDD SERIES RESISTOR TO LIMIT IDD CURRENT DURING NEGATIVE OVP AND FOR ENHANCED ESD AND LATCH-UP IMMUNITY 25 VCOM+ = VCOM- = -5V 20 IDD (mA) 15 10 5 0 100 3.6V 5.25V 2.7V 200 300 400 500 600 700 RESISTOR (Ω) 800 900 1k FIGURE 8. NEGATIVE OVP IDD CURRENT vs RESISTOR VALUE vs VSUPPLY ISL54225 Operation The following will discuss using the ISL54225 shown in the “Application Block Diagram” on page 9. POWER The power supply connected at the VDD pin provides the DC bias voltage required by the ISL54225 part for proper operation. The ISL54225 can be operated with a VDD voltage in the range of 2.7V to 5.25V. For lowest power consumption you should use the lowest VDD supply. A 0.01µF or 0.1µF decoupling capacitor should be connected from the VDD pin to ground to filter out any power supply noise from entering the part. The capacitor should be located as close to the VDD pin as possible. In a typical application, VDD will be in the range of 2.8V to 4.3V and will be connected to the battery or LDO of the portable media device. FN7627.0 July 2, 2010 ISL54225 LOGIC CONTROL The state of the ISL54225 device is determined by the voltage at the SEL pin and the OE pin. SEL is only active when the OE pin is logic “0” (Low). Refer to “Truth Table” on page 2. The ISL54225 logic pins are designed to minimize current consumption when the logic control voltage is lower than the VDD supply voltage. With VDD = 3.6V and logic pins at 1.4V, the part typically draws only 25µA. With VDD = 4.3V and logic pins at 2.6V, the part typically draws only 35µA. Driving the logic pins to the VDD supply rail minimizes power consumption. The SEL pin and OE pin have special circuitry that allows them to be driven with a voltage higher than the VDD supply voltage. These pins can be driven up to 5.25V with a VDD supply in the range of 2.7V to 5.25V. The SEL pin is internally pulled low through 4MΩ resistor to ground. The OE pin is internally pulled high through a 4MΩ resistor to VDD. These pins can be tri-stated by a µProcessor or left floating. Logic Control Voltage Levels TABLE 2. LOGIC CONTROL VOLTAGE LEVELS LOGIC = “0” (LOW) OE ≤ 0.5V SEL ≤ 0.5V or floating ≤ 0.7V or floating ≤ 0.8V or floating LOGIC = “1” (HIGH) OE ≥1.4V or floating ≥1.7V or floating ≥2.0V or floating SEL ≥1.4V When a USB cable from a computer or USB hub is connected at the common USB connector and the part has Channel 2 active, a link will be established between the USB 2 driver section of the media player and the computer. The device will be able to transmit and receive data from the computer. All Switches OFF Mode If the SEL pin = Logic “0” and the OE pin = Logic “1”, all of the switches will turn OFF (high impedance) and the part will be put in a low power mode. In this mode, the part draws only 10µA (max) of current across the operating temperature range. In the low power mode, the persistence checking of the OVP circuitry is de-activated. If the SEL pin = Logic “1” and the OE pin = Logic “1”, all of the switches will turn OFF (high impedance). In this state the complete OTV circuitry is activated. The all OFF state can be used to switch between the two USB sections of the media player. When disconnecting from one USB device to the other USB device, you can momentarily put the ISL54225 switch in the “all off” state in order to get the computer to disconnect from the one device so it can properly connect to the other USB device when that channel is turned ON. Whenever the ISL54225 senses a fault condition on the COM pins, all switches will be turned OFF regardless of the voltage levels at the SEL and OE pins. VDD SUPPLY RANGE 2.7V to 3.6V USB 2.0 VBUS Short Requirements The USB specification in section 7.1.1 states a USB device must be able to withstand a VBUS short (4.4V to 5.25V) or a -1V short to the D+ or D- signal lines when the device is either powered off or powered on for at least 24 hours. The ISL54225 part has special power-off protection and OVP detection circuitry to meet these short circuit requirements. This circuitry allows the ISL54225 to provide protection to the USB down-stream transceivers connected at its signal pins (HS1D-, HS1D+, HS2D-, HS2D+) to meet the USB specification short circuit requirements. The power-off protection and OVP circuitry allows the COM pins (D-, D+) to be driven up to 5.25V or down to -5V while the VDD supply voltage is in the range of 0V to 5.25V. In these overvoltage conditions with a 500Ω external VDD resistor, the part draws < 55µA of current into the COM pins and causes no stress/damage to the IC. In addition, all switches are OFF and the shorted VBUS voltage will be isolated from getting through to the other side of the switch channels, thereby protecting the USB transceivers. 3.7V to 4.2V ≤ 0.7V ≥1.7V 4.3V to 5.25V ≤ 0.8V ≥2.0V HSD1 USB Channel If the SEL pin = Logic “0” and the OE pin = Logic “0”, high-speed Channel 1 will be ON. The HSD1- and HSD1+ switches are ON and the HSD2- and HSD2+ switches are OFF (high impedance). When a computer or USB hub is plugged into the common USB connector and Channel 1 is active, a link will be established between the USB 1 transceiver section of the media player and the computer. The device will be able to transmit and receive data from the computer. HSD2 USB Channel If the SEL pin = Logic “1” and the OE pin = Logic “0”, high-speed Channel 2 will be ON. The HSD2- and HSD2+ switches are ON and the HSD1- and HSD1+ switches are OFF (high impedance). 11 FN7627.0 July 2, 2010 ISL54225 Typical Performance Curves 6.5 6.4 6.3 6.2 rON (Ω) 6.1 6.0 5.9 5.8 5.7 5.6 0 0.1 3.0V 3.3V 3.6V 4.3V ICOM = 17mA 2.7V TA = +25°C, Unless Otherwise Specified 30 ICOM = 17mA 25 20 rON (Ω) 15 2.7V 10 3.0V 3.3V 5 5.25V 0.2 VCOM (V) 0.3 0.4 0 0 0.6 1.2 1.8 VCOM (V) 2.4 3.0 3.6 FIGURE 9. ON-RESISTANCE vs SUPPLY VOLTAGE vs SWITCH VOLTAGE 12 ICOM = 17mA FIGURE 10. ON-RESISTANCE vs SUPPLY VOLTAGE vs SWITCH VOLTAGE 8 +85°C 7 10 3.6V rON (Ω) 8 rON (Ω) +25°C 6 5.25V 6 4.3V 5 VDD = 2.7V -40°C 4 0 0.6 1.2 1.8 VCOM (V) 2.4 3.0 3.6 4 0 ICOM = 17mA 0.1 0.2 VCOM (V) 0.3 0.4 FIGURE 11. ON-RESISTANCE vs SUPPLY VOLTAGE vs SWITCH VOLTAGE 8 FIGURE 12. ON-RESISTANCE vs SWITCH VOLTAGE VDD = 3.3V ICOM = 17mA 8 +85°C VDD = 4.3V ICOM = 17mA 7 +85°C 7 rON (Ω) 6 +25°C rON (Ω) 6 +25°C 5 -40°C 5 -40°C 4 0 0.1 0.2 VCOM (V) 0.3 0.4 4 0 0.1 0.2 VCOM (V) 0.3 0.4 FIGURE 13. ON-RESISTANCE vs SWITCH VOLTAGE FIGURE 14. ON-RESISTANCE vs SWITCH VOLTAGE 12 FN7627.0 July 2, 2010 ISL54225 Typical Performance Curves 30 VDD = 2.7V ICOM = 17mA 25 TA = +25°C, Unless Otherwise Specified (Continued) 18 VDD = 3.3V ICOM = 17mA 15 20 rON (W) 12 rON (W) +85°C 9 +25°C 6 +25°C -40°C -40°C 3 15 +85°C 10 5 0 0 0.6 1.2 VCOM (V) 1.8 2.4 3.0 3.6 0 0 0.6 1.2 1.8 2.4 VCOM (V) 3.0 3.6 FIGURE 15. ON-RESISTANCE vs SWITCH VOLTAGE FIGURE 16. ON-RESISTANCE vs SWITCH VOLTAGE 1.6 -40°C TO +85°C 1.4 VINH AND VINL (V) IDD CURRENT (µA) 1.2 1.0 0.8 0.6 0.4 2.7 VINH 350 300 250 200 150 100 50 0 -50 0 SEL = “0” OR “1” VDD = 5.25V VINL VDD = 3.3V 1 2 3 4 OE LOGIC VOLTAGE (V) 5 3.2 3.7 4.2 VDD (V) 4.7 5.25 FIGURE 17. DIGITAL SWITCHING POINT vs SUPPLY VOLTAGE FIGURE 18. IDD vs OE LOGIC VOLTAGE vs VDD 45 40 35 IDD CURRENT (µA) 30 25 20 15 10 5 0 -5 -10 0 1 2 3 4 OE LOGIC VOLTAGE (V) 5 OE = “1” (LOW POWER) OE = “0” (NORMAL OPERATION) IDD CURRENT (µA) VDD = 3.3V 700 600 500 400 300 200 100 0 -100 0 OE = “1” (LOW POWER) 1 2 3 4 OE LOGIC VOLTAGE (V) 5 OE = “0” (NORMAL OPERATION) VDD = 5.25V FIGURE 19. IDD vs SEL LOGIC VOLTAGE vs OE STATE FIGURE 20. IDD vs SEL LOGIC VOLTAGE vs OE STATE 13 FN7627.0 July 2, 2010 ISL54225 Typical Performance Curves VDD = 3.3V TA = +25°C, Unless Otherwise Specified (Continued) VOLTAGE SCALE (0.1V/DIV) TIME SCALE (0.2ns/DIV) FIGURE 21. EYE PATTERN: 480Mbps WITH USB SWITCHES IN THE SIGNAL PATH VDD = 3.3V VOLTAGE SCALE (0.5V/DIV) TIME SCALE (10ns/DIV) FIGURE 22. EYE PATTERN: 12Mbps WITH USB SWITCHES IN THE SIGNAL PATH 14 FN7627.0 July 2, 2010 ISL54225 Typical Performance Curves 1 0 -1 NORMALIZED GAIN (dB) -2 -3 -4 TA = +25°C, Unless Otherwise Specified (Continued) -10 RL = 50Ω -20 VIN = 0dBm, 0.2VDC BIAS -30 NORMALIZED GAIN (dB) -40 -50 -60 -70 -80 -90 RL = 50Ω VIN = 0dBm, 0.86VDC BIAS 1M 10M 100M FREQUENCY (Hz) 1G -100 -110 0.001 0.01 0.1 1 10 100 500 FREQUENCY (MHz) FIGURE 23. FREQUENCY RESPONSE FIGURE 24. OFF-ISOLATION Die Characteristics -10 RL = 50Ω -20 VIN = 0dBm, 0.2VDC BIAS NORMALIZED GAIN (dB) -30 -40 -50 -60 -70 -80 -90 SUBSTRATE AND TDFN THERMAL PAD POTENTIAL (POWERED UP): GND TRANSISTOR COUNT: 1297 PROCESS: Submicron CMOS -100 -110 0.001 0.01 0.1 1 10 100 500 FREQUENCY (MHz) FIGURE 25. CROSSTALK 15 FN7627.0 July 2, 2010 ISL54225 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest Rev. DATE 7/2/10 REVISION FN7627.0 Initial Release. CHANGE Products Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a complete list of Intersil product families. *For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on intersil.com: ISL54225 To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff FITs are available from our website at http://rel.intersil.com/reports/search.php For additional products, see www.intersil.com/product_tree Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 16 FN7627.0 July 2, 2010 ISL54225 Package Outline Drawing L10.1.8x1.4A 10 LEAD ULTRA THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 5, 3/10 1.80 B 1 10 0.50 A 6 PIN #1 ID 1 2 3 9 X 0.40 10X 0.20 4 0.10 M C A B 0.05 M C 1.40 6 PIN 1 INDEX AREA 0.70 8 0.10 2X TOP VIEW 7 6X 0.40 BOTTOM VIEW 6 5 4X 0.30 SEE DETAIL "X" 0.10 C MAX. 0.55 (9 X 0.60) 1 (10X 0.20) 3 10 (0.70) SIDE VIEW SEATING PLANE 0.08 C C (4X 0.30) 8 5 6 7 (6X 0.40) TYPICAL RECOMMENDED LAND PATTERN (0.70) C 0 .1 27 REF PACKAGE OUTLINE 0-0.05 DETAIL "X" NOTES: 1. 2. 3. 4. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. Dimensioning and tolerancing conform to ASME Y14.5m-1994. Unless otherwise specified, tolerance : Decimal ± 0.05 Dimension applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. 6. JEDEC reference MO-255. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 17 FN7627.0 July 2, 2010 ISL54225 Package Outline Drawing L10.3x3A 10 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE Rev 5, 3/10 3.00 A 6 PIN 1 INDEX AREA 6 PIN 1 INDEX AREA 1 2.0 REF 8X 0.50 BSC 5 10X 0 . 30 B 3.00 1.50 0.15 (4X) 10 5 0.10 M C A B 0.05 M C 4 10 X 0.25 TOP VIEW 2.30 ( 2.30 ) BOTTOM VIEW 0 .80 MAX SEE DETAIL "X" 0.10 C C (2.90) (1.50) SIDE VIEW (10 X 0.50) 0 . 2 REF SEATING PLANE 0.08 C 5 ( 8X 0 .50 ) ( 10X 0.25 ) TYPICAL RECOMMENDED LAND PATTERN NOTES: 1. 2. 3. 4. C 0 . 00 MIN. 0 . 05 MAX. DETAIL "X" Dimensions are in millimeters. Dimensions in ( ) for Reference Only. Dimensioning and tolerancing conform to ASME Y14.5m-1994. Unless otherwise specified, tolerance : Decimal ± 0.05 Angular ±2.50° Dimension applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. 6. Tiebar shown (if present) is a non-functional feature. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Compliant to JEDEC MO-229-WEED-3 except exposed pad length (2.30mm). 18 FN7627.0 July 2, 2010