ISL54226IRUZ-T

DATASHEET ISL54226 FN7614 Rev 2.00 Aug 15, 2016 High-Speed USB 2.0 (480Mbps) DPST Switch with Overvoltage Protection (OVP) and Dedicated Charger Port Detection The ISL54226 is a single supply, dual SPST (Single Pole/Single Throw) switch that is configured as a DPST. It can operate from a single 2.7V to 5.25V supply. The part was designed for switching or isolating a USB high-speed source or a USB high-speed and full-speed source in portable battery powered products. Features The 3.5ΩSPST switches were specifically designed to pass USB full speed and USB high-speed data signals. They have high bandwidth and low capacitance to pass USB high-speed data signals with minimal distortion. • OE/ALM pin to open all switches and indicate overvoltage fault condition The ISL54226 has OVP detection circuitry on the COM pins to open the SPST switches when the voltage at these pins exceeds 3.8V or goes negative by -0.45V. It isolates fault voltages up to +5.25V or down to -5V from getting passed to the other side of the switch, thereby protecting the USB downstream transceiver. The OE/ALM logic pin is an open drain input/output that can be driven to open the switches or monitored to tell when the part is in an overvoltage state. • High-speed (480Mbps) and full-speed (12Mbps) signaling capability per USB 2.0 • 1.8V logic compatible (2.7V to +3.6V supply) • Charger interrupt indicator output • Power OFF protection • COM pins overvoltage protection for +5.25V and -5V fault voltages • -3dB frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 790MHz • Low ON capacitance @ 240MHz. . . . . . . . . . . . . . . . . . . . . 2pF • Low ON-resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5Ω • Single supply operation (VDD). . . . . . . . . . . . . . . 2.7V to 5.25V • Available in µTQFN and TDFN packages The part has an interrupt (INT) output pin to indicate a 1 to 1 (high/high) state on the COM lines to inform the µprocessor when entering a dedicated charging port mode of operation. • Pb-Free (RoHS compliant) The ISL54226 is available in 8 Ld 1.2mmx1.4mm µTQFN and 8 Ld 2mmx2mm TDFN packages. It operates over a temperature range of -40 to +85°C. Applications • Compliant with USB 2.0 short circuit and overvoltage requirements without additional external components • MP3 and other personal media players • Cellular/mobile phones, PDA’s • Digital cameras and camcorders • USB switching 3.3V 3.3V 500Ω USB CONNECTOR INT OE/ALM LOGIC CONTROL VBUS D- COM - D+ OVP DET COM + µP DUSB GND ISL54226 4MΩ D+ HIGH-SPEED TRANSCEIVER VOLTAGE SCALE (0.1V/DIV) 100kΩ VDD GND TIME SCALE (0.2ns/DIV) FIGURE 1. TYPICAL APPLICATION FN7614 Rev 2.00 Aug 15, 2016 FIGURE 2. USB 2.0 HS EYE PATTERN WITH SWITCHES IN THE SIGNAL PATH Page 1 of 17 ISL54226 Pin Configurations ISL54226 (8 LD 2x2 TDFN) TOP VIEW COM + OVP NO LAB VAI 1 A GER LON LE S OR O UP P D RTE 1 8 VDD 7 OE/ALM 6 D- 5 COM- LOGIC D+ 2 4MΩ 5 D- PD INT 6 7 8 GND COM - ISL54226 (8 LD 1.2x1.4 µTQFN) TOP VIEW COM+ 3 GND 4 D+ LOGIC OVP 2 3 4 OE/ALM VDD INT 4MΩ NOTE: 1. Switches Shown for OE/ALM = Logic “0”. Pin Descriptions Truth Table INPUT µTQFN TDFN PIN NAME 4 1 INT Charger Mode Interrupt Output 5 2 D+ 6 3 COM+ 7 4 GND Ground Connection 8 5 COM- USB Data Port 1 6 D- USB Data Port 2 7 3 8 VDD - PD PD DESCRIPTION OUTPUT SIGNAL AT COM PINS OE/ALM D-, D+ INT OE/ALM STATE USB Data Port 0V to 3.6V 0 OFF High Low Normal USB Data Port 0V to 3.6V 1 ON High High Normal Overvoltage Range 0 OFF High Low OVP Overvoltage Range 1 OFF High Low OVP COM Pins Tied Together 0 OFF Low Low Charger Port (CP) COM Pins Tied Together 1 ON High High Normal OE/ALM Switch Enable/Alarm (Open Drain) Drive Low to Open Switches Outputs are Low when OVP is Activated Power Supply Thermal Pad. Tie to Ground or Float Logic “0” when 0.5V, Logic “1” when 1.4V with a 2.7V to 3.6V Supply. TABLE 1. OVP TRIP POINT VOLTAGE SYSTEM VOLTAGE CONDITIONS TRIP POINT CODEC SUPPLY SWITCH SUPPLY (VDD) COMs SHORTED TO PROTECTED MIN MAX 2.7V to 3.3V 2.7V to 5.25V VBUS Yes 3.62V 3.95V 2.7V to 3.3V 2.7V to 5.25V -5V Yes -0.6V -0.29V FN7614 Rev 2.00 Aug 15, 2016 Page 2 of 17 ISL54226 Ordering Information PART NUMBER (Notes 2, 5) PART MARKING TEMP. RANGE (°C) PACKAGE Tape & Reel (Pb-Free) PKG. DWG. # ISL54226IRUZ-T (Note 4) (No longer available or supported) U5 -40 to +85 8 Ld 1.2mmx1.4mm µTQFN L8.1.4x1.2 ISL54226IRTZ-T (Note 3) 226 -40 to +85 8 Ld 2mmx2mm TDFN L8.2x2C ISL54226IRTZ-T7A (Note 3) 226 -40 to +85 8 Ld 2mmx2mm TDFN L8.2x2C ISL54226IRTZEVAL1Z Evaluation Board NOTES: 2. Please refer to TB347 for details on reel specifications. 3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 4. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 5. For Moisture Sensitivity Level (MSL), please see device information page for ISL54226. For more information on MSL please see techbrief TB363. FN7614 Rev 2.00 Aug 15, 2016 Page 3 of 17 ISL54226 Absolute Maximum Ratings Thermal Information VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 6.5V VDD to COMx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.5V COMx to Dx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.6V Input Voltages D+, D- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.5V COM+, COM- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -5V to 6.5V OE/ALM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 6.5V Continuous Current (COM - / D-, COM + / D+) . . . . . . . . . . . . . . . . . ±40mA Peak Current (COM-/D-, COM+/D+) (Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . . . . . . . ±100mA ESD Rating: Human Body Model (Tested per JESD22-A114-F) . . . . . . . . . . . . >5.5kV Machine Model (Tested per JESD22-A115-A) . . . . . . . . . . . . . . . . . >250V Charged Device Model (Tested per JESD22-C101-D) . . . . . . . . . . . . >2kV Latch-up (Tested per JEDEC; Class II Level A) . . . . . . . . . . . . . . . . at +85°C Thermal Resistance (Typical) JA (°C/W) JC (°C/W) 8 Ld µTQFN Package (Notes 7, 9) . . . . . . . 210 165 8 Ld TDFN Package (Notes 6, 8). . . . . . . . . 96 19 Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . +150°C Maximum Storage Temperature Range. . . . . . . . . . . . . . . . . -65°C to +150°C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Normal Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C VDD Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.25V Logic Control Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 5.25V Analog Signal Range VDD = 2.7V to 5.25V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 3.6V CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 6. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 7. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 8. For JC, the “case temp” location is the center of the exposed metal pad on the package underside. 9. For JC, the “case temp” location is taken at the package top center. Electrical Specifications - 2.7V to 5.25V Supply Test Conditions: VDD = +3.3V, GND = 0V, VOE/ALMH = 1.4V, VOE/ALML = 0.5V, (Note 10), Unless Otherwise Specified. Boldface limits apply over the operating temperature range, -40°C to +85°C. PARAMETER TEST CONDITIONS TEMP MIN MAX (°C) (Notes 11, 12) TYP (Notes 11, 12) UNITS ANALOG SWITCH CHARACTERISTICS ON-Resistance, rON (High-Speed) VDD = 2.7V, OE/ALM = 1.4V, IDx = 17mA, VCOM+ or VCOM- = 0V to 400mV (see Figure 4, Note 15) rON Matching Between Channels, rON (High-Speed) VDD = 2.7V, OE/ALM = 1.4V, IDx = 17mA, VCOM+ or VCOM- = Voltage at max rON, (Notes 14, 15) rON Flatness, RFLAT(ON) (High-Speed) VDD = 2.7V, OE/ALM = 1.4V, IDx = 17mA, VCOM+ or VCOM- = 0V to 400mV, (Notes 13, 15) Full ON-Resistance, rON VDD = 3.3V, OE/ALM = 1.4V, ICOMx = 17mA, VCOM+ or VCOM-= 3.3V (see Figure 4, Note 15) +25 Full - - 22 Ω OFF Leakage Current, IDx(OFF) VDD = 5.25V, OE/ALM = 0V, VDx = 0.3V, 3.3V, VCOMX = 3.3V, 0.3V 25 -20 1 20 nA Full - 30 - nA ON Leakage Current, IDx(ON) VDD = 5.25V, OE/ALM = 5.25V, VDx = 0.3V, 3.3V, VCOMX = 0.3V, 3.3V 25 -9 - 9 µA Full -12 - 12 µA 25 - - 11 µA Power OFF Leakage Current, ICOM+, ICOM- VDD = 0V, VCOM+ = 5.25V, VCOM- = 5.25V, OE/ALM = 0V 25 - 3.5 5 Ω Full - - 7 Ω 25 - 0.2 0.45 Ω Full - - 0.55 Ω 25 - 0.26 1 Ω - - 1.2 Ω - 6.8 17 Ω Power OFF Logic Current, IOE/ALM VDD = 0V, OE/ALM = 5.25V 25 - - 22 µA Power OFF D+/D- Current, ID+, ID- VDD = 0V, OE/ALM = VDD, VD+ = VD- = 5.25V 25 - - 1 µA Positive Fault-Protection Trip Threshold, VPFP VDD = 2.7V to 5.25V, OE/ALM = VDD (see Table 1 on page 2) 25 3.62 3.8 3.95 V Negative Fault-Protection Trip Threshold, VNFP VDD = 2.7V to 5.25V, OE/ALM = VDD (see Table 1 on page 2) 25 -0.6 -0.45 -0.29 V OFF Persistence Time Fault Protection Response Time Negative OVP Response: VDD = 2.7V, OE/ALM = VDD, VDx = 0V to -5V, RL = 1.5kΩ 25 - 102 - ns Positive OVP Response: VDD = 2.7V, OE/ALM = VDD, VDx = 0V to 5.25V, RL = 1.5kΩ 25 - 2 - µs Overvoltage Protection Detection FN7614 Rev 2.00 Aug 15, 2016 Page 4 of 17 ISL54226 Electrical Specifications - 2.7V to 5.25V Supply Test Conditions: VDD = +3.3V, GND = 0V, VOE/ALMH = 1.4V, VOE/ALML = 0.5V, (Note 10), Unless Otherwise Specified. Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued) PARAMETER ON Persistence Time Fault Protection Recovery Time TEST CONDITIONS TEMP MIN MAX (°C) (Notes 11, 12) TYP (Notes 11, 12) UNITS VDD = 2.7V, OE/ALM = VDD , VDx = 0V to 5.25V or 0V to -5V, RL = 1.5kΩ 25 - 45 - µs Turn-ON Time, tON VDD = 3.3V, VINPUT = 3V, RL = 50Ω, CL = 50pF (see Figure 3) 25 - 160 - ns Turn-OFF Time, tOFF VDD = 3.3V, VINPUT = 3V, RL = 50Ω, CL = 50pF (see Figure 3) 25 - 60 - ns Skew, (tSKEWOUT - tSKEWIN) VDD = 3.3V, OE/ALM = 3.3V, RL = 45Ω,CL = 10pF, tR = tF = 500ps at 480Mbps, (Duty Cycle = 50%) (see Figure 7) 25 - 50 - ps Rise/Fall Degradation (Propagation Delay), tPD VDD = 3.3V, OE/ALM = 3.3V, RL = 45Ω,CL = 10pF, see Figure 7) 25 - 250 - ps Crosstalk VDD = 3.3V, RL = 50Ω, f = 240MHz (see Figure 6) 25 - -39 - dB OFF-Isolation VDD = 3.3V, OE/ALM = 0V, RL = 50Ω, f = 240MHz 25 - -23 - dB DYNAMIC CHARACTERISTICS -3dB Bandwidth Signal = 0dBm, 0.86VDC offset, RL = 50Ω 25 - 790 - MHz OFF Capacitance, COFF f = 1MHz, VDD = 3.3V, OE/ALM = 0V (see Figure 5) 25 - 2.5 - pF COM ON Capacitance, C(ON) f = 1MHz, VDD = 3.3V, OE/ALM = 3.3V, (see Figure 5) 25 - 4 - pF COM ON Capacitance, C(ON) f = 240MHz, VDD = 3.3V, OE/ALM = 3.3V 25 - 2 - pF Full 2.7 5.25 V POWER SUPPLY CHARACTERISTICS Power Supply Range, VDD Positive Supply Current, IDD Positive Supply Current, IDD Positive Supply Current, IDD Positive Supply Current, IDD VDD = 5.25V, OE/ALM = 5.25V VDD = 3.6V, OE/ALM = 3.6V VDD = 4.3V, OE/ALM = 2.6V VDD = 3.6V, OE/ALM = 1.4V 25 - 45 56 µA Full - - 59 µA 25 - 23 30 µA Full - - 34 µA 25 - 35 45 µA Full - - 50 µA 25 - 25 32 µA Full - - 38 µA - 0.5 V DIGITAL INPUT CHARACTERISTICS Input Voltage Low, VOE/ALML VDD = 2.7V to 3.6V Full - Input Voltage High, VOE/ALMH VDD = 2.7V to 3.6V Full 1.4 - - V Input Voltage Low, VOE/ALML VDD = 3.7V to 4.2V Full - - 0.7 V Input Voltage High, VOE/ALMH VDD = 3.7V to 4.2 Full 1.7 - - V Input Voltage Low, VOE/ALML VDD = 4.3V to 5.25V Full - - 0.8 V Input Voltage High, VOE/ALMH VDD = 4.3V to 5.25V Full 2.0 - - V Input Current, IOE/ALML VDD = 5.25V, OE/ALM = 0V Full - -8.2 - nA Input Current, IOE/ALMH VDD = 5.25V, OE/ALM = 5.25V, 4MΩ Pull-down Full - 1.4 - µA NOTES: 10. VLOGIC = Input voltage to perform proper function. 11. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. 12. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. 13. Flatness is defined as the difference between maximum and minimum value of ON-resistance over the specified analog signal range. 14. rON matching between channels is calculated by subtracting the channel with the highest max rON value from the channel with lowest max rON value. 15. Limits established by characterization and are not production tested. FN7614 Rev 2.00 Aug 15, 2016 Page 5 of 17 ISL54226 Test Circuits and Waveforms VDD LOGIC INPUT VDD tr < 20ns tf < 20ns 50% 0V VINPUT tOFF SWITCH INPUT VINPUT VOUT Dx COMx SWITCH INPUT OE/ALM VOUT 90% SWITCH OUTPUT C 90% VIN RL 50Ω GND 0V CL 50pF tON Logic input waveform is inverted for switches that have the opposite logic sense. Repeat test for all switches. CL includes fixture and stray capacitance. RL V OUT = V (INPUT) -----------------------R L + r ON FIGURE 3A. MEASUREMENT POINTS FIGURE 3B. TEST CIRCUIT FIGURE 3. SWITCHING TIMES VDD C rON = V1/17mA COMx VHSDX 17mA VDD OE/ALM V1 Dx GND Repeat test for all switches. FIGURE 4. rON TEST CIRCUIT VDD VDD C C SIGNAL GENERATOR COMx COM+ VIN 0V OR VDD Dx GND 50Ω OE/ALM OE/ALM IMPEDANCE ANALYZER D+ COM- D- ANALYZER GND NC RL Repeat test for all switches. FIGURE 5. CAPACITANCE TEST CIRCUIT FN7614 Rev 2.00 Aug 15, 2016 Signal direction through switch is reversed, worst case values are recorded. Repeat test for all switches. FIGURE 6. CROSSTALK TEST CIRCUIT Page 6 of 17 ISL54226 Test Circuits and Waveforms (Continued) VDD C tri 90% 10% DIN+ 50% VDD tskew_i DIN- 90% OE/ALM 15.8Ω DIN+ 50% COM- 143Ω 10% DIN- tfi tro 15.8Ω OUT+ DCL COM+ OUT- D+ CL 143Ω 45Ω 45Ω 90% 10% OUT+ 50% GND tskew_o OUT- |tro - tri| Delay Due to Switch for Rising Input and Rising Output Signals. 50% 90% tf0 |tfo - tfi| Delay Due to Switch for Falling Input and Falling Output Signals. 10% |tskew_0| Change in Skew through the Switch for Output Signals. |tskew_i| Change in Skew through the Switch for Input Signals. FIGURE 7A. MEASUREMENT POINTS FIGURE 7B. TEST CIRCUIT FIGURE 7. SKEW TEST Application Block Diagram 3.3V 3.3V 500Ω 100kΩ VDD INT 3.6V USB CONNECTOR VBUS >1MΩ LOGIC CONTROL µCONTROLLER OE/ALM 4MΩ D- COM - D- D+ OVP DET COM + D+ USB HIGH-SPEED OR FULL-SPEED TRANSCEIVER GND ISL54226 FN7614 Rev 2.00 Aug 15, 2016 GND PORTABLE MEDIA DEVICE Page 7 of 17 ISL54226 Detailed Description The ISL54226 device is a dual single pole/single throw (SPST) analog switch configured as a DPST that operates from a single DC power supply in the range of 2.7V to 5.25V. It was designed for switching a USB high-speed or full-speed source in portable battery powered products. It is offered in small µTQFN and TDFN packages for use in MP3 players, cameras, PDAs, cellphones, and other personal media players. The part consists of two 3.5Ω high-speed SPST switches. These switches have high bandwidth and low capacitance to pass USB high-speed (480Mbps) differential data signals with minimal edge and phase distortion. They can also swing from 0V to 3.6V to pass USB full speed (12Mbps) differential data signals with minimal distortion. The part contains special overvoltage detection and protection (OVP) circuitry on the COM+ and COM- pins. This circuitry acts to open the USB in-line switches when the part senses a voltage on the COM pins that is >3.8V (typ) or < -0.45V (typ). It isolates voltages up to 5.25V and down to -5V from getting through to the other side of the switch to protect the USB transceiver connected at the D+ and D- pins. The device has an open drain OE/ALM pin that can be driven “Low” to open all switches. The OE/ALM pin gets internally pulled “Low” whenever the part senses an overvoltage condition. The pin must be externally pulled “High” with a 100kΩ pull-up resistor and monitored for a “Low” to determine when an overvoltage condition has occurred. The part has charger port interrupt detection circuitry (CP) on the COM pins that outputs a Low on the INT pin to inform the µController or power management circuitry when entering a dedicated charging port mode of operation. The charger mode operation is initiated by driving the OE/ALM pin Low and externally connecting the COM pins together which pulls the COM lines High, triggering the INT pin to go Low and the SPST switches to open. The ISL54226 was designed for MP3 players, cameras, cellphones, and other personal media player applications that need to switch a high-speed or full-speed transceiver source. A “Typical Application Block Diagram” of this functionality is shown on page 7. A detailed description of the SPST switches is provided in the following section. See Figures 11, 12, 13, 14, 15, 16 in the “Typical Performance Curves” beginning on page 11. The Dx switches were specifically designed to pass USB 2.0 high-speed (480Mbps) differential signals in the range of 0V to 400mV. They have low capacitance and high bandwidth to pass the USB high-speed signals with minimum edge and phase distortion to meet USB 2.0 high-speed signal quality specifications. See Figure 17 in the “Typical Performance Curves” on page 12 for USB High-speed Eye Pattern taken with switch in the signal path. The Dx switches can also pass USB full-speed signals (12Mbps) in the range of 0V to 3.6V with minimal distortion and meet all the USB requirements for USB 2.0 full-speed signaling. See Figure 18 in the “Typical Performance Curves” on page 13 for USB Full-speed Eye Pattern taken with switch in the signal path. The switches are active (turned ON) whenever the OE/ALM voltage is logic “1” (High) and OFF when the OE/ALM voltage is logic “0” (Low). Overvoltage Protection (OVP) The maximum normal operating signal range for the Dx switches is from 0V to 3.6V. For normal operation the signal voltage should not be allow to exceed these voltage levels or go below ground by more than -0.3V. However, in the event that a positive voltage >3.8V (typ) to 5.25V, such as the USB 5V VBUS voltage, gets shorted to one or both of the COM+ and COM- pins or a negative voltage < -0.45V (typ) to -5V gets shorted to one or both of the COM pins, the ISL54226 has OVP circuitry to detect the over voltage condition and open the SPST switches to prevent damage to the USB down-stream transceiver connected at the signal pins (D-, D+). The OVP and power-off circuitry allows the COM pins (COM-, COM+) to be driven up to 5.25V while the VDD supply voltage is in the range of 0V to 5.25V. In this condition the part draws 150V Charged Device Model (Tested per JESD22-C101-D)......>2kV to: Human Body Model (Tested per JESD22-A114-F)..........>5.5kV Machine Model (Tested per JESD22-A115-A)................>250V Charged Device Model (Tested per JESD22-C101-D)......>2kV July 29, 2010 FN7614.0 Initial Release. About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support © Copyright Intersil Americas LLC 2010-2016. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN7614 Rev 2.00 Aug 15, 2016 Page 15 of 17 ISL54226 Package Outline Drawing L8.2x2C 8 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE (TDFN) WITH E-PAD Rev 1, 5/15 2.00 6 PIN #1 INDEX AREA A B 6 PIN 1 INDEX AREA 8 1 0.50 2.00 1.45±0.050 Exp.DAP (4X) 0.15 0.25 0.10 M C A B ( 8x0.30 ) TOP VIEW 0.80±0.050 Exp.DAP BOTTOM VIEW ( 8x0.20 ) Package Outline ( 8x0.30 ) SEE DETAIL "X" ( 6x0.50 ) 1.45 2.00 0.10 C 0 . 75 ( 0 . 80 max) C BASE PLANE SEATING PLANE 0.08 C SIDE VIEW ( 8x0.25 ) 0.80 2.00 TYPICAL RECOMMENDED LAND PATTERN C 0 . 2 REF 0 . 00 MIN. 0 . 05 MAX. DETAIL "X" NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal ± 0.05 4. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature and may be located on any of the 4 sides (or ends). 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. FN7614 Rev 2.00 Aug 15, 2016 Page 16 of 17 ISL54226 Package Outline Drawing L8.1.4x1.2 8 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 0, 4/09 0.80 REF 4X 0.40 BSC 1.40 A PIN 1 INDEX AREA PIN 1 B 1.20 6 INDEX AREA 8 0.30 C0.10 5 1 0.40 0.60 7X 0.30 0.10 4 2X ±0.05 2 0.10 M C A B 0.40 BSC TOP VIEW 0.05 M C 4 8 X 0.20 BOTTOM VIEW SEE DETAIL "X" 0.80 REF MAX. 0.50 4X 0.40 PKG OUTLINE 0.10 C C SEATING PLANE 0.08 8 X 0.20 C SIDE VIEW 0.60 0.60 7X 0.50 C 0 . 2 REF 0.70 0.60 0-0.05 TYPICAL RECOMMENDED LAND PATTERN DETAIL "X" NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal ± 0.05 4. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 indentifier may be either a mold or mark feature. FN7614 Rev 2.00 Aug 15, 2016 Page 17 of 17