ISL55100AIRZ-T7A

DATASHEET ISL55100A FN7486 Rev 3.00 December 4, 2014 Quad 18V Pin Electronics Driver/Window Comparator The ISL55100A is a Quad pin driver and window comparator fabricated in a wide voltage CMOS process. It is designed specifically for Test During Burn In (TDBI) applications, where cost, functional density and power are all at a premium. Features This IC incorporates four channels of programmable drivers and window comparators into a small 72 Ld QFN package. Each channel has independent driver levels, data and high impedance control. Each receiver has dual comparators, which provide high and low threshold levels. • 18V I/O range The ISL55100A uses differential mode digital inputs and can therefore mate directly with LVDS or CML outputs. Single-ended logic families are handled by connecting one of the digital input pins to an appropriate threshold voltage (e.g., 1.4V for TTL compatibility). The comparator outputs are single-ended and the output levels are user defined to mate directly with any digital technology. • Differential or single-ended digital inputs • Low driver output resistance - ROUT maximum: ISL55100A 7.0Ω • 50MHz operation • 4-channel driver/receiver pairs with per pin flexibility • Dual level - per pin - input thresholds • User defined comparator output levels • Low channel-to-channel timing skew • Small footprint (72 Ld QFN) • Pb-free (RoHS compliant) Applications The 18V driver output and receiver input ranges allow this device to interface directly with TTL, ECL, CMOS (3V, 5V and 7V), LVCMOS and custom level circuitry, as well as the high voltage (super voltage) level required for many special test modes for Flash Devices. • Burn in ATE • Wafer level flash memory test • LCD panel test • Low cost ATE • Instrumentation • Emulation • Device programmers Functional Block Diagram QUAD - WIDE RANGE, LOW ROUT, TRI-STATEABLE - DRIVERS VH(0:3) DATA+(0:3) DATA-(0:3) DOUT(0:3) + - VL(0:3) DRVEN+(0:3) + DRVEN-(0:3) QUAD - DUAL LEVEL COMPARATOR - RECEIVERS COMP HIGH QA(0:3) COMP LOW COMP HIGH QB(0:3) COMP LOW FN7486 Rev 3.00 December 4, 2014 VCC + - CVA(0:3) VEE VCC + - VINP(0:3) CVB(0:3) VEE Page 1 of 14 ISL55100A Ordering Information PART NUMBER (Notes 1, 2, 3) TEMP. RANGE (°C) PART MARKING ISL55100AIRZ ISL55100 AIRZ ISL55100AEVAL3Z Evaluation Board PACKAGE (RoHS Compliant) -40 to +85 72 Ld QFN PKG. DWG. # L72.10x10 NOTES: 1. Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see product information page for ISL55100A For more information on MSL, please see tech brief TB363. Pin Configuration QA 0 QB 0 VEE VCC NC NC NC NC VEE VCC VEE VCC NC NC 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 NC DRV EN- 0 72 NC DRV EN+ 0 ISL55100A (72 LD QFN) TOP VIEW 55 DATA+ 0 1 54 VEXT DATA- 0 2 53 VH 0 QA 1 3 52 DOUT 0 QB 1 4 51 NC DRV EN+ 1 5 50 VL 0 DRV EN- 1 6 49 VH 1 DATA+ 1 7 48 DOUT 1 DATA- 1 8 47 NC QA 2 9 QB 2 10 45 VH 2 DRV EN+ 2 11 44 DOUT 2 DRV EN- 2 12 43 NC DATA+ 2 13 42 VL 2 DATA- 2 14 41 VH 3 QA 3 15 40 DOUT 3 QB 3 16 39 NC DRV EN+ 3 17 38 VL 3 DRV EN- 3 18 37 LOWSWING FN7486 Rev 3.00 December 4, 2014 46 VL 1 25 26 27 28 29 30 DATA- 3 CVA 0 VINP 0 CVB 0 COMP HIGH COMP LOW VEE VCC CVA 1 VINP 1 CVB 1 31 32 33 34 35 36 VINP 3 24 CVB 3 23 CVA 3 22 CVB 2 21 VINP 2 20 CVA 2 19 DATA+ 3 EP Page 2 of 14 ISL55100A Pin Descriptions PIN NAME FUNCTION DATA+(0:3) Positive differential digital input that determines the driver output state when it is enabled. DATA-(0:3) Negative differential digital input that determines the driver output state when it is enabled. DRV EN+(0:3) Positive differential digital input that enables or disables the corresponding driver. DRV EN-(0:3) Negative differential digital input that enables or disables the corresponding driver. QA (0:3) Comparator digital outputs. QA(X) is high when VINP(X) exceeds CVA(X). QB (0:3) Comparator digital outputs. QB(X) is high when VINP(X) exceeds CVB(X). DOUT (0:3) Driver outputs. VINP (0:3) Comparator inputs. VH (0:3) Unbuffered analog inputs that set each individual driver’s “high” voltage level. VL (0:3) Unbuffered analog inputs that set each individual driver’s “low” voltage level. VL must be a lower voltage than VH. NC No internal connection. CVA (0:3) Analog inputs that set the threshold for the corresponding Channel’s A comparators. CVB (0:3) Analog inputs that set the threshold for the corresponding Channel’s B comparators. COMP HI Supply voltage, unbuffered input that sets the high output level of all comparators. Must be greater than COMP LO. COMP LO Supply voltage, unbuffered input that sets the low output level of all comparators. Must be less than COMP HI. VCC Positive power supply (5% tolerance). VEE Negative power supply (5% tolerance). This is also the potential of the exposed thermal pad on the package bottom. VEXT External 5.5VDC power supply (5.5VDC to 6.0VDC as referenced to VEE, NOT GND. Recommended VEXT = 5.5V) for internal logic. Connect pin to VEE when not using an external supply. LOWSWING EP Input that selects driver output configurations optimized to yield minimum overshoots for low level swings (VH < VEE +5V), or optimized for large output swings. Connect LOWSWING to VEE to select low swing circuitry, or connect it to VCC to select high swing circuitry. QFN package exposed thermal pad; connect to VEE. Truth Tables RECEIVERS INPUT DRIVERS INPUTS OUTPUTS VINP OUTPUT QA QB DATA DRV EN DOUT - +CVA CVA >CVB 1 1 +