ISL5585ECR

ISL5585 ® Data Sheet October 21, 2004 3.3V Ringing SLIC Family for Voice Over Broadband (VOB) Features • 3.3V Operation The 3.3V family of ringing subscriber line interface circuits (SLIC) supports analog Plain Old Telephone Service (POTS) in short and medium loop length, wireless and wireline voice over broadband applications. Ideally suited for customer premise equipment, this family of products offers flexibility to designers with high ringing voltage and low power consumption system requirements. The ISL5585 family is capable of operating with 100V ringing battery supply, which translates directly to the amount of ringing voltage supplied to the subscriber. With the high operating voltage, subscriber loop lengths can be extended to 500Ω (i.e., 5,000 feet) and beyond, allowing this family to serve emerging Fiber In The Loop (FITL) markets. Other key features across the product family include: 3.3V VCC operation, low power consumption, ringing using sinusoidal or trapezoidal waveforms, robust auto-detection mechanisms for when subscribers go on or off hook, and minimal external discrete application components. Integrated test access features are also offered on selected products to support loopback testing as well as line measurement tests. • Onboard Ringing Generation • Low Standby Power Consumption (75V, 65mW) • Programmable Transient Current Limit • Improved Off Hook Software Interface • Integrated MTU DC Characteristics • Low External Component Count • Silent Polarity Reversal • Pulse Metering and On Hook Transmission • Tip Open Ground Start Operation • Balanced and Unbalanced Ringing • Thermal Shutdown with Alarm Indicator • 28 Lead Surface Mount Packaging • QFN Package: - Compliant to JEDEC PUB95 MO-220 QFN - Quad Flat No Leads - Package Outline - Near Chip Scale Package footprint, which improves PCB efficiency and has a thinner profile There are ten product offerings of the ISL5585 providing various grades of ringing battery voltage and longitudinal balance. • Pb-Free Available (RoHS Compliant) Block Diagram • Short Loop Access Platforms POL CDC VBL FN6026.6 Applications • Voice Over Internet Protocol (VoIP) VBH • Voice Over Cable and DSL Modems ILIM DC CONTROL BATTERY SWITCH RINGING PORT VRS • Internet Protocol PBX • FiberTo The Home (FTTH) TIP RING TL SW+ SW- • Remote Subscriber Units 2-WIRE PORT TRANSIENT CURRENT LIMIT TEST ACCESS TRANSMIT SENSING AUX VTX -IN VFB 4-WIRE PORT • Ethernet Terminal Adapters Related Literature • AN1038, User’s Guide for Development Board DETECTOR LOGIC RT SH E0 DET ALM 1 F2 F1 F0 CONTROL LOGIC BSEL SWC • AN9824, Modeling of the AC Loop • TB379 Thermal Characterization of Packages for ICs • AN9922, Thermal Characterization and Modeling of the RSLIC18 in the Micro Leadframe Package CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2002-2004. All Rights Reserved. All other trademarks mentioned are the property of their respective owners. ISL5585 Ordering Information HIGH BATTERY (VBH) PART NUMBER 100V 85V 75V LONGITUDINAL BALANCE 58dB 53dB FULL TEST TEMP. RANGE (°C) PACKAGE PKG. DWG. # ISL5585AIM • • • -40 to 85 28 Ld PLCC N28.45 ISL5585AIMZ (See Note) • • • -40 to 85 28 Ld PLCC (Pb-free) N28.45 ISL5585BIM • • • -40 to 85 28 Ld PLCC N28.45 ISL5585BIMZ (See Note) • • • -40 to 85 28 Ld PLCC (Pb-free) N28.45 ISL5585CIM • • • -40 to 85 28 Ld PLCC N28.45 ISL5585CIMZ (See Note) • • • -40 to 85 28 Ld PLCC (Pb-free) N28.45 ISL5585DIM • • • -40 to 85 28 Ld PLCC N28.45 ISL5585DIMZ (See Note) • • • -40 to 85 28 Ld PLCC (Pb-free) N28.45 ISL5585ECM • • 0 to 75 28 Ld PLCC N28.45 ISL5585ECMZ (See Note) • • 0 to 75 28 Ld PLCC (Pb-free) N28.45 ISL5585ECR • • 0 to 75 32 Pad QFN L32.7x7* ISL5585ECRZ (See Note) • • 0 to 75 32 Pad QFN (Pb-free) L32.7x7* ISL5585FCM • • • 0 to 85 28 Ld PLCC N28.45 ISL5585FCMZ (See Note) • • • 0 to 85 28 Ld PLCC (Pb-free) N28.45 ISL5585FCR • • • 0 to 85 32 Pad QFN L32.7x7* ISL5585FCRZ (See Note) • • • 0 to 85 32 Pad QFN (Pb-free) L32.7x7* ISL5585GCM • • • 0 to 85 28 Ld PLCC N28.45 ISL5585GCMZ (See Note) • • • 0 to 85 28 Ld PLCC (Pb-free) N28.45 ISL5585GCR • • • 0 to 85 32 pad QFN L32.7x7* ISL5585GCRZ (See Note) • • • 0 to 85 32 pad QFN (Pb-free) L32.7x7* ISL5585 XXX Evaluation board platform, including CODEC. Also available in Tape and Reel *Reference “Special Considerations for the QFN Package” text. NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pbfree peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020C. 2 ISL5585 Device Operating Modes MODE F2 F1 F0 E0 = 1 E0 = 0 ISL5585A ISL5585B ISL5585C ISL5585D ISL5585E ISL5585F ISL5585G Low Power Standby 0 0 0 SHD GKD • • • • • • • Forward Active 0 0 1 SHD GKD • • • • • • • Unbalanced Ringing 0 1 0 RTD RTD Reverse Active 0 1 1 SHD GKD • • • • • • • Ringing 1 0 0 RTD RTD • • • • • • • Forward Loop Back 1 0 1 SHD GKD • • • • • • Tip Open 1 1 0 SHD GKD • • • • • • Power Denial 1 1 1 n/a n/a • • • • • • • Pinouts • 26 SH ILIM 27 SCC SH 28 RING RING 1 NC TIP 2 TIP BGND 3 BGND VBL 4 VBL VBH ISL5585 (PLCC) TOP VIEW VBH ISL5585 QFN TOP VIEW 32 31 30 29 28 27 26 25 SW+ 1 24 ILIM SW- 2 23 RT SWC 3 22 CDC F2 4 21 VCC F1 5 20 -IN -IN F1 9 21 VFB F0 6 19 VFB F0 10 20 VTX E0 7 18 VTX E0 11 19 AUX NC 8 17 AUX 12 13 14 15 16 17 18 9 10 11 12 13 14 15 16 NC 22 VRS 8 POL F2 TL VCC BSEL 23 AGND 7 ALM SWC DET CDC VRS 24 POL 6 TL SW- BSEL RT AGND 25 ALM 5 DET SW+ Pin Description PLCC QFN SYMBOL DESCRIPTION 1 29 TIP 2 30 BGND 3 31 VBL Low battery supply connection. 4 32 VBH High battery supply connection for the most negative battery. 5 1 SW+ Uncommitted switch positive terminal. 6 2 SW- Uncommitted switch negative terminal. 7 3 SWC Switch control input. This TTL compatible input controls the uncommitted switch, with a logic “0” enabling the switch and logic “1” disabling the switch. 8 4 F2 Mode Control Input - MSB. F2-F0 for the TTL compatible parallel control interface for controlling the various modes of operation of the device. 9 5 F1 Mode control input. TIP power amplifier output. Battery Ground - To be connected to zero potential. All loop current and longitudinal current flow from this ground. Internally separate from AGND. This ground must be connected to the same potential as AGND. 3 ISL5585 Pin Description (Continued) PLCC QFN SYMBOL DESCRIPTION 10 6 F0 Mode control input. 11 7 E0 Detector Output Selection Input. This TTL input controls the multiplexing of the SHD (E0 = 1) and GKD (E0 = 0) comparator outputs to the DET output based upon the state at the F2-F0 pins (see the Device Operating Modes table shown on page 2). 12 9 DET Detector Output - This TTL output provides on-hook/off-hook status of the loop based upon the selected operating mode. The detected output will either be switch hook, ground key or ring trip (see the Device Operating Modes table shown on page 2). DET will be latched low following a ring trip. Unlatching the DET pin is accomplished by changing logic state. 13 10 ALM Thermal Shutdown Alarm. This pin signals the internal die temperature has exceeded safe operating temperature (approximately 175°C) and the device has been powered down automatically. 14 11 AGND Analog ground reference. This pin should be externally connected to BGND. 15 12 BSEL Selects between high and low battery, with a logic “1” selecting the high battery and logic “0” the low battery. 16 13 TL 17 14 POL External capacitor on this pin sets the polarity reversal time. 18 15 VRS Ringing Signal Input - Analog input for driving 2-wire interface while in Ring Mode. 19 17 AUX Auxiliary input - Float if not used. 20 18 VTX Transmit Output Voltage - Output of impedance matching amplifier, AC couples through a resistor to CODEC. 21 19 VFB Feedback voltage for impedance matching. This voltage is scaled to accomplish impedance matching. The CFB capacitor connects between this pin and the -IN pin. The CFB cap needs to be non-polarized for proper device operation in the Reverse Active mode. Ceramic surface mount capacitors (1206 body style) are available from Panasonic with a 6.3V voltage rating. These can be used for CFB since it is internally limited to approximately ±3V. 22 20 -IN Analog Receive Voltage - 4-wire analog audio input voltage. connects to CODEC via receive gain setting resistor RIN (see Figure 18). Resistor RIN needs to be as close to the -IN pin as possible to minimize parasitic capacitance. 23 21 VCC Positive voltage power supply,+3.3V 24 22 CDC DC Biasing Filter Capacitor - Connects between this pin and VCC.The CDC capacitor may be either polarized or non polarized with a 6.3V voltage rating. 25 23 RT Ring trip filter network. 26 24 ILIM Loop Current Limit programming resistor. 27 25 SH Switch hook detection threshold programming resistor. --- 26 SCC Substrate Common Connection - Connect this pin to VBH Supply. This pin is used to connect the substrate of the die and the thermal heatsink plane of the QFN package. 28 27 RING RING power amplifier output. Programming pin for the transient current limit feature, set by an external resistor to ground. 4 ISL5585 Absolute Maximum Ratings TA = 25°C Thermal Information Maximum Supply Voltages VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V VCC - VBH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110V Uncommitted Switch Voltage . . . . . . . . . . . . . . . . . . . . . . . -110V Maximum Tip/Ring Negative Voltage Pulse (Note 8). . . . . . . VBH -15V Maximum Tip/Ring Positive Voltage Pulse (Note 8) . . . . . . . . . . . .+8V ESD (Human Body Model). . . . . . . . . . . . . . . . . . . . . . . . . . . 1000V Thermal Resistance (Typical) θJA (°C/W) θJC (°C/W) PLCC (Note 1) . . . . . . . . . . . . . . . . . . . 55 N/A QFN (Note 2) . . . . . . . . . . . . . . . . . . . . 28 1 Maximum Junction Temperature Plastic . . . . . . . . . . . . . . . . 150°C Maximum Storage Temperature Range . . . . . . . . . . -65°C to 150°C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300°C (PLCC - Lead Tips Only) For Recommended soldering conditions see Tech Brief TB389. Operating Conditions Temperature Range Commercial (C suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 85°C Industrial (I suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to 85°C Positive Power Supply (VCC) . . . . . . . . . . . . . . . . . . . . +3.3V ±10% Low Battery Power Supply (VBL) . . . . . . . . . . . . . -16V to -52V, ±5% High Battery Power Supply (VBH) ISL5585AIM, CIM, GCM, GCR . . . . . . . . . . . . . . .VBL to 100V, ±5% ISL5585BIM, DIM. . . . . . . . . . . . . . . . . . . . . . . . VBL to -85V, ±10% ISL5585ECM, ECR, FCM, FCR. . . . . . . . . . . . . VBL to -75V, ±10% Uncommitted Switch (loop back or relay driver). . . . . . +5V to -100V Die Characteristics Substrate Potential. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VBH Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bipolar-DI CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 2. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. θJC, the “case temp” is measured at the center of the exposed metal pad on the package underside. See Tech Brief TB379. Electrical Specifications Unless Otherwise Specified, TA = -40°C to 85°C for industrial (I) grade and TA = 0°C to 85°C for commercial (C) grade, VBL = -24V, VBH = -100V, -85V or -75V, VCC = +3.3V, AGND = BGND = 0V, loop current limit = 25mA. All AC transmission parameters are specified at 600W 2-wire terminating impedance over the frequency band of 300Hz to 3.4kHz. Protection resistors = 0W. PARAMETER TEST CONDITIONS MIN TYP MAX UNITS 450 - - kΩ Balanced Ringing, VRS to 2-Wire, RLOAD=∞ 78 80 82 V/V Unbalanced Ringing, VRS to 2-Wire, RLOAD=∞ 38 40 42 V/V Tip, Referenced to VBH/2 + 0.5 (Note 9) - ± 2.5 - V Ring, Referenced to VBH/2 + 0.5 - ± 2.5 - V Balanced Ringing, VRS Input=0.840VRMS - 67 - VRMS Unbalanced Ringing, VRS Input=0.840VRMS - 33.5 - VRMS Ringing Voltage Total Distortion RL=1.3 kΩ, VT-R=|VBH| -5 - - 4.0 % 4-Wire to 2-Wire Ringing Off Isolation Active Mode, Referenced to VRS Input - 90 - dB 2-Wire to 4-Wire Transmit Isolation Ringing Mode Referenced to the Differential Ringing Amplitude - 80 - dB 160 - - kΩ - - 1 Ω RINGING PARAMETERS VRS Input Impedance (Note 3) Differential Ringing Gain (Note 4) Centering Voltage Accuracy Open Circuit Ringing Voltage AC TRANSMISSION PARAMETERS Auxiliary Input Impedance (Note 3) Transmit Output Impedance (Note 3) 4-Wire Port Overload Level THD=1% - 1.0 - VPK 2-Wire Port Overload Level THD=1% 3.1 3.5 - VPK 5 ISL5585 Electrical Specifications Unless Otherwise Specified, TA = -40°C to 85°C for industrial (I) grade and TA = 0°C to 85°C for commercial (C) grade, VBL = -24V, VBH = -100V, -85V or -75V, VCC = +3.3V, AGND = BGND = 0V, loop current limit = 25mA. All AC transmission parameters are specified at 600W 2-wire terminating impedance over the frequency band of 300Hz to 3.4kHz. Protection resistors = 0W. (Continued) PARAMETER TEST CONDITIONS 2-Wire Return Loss MIN TYP MAX UNITS 300Hz - 24 - dB 1kHz - 40 - 3.4kHz - 21 - dB 1 dB 2-Wire Longitudinal Balance (Notes 5, 6) 300Hz to 1kHz Forward Active, Grade A and B 58 62 - dB Forward Active, Grade C, D and E 53 59 - dB 2-Wire Longitudinal Balance (Notes 5, 6) 1kHz to 3.4kHz Forward Active, Grade A and B 54 58 - dB Forward Active, Grade C, D and E 53 58 - dB 4-Wire Longitudinal Balance (Notes 5, 6) 300Hz to 1kHz Forward Active, Grade A and B 58 67 - dB Forward Active, Grade C, D and E 53 64 - dB 4-Wire Longitudinal Balance (Notes 5, 6) 1kHz to 3.4kHz Forward Active, Grade A and B 54 66 - dB Forward Active, Grade C, D and E 53 63 - dB 2-Wire to 4-Wire Level Linearity 4-Wire to 2-Wire Level Linearity Referenced to -10dBm +3 to -40dBm, 1kHz - ±0.025 - dB -40 to -50dBm, 1kHz - ±0.050 - dB -50 to -55dBm, 1kHz - ±0.100 - dB 20 - - mARMS 4-Wire to 2-Wire Insertion Loss -0.20 0.00 +0.20 dB 2-Wire to 4-Wire Insertion Loss -6.22 -6.02 -5.82 dB 4-Wire to 4-Wire Insertion Loss -6.22 -6.02 -5.82 dB Forward Active Idle Channel Noise (Note 6) 2-Wire C-Message, T=25°C - 10 13 dBrnC 4-Wire C-Message, T=25°C - 4 7 dBrnC Reverse Active Idle Channel Noise (Note 6) 2-Wire C-Message, T=25°C - 10 13 dBrnC 4-Wire C-Message, T=25°C - 4 7 dBrnC -8.5 - +8.5 % Programming Range 15 - 45 mA Programming Accuracy (1% programming resistor) -20 - +20 % Programming Range 40 - 100 mA Loop Current During Low Power Standby Forward Polarity Only 18 - 26 mA Open Circuit Voltage (|Tip - Ring|) VBL=-16V - 8.0 - VDC VBL=-24V 14 15.5 17 VDC VBH > -60V 43 49 - VDC - 44.5 - VDC 43 51.5 - VDC Longitudinal Current Capability Per Wire (Note 3) OHT, Active DC PARAMETERS Off Hook Loop Current Limit Programming Accuracy(1% programming resistor) Off Hook Transient Current Limit Low Power Standby, Open Circuit Voltage (Tip - Ring) VBL=-48V Absolute Open Circuit Voltage VRG in LPS and FA; VTG in RA; VBH > -60V - -53 -56 VDC IOL=45mA - 0.20 0.60 V - - 52 V VBH > -60V TEST ACCESS FUNCTIONS Switch On Voltage Loopback Max Battery (VBL or VBH) 6 ISL5585 Electrical Specifications Unless Otherwise Specified, TA = -40°C to 85°C for industrial (I) grade and TA = 0°C to 85°C for commercial (C) grade, VBL = -24V, VBH = -100V, -85V or -75V, VCC = +3.3V, AGND = BGND = 0V, loop current limit = 25mA. All AC transmission parameters are specified at 600W 2-wire terminating impedance over the frequency band of 300Hz to 3.4kHz. Protection resistors = 0W. (Continued) PARAMETER TEST CONDITIONS MIN TYP MAX UNITS 5 - 15 mA -10 - +10 % - 1.0 - % 1.12 1.25 1.37 V -10 - +10 % Ground Key Threshold - 12 - mA E0 Transition, DET Output Delay - 20 - µs - 175 - °C Input Low Voltage - - 0.8 V Input High Voltage 2.0 - - V LOOP DETECTORS AND SUPERVISORY FUNCTIONS Switch Hook Programming Range Switch Hook Programming Accuracy (1% programming resistor) Dial Pulse Distortion Ring Trip Comparator Threshold Ring Trip Programming Current Accuracy Thermal Alarm Output (1% programming resistor) IC Junction Temperature LOGIC INPUTS (F0, F1, F2, E0, SWC, BSEL) Input Low Current VIL=0.4V -20 -10 - µA Input High Current VIH=2.4V - - 1 µA Output Low Voltage IOL=1mA - .15 0.4 V Output High Voltage IOH=100µA 2.4 2.8 - V ICC - 3.9 6.0 mA IBH - 0.66 0.90 mA ICC - 4.9 6.5 mA IBL - 1.2 2.5 mA ICC - 7.0 9.5 mA IBL - 0.9 2.0 mA IBH - 2.2 3.0 mA ICC - 6.4 9.0 mA IBL - 1.0 1.3 mA IBH - 2.0 3.0 mA Ringing, BSEL=1 (Unbalanced Ringing, 010) ICC - 9.3 9.0 mA IBL - 1.0 1.3 mA IBH - 2.4 3.0 mA ICC - 10.3 13.5 mA IBL - 23.5 32 mA ICC - 3.8 5.5 mA IBL - 0.4 1.0 mA IBH - 0.6 1.0 mA LOGIC OUTPUTS (DET, ALM) SUPPLY CURRENTS Low Power Standby, BSEL=1 Forward or Reverse Active, BSEL=0 Forward Active, BSEL=1 Ringing, BSEL=1 (Balanced Ringing, 100) Forward Loopback, BSEL=0 Tip Open, BSEL=1 7 ISL5585 Electrical Specifications Unless Otherwise Specified, TA = -40°C to 85°C for industrial (I) grade and TA = 0°C to 85°C for commercial (C) grade, VBL = -24V, VBH = -100V, -85V or -75V, VCC = +3.3V, AGND = BGND = 0V, loop current limit = 25mA. All AC transmission parameters are specified at 600W 2-wire terminating impedance over the frequency band of 300Hz to 3.4kHz. Protection resistors = 0W. (Continued) PARAMETER TEST CONDITIONS MIN TYP MAX UNITS ICC - 4.0 6.0 mA IBL - 0.4 1.0 IBH - 0.4 0.6 mA Forward or Reverse VBL=-24V - 55 - mW Low Power Standby VBH=-100V - 85 - mW VBH=-85V - 75 - mW VBH=-75V - 65 - mW VBH=-100V - 250 - mW VBH=-85V - 230 - mW VBH=-75V - 225 - mW VB =-24V - 305 - mW f=300Hz - 40 - dB f=1kHz - 35 - dB f=3.4kHz - 28 - dB f=300Hz - 45 - dB f=1kHz - 43 - dB f=3.4kHz - 33 - dB VBL to 2-Wire 300Hz ≤ f ≤ 3.4kHz - 30 - dB VBL to 4-Wire 300Hz ≤ f ≤ 3.4kHz - 35 - dB VBH to 2-Wire 300Hz ≤ f ≤ 3.4kHz - 33 - dB VBH to 4-Wire 300Hz ≤ f ≤ 1kHz - 40 - dB 1kHz < f ≤ 3.4kHz - 45 - dB Power Denial, BSEL=0 or 1 ON HOOK POWER DISSIPATION (Note 7) Ringing OFF HOOK POWER DISSIPATION (Note 7) Forward or Reverse POWER SUPPLY REJECTION RATIO VCC to 2-Wire VCC to 4-Wire NOTES: 3. These parameters are controlled via design or process parameters and are not directly tested. These parameters are characterized upon initial design release and upon design changes which would affect these characteristics. 4. Differential Ringing Gain is measured with VRS = 0.795VRMS for -100V devices, VRS = 0.663 VRMS for -85V devices and VRS = 0.575VRMS for -75V devices. 5. Longitudinal Balance is tested per IEEE455-1985, with 368Ω per Tip and Ring terminal. 6. These parameters are tested 100% at room temperature. These parameters are guaranteed not tested across temperature via statistical characterization and design. 7. The power dissipation is based on actual device measurements and will be less than worst case calculations based on data sheet supply current limits. 8. Characterized with 2 x 10µs, and 10 x 1000µs first level lightning surge waveforms (GR-1089-CORE) 9. For Unbalanced Ringing the Tip terminal is offset to 0V and the Ring terminal is centered at Vbh/2 + 0.5V. 8 ISL5585 Design Equations Switch Hook Detect The switch hook detect threshold is set by a single external resistor, RSH . Equation 1 is used to calculate the value of RSH. (EQ. 1) R SH = 600 ⁄ I SH The term ISH is the desired DC loop current threshold. The loop current threshold programming range is from 5mA to 15mA (40kΩ < RSH 100V. Design Parameters: Ring Trip Threshold = 76mAPEAK , Switch Hook Threshold = 12mA, Loop Current Limit = 24.6mA, Synthesize Device Impedance = (3*66.5kΩ)/400 = 498.8Ω, with 49.9Ω protection resistors, impedance across Tip and Ring terminals = 599Ω. Transient current limit = 95mA. Special Considerations for the QFN Package TEST LOAD SW+ SW- SWC FIGURE 16. TEST LOAD SWITCHING The diode in series with the test load blocks current from flowing through the uncommitted switch when the polarity of the Tip and Ring terminals are reversed. In addition to the reverse active state, the polarity of Tip and Ring are reversed for half of the ringing cycle. With independent logic control and the blocking diode, the uncommitted switch may be continuously connected to the Tip and Ring terminals. 21 The new Quad Flatpack No-lead (QFN) package offers a significant footprint reduction (65%) and improved thermal performance with respect to the 28 lead PLCC. To realize the thermal enhancements and maintain the high voltage (-100V) performance, the exposed pad on the bottom of the QFN package should be soldered to a power/heat sink plane that is electrically connected to the ISL5585 Substrate Common Connection (SCC) pin. The heat is distributed evenly across the board by way of the heat sink plane. This is accomplished by using conductive thermal vias. Reference technical brief TB379 and AN9922 for additional information on thermal characterization and board layout considerations. ISL5585 CPS1 CPS2 RP1 49.9Ω + V2W - VCC VBL VBH AUX TIP 600Ω U1 RP2 49.9Ω 0.47uF 0.47uF 36.5kΩ RS CRT ISL5585 RB 66.5kΩ RIN 42.2kΩ RF Digital Gain 0dB + 45.3kΩ CFB 0.47uF VFB +2.4V Digital Gain 0dB PCM to V2W Gain = +3.33dB, digital gain set to 0dB SH CDC RIL CPOL ILIM POL CDC RTL VRS AGND TL BGND VCC V2W to PCM Gain = -9.3 dB, digital gain set to 0dB 0 dBm0, CODEC output voltage = 0.531Vrms 0 dBm0, V2W = 0.7795Vrms Design Equations RS = 133.33(ZL - 2RP) Gain PCM to V2W = RS/RIN = 66.5k/45.3k =1.46 dB Gain =20log (0.7795/ 0.531) = +3.33dB V2W to PCM Gain = V2W (G2-4)(RF/RA) = (0.7795)(0.416)(30.1k/36.5k) = 0.267 dB Gain =20log (0.267/0.7795) = - 9.3dB FIGURE 17. ISL5585 3.3V APPLICATION CIRCUIT 22 PCM TX IN -IN RT RSH CRS 30.1kΩ RA VTX RING RRT CODEC D1 1N4004 CPS3 PCM ISL5585 Quad Flat No-Lead Plastic Package (QFN) Micro Lead Frame Plastic Package (MLFP) 2X L32.7x7 32 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220VKKC ISSUE C) 0.15 C A MILLIMETERS D A 9 D/2 D1 D1/2 2X N 6 INDEX AREA 0.15 C B 1 2 3 E1/2 E 0.15 C B 0.15 C A B TOP VIEW A / / 0.10 C C 0.08 C SEATING PLANE 9 4X P 0.90 1.00 - - 0.05 - A2 - - 1.00 9 A3 0.20 REF 0.23 0.28 - 9 0.38 5, 8 D 7.00 BSC - D1 6.75 BSC 9 4.55 4.70 4.85 7, 8 E 7.00 BSC - E1 6.75 BSC 9 4.55 4.70 4.85 0.65 BSC 7, 8 - k 0.25 - - - L 0.50 0.60 0.75 8 L1 - - 0.15 10 N 32 2 3 Nd 8 Ne 8 8 P - - 0.60 9 NX k θ - - 12 9 D2 7 D2 2 N 3 Rev. 4 8/03 4X P NOTES: 1 (DATUM A) 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2 3 6 INDEX AREA N e (Ne-1)Xe REF. E2 E2/2 NX L 8 0.80 0.10 M C A B 5 NX b (DATUM B) A1 A3 SIDE VIEW NOTES A e A2 MAX A1 E2 0 4X TYP D2 9 2X 2X MIN b E/2 E1 SYMBOL 2. N is the number of terminals. 7 3. Nd and Ne refer to the number of terminals on each D and E. 8 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 9 CORNER OPTION 4X (Nd-1)Xe REF. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. BOTTOM VIEW A1 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. NX b 5 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. C L 9. Features and dimensions A2, A3, D1, E1, P & θ are present when Anvil singulation method is used and not present for saw singulation. SECTION "C-C" C L L1 10 L L1 e 10 L e C C TERMINAL TIP FOR ODD TERMINAL/SIDE FOR EVEN TERMINAL/SIDE 23 10. Depending on the method of lead termination at the edge of the package, a maximum 0.15mm pull back (L1) maybe present. L minus L1 to be equal to or greater than 0.3mm. ISL5585 Plastic Leaded Chip Carrier Packages (PLCC) 0.042 (1.07) 0.048 (1.22) PIN (1) IDENTIFIER N28.45 (JEDEC MS-018AB ISSUE A) 0.042 (1.07) 0.056 (1.42) 0.004 (0.10) C 0.025 (0.64) R 0.045 (1.14) 0.050 (1.27) TP C L D2/E2 C L E1 E D2/E2 VIEW “A” 0.020 (0.51) MIN A1 A D1 D 28 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A 0.165 0.180 4.20 4.57 - A1 0.090 0.120 2.29 3.04 - D 0.485 0.495 12.32 12.57 - D1 0.450 0.456 11.43 11.58 3 D2 0.191 0.219 4.86 5.56 4, 5 E 0.485 0.495 12.32 12.57 - E1 0.450 0.456 11.43 11.58 3 E2 0.191 0.219 4.86 5.56 4, 5 N 28 28 6 Rev. 2 11/97 SEATING -C- PLANE 0.020 (0.51) MAX 3 PLCS 0.026 (0.66) 0.032 (0.81) 0.013 (0.33) 0.021 (0.53) 0.025 (0.64) MIN 0.045 (1.14) MIN VIEW “A” TYP. NOTES: 1. Controlling dimension: INCH. Converted millimeter dimensions are not necessarily exact. 2. Dimensions and tolerancing per ANSI Y14.5M-1982. 3. Dimensions D1 and E1 do not include mold protrusions. Allowable mold protrusion is 0.010 inch (0.25mm) per side. Dimensions D1 and E1 include mold mismatch and are measured at the extreme material condition at the body parting line. 4. To be measured at seating plane -C- contact point. 5. Centerline to be determined where center leads exit plastic body. 6. “N” is the number of terminal positions. All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 24