DATASHEET
ISL6119
FN9002
Rev 3.00
March 2004
USB Dual Port Power Supply Controller
The ISL6119 is a USB dual port power controller, fully
independent overcurrent (OC) fault protection IC.
Operational over the +2.5V to +5.5V range, this device
features internal current monitoring, accurate current
limiting, integrated power switches and current limited
delay to latch-off for system protection.
The ISL6119 current sense and limiting circuitry sets the current
limit to a nominal 1A, making this device well suited for the USB
port power management application. The ISL6119 provides OC
fault notification, accurate current limiting and a consistent
timed latch-off thus isolating and protecting the voltage bus in
the presence of an OC event or short circuit. The 12ms time to
latch-off is independent of the adjoining switch’s electrical or
thermal condition and the OC response time is inversely related
to the OC magnitude.
Each ISL6119 incorporates in a single 8 lead SOIC
package two 80m N-channel MOSFET power switches
for power control. Each switch is driven by a constant
current source giving a controlled ramp up of the output
voltage. This provides a soft start turn-on eliminating bus
voltage drooping caused by inrush current while charging
heavy load capacitances. Independent enabling inputs and
fault reporting outputs for each channel are compatible with
3V and 5V logic to allow external control and monitoring.
The ISL6119 undervoltage lockout feature prevents turn-on
of the outputs unless the correct ENABLE state and VIN >
2.5V are present. During initial turn-on the ISL6119
prevents fault reporting by blanking the fault signal. Rising
and falling outputs are current limited voltage ramps so that
both the inrush current and voltage slew rate are limited,
independent of load. This reduces supply droop due to
surge and eliminates the need for external EMI filters.
During operation, once an OC condition is detected the
appropriate output is current limited for 12ms to allow
transient conditions to pass. If still in current limit after the
current limit period has elapsed, the output is then latched
off and the fault is reported by pulling the corresponding
FAULT low. The FAULT signal is latched low until reset by
the ENABLE signal being de-asserted at which time the
FAULT signal will clear.
Features
• 80m Integrated Power N-channel MOSFET Switches
• Accurate Current Sensing and 1A Current Limiting
• 12ms Fault Delay to Latch-Off, No Thermal Dependency
• 2.5V to 5.5V Operating Range
• Disabled Output Internally Pulled Low
• Undervoltage Lockout
• Controlled Turn-on Ramp Time
• Channel Independent Fault Output Signals
• Compatible with 3.3V and 5V Logic Families
• Channel Independent Logic Level Enable High Inputs
(ISL6119H) or Enable Low Inputs (ISL6119L)
• Pb-Free Package Options
• Available in Tape & Reel with ‘-T’ Part Number Suffix
Applications
• USB Port Power Management
• Electronic Circuit Limiting and Breaker
Ordering Information
PART
NUMBER
TEMP.
RANGE (°C)
PKG.
DWG. #
ISL6119LIB
-40 to 85
8 Lead SOIC
ISL6119LIBZA
(Note)
-40 to 85
8 Lead SOIC (Pb-free) M8.15
ISL6119HIB
-40 to 85
8 Lead SOIC
ISL6119HIBZA
(Note)
-40 to 85
8 Lead SOIC (Pb-free) M8.15
ISL6119EVAL1
M8.15
M8.15
Evaluation Platform
ISL6119USBEVAL1 USB Dual Port Evaluation Platform
NOTE: Intersil Pb-free products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which is compatible with both SnPb and
Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J Std-020B.
Pinout
FN9002 Rev 3.00
March 2004
PACKAGE
ISL6119 (SOIC)
TOP VIEW
GND
1
8
FAULT_1
VIN
2
7
OUT_1
ENABLE_1
3
6
OUT_2
ENABLE_2
4
5
FAULT_2
Page 1 of 13
ISL6119
Typical Application: Dual USB Port Power
D+
D-
U
S
B
USB
PORT 1
V+
OUT_1
ENABLE_1
FAULT_1
C
O
N
T
R
O
L
L
E
R
+5V
VIN
GND
ISL6119L
FAULT_2
ENABLE_2
OUT_2
V+
USB
PORT_2
D+
D-
Simplified Block Diagram
CHANNEL 1 LIKE CHANNEL 2
GND
FAULT_1
VIN
OUT_1
Q-PUMP
POR
EN_1
EN_2
FN9002 Rev 3.00
March 2004
CURRENT AND TEMP.
MONITORING, GATE AND
OUTPUT CONTROL
LOGIC
OUT_2
FAULT_2
Page 2 of 13
ISL6119
Pin Descriptions
PIN NO.
DESIGNATOR
1
GND
IC Reference
2
VIN
Chip bias, Controlled
Supply Input,
Undervoltage lock-out
VIN provides chip bias voltage. At VIN < 2.5V chip functionality is disabled, FAULT latch
is cleared and floating and OUT is held low.
3, 4
ENABLE_1, 2/
ENABLE_1, 2
Channel Enable/
Enable Not Inputs
Enables/Disables switch.
5, 8
FAULT_2, 1
Channel 2, 1 Over
Current Fault Not
Indicator
Channel overcurrent fault indicator. FAULT floats and is disabled until VIN >2.5V. This
output is pulled low after the OC timeout period has expired and stays latched until
ENABLE is deasserted.
6, 7
OUT_2, 1
FN9002 Rev 3.00
March 2004
FUNCTION
DESCRIPTION
Channel 2,1 Controlled Channel voltage output, connect to load to protect. Upon an OC condition IOUT is
Supply Output
current limited to 1A. Current limit response time is within 200s. This output will remain
in current limit for a nominal 12ms before being latched off.
Page 3 of 13
ISL6119
Absolute Maximum Ratings
Thermal Information
Supply Voltage (VIN to GND). . . . . . . . . . . . . . . . . . . . . . . . . . . 6.0V
EN, FAULT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V
OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND -0.3V to VIN 0.3V
Output Current . . . . . . . . . . . . . . . . . . . . . . . Short Circuit Protected
ESD Rating
Human Body Model (Per MIL-STD-883 Method 3015.7) . . . . 3KV
Thermal Resistance (Typical, Note 1)
JA (°C/W)
8 Lead SOIC Package . . . . . . . . . . . . . . . . . . . . . . .
96
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150°C
Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C
(SOIC - Lead Tips Only)
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to 85°C
Supply Voltage Range (Typical). . . . . . . . . . . . . . . . . . 2.7V to 5.5V
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
2. All voltages are relative to GND, unless otherwise specified.
Electrical Specifications
Supply Voltages = 5V, TA = TJ = -40 to 85°C, Unless Otherwise Specified
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
VIN = 2.7V IOUT = 0.7A TA = TJ = 25°C
-
90
105
m
TA = TJ = 85°C
-
115
130
m
POWER SWITCH
ISL6119 On Resistance at 2.7V
ISL6119 On Resistance at 3.3V
ISL6119 On Resistance at 5.0V
Disabled Output Voltage
rDS(ON)_27
rDS(ON)_33
rDS(ON)_50
VOUT_DIS
VIN = 3.3V, IOUT = 0.7A TA = TJ = 25°C
-
80
100
m
TA = TJ = 85°C
-
115
130
m
VIN = 5V, IOUT = 0.7A TA = TJ = 25°C
-
80
95
m
TA = TJ = 85°C
-
115
130
m
VIN = 5V, Switch Disabled, 50A Load
-
300
450
mV
t_vout_rt
RL = 10CL = 0.1F, 10%-90%
-
10
-
V/ms
Slow Vout Turn-off Rate
t_svout_offt
RL = 10CL = 0.1F, 90%-10%
-
10
-
V/ms
Fast Vout Turn-off Rate
t_fvout_offt
RL = 1CL = 0.1F, 90%-10%
-
4
-
V/s
0.75
1
1.25
A
Vout Rising Rate
CURRENT CONTROL
Current Limit, VIN = 3.3V - 5V
Ilim
Vout = 0.8V
tsettIlim
RL = 5CL = 0.1F to Within 10% of CR
-
2
-
ms
tsettIlim_sev
RL< 1CL = 0.1F to Within 10% of CR
-
100
-
s
tOC_loff
ISL6119X, Tj = +25°C
-
10
-
ms
Fault Output Voltage
Vfault_hi
Fault IOUT = 10mA
-
-
0.4
V
ENABLE High Threshold
Ven_vih
VIN = 5.5V
2.0
-
-
V
ENABLE Low Threshold at 2.7V
Ven_vil
VIN = 2.7V
-
-
0.6
V
ENABLE Low Threshold at 5.5V
Ven_vil
VIN = 5.5V
-
-
0.8
V
-0.5
-
0.5
A
-
120
200
A
OC Regulation Settling Time
Severe OC Regulation Settling Time
Over Current Latch-off Time
I/O PARAMETERS
ENABLE Input Current
Ien_i
ENABLE = 0V to 5V, VIN = 5V, TJ > 25°C
IVDD
Switches Closed, OUTPUT = OPEN, TJ > 0°C
IVDD
Switches Open, OUTPUT = OPEN
BIAS PARAMETERS
Enabled VIN Current
Disabled VIN Current
-
1
5
A
1.7
2.25
2.5
V
UVHYS
50
100
-
mV
Temp_dis
-
150
-
°C
Undervoltage Lockout Threshold
VUVLO
UV Hysteresis
Over Temperature Disable
FN9002 Rev 3.00
March 2004
VIN Rising, Switch Enabled
Page 4 of 13
ISL6119
Introduction
Latch-Off Time Delay
The ISL6119 is a fully independent dual channel overcurrent
(OC) fault protection IC for the +2.5V to +5.5V environment.
Each ISL6119 incorporates in a single 8 lead SOIC package
two 80mW N-channel MOSFET power switches for power
control. Independent enabling inputs and fault reporting
outputs compatible with 3V and 5V logic allows for external
control and monitoring. This device features internal current
monitoring, accurate current limiting, integrated power
switches and current limited timed delay to latch-off for system
protection. See Figure 1 for typical operational waveforms
including both under and overcurrent situations.
The primary function of any OC protection device is to quickly
isolate the voltage bus from a faulty load. Unlike many other IC
products that sense the IC thermal condition (the monitored IC
junction temperature depends on a number of factors the most
important of which are power dissipation of the faulted and
adjacent switches and package temp) to isolate a faulty load,
the ISL6119 uses an internal 12ms timer that starts upon OC
detection. Once an OC condition is detected the appropriate
output is current limited for a maximum of 12ms to allow
transient conditions to pass before latch-off. This time to latchoff is independent of device thermal or adjacent switch
condition. See Figure 18 for waveforms illustrating
independent latch-off.
Key Feature Description and Operation
UV Lock Out
The ISL6119 undervoltage lockout feature prevents
functionality of the device unless the correct ENABLE state
and VIN > 2.5V are present.
Soft Start
A constant 500nA current source ramps up the switch’s gate
causing a voltage follower effect on the output voltage. This
provides a soft start turn-on eliminating bus voltage drooping
caused by in-rush current charging heavy load capacitances.
Rising and falling outputs are current limited voltage ramps so
that both the inrush current and voltage slew rate are limited,
independent of load. This reduces supply droop due to surge
and also eliminates the need for EMI filters necessary on other
IC products.
Fault Blanking On Start-Up
During initial turn-on the ISL6119 prevents nuisance faults
being reported to the system controller by blanking the fault
signal for 12ms. This blanking eliminates the need for external
RC filters necessary for other vendor products that assert a
fault signal upon initial turn-on into a temporary high current
condition. See Figures 10 through 12 for waveform examples.
If, after the ISL6119 has latched off, and the fault has asserted
and, the enable is not deasserted but the OC condition still
exists, the ISL6119 unlike other IC devices does not send to
the controller a continuous string of fault pulses. The ISL6119’s
single fault signal is sent at the time of latch-off unlike other
devices.
Slow And Fast Shutdown
The ISL6119 has two shutdown modes. When turned off with a
load current less than the current regulation (CR) level the
ISL6119 shuts down in a controlled manner using a 500nA
constant current source controlled ramp. When latched off due
to CR and the timer has expired, the ISL6119 quickly pulls
down the output thereby quickly removing the faulted load from
the voltage bus. See Figures 8 and 9 for waveforms of each
mode.
Active Output Pulldown
Another unique ISL6119 feature is the active pull down on the
outputs to 300mV above GND when the device is disabled.
Competitors’ parts’ switch leakage causes the output voltage to
drift up to VIN voltage even when the part is supposed to be
disabled.
Current Regulation
The ISL6119 has integrated current sensing on the power
MOSFET that allows for rapid control of OC events. Once an
OC is detected the ISL6119 goes into its current regulation
(CR) control mode. The ISL6119 CR level is set to a nominal
1A. This current regulation is 25% over the full operating
temperature and voltage bias range. See Figures 4 and 5 for
illustrative curves. The speed of this control is inversely related
to the magnitude of the OC fault. Thus a hard overcurrent is
more quickly controlled than a marginal OC condition. See
Figure 6 for waveforms illustrating this and Figure 7 for an
accompanying graph.
Over Temperature Shutdown
Although the ISL6119 has a thermal shutdown feature,
because of the 12ms timed shutdown this will only be invoked
in extremely high ambient temperatures
FN9002 Rev 3.00
March 2004
ON
FAULT
OFF
ENABLE
LATCH-OFF SET
RESET BY
ENABLE
CURRENT
REGULATION
SETTLING TIME
(1.4ms)
VOUT
OVER CURRENT
1A CURRENT
LIMIT
IOUT
12ms CURRENT REGULATION PERIOD
FIGURE 1. TYPICAL OPERATIONAL WAVEFORMS
Page 5 of 13
ISL6119
Typical Performance Curves
120
ENABLE
SWITCH ON RESISTANCE (m)
110
VIN = 2.7V
100
10µF
90
CL = 0.1µF
VIN = 5V
80
70
60
CL = 100µF
VIN = 3.3V
50
OUTPUT
40
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90 100
TEMPERATURE (°C)
TIME (400µs/DIV)
FIGURE 2. SWITCH ON RESISTANCE AT 0.7A
FIGURE 3. VOUT SOFT START vs CLOAD, Rl = 10
1200
3.1
1200
-40°C
-40°C
1100
1000
IOUT (mA)
IOUT (mA)
1100
+25°C
+25°C
1000
+85°C
900
900
+85°C
800
1.25
1.5
1.75
2.0
2.25
2.5
2.75
800
3.0
1.3 1.5
2.0
2.5
3.0
3.5
4.0
4.5 4.8
VOUT (V)
VOUT (V)
FIGURE 4. CURRENT REGULATION vs Vout (VIN = 3.3V)
FIGURE 5. CURRENT REGULATION vs VOUT (VIN = 5.0V)
CURRENT REGULATED
LEVEL
NOMINAL CURRENT
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
TIME (200µs /DIV)
FIGURE 6. OC TO CR SETTLING TIME WAVEFORMS
FN9002 Rev 3.00
March 2004
TIME TO CURRENT REGULATION (ms)
OUTPUT CURRENT (1A/DIV)
1.6
1
2
3
4
5
6
7
8
9
FAULT CURRENT (A)
FIGURE 7. CR SETTLING TIME vs FAULT CURRENT
Page 6 of 13
10
ISL6119
Typical Performance Curves
(Continued)
ENABLE
CL = 10µF
CL = 10µF
CL = 100µF
CL = 100µF
CL = 0.1µF
VOUT
VOUT
CL = 0.1µF
VOUT VOLTAGE (1V/DIV)
VOUT
TIME (400µs /DIV)
VOUT VOLTAGE (1V/DIV)
FIGURE 8. SLOW TURN -OFF vs CLOAD, Rl = 10
TIME (400µs /DIV)
FIGURE 9. FAST TURN-OFF vs CLOAD
ENABLE
ENABLE
FAULT
FAULT
VOUT
VOUT
VOUT (1V/DIV)
TIME (2ms /DIV)
FIGURE 10. ISL6119L TURN-ON INTO 1.5A OCS
VOLTAGE (2V/DIV)
TIME (2ms /DIV)
FIGURE 11. ISL6119L TURN-ON INTO 1.5A MOMENTARY OC
ENABLE
VDD = 5.08V
FAULT
ISL6119 = 5.04 VOUT
PPTC = 4.98 VOUT
VOUT
TIME (2ms /DIV)
FIGURE 12. VENDOR IC TURN-ON INTO MOMENTARY OC
FN9002 Rev 3.00
March 2004
VOUT (100mV/DIV)
FIGURE 13. ISL6119 vs PPTC INTO 500mA LOAD
Page 7 of 13
ISL6119
Typical Performance Curves
(Continued)
PPTC
PPTC
8S
ISL6119
0.012S
ISL6119
VOUT (1V/DIV)
VOUT (1V/DIV)
TIME (10ms/DIV)
FIGURE 14. ISL6119 vs PPTC PLUGGED ONTO 1.5A LOAD
ENABLE
TIME (1s/DIV)
FIGURE 15. ISL6119 vs PPTC WITH EXTENDED 1.5A LOAD
ENABLE
ISL6119
COMP IC
COMP IC
ISL6119
VOUT (1V/DIV)
TIME (1ms /DIV)
FIGURE 16. COMPARATIVE TURN-ON WAVEFORMS, Rl = 10
VOUT (1V/DIV)
TIME (2ms/DIV)
FIGURE 17. I COMPARATIVE TURN-OFF WAVEFORMS
VIN
OUT 1
VOUT 2 = 3.7V IN CURRENT
REGULATION
OUT 2
VOLTAGE (1V/DIV)
TIME (100µs/DIV)
FIGURE 18. SWITCH FAULT INDEPENDENCE
FN9002 Rev 3.00
March 2004
Page 8 of 13
ISL6119
Using the ISL6119EVAL1 Platform
General and Biasing Information
The ISL6119EVAL1 platform, Figure 19, allows evaluation of
the ISL6119 dual power supply control IC and comparison
against a suitably sized PPTC component.
The evaluation platform is biased and monitored through
numerous test points (TP#). See Table 1 for test point
assignments and descriptions.
TABLE 1. ISL6119EVAL1 TEST POINT ASSIGNMENTS
TP #
DESCRIPTION
TP1
Eval Board and IC Gnd
TP2
Eval Bd +5V Bias
TP3
Enable Switch 1
TP4
Enable Switch 2
TP5
Switch 2 Fault
TP6
Switch Out 2
TP7
Switch Out 1
TP8
Switch 1 Fault
TP9
IC VIN Pin
TP10
PPTC Load Side
TP11
Invoke Over Current
Upon proper bias the PPTC, F1 has a nominal 500mA load
current passing through it which is the hold current rating for
that particular device. Removal of the PPTC is necessary to
isolate the ISL6119 as the PPTC load current is common to the
ISL6119EVAL1 bias connections.
By enabling either or both of the ISL6119L switches by
signaling TP3 and/or TP4 low ( 2.5V and on the FLTn pin. Once turned
on and an overcurrent (OC) condition occurs the IC provides
CR protection for 10ms and then the FLTn pin pulls low
through Rpu and also pulling the ENABLE low thus resetting
the device fault condition. At this time the Rpu charges the cap
and the voltage on the ENABLE/FLTn node rises until the
ENABLE > 2.0 and the output is asserted on once again. This
automatic reset cycle will continue until the OC fault no longer
exists on the output. After several seconds in this mode of
operation the IC thermal protection invokes adjusting the
timing of the on-off cycle to prevent excessive thermal
dissipation in the power switch protecting itself and
surrounding circuitry. See Figure 22 for operation waveform.
.
VIN/FLTn 5V/DIV
VOUT 2V/DIV
0V
IOUT 0.5A/DIV
0A
4ms/DIV
FIGURE 22. AUTO RESET OPERATION
Applications
• USB
• 2.5V to 5V up to 10W power port protection
Figure 21 illustrates the RC network needed with suggested
component values and the configuration of the relevant pins for
each autoreset channel.
FN9002 Rev 3.00
March 2004
Page 12 of 13
ISL6119
Small Outline Plastic Packages (SOIC)
M8.15 (JEDEC MS-012-AA ISSUE C)
N
INDEX
AREA
0.25(0.010) M
H
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC
PACKAGE
B M
E
INCHES
-B-
1
2
SYMBOL
3
L
SEATING PLANE
-A-
h x 45o
A
D
-C-
µ
e
B
0.25(0.010) M
C
0.10(0.004)
C A M
B S
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
MILLIMETERS
MIN
MAX
NOTES
A
0.0532
0.0688
1.35
1.75
-
0.0040
0.0098
0.10
0.25
-
B
0.013
0.020
0.33
0.51
9
C
0.0075
0.0098
0.19
0.25
-
D
0.1890
0.1968
4.80
5.00
3
E
0.1497
0.1574
3.80
4.00
4
0.050 BSC
1.27 BSC
-
H
0.2284
0.2440
5.80
6.20
-
h
0.0099
0.0196
0.25
0.50
5
L
0.016
0.050
0.40
1.27
6
8°
0°
N
NOTES:
MAX
A1
e
A1
MIN
8
0°
8
7
8°
Rev. 0 12/93
2. Dimensioning and tolerances per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
© Copyright Intersil Americas LLC 2001-2004. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN9002 Rev 3.00
March 2004
Page 13 of 13
