ISL6217ACVZA

ISL6217A ® Data Sheet June 30, 2005 FN9107.3 Precision Multi-Phase Buck PWM Controller for Intel, Mobile Voltage Positioning IMVP-IV™ and IMVP-IV+™ Features The ISL6217A Multi-Phase Buck PWM controller IC, with integrated half bridge gate drivers, provides a precision voltage regulation system for advanced Pentium IV microprocessors in notebook computers. Two-phase operation eases the thermal management issues and load demand of Intel’s latest high performance processors. This control IC also features both input voltage feed-forward and average current mode control for excellent dynamic response, “Loss-less” current sensing using MOSFET rDS(ON) and user-selectable switching frequencies from 250kHz to 1MHz per phase. • IMVP-IV™ and IMVP-IV+™ Compliant CORE Regulator The ISL6217A includes a 6-bit digital-to-analog converter (DAC) that dynamically adjusts the CORE PWM output voltage from 0.700V to 1.708V in 16mV steps and conforms to the Intel IMVP-IV™ and IMVP-IV+™ mobile VID specification. The ISL6217A also has logic inputs to select Active, Deep Sleep and Deeper Sleep modes of operation. A precision reference, remote sensing and proprietary architecture, with integrated, processor-mode, compensated “Droop”, provide excellent static and dynamic CORE voltage regulation. • Programmable “Droop” and CORE Voltage Slew Rate to comply with IMVP-IV™ and IMVP-IV+™ specification To improve efficiency at light loading, the ISL6217A can be configured to run in single phase PWM in ACTIVE, DEEP or DEEPER SLEEP modes of operation. Also, in deep and deeper sleep modes the ISL6217A will operate in diode emulation. Another feature of this IC controller is the PGOOD monitor circuit that is held low until CORE voltage increases, during its soft-start sequence, to within 12% of the “Boot” voltage. This PGOOD signal is masked during VID changes. Output overcurrent, overvoltage and undervoltage are monitored and result in the converter latching off and PGOOD signal being held low. • Diode Emulation Functionality in deep and deeper sleep modes for improved light load efficiency • Single and/or Two-phase Power Conversion • “Loss-less” Current sensing for improved efficiency and reduced board area - Optional Discrete Precision Current Sense Resistor • Internal Gate-Drive and Boot-Strap Diodes • Precision CORE Voltage Regulation - 0.8% system accuracy over temperature • 6-Bit Microprocessor Voltage Identification Input • Direct Interface with System Logic (STP_CPU# and DPRSLPVR) for Deep and Deeper Sleep modes of operation • Easily Programmable voltage setpoints for Initial “Boot”, Deep Sleep and Deeper Sleep Modes • Excellent Dynamic Response - Combined Voltage Feed-Forward and Average Current Mode Control • Overvoltage, Undervoltage and Overcurrent Protection • Power-Good Output with internal blanking during VID and mode changes • User programmable Switching Frequency of 250kHz 1MHz per phase • Pb-Free Plus Anneal Available (RoHS Compliant) The overvoltage and undervoltage thresholds are 112% and 84% of the VID, Deep or Deeper Sleep setpoint, respectively. Overcurrent protection features a 32 cycle overcurrent shutdown. PGOOD, overvoltage, undervoltage and overcurrent provide monitoring and protection for the microprocessor and power system. The ISL6217A IC is available in a 38 lead TSSOP. 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2004, 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL6217A Pinout Ordering Information PART NUMBER ISL6217ACV ISL6217ACV-T ISL6217ACVZ (Note 1) ISL6217ACVZ-T (Note 1) ISL6217ACVZA TEMP (°C) -10 to 85 PACKAGE PKG. DWG. # 38 Ld TSSOP M38.173 38 Ld TSSOP Tape and Reel -10 to 85 M38.173 38 Ld TSSOP (Pb-free) M38.173 38 Ld TSSOP Tape and Reel (Pb-free) M38.173 -10 to 85 38 Ld TSSOP (Pb-free) ISL6217ACVZA-T 38 Ld TSSOP Tape and Reel (Pb-free) M38.173 ISL6217A (38 LD TSSOP) TOP VIEW VDD 1 38 VBAT DACOUT 2 37 ISEN1 FSET 4 NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 34 BOOT1 EN 6 33 VSSP1 DRSEN 7 32 LG1 DSEN# 8 31 VDDP VID1 10 VID2 11 VID3 12 ISL6217A TSSOP 30 LG2 29 VSSP2 28 BOOT2 27 UG2 VID4 13 26 PHASE2 VID5 14 25 ISEN2 PGOOD 15 24 VSEN EA+ 16 23 DRSV COMP 17 FB 18 SOFT 19 2 35 UG1 PWRCH 5 VID0 9 M38.173 36 PHASE1 DSV 3 22 STV 21 OCSET 20 VSS FN9107.3 June 30, 2005 ISL6217A Absolute Voltage Ratings Thermal Information Supply Voltage, VDD, VDDP . . . . . . . . . . . . . . . . . . . . . . . . -0.3-+7V Battery Voltage, VBAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+25V Boot1,2 and UGATE1,2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+35V Phase1,2 and ISEN1,2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+30V Boot1,2 with respect to Phase1,2 . . . . . . . . . . . . . . . . . . . . . . +6.5V UGATE1,2 . . . . . . . . . . . . . . . (Phase1,2 - 0.3V) to (Boot1,2 + 0.3V) All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to (VDD + 0.3V) Thermal Resistance (Typical, Note 1) θJA (°C/W) TSSOP Package (Note 1) . . . . . . . . . . . . . . . . . . . . 72° Maximum Operating Junction Temperature. . . . . . . . . . . . . . . 125°C Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150°C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C Recommended Operating Conditions Supply Voltage, VDD, VDDP . . . . . . . . . . . . . . . . . . . . . . . +5V ±5% Ambient Temperature. . . . . . . . . . . . . . . . . . . . . . . . . .-10°C to 85°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . .-10°C to 125°C CAUTION: Stress above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. Electrical Specifications Operating Conditions: VDD = 5V, TA = -10°C to 85°C, Unless Otherwise Specified PARAMETER TEST CONDITIONS MIN TYP MAX UNITS EN = 3.3V, DSEN# = 0, DRSEN = 0, PWRCH = 0 - 1.4 - mA EN = 0V - 1 - µA VDD Rising 4.35 4.45 4.5 V VDD Falling 4.05 4.20 4.40 V Percent system deviation from programmed VID Codes @ 1.356 -0.8 - 0.8 % - - 0.3 V 0.7 - - V Maximum Output Voltage - 1.708 - V Minimum Output Voltage - 0.70 - V INPUT POWER SUPPLY Input Supply Current, I(VDD) POR (Power-On Reset) Threshold REFERENCE AND DAC System Accuracy DAC (VID0 - VID5) Input Low Voltage DAC Programming Input Low Threshold Voltage DAC (VID0 - VID5) Input High Voltage DAC Programming Input High Threshold Voltage CHANNEL GENERATOR Frequency, FSW RFset = 243K, ±1% 225 250 275 kHz Adjustment Range Guaranteed by Design 0.25 - 1.0 MHz - 100 - dB ERROR AMPLIFIER DC Gain Gain-Bandwidth Product CL = 20pF - 18 - MHz Slew Rate CL = 20pF - 4.0 - V/µs - 32 - µA - 64 - µA - 31 - µA 27 28 30 µA ISEN Full Scale Input Current Overcurrent Threshold ROCSET = 124K Soft-Start Current Droop Current GATE DRIVER UGATE Source Resistance 500mA Source Current - 1 1.5 Ω UGATE Source Current VUGATE-PHASE = 2.5V - 2 - A 3 FN9107.3 June 30, 2005 ISL6217A Electrical Specifications Operating Conditions: VDD = 5V, TA = -10°C to 85°C, Unless Otherwise Specified (Continued) PARAMETER TEST CONDITIONS MIN TYP MAX UNITS UGATE Sink Resistance 500mA Sink Current - 1 1.5 Ω UGATE Sink Current VUGATE-PHASE = 2.5V - 2 - A LGATE Source Resistance 500mA Source Current - 1 1.5 Ω LGATE Source Current VLGATE = 2.5V - 2 - A LGATE Sink Resistance 500mA Sink Current - 0.5 0.8 Ω LGATE Sink Current VLGATE = 2.5V - 4 - A 0.58 0.68 0.76 V 2.43 - - mA 56 63 82 Ω BOOTSTRAP DIODE Forward Voltage VDDP = 5V, Forward Bias Current = 10mA POWER GOOD MONITOR PGOOD Sense Current PGOOD pull down MOSFET rDS(ON) (See Figure 10) Undervoltage Threshold (Vsen/Vref) VSEN Rising - 85.0 - % Undervoltage Threshold (Vsen/Vref) VSEN Falling - 84.0 - % PGOOD Low Output Voltage IPGOOD = 4mA - 0.26 0.4 V EN, DSEN#, DRSEN Low - - 1 V EN, DSEN#, DRSEN High 2 - - V - 112.0 - % LOGIC THRESHOLD PROTECTION Overvoltage Threshold (Vsen/Vref) VSEN Rising Delay Time Delay Time from LGATE Falling to UGATE Rising VDDP = 5V, BOOT to PHASE = 5V, UGATE - PHASE = 2.5V, LGATE = 2.5V 10 18 30 ns Delay Time from UGATE Falling to LGATE Rising VDDP = 5V, BOOT to PHASE = 5V, UGATE - PHASE = 2.5V, LGATE = 2.5V 10 18 30 ns 4 FN9107.3 June 30, 2005 ISL6217A Functional Pin Description VDD - This pin is used to connect +5V to the IC to supply all power necessary to operate the chip. The IC starts to operate when the voltage on this pin exceeds the rising POR threshold and shuts down when the voltage on this pin drops below the falling POR threshold. FB - This pin is connected to the inverting input of the error amplifier. SOFT - This pin programs the slew rate of VID changes, Deep Sleep and Deeper Sleep transitions and Soft-Start after initializing. This pin is connected to ground via a capacitor, and to EA+ through an external “Droop” resistor. DACOUT - This pin provides access to the output of the Digital-to-Analog Converter. VBAT - Voltage on this pin provides feed-forward battery information which adjusts the oscillator ramp amplitude. DSV - The voltage on this pin provides the set point for output voltage during Deep Sleep Mode of operation. ISEN1, ISEN2 - These pins are used as current sense inputs from the individual converter channel phase nodes. FSET - A resistor from this pin to ground programs the switching frequency. PHASE1, PHASE2 - These pins are connected to the phase nodes of channels 1 and 2, respectively. PWRCH - This pin selects the number of power channels. A HIGH logic level on this pin enables 2 channel operation, and a LOW logic signal enables single channel operation. UG1, UG2 - These pins are the gate-drive outputs to the high side MOSFETs for channels 1 and 2, respectively. EN - This pin is connected to the system signal VR_ON and provides the enable/disable function for the PWM controller. DRSEN - This pin connects to system logic “DPRSLPVR” and enables Deeper Sleep mode of operation when a logic HIGH is detected on this pin. DSEN# - This pin connects to system logic “STP_CPU#” and enables Deep Sleep mode of operation. Deep Sleep is enabled when a logic LOW signal is detected on this pin. VID0, VID1, VID2, VID3, VID4, VID5 - These pins are used as inputs to the 6-bit Digital-to-Analog converter (DAC). VID0 is the least significant bit and VID5 is the most significant bit. PGOOD - This pin is used as an input and an output and is tied to the Vccp and Vcc_mch PGOOD signals. During startup, this pin is recognized as an input and prevents further slewing of the output voltage from the “Boot” level until PGOOD from Vccp and Vcc_mch is enabled High. After Start-up, this pin has an open drain output used to indicate the status of the CORE output voltage. This pin is pulled low when the system output is outside of the regulation limits. PGOOD includes a timer for power-on delay. EA+ - This pin is connected to the non-inverting input of the error amplifier and is used for setting the “Droop” voltage. BOOT1, BOOT2 - These pins are connected to the bootstrap capacitors, for upper gate-drive, for channels 1 and 2, respectively. VSSP1, VSSP2 - These pins are connected to the power ground of channels 1 and 2, respectively. LG1, LG2 - These pins are the gate-drive outputs to the low side MOSFETs for channels 1 and 2, respectively. VDDP - This pin provides a low-esr bypass connection to the internal gate drivers for the +5V source. VSEN - This pin is used for remote sensing of the microprocessor CORE voltage. DRSV - The voltage on this pin provides the set point for output voltage during Deeper Sleep Mode of operation. OCSET - A resistor from this pin to ground sets the overcurrent protection threshold. The current from this pin should be between 10µA and 25µA (70kΩ - 175kΩ equivalent) pull-down resistance. STV - The voltage on this pin sets the initial Start-Up or “Boot” voltage. VSS - This pin provides connection for signal ground. COMP - This pin provides connection to the error amplifier output. 5 FN9107.3 June 30, 2005 ISL6217A Block Diagram VSEN PGOOD VDD EN 1.3V + POWER-ON - RESET(POR) + CONTROL AND FAULT LOGIC OVP - VBAT CLOCK AND SAWTOOTH GENERATOR 1.75V FS HIGH-IMPEDANCE STATE + 112% RISING 102% FALLING Σ + PWM1 PWM - - 88% RISING 84% FALLING HIGH-IMPEDANCE STATE - + UV + Σ PWM2 PWM - 32 COUNT CLOCK CYCLE PWRCH + - BOOT1 VDDP UG1 DACOUT VSOFT SOFT PWM1 SOFT START PHASE LOGIC PHASE1 VDDP EA+ LG1 VID0 PWM2 VID1 VDDP VID2 + VID VID3 VSSP1 PHASE LOGIC D/A BOOT2 E/A - VID4 UG2 CHANNEL CURRENT BALANCE VID5 PWRCH PHASE2 COMP VDDP FB 1.75V + OCSET IDROOP OC MUX DRSV VCORE REF Σ - + DSV 1 2N Σ IOCSET STV LG2 0.435 -2µA VSSP2 Σ SAMPLE & HOLD 8µA ISEN1 CHANNEL CURRENT SENSE 32 COUNT CLOCK CYCLE ISEN2 VSS DSEN# DRSEN 6 PWRCH FN9107.3 June 30, 2005 ISL6217A Typical Application - 2-Phase Converter Figure 1 shows a 2-Phase Synchronous Buck Converter circuit used to provide “CORE” voltage regulation for the Intel Pentium IV mobile processor using IMVP-IV™ and IMVP-IV+™ voltage positioning. The ISL6217A PWM controller can be configured for two or one channel operation, and the ISL6217A can change the number of power channels in operation, dynamically. The number of channels of operation can be changed through +5VDC +5VDC the PWRCH pin. The ISL6217A can be configured for two channel operation in “Active” mode and one channel operation in “Deep” and “Deeper Sleep” modes through logic connections to the PWRCH pin. The following configuration uses two channel operation in “Active” mode and one channel operation in “Deep” and “Deeper Sleep” modes. The circuit shows pin connections for the ISL6217A PWM controller in the 38 lead TSSOP package. Vbattery VBAT VDD DACOUT ISEN1 DSV PHASE1 UG1 FSET BOOT1 PWRCH EN VSSP1 DRSEN LG1 DSEN# VDDP VID0 ISL6217A LG2 VID1 TSSOP VSSP2 VID2 BOOT2 VID3 UG2 VID4 PHASE2 VID5 ISEN2 PGOOD VSEN EA+ DRSV COMP STV FB OCSET VSS SOFT VR_ON DPRSLPVR STP_CPU# VID PWRGD +Vcc_core FIGURE 1. TYPICAL APPLICATION CIRCUIT FOR ISL6217A MULTIPHASE PWM CONTROLLER 7 FN9107.3 June 30, 2005 ISL6217A VID Capture VID Code < 3m s VR_ON / EN V BOOT >10us -12% V CC-CORE V VID t2 t1 PGOOD Vccp / Vcc_m ch 3m s to 12m s PGOOD Vcc_core FIGURE 2. TIMING DIAGRAM SHOWING VR_ON, VCC_CORE AND PGOOD FOR VCC_CORE, VCCP AND VCC_MCH Operation Initialization Soft-Start Interval Once the +5VDC supply voltage, as connected to the ISL6217A VDD pin, reaches the Power-On Reset (POR) rising threshold, the PWM drive signals are held in “highimpedance state” or high impedance mode. This results in both high and low side MOSFETs being held low. Once the supply voltage exceeds the POR rising threshold, the controller will respond to a logic level high on the EN pin and initiate the soft-start interval. If the supply voltage drops below the POR falling threshold, POR shutdown is triggered and the PWM signals are again driven to “high-impedance state”. Once VDD rises above the POR rising threshold and the EN pin voltage is above the threshold of 2.0V, a soft-start interval is initiated. Refer to Figure 2 and Figure 3. The system signal, VR_ON is directly connected to the EN pin of the ISL6217A. Once the voltage on the EN pin rises above 2.0V, the chip is enabled and soft-start begins. The EN pin of the ISL6217A is also used to reset the ISL6217A, for cases when an undervoltage or overcurrent fault condition has latched the IC off. A toggling of the state of this pin to a level below 1.0V will re-enable the IC. For the case of an overvoltage fault, the VDD pin must be reset. During Start-Up, the ISL6217A regulates to the voltage on the STV pin. This is referred to as the “Boot” voltage and is labelled VBOOT in Figure 2. Once power good signals are received from the Vccp and Vcc_mch regulators, the ISL6217A will capture the VID code and regulate to this command voltage within 3ms to 12ms. The PGOOD pin of the ISL6217A is both an input and an output and is further described in the “Fault Protection” section of this document. 8 The voltage on the EA+ pin is the reference voltage for the regulator. The voltage on the EA+ pin is equal to the voltage on the SOFT pin minus the “Droop” resistor voltage, VDROOP. During Start-Up, when the voltage on SOFT is less than the “Boot” voltage VBOOT, a small 30µA current source, I1, is used to slowly ramp up the voltage on the softstart capacitor CSOFT. This slowly ramps up the reference voltage for the controller, and therefore, controls the slew rate of the output voltage. The STV pin is externally programmable and sets the Start-Up, or “Boot” voltage, VBOOT. The programming of this voltage level is explained in the “STV, DSV and DRSV” section of this document. The ISL6217A PGOOD pin is both an input and an output. The system signal, IMVP4_PWRGD, is connected to power good signals from the Vccp and Vcc_mch supplies. The Intersil ISL6227, Dual Voltage Regulator is an ideal choice for the Vccp and Vcc_mch supplies. Once the output voltage is within the “Boot” level regulation limits and a logic high PGOOD signal from the Vccp and Vccp_mch regulators is received, the ISL6217A is enabled to capture the VID code and regulate to that command voltage. Refer to Figure 2 and Figure 3. A second current source, I2, is added to I1, after the initial Start-Up transition. I2 is approximately 100µA, and raises the total SOFT pin sinking and sourcing current to 130µA. This increased current is used to increase the slew rate of the reference to FN9107.3 June 30, 2005 ISL6217A meet all Active, Deep and Deeper Sleep slew rate requirements of the Intel IMVP-IV™ and IMVP-IV+™ specification. FSET RESISTOR VALUE (kΩ) 250 ISL6217A I1 I2 IDROOP Error Amplifier + SOFT R DROOP EA+ 200 150 100 50 0 250 500 750 1000 CHANNEL SWITCHING FREQUENCY, Fsw, (kHz) + V DROOP C SOFT FIGURE 4. CHANNEL SWITCHING FREQUENCY vs RFSET FIGURE 3. SOFT-START TRACKING CIRCUITRY SHOWING INTERNAL CURRENT SOURCES AND "DROOP" FOR ACTIVE, DEEP AND DEEPER SLEEP MODES OF OPERATION The “Droop” current source, IDROOP, is proportional to load current. This current source is used to reduce the reference voltage on EA+ by the voltage drop across the “Droop” resistor. A more in-depth explanation of “Droop”, and the sizing of this resistor, can be found in the “Droop Compensation” section of this document. The choice of value for soft-start capacitor is determined by the maximum slew rate required for the application. An example calculation is shown below. Using the combined I1 and I2 current sources on the SOFT pin as 130µA, and the worst case slew rate of (10mV/µs), the SOFT capacitor is calculated as follows: I 1µs CSOFT = SOURCE = 130µA × = 0.013µF ≈ 0.012µF SlewRate 10mV (EQ. 1) Gate-Drive Signals The ISL6217A provides internal gate-drive for a two channel, Synchronous Buck, Core Regulator. During two channel mode of operation, the PWM drive signals are switched 180° out of phase to reduce ripple current delivered from the DC rail and to the load. The ISL6217A was designed with a 4A, low-side gate current sink ability, and a 2A low-side gate current source ability, to efficiently drive the latest, high-performance MOSFETs. This feature will provide the system designer with flexibility in MOSFET selection, as well as optimum efficiency during Active mode of operation. 9 PWRCH Pin A HIGH logic level on this pin enables two channel operation and a LOW logic signal enables single channel operation. By tying this pin to the STP_CPU# system signal, (DSEN# pin on ISL6217A) single channel operation will be invoked during the light loading of both Deep and Deeper Sleep. If single channel operation is desired only during Deeper Sleep, the inversion of system signal DPRSLPVR can be connected to this pin. The aggressive gate-drive capability and diode emulation of ISL6217A, coupled with the single channel operation feature results in superior efficiency performance over both light and heavy loads. Frequency Setting Both channel switching frequencies are set up by a resistor from the FSET pin to ground. The choice of FSET resistance for a desired switching frequency can be approximated using Figure 4. The switching frequency is designed to operate between 250kHz and 1MHz per phase. CORE Voltage Programming The voltage identification pins (VID0, VID1, VID2, VID3, VID4 and VID5) set the DAC output voltage. These pins do not have internal pull-up or pull-down capability. These pins will recognize 1.0V, 3.3V, or 5.0V CMOS logic. Table 1 shows the command voltage, VDAC for the 6 bit VID codes. The IC responds to VID code changes as shown in Figure 5. PGOOD is masked between these transitions. FN9107.3 June 30, 2005 ISL6217A TABLE 1. IMPV-IV VID CODES (Continued) TABLE 1. IMPV-IV VID CODES VID5 VID4 VID3 VID2 VID1 VID0 VDAC VID5 VID4 VID3 VID2 VID1 VID0 VDAC 0 0 0 0 0 0 1.708 1 0 0 0 0 0 1.196 0 0 0 0 0 1 1.692 1 0 0 0 0 1 1.180 0 0 0 0 1 0 1.676 1 0 0 0 1 0 1.164 0 0 0 0 1 1 1.660 1 0 0 0 1 1 1.148 0 0 0 1 0 0 1.644 1 0 0 1 0 0 1.132 0 0 0 1 0 1 1.628 1 0 0 1 0 1 1.116 0 0 0 1 1 0 1.612 1 0 0 1 1 0 1.100 0 0 0 1 1 1 1.596 1 0 0 1 1 1 1.084 0 0 1 0 0 0 1.580 1 0 1 0 0 0 1.068 0 0 1 0 0 1 1.564 1 0 1 0 0 1 1.052 0 0 1 0 1 0 1.548 1 0 1 0 1 0 1.036 0 0 1 0 1 1 1.532 1 0 1 0 1 1 1.020 0 0 1 1 0 0 1.516 1 0 1 1 0 0 1.004 0 0 1 1 0 1 1.500 1 0 1 1 0 1 0.988 0 0 1 1 1 0 1.484 1 0 1 1 1 0 0.972 0 0 1 1 1 1 1.468 1 0 1 1 1 1 0.956 0 1 0 0 0 0 1.452 1 1 0 0 0 0 0.940 0 1 0 0 0 1 1.436 1 1 0 0 0 1 0.924 0 1 0 0 1 0 1.420 1 1 0 0 1 0 0.908 0 1 0 0 1 1 1.404 1 1 0 0 1 1 0.892 0 1 0 1 0 0 1.388 1 1 0 1 0 0 0.876 0 1 0 1 0 1 1.372 1 1 0 1 0 1 0.860 0 1 0 1 1 0 1.356 1 1 0 1 1 0 0.844 0 1 0 1 1 1 1.340 1 1 0 1 1 1 0.828 0 1 1 0 0 0 1.324 1 1 1 0 0 0 0.812 0 1 1 0 0 1 1.308 1 1 1 0 0 1 0.796 0 1 1 0 1 0 1.292 1 1 1 0 1 0 0.780 0 1 1 0 1 1 1.276 1 1 1 0 1 1 0.764 0 1 1 1 0 0 1.260 1 1 1 1 0 0 0.748 0 1 1 1 0 1 1.244 1 1 1 1 0 1 0.732 0 1 1 1 1 0 1.228 1 1 1 1 1 0 0.716 0 1 1 1 1 1 1.212 1 1 1 1 1 1 0.700 10 FN9107.3 June 30, 2005 ISL6217A Active, Deep Sleep and Deeper Sleep Modes TABLE 2. OUTPUT VOLTAGE AS A FUNCTION OF DSEN# AND DRSEN LOGIC STATES The ISL6217A Multi-Phase Controller is designed to control the CORE output voltage as per the IMVP-IV™ and IMVP-IV+™ specifications for Active, Deep Sleep, and Deeper Sleep Modes of Operation. DSEN# STP_CPU# DRSEN DPRSLPVR MODE OF OPERATION OUTPUT VOLTAGE 1 0 Active VID 0 0 Deep Sleep DSV 0 1 Deeper Sleep DRSV 1 1 Deeper Sleep DRSV After initial Start-up, a logic high signal on DSEN# and a logic low signal on DRSEN signals the ISL6217A to operate in Active mode. Refer to Table 2. This mode will recognize VID code changes and regulate the output voltage to these command voltages. VID[0..5] Current VID Code New VID Code