DATASHEET
ISL6227
FN9094
Rev 7.00
May 4, 2009
Dual Mobile-Friendly PWM Controller with DDR Option
The ISL6227 dual PWM controller delivers high efficiency
precision voltage regulation from two synchronous buck DC/DC
converters. It was designed especially to provide power
regulation for DDR memory, chipsets, graphics and other
system electronics in Notebook PCs. The ISL6227’s wide
input voltage range capability allows for voltage conversion
directly from AC/DC adaptor or Li-Ion battery pack.
Automatic mode transition of constant-frequency synchronous
rectification at heavy load, and hysteretic (HYS)
diode-emulation at light load, assure high efficiency over a wide
range of conditions. The HYS mode of operation can be
disabled separately on each PWM converter if
constant-frequency continuous-conduction operation is desired
for all load levels. Efficiency is further enhanced by using the
lower MOSFET rDS(ON) as the current sense element.
Voltage-feed-forward ramp modulation, current mode
control, and internal feedback compensation provide fast
response to input voltage and load transients. Input current
ripple is minimized by channel-to-channel PWM phase shift
of 0°, 90° or 180° (determined by input voltage and status of
the DDR pin).
The ISL6227 can control two independent output voltages
adjustable from 0.9V to 5.5V, or by activating the DDR pin,
transform into a complete DDR memory power supply
solution. In DDR mode, CH2 output voltage VTT tracks CH1
output voltage VDDQ. CH2 output can both source and sink
current, an essential power supply feature for DDR memory.
The reference voltage VREF required by DDR memory is
generated as well.
In dual power supply applications the ISL6227 monitors the
output voltage of both CH1 and CH2. An independent PGOOD
(power good) signal is asserted for each channel after the
soft-start sequence has completed, and the output voltage is
within PGOOD window. In DDR mode CH1 generates the only
PGOOD signal.
Built-in overvoltage protection prevents the output from going
above 115% of the set point by holding the lower MOSFET on
and the upper MOSFET off. When the output voltage re-enters
regulation, PGOOD will go HIGH and normal operation
automatically resumes. Once the soft-start sequence has
completed, undervoltage protection latches the offending
channel off if the output drops below 75% of its set point value.
Adjustable overcurrent protection (OCP) monitors the voltage
drop across the rDS(ON) of the lower MOSFET. If more precise
current-sensing is required, an external current sense resistor
may be used.
FN9094 Rev 7.00
May 4, 2009
Features
• Provides Regulated Output Voltage in the Range 0.9V to
5.5V
• Operates From an Input Battery Voltage Range of 5V to
28V or From 3.3V/5V System Rail
• Complete DDR1 and DDR2 Memory Power Solution with
VTT Tracking VDDQ/2 and a VDDQ/2 Buffered Reference
Output
• Flexible PWM or HYS Plus PWM Mode Selection with
HYS Diode Emulation at Light Loads for Higher System
Efficiency
• rDS(ON) Current Sensing
• Excellent Dynamic Response With Voltage Feed-Forward
and Current Mode Control Accommodating Wide Range
LC Filter Selections
• Undervoltage Lock-Out on VCC Pin
• Power-Good, Overcurrent, Overvoltage, Undervoltage
Protection for Both Channels
• Synchronized 300kHz PWM Operation in PWM Mode
• Pb-Free Available (RoHS compliant)
Applications
• Notebook PCs and Desknotes
• Tablet PCs/Slates
• Hand-Held Portable Instruments
Ordering Information
PART
NUMBER
PART
MARKING
ISL6227CA*
ISL 6227CA
TEMP.
RANGE (°C)
PACKAGE
PKG.
DWG. #
-10 to +100 28 Ld QSOP M28.15
ISL6227CAZ* ISL 6227CAZ -10 to +100 28 Ld QSOP M28.15
(Note)
(Pb-Free)
ISL6227IA*
ISL 6227IA
ISL6227IAZ* ISL 6227IAZ
(Note)
-40 to +100 28 Ld QSOP M28.15
-40 to +100 28 Ld QSOP M28.15
(Pb-Free)
ISL6227HRZ* ISL 6227HRZ -10 to +100 28 Ld QFN
(Note)
(Pb-Free)
L28.5x5
ISL6227IRZ* ISL 6227IRZ
(Note)
L28.5x5
-40 to +100 28 Ld QFN
(Pb-Free)
*Add “-T” suffix for tape and reel. Please refer to TB347 for details on
reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination
finish, which is RoHS compliant and compatible with both SnPb and
Pb-free soldering operations). Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020.
Page 1 of 27
ISL6227
Pinouts
ISL6227
28 LD QSOP
ISL6227
28 LD 5X5 QFN
23 BOOT2
ISEN1 7
22 ISEN2
BOOT1 3
21 EN2
18 OCSET2
VOUT1 6
16 VSEN2
15 OCSET2
VSEN1 7
17 SOFT2
8
VIN 14
OCSET1
16 PG2/REF
DDR 13
15 PG1
9 10 11 12 13 14
SOFT2
SOFT1 12
17 VOUT2
DDR
19 VSEN2
18 EN2
EN1 5
SOFT1
VSEN1 10
OCSET1 11
19 ISEN2
GND
29
ISEN1 4
20 VOUT2
PHASE2
20 BOOT2
BOOT1 6
VOUT1 9
PGND2
21 UGATE2
UGATE1 2
EN1 8
LGATE2
24 UGATE2
28 27 26 25 24 23 22
PHASE1 1
PG2/REF
UGATE1 5
VCC
26 PGND2
25 PHASE2
PG1
PGND1 3
PHASE1 4
GND
28 VCC
27 LGATE2
VIN
GND 1
LGATE1 2
LGATE1
TOP VIEW
PGN1
TOP VIEW
Generic Application Circuits
OCSET1
Q1
L1
PWM1
C1
Q2
VIN
VOUT1
+1.80V
+
EN1
+5V TO +28V
EN2
Q3
VCC
DDR
+5V
OCSET2
L2
VOUT2
PWM2
C2
Q4
+
+1.20V
ISL6227 APPLICATION CIRCUIT FOR TWO CHANNEL POWER SUPPLY
OCSET1
Q1
L1
PWM1
Q2
VIN
EN1
+5V TO 28V
EN2
+5V
PG2/VREF
+2.50V
+
Q3
VCC
DDR
C1
VDDQ
PWM2
L2
VTT
OCSET2
Q4
C2
+
+1.25V
VREF
+1.25V
ISL6227 APPLICATION CIRCUIT FOR COMPLETE DDR MEMORY POWER SUPPLY
FN9094 Rev 7.00
May 4, 2009
Page 2 of 27
ISL6227
Absolute Maximum Ratings
Thermal Information
Bias Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +6.5V
Input Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +28.0V
PHASE, UGATE . . . . . . . . . . . . . . . . . . . GND -5V (Note 1) to 33.0V
BOOT, ISEN . . . . . . . . . . . . . . . . . . . . . . . . . . GND -0.3V to +33.0V
BOOT with Respect to PHASE . . . . . . . . . . . . . . . . . . . . . . . . + 6.5V
All Other Pins . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to VCC + 0.3V
Thermal Resistance (Typical)
JA (°C/W) JC (°C/W)
80
N/A
QSOP Package (Note 2) . . . . . . . . . . . . .
QFN Package (Notes 3, 4). . . . . . . . . . . .
36
6
Maximum Junction Temperature (Plastic Package). . . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Bias Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5.0V 5%
Input Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . .+5.0V to +28.0V
Ambient Temperature Range . . . . . . . . . . . . . . . . . -10°C to +100°C
Junction Temperature Range . . . . . . . . . . . . . . . . . -10°C to +125°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1. 250ns transient. See Confining The Negative Phase Node Voltage Swing in Application Information Section
2. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
3. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
4. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
5. Limits established by characterization and are not production tested.
Electrical Specifications
PARAMETER
Recommended Operating Conditions, Unless Otherwise Noted. Parameters with MIN and/or MAX limits are
100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are
not production tested.
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
-
1.8
3.0
mA
ICCSN
-
-
1
µA
Rising VCC Threshold
VCCU
4.3
4.45
4.5
V
Falling VCC Threshold
VCCD
4
4.14
4.34
V
IVIN
-
-
35
µA
IVINS
-
-
1
µA
Commercial, ISL6227C
255
300
345
kHz
Industrial, ISL6227I
240
300
345
kHz
VCC SUPPLY
Bias Current
Shut-down Current
ICC
LGATEx, UGATEx Open, VSENx forced above
regulation point, VIN > 5V
VCC UVLO
VIN
Input Voltage Pin Current (Sink)
Shut-Down Current
OSCILLATOR
PWM1 Oscillator Frequency
fc
Ramp Amplitude, pk-pk
VR1
VIN = 16V (Note 5)
-
2
-
V
Ramp Amplitude, pk-pk
VR2
VIN = 5V (Note 5)
-
0.625
-
V
(Note 5)
-
1
-
V
Ramp Offset
VROFF
Ramp/VIN Gain
GRB1
VIN 4.2V (Note 5)
-
125
-
mV/V
Ramp/VIN Gain
GRB2
VIN 4.1V (Note 5)
-
250
-
mV/V
-
0.9
-
V
-1.0
-
+1.0
%
REFERENCE AND SOFT-START
Internal Reference Voltage
Reference Voltage Accuracy
FN9094 Rev 7.00
May 4, 2009
VREF
Page 3 of 27
ISL6227
Electrical Specifications
Recommended Operating Conditions, Unless Otherwise Noted. Parameters with MIN and/or MAX limits are
100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are
not production tested. (Continued)
PARAMETER
Soft-Start Current During Start-Up
Soft-Start Complete Threshold
SYMBOL
TEST CONDITIONS
ISOFT
VST
(Note 5)
MIN
TYP
MAX
UNITS
-
-4.5
-
µA
-
1.5
-
V
-2.0
-
+2.0
%
-
80
-
nA
PWM CONVERTERS
0.0mA < IVOUT1 < 5.0A; 5.0V < VBATT < 28.0V
Load Regulation
(Note 5)
VSEN Pin Bias Current
IVSEN
Minimum Duty Cycle
Dmin
-
4
-
%
Maximum Duty Cycle
Dmax
-
87
-
%
VOUT Pin Input Impedance
IVOUT
VOUT = 5V
-
134
-
k
Undervoltage Shut-Down Level
VUVL
Fraction of the set point; ~2µs noise filter
70
75
80
%
VOVP1
Fraction of the set point; ~2µs noise filter
110
115
-
%
Overvoltage Protection
GATE DRIVERS
Upper Drive Pull-Up Resistance
R2UGPUP
VCC = 5V
-
4
8
Upper Drive Pull-Down Resistance
R2UGPDN
VCC = 5V
-
2.3
4
Lower Drive Pull-Up Resistance
R2LGPUP
VCC = 5V
-
4
8
Lower Drive Pull-Down Resistance
R2LGPDN
VCC = 5V
-
1.1
3
POWER GOOD AND CONTROL FUNCTIONS
Power Good Lower Threshold
VPG-
Fraction of the set point; ~3µs noise filter
84
89
92
%
Power Good Higher Threshold
VPG+
Fraction of the set point; ~3µs noise filter.
110
115
120
%
IPGLKG
VPULLUP = 5.5V
-
-
1
µA
VPGOOD
IPGOOD = -4mA
-
0.5
1
V
(Note 5)
-
-
260
µA
OCSET Sourcing Current Range
2
-
20
µA
EN - Low (Off)
-
-
0.8
V
EN - High (On)
2.0
-
-
V
-
-
0.1
V
0.9
-
-
V
DDR - Low (Off)
-
-
0.8
V
DDR - High (On)
3
-
-
V
0.99*
VOC2
VOC2
1.01*
VOC2
V
-
10
12
mA
PGOODx Leakage Current
PGOODx Voltage Low
ISEN Sourcing Current
Continuous-Conduction-Mode(CCM)
Enforced (HYS Operation Inhibited)
VOUTX pulled low
Automatic CCM/HYS Operation
Enabled
VOUTX connected to the output
DDR REF Output Voltage
VDDREF
DDR = 1, IREF = 0...10mA
DDR REF Output Current
IDDREF
DDR = 1 (Note 5)
FN9094 Rev 7.00
May 4, 2009
Page 4 of 27
ISL6227
Typical Operation Performance
EFF@ 5V
90
100
EFF@ 12V
EFFICIENCY (%)
80
80
EFF@ 19.5V
70 EFF@ 5V, PWM
60
EFF@ 12V, PWM
50
40
30
EFF@ 19.5V, PWM
20
EFF@ 5V
60
0.10
1.00
LOAD CURRENT (A)
50
EFF@ 12V, PWM
40
EFF@ 5V, PWM
30
0
0.01
10.0
FIGURE 1. EFFICIENCY OF CHANNEL 1, 2.5V,
HYS/PWM MODE
1.83
OUTPUT VOLTAGE (V)
2.52
VOUT @ 12V
2.51
VOUT @ 19.5V, PWM
2.50
2.49
VOUT @ 5V, PWM
2.48
VOUT @ 12V, PWM
1.82
VOUT @ 12V
1.81
VOUT @ 12V, PWM
VOUT @ 19.5V, PWM
1.80
VOUT @ 5V, PWM
1.79
VOUT @ 5V
VOUT @ 5V
0
1
2
3
LOAD CURRENT (A)
4
1.78
5
FIGURE 3. OUTPUT VOLTAGE OF CHANNEL 1 vs LOAD
308
1
2
3
LOAD CURRENT (A)
0.9025
5
0.9015
0.9010
VREF (V)
300
298
25% QUANTILE
296
4
75% QUANTILE
0.9020
FREQUENCY MEAN
302
0
FIGURE 4. OUTPUT VOLTAGE OF CHANNEL 2 vs LOAD
75% QUANTILE
306
304
10.0
VOUT @ 19.5V
VOUT @ 19.5V
2.53
2.47
0.10
1.00
LOAD CURRENT (A)
FIGURE 2. EFFICIENCY OF CHANNEL 2, 1.8V,
HYS/PWM MODE
2.54
294
VREF MEAN
0.9005
0.9000
25% QUANTILE
0.8995
0.8990
292
290
0.8985
288
0.8980
286
EFF@ 19.5V, PWM
10
0
0.01
OUTPUT VOLTAGE (V)
EFF@ 19.5V
70
20
10
FREQUENCY (kHz)
EFF@ 12V
90
EFFICIENCY (%)
100
-20
0
20
40
60
80
100
120
TEMPERATURE (°C)
FIGURE 5. SWITCHING FREQUENCY OVER-TEMPERATURE
FN9094 Rev 7.00
May 4, 2009
0.8975
-20
0
20
40
60
80
TEMPERATURE (°C)
100
FIGURE 6. REFERENCE VOLTAGE ACCURACY
OVER-TEMPERATURE
Page 5 of 27
120
ISL6227
Typical Operation Performance
(Continued)
Vo1
VO1
VO1
Vo1
VPHASE1
Vphase1
VPHASE1
Vphase1
ILO1
Ilo1
ILO1
Ilo1
VO2
Vo2
VO2
Vo2
FIGURE 7. LOAD TRANSIENT (0A TO 3A AT CHANNEL 1)
(DIODE EMULATION MODE)
VO1
Vo1
VPHASE2
Vphase2
FIGURE 8. LOAD TRANSIENT (0A TO 3A AT CHANNEL 1)
(FORCED PWM MODE)
VO1
Vo1
VPHASE2
Vphase2
ILO2
Ilo2
ILO2
Ilo2
VO2
Vo2
VO2
Vo2
FIGURE 9. LOAD TRANSIENT (0A TO 2A AT CHANNEL 2)
(DIODE EMULATION MODE)
FIGURE 10. LOAD TRANSIENT (0A TO 3A AT CHANNEL 2)
(FORCED PWM MODE)
Vin1
VIN1
VIN1
Vin1
VO1
Vo1
VO1
Vo1
VO2
Vo2
VO2
Vo2
FIGURE 11. INPUT STEP-UP TRANSIENT AT PWM MODE
FN9094 Rev 7.00
May 4, 2009
FIGURE 12. INPUT STEP-UP TRANSIENT AT HYS MODE
Page 6 of 27
ISL6227
Typical Operation Performance
(Continued)
Vin1
VIN1
VIN1
Vin1
Vo1
VO1
VO1
Vo1
VO2
Vo2
Vo2
VO2
FIGURE 13. INPUT STEP-DOWN TRANSIENT AT PWM MODE
FIGURE 14. INPUT STEP-DOWN TRANSIENT AT HYS MODE
EN1
EN1
EN1
EN1
PG1
PG1
PG1
PG1
SOFT1
SOFT1
Vo1
VO1
FIGURE 15. SOFT-START INTERVAL AT ZERO INITIAL
VOLTAGE OF VO
VO1
Vo1
Vphase1
VPHASE1
SOFT1
SOFT1
VO1
Vo1
FIGURE 16. SOFT-START INTERVAL WITH NON-ZERO INITIAL
VOLTAGE OF VO
VO1
Vo1
Vphase1
VPHASE1
ILO1
Ilo1
ILO1
Ilo1
VO2
Vo2
VO2
Vo2
FIGURE 17. OPERATION AT LIGHT LOAD OF 100mA,
CHANNEL 1
FN9094 Rev 7.00
May 4, 2009
FIGURE 18. OPERATION AT HEAVY LOAD OF 4A,
CHANNEL 1
Page 7 of 27
ISL6227
Typical Operation Performance
(Continued)
VO1
Vo1
VO1
Vo1
PG1
PG1
PG1
PG1
ILO1
Ilo1
ILO1
Ilo1
VO2
Vo2
Vo2
VO2
FIGURE 19. OVERCURRENT PROTECTION AT CHANNEL 1
VO1
Vo1
FIGURE 20. SHORT-CIRCUIT PROTECTION AT CHANNEL 1
VO1
Vo1
VPHASE1
Vphase1
VPHASE2
Vphase2
ILO1
Ilo1
Ilo2
ILO2
VO2
Vo2
Vo2
VO2
FIGURE 21. MODE TRANSITION OF HYS _PWM
FIGURE 22. MODE TRANSITION OF PWM HYS
EN1
EN1
VTT
VTT
PG1
PG1
OCSET
OCSET
SOFT1
SOFT1
VDDQ
VDDQ
Vo1
VO1
VCC
VCC
FIGURE 23. NORMAL SHUTDOWN, IOUT = 1.5A
FN9094 Rev 7.00
May 4, 2009
FIGURE 24. VCC POWER-UP IN DDR MODE
Page 8 of 27
ISL6227
Typical Operation Performance
(Continued)
VDDQ
VDDQ
PGOOD1
PGOOD1
VDDQ
VDDQ
PGOOD1
PGOOD1
VTT
VTT
VTT
VTT
IL1
IL1
IL1
IL1
FIGURE 25. VIN = 19V, VDDQ 3A STEP LOAD, VTT 0A LOAD
FIGURE 26. VIN = 19V, VDDQ 3A STEP LOAD, VTT 3A LOAD
VDDQ
VDDQ
VDDQ
VDDQ
VTT
VTT
VTT
VTT
OCSET2
OCSET2
IL2
IL2
FIGURE 27. VIN = 19V, LOAD STEP ON VTT,
VDDQ HYS MODE, 0.14A
OCSET2
OCSET2
IL2
IL2
FIGURE 28. VIN = 19V, LOAD STEP ON VTT,
VDDQ PWM MODE, 0.14A
VDDQ
VDDQ
VTT
VTT
VIN
Vin
EN1
EN1
VTT
VTT
VDDQ
VDDQ
OCSET2
OCSET2
FIGURE 29. INPUT LINE TRANSIENT IN DDR MODE
FN9094 Rev 7.00
May 4, 2009
IL1
IL1
FIGURE 30. VTT FOLLOWS VDDQ, ENABLE 2 IS HIGH
Page 9 of 27
ISL6227
Functional Pin Description
OCSET1
Signal ground for the IC.
This pin is a buffered 0.9V internal reference voltage. A
resistor from this pin to ground sets the overcurrent
threshold for the first controller.
LGATE1, LGATE2
SOFT1, SOFT2
These are the outputs of the lower MOSFET drivers.
These pins provide soft-start function for their respective
controllers. When the chip is enabled, the regulated 4.5µA
pull-up current source charges the capacitor connected from
the pin to ground. The output voltage of the converter follows
the ramping voltage on the SOFT pin in the soft-start
process with the SOFT pin voltage as reference. When the
SOFT pin voltage is higher than 0.9V, the error amplifier will
use the internal 0.9V reference to regulate output voltage.
GND
PGND1, PGND2
These pins provide the return connection for lower gate
drivers, and are connected to sources of the lower
MOSFETs of their respective converters.
PHASE1, PHASE2
The PHASE1 and PHASE2 points are the junction points of
the upper MOSFET sources, output filter inductors, and
lower MOSFET drains. Connect these pins to the respective
converter’s upper MOSFET source.
In the event of undervoltage and overcurrent shutdown, the
soft-start pin is pulled down though a 2k resistor to ground to
discharge the soft-start capacitor.
UGATE1, UGATE2
DDR
These pins provide the gate drive for the upper MOSFETs.
These pins are used to monitor the voltage drop across the
lower MOSFET for current feedback and Overcurrent
protection. For precise current detection these inputs can be
connected to the optional current sense resistors placed in
series with the source of the lower MOSFETs.
When the DDR pin is low, the chip can be used as a dual
switcher controller. The output voltage of the two channels
can be programmed independently by VSENx pin resistor
dividers. The PWM signals of Channel 1 and Channel 2 will
be synchronized 180° out-of-phase. When the DDR pin is
high, the chip transforms into a complete DDR memory
solution. The OCSET2 pin becomes an input through a
resistor divider tracking to VDDQ/2. The PG2/REF pin
becomes the output of the VDDQ/2 buffered voltage. The
VDDQ/2 voltage is also used as the reference to the error
amplifier by the second channel. The channel phase-shift
synchronization is determined by the VIN pin when DDR = 1
as described in VIN below.
EN1, EN2
VIN
These pins enable operation of the respective converter
when high. When both pins are low, the chip is disabled and
only low leakage current is taken from VCC and VIN. EN1
and EN2 can be used independently to enable either
Channel 1 or Channel 2.
This pin has multiple functions. When connected to battery
voltage, it provides battery voltage to the oscillator as a
feed-forward for the rejection of input voltage variation. The
ramp of the PWM comparator is proportional to the voltage
on this pin (see Table 1 and Table 2 for details). While the
DDR pin is high in the DDR application, and when the VIN
pin voltage is greater than 4.2V when connecting to a
battery, it commands 90° out-of-phase channel
synchronization, with the second channel lagging the first
channel, to reduce inter-channel interference. When the pin
voltage is less than 4.2V, this pin commands in-phase
channel synchronization.
BOOT1, BOOT2
These pins power the upper MOSFET drivers of the PWM
converter. Connect this pin to the junction of the bootstrap
capacitor with the cathode of the bootstrap diode. The anode
of the bootstrap diode is connected to the VCC voltage.
ISEN1, ISEN2
VOUT1, VOUT2
These pins, when connected to the converter’s respective
outputs, set the converter operating in a mixed hysteretic
mode or PWM mode, depending on the load conditions. It
also provides the voltage to the chip to clamp the PWM error
amplifier in hysteretic mode to achieve smooth HYS/PWM
transition. When connected to ground, these pins command
forced continuous conduction mode (PWM) at all load levels.
VSEN1, VSEN2
These pins are connected to the resistive dividers that set
the desired output voltage. The PGOOD, UVP, and OVP
circuits use this signal to report output voltage status.
FN9094 Rev 7.00
May 4, 2009
PG1
PGOOD1 is an open drain output used to indicate the status
of the output voltage. This pin is pulled low when the first
channel output is out of -11% to +15% of the set value.
Page 10 of 27
ISL6227
PG2/REF
Typical Application
This pin has a double function, depending on the mode of
operation.
Figures 31 and 32 show the application circuits of a dual
channel DC/DC converter for a notebook PC.
When the chip is used as a dual channel PWM controller
(DDR = 0), the pin provides an open drain PGOOD2 function
for the second channel the same way as PG1. The pin is
pulled low when the second channel output is out of
-11% to +15% of the set value.
The power supply in Figure 31 provides +2.5V and +1.8V
voltages for memory and the graphics interface chipset from
a +5.0VDC to a 28VDC battery voltage.
In DDR mode (DDR = 1), this pin is the output of the buffer
amplifier that takes VDDQ/2 voltage applied to OCSET2 pin
from the resister divider. It can source a typical 10mA
current.
OCSET2
Figure 32 illustrates the application circuit for a DDR memory
power solution. The power supply shown in Figure 32
generates +2.5V VDDQ voltage from a battery. The +1.25V
VTT termination voltage tracks VDDQ/2 and is derived from
+2.5V VDDQ. To complete the DDR memory power
requirements, the +1.25V reference voltage is provided
through the PG2 pin.
In a dual channel application with DDR = 0, a resistor from
this pin to ground sets the overcurrent threshold for the
second channel controller. Its voltage is the buffered internal
0.9V reference.
In the DDR application with DDR = 1, this pin connects to the
center point of a resistor divider tracking the VDDQ/2. This
voltage is then buffered by an amplifier voltage follower and
sent to the PG2/REF pin. It sets the reference voltage of
Channel 2 for its regulation.
VCC
This pin powers the controller.
FN9094 Rev 7.00
May 4, 2009
Page 11 of 27
ISL6227
VIN
VCC (5V)
D1
BAT54W
Cdc
4.7µF
GND
Cin1
10 µ F
Cfb1
0.01µ F
Rbt1
0
Lo1
V1 (2.5V)
Rfb11
17.8k
Cbt1
Cb
0.15µF
4.7µH
Co11
220 µF
Q1
Rs1
2.0k
Co12
4.7µ F
FDS6912A
D2
BAT54W
VIN VCC
BOOT1
DDR
BOOT2
UGATE1
UGATE2
PHASE1
PHASE2
ISEN1
ISEN2
LGATE1
LGATE2
PGND1
PGND2
VOUT1
VOUT2
VSEN1
VSEN2
PG1
Rfb12
10k
Cbt2
0.15µF
Cin2
10µF
0
Lo2
Rs2
2.0k
Q2
V2 (1.8V)
V
4.7µH
Co21 Co22
220 µF 4.7µF
U1
Rfb21
10k
Rfb22
10k
EN2
SOFT1
SOFT2
OCSET2
OCSET1
Rset1
100k
Cfb2
0.01µF
FDS6912A
PG2
EN1
Csoft1
0.01 µ F
Rbt2
Csoft2
Rset2
100k
ISL6227
0.01µF
FIGURE 31. TYPICAL APPLICATION CIRCUIT AS DUAL SWITCHER, VOUT1 = 2.5V, VOUT = 1.8V
Vin
VCC (5V)
D1
BAT54W
Cdc
4.7µ F
GND
Cin1
10 µ F
Cbt1
0.15µF
0
Lo1
4.6µ
4.6 H
VDDQ (2.5V)
Q1
Rfb1
17.8k
Cfb1
0.01µ
0.01 F
Rbt1
Co11
Co13
220 µ F 4.7µ F
Rs1
2.0k
FDS6912A
VIN VCC
BOOT1
DDR
BOOT2
UGATE1
UGATE2
PHASE1
PHASE2
ISEN1
ISEN2
LGATE1
LGATE2
PGND1
PGND2
VOUT1
VSEN2
VSEN1
PG2_REF
Rbt2
Cbt2
0.15µF
U1
EN1
EN2
Cin2
4.7µF
0
Lo2
Rs2
1.0k
Q2
Vref (VDDQ/2)
Cref
4.7µF
OCSET2_VDDQ/2
VDDQ
Rd1
10k
VDDQ/2
OCSET1
Rset1
100k
Co22
4.7µF
FDS6912A
SOFT1
Csoft1
0.01µF
VTT (1.25V)
1.5
1.5µH
Co21
220µF
VOUT2
PG1
Rfb12
10K
D2
BAT54W VDDQ
SOFT2
ISL6227
Cf
0.1
0.1µF
Csoft2 (N/U)
0.01µF
Rd2
10k
FIGURE 32. TYPICAL APPLICATION AS DDR MEMORY POWER SUPPLY, VDDQ = 2.5V, VTT = 1.25V
FN9094 Rev 7.00
May 4, 2009
Page 12 of 27
BOOT1
PG1
VCC GND
EN1 VOUT1
VOUT2
EN2
BOOT2
REF/PG2
UGATE2
UGATE1
PHASE1
DDR = 0
ADAPTIVE DEAD-TIME
DIODE EMULATION
V/I SAMPLE TIMING
PWM/HYS TRANSITION
PGND1
LGATE1
VCC
DDR = 1
PHASE2
ADAPTIVE DEAD-TIME
DIODE EMULATION
V/I SAMPLE TIMING
PWM/HYS TRANSITION
PGND2
LGATE2
VCC
POR
MODE CHANGE COMP 1
MODE CHANGE COMP 2
ENABLE
HYSTERETIC COMPARATOR 1
SAME STATE FOR
8 CLOCK CYCLES
REQUIRED TO CHANGE
PWM OR HYS MODE
SAME STATE FOR
8 CLOCK CYCLES
REQUIRED TO CHANGE
PWM OR HYS MODE
BIAS SUPPLIES
REFERENCE
HYSTERETIC COMPARATOR 2
FAULT LATCH
VHYS = 15mV
VHYS = 15mV
SOFT-START
15pF
1M
300k
1M
500k
PWM1
PWM2
4.4k
(200k, DDR = 1)
SOFT2
ERROR AMP 2
DDR = 0
DUTY CYCLE RAMP GENERATOR
PWM CHANNEL PHASE CONTROL
SOFT1
DDR EN1 EN2
CURRENT
SAMPLE
DDR = 1
+
0.9V
REF
CH1/CH2
VIN
140
CURRENT
SAMPLE
VSEN2
300k
1.25pF
OC1 DDR OC2
ERROR AMP 1
+ 0.9V
REF
15pF
VOLTS/SEC
CLAMP
1.25pF
4.4k
ISEN1
OV UV
PGOOD
DDR MODE
CONTROL
VOLTS/SEC
CLAMP
500k
VSEN1
OV UV
PGOOD
0
1
1
0V 28.0V
1
1
1
4.2 IHYS1
PWM
FN9094 Rev 7.00
May 4, 2009
The critical discontinuous conduction current value for the
PWM to HYS mode switch-over can be calculated by
Equation 4:
V IN – V O V O
I HYS = ---------------------------------------------------2 F SW L O V IN
(EQ. 4)
The HYS mode to PWM switch-over current IHYS1 is
determined by the activation time of the HYS mode
controller. It is affected by the ESR, the inductor value, the
input and output voltage.
VIN
ISEN
The two channels can be programmed to operate in different
modes depending on the VOUTx connection and the load
current. Once both channels operate in the PWM mode,
however, they will be synchronized to the 300kHz switching
clock. The 180° phase shift reduces the noise couplings
between the two channels and reduces the input current ripple.
The HYS mode control can improve converter efficiency with
reduced switching frequency. The efficiency is further
improved by the diode emulation scheme in discontinuous
conduction mode. The diode emulation scheme does not
allow the inductor sink current from the output capacitor,
thereby reducing the circulating energy. It is achieved by
sensing the free-wheeling current going through the
synchronous MOSFET through Phase node voltage polarity
change after the upper MOSFET is turned off. Before the
current reverses direction, the lower MOSFET gate pulses
are terminated.
The PWM-HYS and HYS-PWM switch-over is provided
automatically by the mode control circuit, which constantly
monitors the inductor current through phase voltage polarity,
and alters the way the gate driver pulse signal is generated.
Mode Transition
For a buck regulator, if the load current is higher than critical
value IHYS1, the voltage drop on the synchronous MOSFET
in the free-wheeling period is always negative, and vice
versa. The mode control circuit monitors the phase node
voltage in the off-period. The polarity of this voltage is used
as the criteria for whether the load current is greater than the
critical value, and thus determines whether the converter will
operate in PWM or HYS mode.
To prevent chatter between operating modes, the circuit
looks for eight sequentially matching polarity signals before it
decides to perform a mode change. The algorithm is true for
both CCM-HYS and HYS-CCM transitions.
In the HYS mode, the PWM comparator and the error
amplifier, that provided control in the CCM mode, are put in a
clamped stage and the hysteretic comparator is activated. A
change is also made to the gate logic. The synchronous
MOSFET is controlled in diode emulation fashion, hence the
current in the synchronous MOSFET will be kept in one
direction only. Figures 35 and 36 illustrate the mode change
by counting eight switching cycles.
Page 15 of 27
ISL6227
VOUT
and the input voltage through the VIN pin are used to
determine the error amplifier output voltage and the duty
cycle. The error amplifier stays in an armed state while
waiting for the transition to occur. The transition decision
point is aligned with the PWM clock. When the need for
transition is detected, there is a 500ns delay between the
first/last pulse of the PWM controller from the last/first pulse
of the hysteretic mode controller.
t
IIND
t
PHASE
COMP
t
1 2 3 4 5 6 7 8
MODE
OF
OPERAT ION
PWM
Current Sensing
HYSTERETIC
t
FIGURE 35. CCM—HYSTERETIC TRANSITION
VOUT
t
IIND
1
2 3 4 5
6 7
t
8
PHASE
COMP
MODE
OF
OPERAT ION
t
HYSTERETIC
PWM
t
FIGURE 36. HYSTERETIC—CCM TRANSITION
If load current slowly increases or decreases, mode
transition will occur naturally, as described in Figures 35 and
36; however, if there is an instantaneous load current
increase resulting in a large output voltage drop before the
hysteretic mode controller responds, a comparator with
threshold of 20mV below the reference voltage will be
tripped, and the chip will jump into the forced PWM mode
immediately. The PWM controller will process the load
transient smoothly.
Once the PWM controller is engaged, eight consecutive
switching cycles of negative inductor current are required to
transition back to the hysteretic mode. In this way, chattering
between the two modes is prevented. Current sinking during
the 8 PWM switching cycle dumps energy to input,
smoothing output voltage load step-down.
As a side effect to this design, the comparator may be
triggered consistently if the ESR of the capacitor is so big
that the output ripple voltage exceeds the 20mV window,
resulting in a pure PWM pulse.
The PWM error amplifier is put in clamped voltage during the
hysteretic mode. The output voltage through the VOUT pin
FN9094 Rev 7.00
May 4, 2009
The current on the lower MOSFET is sensed by measuring
its voltage drop within its on-time. In order to activate the
current sampling circuitry, two conditions need to be met.
(1) the Lgate is high and (2) the phase pin sees a negative
voltage for regular buck operation, which means the current
is freewheeling through lower MOSFET. For the second
channel of the DDR application, the phase pin voltage needs
to be higher than 0.1V to activate the current sensing circuit
for bidirectional current sensing. The current sampling
finishes at about 400ns after the lower MOSFET has turned
on. This current information is held for current mode control
and overcurrent protection. The current sensing pin can
source up to 260µA. The current sense resistor and OCSET
resistor can be adjusted simultaneously for the same
overcurrent protection level, however, the current sensing
gain will be changed only according to the current sense
resistor value, which will affect the current feedback loop
gain. The middle point of the Isen current can be at 75µA,
but it can be tuned up and down to fit application needs.
If another channel is switching at the moment the current
sample is finishing, it could cause current sensing error and
phase voltage jitter. In the design stage, the duty cycles and
synchronization have to be analyzed for all the input voltage
and load conditions to reduce the chance of current sensing
error. The relationship between the sampled current and
MOSFET current is given by Equation 5:
I SEN R CS + 140 = r DS ON I D
(EQ. 5)
Which means the current sensing pin will source current to
make the voltage drop on the MOSFET equal to the voltage
generated on the sensing resistor, plus the internal resistor,
along the ISEN pin current flowing path.
Feedback Loop Compensation
Both channel PWM controllers have internally compensated
error amplifiers. To make internal compensation possible
several design measures were taken.
• The ramp signal applied to the PWM comparator has been
made proportional to the input voltage by the VIN pin. This
keeps the product of the modulator gain and the input
voltage constant even when the input voltage varies.
• The load current proportional signal is derived from the
voltage drop across the lower MOSFET during the PWM
off time interval, and is subtracted from the error amplifier
Page 16 of 27
ISL6227
output signal before the PWM comparator input. This
effectively creates an internal current control loop.
TABLE 2. PWM COMPARATOR RAMP VOLTAGE AMPLITUDE
FOR DDR APPLICATION
The resistor connected to the ISEN pin sets the gain in the
current sensing. The following expression estimates the
required value of the current sense resistor, depending on
the maximum continuous load current, and the value of the
MOSFETs rDS(ON), assuming the ISEN pin sources 75µA
current.
Ch1
I MAX r DS ON
R CS = ------------------------------------------ – 140
75A
Ch2
(EQ. 6)
Because the current sensing circuit is a sample-and-hold
type, the information obtained at the last moment of the
sampling is used. This current sensing circuit samples the
inductor current very close to its peak value. The current
feedback essentially injects a resistor Ri in series with the
original LC filter as shown in Figure 37, where the
sample-and-hold effect of the current loop has been ignored.
Vc and Vo are small signal components extracted from its
DC operation points.
Ri
Lo
DCR
+
Co
Gm*Vc
+
-
ESR
Ro
Vo
VRAMP
AMPLITUDE
VIN PIN CONNECTION
Input Voltage
Input voltage >4.2V
Vin/8
Input voltage 4.2V
0.625V
GND
1.25V
The small signal transfer function from the error amplifier
output voltage Vc to the output voltage Vo can be written in
Equation 8:
s
-------- + 1
Ro
Wz
G s = G m --------------------------------------- --------------------------------------------------------R i + DCR + R o s
s
------------- + 1 ------------- + 1
Wp1
Wp2
(EQ. 8)
The DC gain is derived by shorting the inductor and opening
the capacitor. There is one zero and two poles in this transfer
function. The zero is related to ESR and the output
capacitor.
The value of the injected resistor can be estimated by
Equation 7:
The first pole is a low frequency pole associated with the
output capacitor and its charging resistors. The inductor can
be regarded as short. The second pole is the high frequency
pole related to the inductor. At high frequency the output
capacitor can be regarded as a short circuit. By
approximation, the poles and zero are inversely proportional
to the time constants, associated with inductor and capacitor,
by Equations 9, 10 and 11:
V IN r DS ON
R i = ----------------- ---------------------------- 4.4k
V ramp R CS + 140
1
Wz = -----------------------ESR*C o
FIGURE 37. THE EQUIVALENT CIRCUIT OF THE POWER
STAGE WITH CURRENT LOOP INCLUDED
(EQ. 7)
Ri is in k and rDS and RCS are in VIN divided by Vramp,
is defined as Gm, which is a constant 8dB or 18dB for both
channels in dual switcher applications, when VIN is above
3V. Refer to Table 1 for the ramp amplitude in different VIN
pin connections. The feed-forward effect of the VIN is
reflected in Gm. VC is defined as the error amplifier output
voltage.
TABLE 1. PWM COMPARATOR RAMP AMPLITUDE FOR
DUAL SWITCHER APPLICATION
VIN PIN CONNECTIONS
Ch1 and Ch2 Input Voltage
GND
FN9094 Rev 7.00
May 4, 2009
VRAMP
AMPLITUDE
Input voltage >4.2V
VIN/8
Input voltage 4.2V
180° out of phase
1
VIN pin voltage 4.2V
90° phase shift
Page 20 of 27
ISL6227
current of the ISEN pin to meet the overcurrent protection
and the change the current loop gain. The lower the current
sensing resistor, the higher gain of the current loop, which
can damp the output LC filter more.
Application Information
Design Procedures
GENERAL
A ceramic decoupling capacitor should be used between the
VCC and GND pin of the chip. There are three major
currents drawn from the decoupling capacitor:
1. the quiescent current, supporting the internal logic and
normal operation of the IC
2. the gate driver current for the lower MOSFETs
3. and the current going through the external diodes to the
bootstrap capacitor for upper MOSFET.
In order to reduce the noisy effect of the bootstrap capacitor
current to the IC, a small resistor, such as 10, can be used
with the decoupling capacitor to construct a low pass filter for
the IC, as shown in Figure 41. The soft-start capacitor and
the resistor divider setting the output voltage is easy to
select as discussed in the “Block Diagram” on page 13.
TO BOOT
VCC
5V
10
FIGURE 41. INPUT FILTERING FOR THE CHIP
Selection of the Current Sense Resistor
The value of the current sense resistor determines the gain
of the current sensing circuit. It affects the current loop gain
and the overcurrent protection setpoint. The voltage drop on
the lower MOSFET is sensed within 400ns after the upper
MOSFET is turned off. The current sense pin has a 140
resistor in series with the external current sensing resistor.
The current sense pin can source up to a 260µA current
while sensing current on the lower MOSFET, in such a way
that the voltage drop on the current sensing path would be
equal to the voltage on the MOSFET.
A higher value current-sensing resistor will decrease the
current sense gain. If the phase node of the converter is very
noisy due to poor layout, the sensed current will be
contaminated, resulting in duty cycle jittering by the current
loop. In such a case, a bigger current sense resistor can be
used to reduce both real and noise current levels. This can
help damp the phase node wave form jittering.
Sometimes, if the phase node is very noisy, a resistor can be
put on the ISEN pin to ground. This resistor together with the
RCS can divide the phase node voltage down, seen by the
internal current sense amplifier, and reduce noise coupling.
Sizing the Overcurrent Setpoint Resistor
The internal 0.9V reference is buffered to the OCSET pin
with a voltage follower (refer to the equivalent circuit in
Figure 42). The current going through the external
overcurrent set resistor is sensed from the OCSET pin. This
current, divided by 2.9, sets up the overcurrent threshold and
compares with the scaled ISEN pin current going through
RCS with an 8µA offset. Once the sensed current is higher
than the threshold value, an OC signal is generated. The first
OC signal starts a counter and activates a pulse skipping
function. The inductor current will be continuously monitored
through the phase node voltage after the first OC trip. As
long as the sensed current exceeds the OC threshold value,
the following PWM pulse will be skipped. This operation will
be the same for 8 switching cycles. Another OC occurring
between 8 to 16 switching cycles would result in a latch off
with both upper and lower drives low. If there is no OC within
8 to 16 switching cycles, normal operation resumes.
PHASE
_
I SOURCING R CS + 140 = I D r DS ON
(EQ.17)
ID can be assumed to be the inductor peak current. In a
worst case scenario, the high temperature rDS(ON) could
increase to 150% of the room temperature level. During
overload condition, the MOSFET drain current ID could be
130% higher than the normal inductor peak. If the inductor
has 30% peak-to-peak ripple, ID would equal to 115% of the
load current. The design should consider the above factors
so that the maximum ISOURCING will not saturate to 260µA
under worst case conditions. To be safe, ISOURCING should
be less than 100µA in normal operation at room
temperature. The formula in the earlier discussion assumes
a 75µA sourcing current. Users can tune the sourcing
FN9094 Rev 7.00
May 4, 2009
+
ISEN 140
+
RCS
rDS(ON)
+
8µA
+ 8uA
+33.1
OCSET
RSET
+
0.9V
AMPLIFIER REFERENCE
+2.9
ISENSE
+
-
OC
COMPARATOR
FIGURE 42. EQUIVALENT CIRCUIT FOR OC SIGNAL
GENERATOR
Page 21 of 27
ISL6227
Based on the above description and functional block
diagram, the OC set resistor can be calculated as
Equation 18:
10.3V
R set = --------------------------------------------------I OC r DS ON
--------------------------------- + 8A
R CS + 140
(EQ.18)
IOC is the inductor peak current and not the load current.
Since inductor peak current changes with input voltage, it is
better to use an oscilloscope when testing the overcurrent
setting point to monitor the inductor current, and to
determine when the OC occurs. To get consistent test results
on different boards, it is best to keep the MOSFET at a fixed
temperature.
The MOSFET will not heat-up when applying a very low
frequency and short load pulses with an electronic load to
the output.
Output voltage ripple and the transient voltage deviation are
factors that have to be taken into consideration when
selecting an output capacitor. In addition to high frequency
noise related MOSFET turn-on and turn-off, the output
voltage ripple includes the capacitance voltage drop and
ESR voltage drop caused by the AC peak-to-peak current.
These two voltages can be represented by Equations 22
and 23:
I pp
V c = ---------------------8C o F
(EQ.22)
sw
(EQ.23)
V esr = I p – p ESR
As an example, assume the following:
• The maximum normal operation load current is 1
• The inductor peak current is 1.15x to 1.3x higher than the
load current, depending on the inductor value and the
input voltage
• The rDS(ON) has a 45% increase at higher temperature
IOC should set at least 1.8 to 2 times higher than the
maximum load current to avoid nuisance overcurrent trip.
Selection of the LC Filter
The duty cycle of a buck converter is a function of the input
voltage and output voltage. Once an output voltage is fixed,
it can be written as Equation 19:
Vo
D V IN = --------V IN
The inductor copper loss can be significant in the total
system power loss. Attention has to be given to the DCR
selection. Another factor to consider when choosing the
inductor is its saturation characteristics at elevated
temperature. Saturated inductors could result in nuisance
OC, or OV trip.
(EQ.19)
These two components constitute a large portion of the total
output voltage ripple. Several capacitors have to be
paralleled in order to reduce the ESR and the voltage ripple.
If the output of the converter has to support another load
with high pulsating current, more capacitors are needed in
order to reduce the equivalent ESR and suppress the
voltage ripple to a tolerable level.
To support a load transient that is faster than the switching
frequency, more capacitors have to be used to reduce the
voltage excursion during load step change. Another aspect
of the capacitor selection is that the total AC current going
through the capacitors has to be less than the rated RMS
current specified on the capacitors, to prevent the capacitor
from over-heating.
Selection of the Input Capacitor
The switching frequency, Fsw, of ISL6227 is 300kHz. The
peak-to-peak ripple current going through the inductor can
be written as Equation 20:
V o 1 – D V IN
I pp = ----------------------------------------F sw L o
(EQ.20)
lin rms V IN =
As higher ripple current will result in higher switching loss
and higher output voltage ripple, the peak-to-peak current of
the inductor is generally designed with a 20% to 40%
peak-to-peak ripple of the nominal operation current. Based
on this assumption, the inductor value can be selected with
Equation 20. In addition to the mechanical dimension, a
shielded ferrite core inductor with a very low DC resistance,
DCR, is preferred for less core loss and copper loss. The DC
copper loss of the inductor can be estimated by Equation 21:
2
P copper = I load DCR
FN9094 Rev 7.00
May 4, 2009
When the upper MOSFET is on, the current in the output
inductor will be seen by the input capacitor. Even though this
current has a triangular shape top, its RMS value can be
fairly approximated by Equation 24:
(EQ.21)
(EQ.24)
D V IN *I load
This RMS current includes both DC and AC components.
Since the DC component is the product of duty cycle and
load current, the AC component can be approximated by
Equation 25:
li nac V IN =
2
D V IN – D V IN I load
(EQ.25)
AC components will be provided from the input capacitor.
The input capacitor has to be able to handle this ripple
current without overheating and with tolerable voltage ripple.
In addition to the capacitance, a ceramic capacitor is
generally used between the drain terminal of the upper
Page 22 of 27
ISL6227
MOSFET and the source terminal of the lower MOSFET, in
order to clamp the parasitic voltage ringing at the phase
node in switching.
Choosing MOSFETs
For a notebook battery with a maximum voltage of 28V, at
least a minimum 30V MOSFETs should be used. The design
has to trade off the gate charge with the rDS(ON) of the
MOSFET:
• For the lower MOSFET, before it is turned on, the body
diode has been conducting. The lower MOSFET driver will
not charge the miller capacitor of this MOSFET.
• In the turning off process of the lower MOSFET, the load
current will shift to the body diode first. The high dv/dt of
the phase node voltage will charge the miller capacitor
through the lower MOSFET driver sinking current path.
This results in much less switching loss of the lower
MOSFETs.
The upper MOSFET does not have this zero voltage
switching condition, and because it conducts for less time
compared to the lower MOSFET, the switching loss tends to
be dominant. Priority should be given to the MOSFETs with
less gate charge, so that both the gate driver loss, and
switching loss, will be minimized.
For the lower MOSFET, its power loss can be assumed to be
the conduction loss only.
2
(EQ.26)
For the upper MOSFET, its conduction loss can be written as
Equation 27:
2
P uppercond V IN = D V IN I load rDS ON upper
(EQ.27)
and its switching loss can be written as Equation 28:
V IN I vally T on f sw V IN I peak T off f sw
P uppersw V IN = -------------------------------------------- + --------------------------------------------2
2
(EQ.28)
The peak and valley current of the inductor can be obtained
based on the inductor peak-to-peak current and the load
current. The turn-on and turn-off time can be estimated with the
given gate driver parameters in the “Electrical Specifications”
Table on page 3. For example, if the gate driver turn-on path of
MOSFET has a typical on-resistance of 4W, its maximum
turn-on current is 1.2A with 5V VCC. This current would decay
as the gate voltage increased. With the assumption of linear
current decay, the turn-on time of the MOSFETs can be written
with Equation 29:
2Q gd
t on = ----------------I driver
FN9094 Rev 7.00
May 4, 2009
The total power loss of the upper MOSFET is the sum of the
switching loss and the conduction loss. The temperature rise on
the MOSFET can be calculated based on the thermal
impedance given on the datasheet of the MOSFET. If the
temperature rise is too much, a different MOSFET package
size, layout copper size, and other options have to be
considered to keep the MOSFET cool. The temperature rise
can be calculated by Equation 30:
T rise = jaPtotalpower loss
(EQ.30)
The MOSFET gate driver loss can be calculated with the
total gate charge and the driver voltage VCC. The lower
MOSFET only charges the miller capacitor at turn-off.
(EQ.31)
P driver = V cc Q gs F sw
The duty cycle is often very small in high battery voltage
applications, and the lower MOSFET will conduct most of
the switching cycle; therefore, the lower the rDS(ON) of the
lower MOSFET, the less the power loss. The gate charge for
this MOSFET is usually of secondary consideration.
P lower V IN 1 – D V IN I load rDS ON Lower
Qgd is used because when the MOSFET drain-to-source
voltage has fallen to zero, it gets charged. Similarly, the turn-off
time can be estimated based on the gate charge and the gate
drivers sinking current capability.
Based on Equation 31, the system efficiency can be
estimated by the designer.
Confining the Negative Phase Node Voltage Swing
with Schottky Diode
At each switching cycle, the body diode of the lower MOSFET
will conduct before the MOSFET is turned on, as the inductor
current is flowing to the output capacitor. This will result in a
negative voltage on the phase node. The higher the load
current, the lower this negative voltage. This voltage will ring
back less negative when the lower MOSFET is turned on.
A total 400ns period is given to the current sample-and-hold
circuit on the ISEN pin to sense the current going through the
lower MOSFET after the upper MOSFET turns off. An
excessive negative voltage on the lower MOSFET will be
treated as overcurrent. In order to confine this voltage, a
schottky diode can be used in parallel with the lower MOSFET
for high load current applications. PCB layout parasitics should
be minimized in order to reduce the negative ringing of phase
voltage.
The second concern for the phase node voltage going into
negative is that the boot strap capacitor between the BOOT
and PHASE pin could get be charged higher than VCC voltage,
exceeding the 6.5V absolute maximum voltage between BOOT
and PHASE when the phase node voltage became negative. A
resistor can be placed between the cathode of the boot strap
diode and BOOT pin to increase the charging time constant of
the boot cap. This resistor will not affect the turn-on and off of
the upper MOSFET.
Schottky diode can reduce the reverse recovery of the lower
MOSFET when transition from freewheeling to blocking,
therefore, it is generally good practice to have a Schottky
diode closely parallel with the lower MOSFET. B340LA, from
Diodes, Inc.®, can be used as the external Schottky diode.
(EQ.29)
Page 23 of 27
ISL6227
Tuning the Turn-on of Upper MOSFET
The turn-on speed of the upper MOSFET can be adjusted by
the resistor connecting the boot cap to the BOOT pin of the
chip. This resistor can confine the voltage ringing on the boot
capacitor from coupling to the boot pin. This resistor slows
down only the turn-on of the upper MOSFET.
If the upper MOSFET is turned on very fast, it could result in
a very high dv/dt on the phase node, which could couple into
the lower MOSFET gate through the miller capacitor,
causing momentous shoot-through. This phenomenon,
together with the reverse recovery of the body diode of the
lower MOSFET, can over-shoot the phase node voltage to
beyond the voltage rating of the MOSFET. However, a bigger
resistor will slow the turn-on of the MOSFET too much and
lower the efficiency. Trade-offs need to be made in choosing
a suitable resistor value.
System Loop Gain and Stability
The system loop gain is a product of three transfer functions:
1. the transfer function from the output voltage to the
feedback point,
2. the transfer function of the internal compensation circuit
from the feedback point to the error amplifier output voltage,
3. and the transfer function from the error amplifier output to
the converter output voltage.
These transfer functions are written in a closed form in the
“Theory of Operation” on page 14. The external capacitor, in
parallel with the upper resistor of the resistor divider, Cz, can
be used to tune the loop gain and phase margin. Other
component parameters, such as the inductor value, can be
changed for a wider cross-over frequency of the system loop
gain. A body plot of the loop gain transfer function with a 45°
phase margin (a 60° phase margin is better) is desirable to
cover component parameter variations.
Testing the Overvoltage on Buck Converters
For synchronous buck converters, if an active source is used
to raise the output voltage for the overvoltage protection test,
the buck converter will behave like a boost converter and
dump energy from the external source to the input. The
overvoltage test can be done on ISL6227 by connecting the
VSEN pin to an external voltage source or signal generator
through a diode. When the external voltage, or signal
generator voltage, is tuned to a higher level than the
overvoltage threshold (the lower MOSFET will be on), it
indicates the overvoltage protection works. This kind of
overvoltage protection does not require an external schottky
in parallel with the output capacitor.
Layout Considerations
Power and Signal Layer Placement on the PCB
As a general rule, power layers should be close together,
either on the top or bottom of the board, with signal layers on
FN9094 Rev 7.00
May 4, 2009
the opposite side of the board. For example, prospective
layer arrangement on a 4 layer board is shown below:
1. Top Layer: ISL6227 signal lines
2. Signal Ground
3. Power Layers: Power Ground
4. Bottom Layer: Power MOSFET, Inductors and other
Power traces
It is a good engineering practice to separate the power
voltage and current flowing path from the control and logic
level signal path. The controller IC will stay on the signal
layer, which is isolated by the signal ground to the power
signal traces.
Component Placement
The control pins of the two-channel ISL6227 are located
symmetrically on two sides of the IC; it is desirable to
arrange the two channels symmetrically around the IC.
The power MOSFET should be close to the IC so that the
gate drive signal, the LGATEx, UGATEx, PHASEx, BOOTx,
and ISENx traces can be short.
Place the components in such a way that the area under the
ISL6227 has fewer noise traces with high dv/dt and di/dt,
such as gate signals and phase node signals.
Signal Ground and Power Ground Connection
At minimum, a reasonably large area of copper, which will
shield other noise couplings through the IC, could be used
as signal ground beneath the ISL6227. The best tie-point
between the signal ground and the power ground is at the
negative side of the output capacitor on each channel, where
there is less noise. Noisy traces beneath the ISL6227 are
not recommended.
GND and VCC
At least one high quality ceramic decoupling cap should be
used across these two pins. A via can tie Pin 1 to signal
ground. Since Pin 1 and Pin 28 are close together, the
decoupling cap can be put close to the IC.
LGATE1 and LGATE2
These are the gate drive signals for the bottom MOSFETs of
the buck converter. The signal going through these traces
have both high dv/dt and high di/dt, with high peak charging
and discharging current. These two traces should be short,
wide, and away from other traces. There should be no other
weak signal traces in parallel with these traces on any layer.
PGND1 and PGND2
Each pin should be laid out to the negative side of the
relevant output capacitor with separate traces.The negative
side of the output capacitor must be close to the source node
of the bottom MOSFET. These traces are the return path of
LGATE1 and LGATE2.
Page 24 of 27
ISL6227
PHASE1 and PHASE2
PG1 and PG2/REF
These traces should be short, and positioned away from other
weak signal traces. The phase node has a very high dv/dt with
a voltage swing from the input voltage to ground. No trace
should be in parallel with these traces. These traces are also
the return path for UGATE1 and UGATE2. Connect these pins
to the respective converter’s upper MOSFET source.
For dual switcher operations, these two lines are less noise
sensitive. For DDR applications, a capacitor should be
placed to the PG2/REF pin.
Pin 5 and Pin 24, the UGATE1 and UGATE2
VIN
These pins have a square shape waveform with high dv/dt. It
provides the gate drive current to charge and discharge the
top MOSFET with high di/dt. This trace should wide, short,
and away from other traces similar to the LGATEx.
This pin connects to battery voltage, and is less noise sensitive.
BOOT1 and BOOT2
These pins di/dt are as high as that of the UGATEx;
therefore, the traces should be as short as possible.
ISEN1 and ISEN2
The ISEN trace should be a separate trace, and
independently go to the drain terminal of the lower MOSFET.
The current sense resistor should be close to ISEN pin.
The loop formed by the bottom MOSFET, output inductor,
and output capacitor, should be very small. The source of
the bottom MOSFET should tie to the negative side of the
output capacitor in order for the current sense pin to get the
voltage drop on the rDS(ON).
EN1 and EN2
These pins stay high in enable mode and low in idle mode
and are relatively robust. Enable signals should refer to the
signal ground.
VOUT1 and VOUT2
DDR
This pin should connect to VCC in DDR applications, and to
signal ground in dual switcher applications.
Copper Size for the Phase Node
Big coppers on both sides of the Phase node introduce
parasitic capacitance. The capacitance of PHASE should be
kept very low to minimize ringing. If ringing is excessive, it
could easily affect current sample information. It would be
best to limit the size of the PHASE node copper in strict
accordance with the current and thermal management of the
application.
Identify the Power and Signal Ground
The input and output capacitors of the converters, the source
terminals of the bottom switching MOSFET PGND1, and
PGND2, should be closely connected to the power ground.
The other components should connect to signal ground.
Signal and power ground are tied together at the negative
terminal of the output capacitors.
Decoupling Capacitor for Switching MOSFET
It is recommended that ceramic caps be used closely
connected to the drain side of the upper MOSFET, and the
source of the lower MOSFET. This capacitor reduces the
noise and the power loss of the MOSFET. Refer to Figure 43
for the power component placement. IN
.
--
These pins connect either to the output voltage or to the
signal ground. They are signal lines and should be kept
away from noisy lines.
VSEN1 and VSEN2
1
There is usually a resistor divider connecting the output
voltage to this pin. The input impedance of these two pins is
high because they are the input to the amplifiers. The correct
layout should bring the output voltage from the regulation
point to the SEN pin with kelvin traces. Build the resistor
divider close to the pin so that the high impedance trace is
shorter.
2
OCSET1 and OCSET2
In dual switcher mode operation, the overcurrent set resistor
should be put close to this pin. In DDR mode operation, the
voltage divider, which divides the VDQQ voltage in half,
should be put very close to this pin. The other side of the OC
set resistor should connect to signal ground.
-VoV
3
O
+
OUTPUT
CAP
++
VIN
8
7
SI4816DY
6
5
4
+
INDUCTOR
Lo
LO
Lo
FIGURE 43. A GOOD EXAMPLE POWER COMPONENT
REPLACEMENT. IT SHOWS THE NEGATIVE OF INPUT
AND OUTPUT CAPACITOR AND SOURCE OF THE
MOSFET ARE TIED AT ONE POINT.
SOFT1 and SOFT2
The soft-start capacitors should be laid out close to this pin.
The other side of the soft-start cap should tie to signal ground.
FN9094 Rev 7.00
May 4, 2009
Page 25 of 27
ISL6227
Package Outline Drawing
L28.5x5
28 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 2, 10/07
4X 3.0
5.00
24X 0.50
A
B
6
PIN 1
INDEX AREA
6
PIN #1 INDEX AREA
28
22
1
5.00
21
3 .10 ± 0 . 15
15
(4X)
7
0.15
8
14
TOP VIEW
0.10 M C A B
- 0.07
4 28X 0.25 + 0.05
28X 0.55 ± 0.10
BOTTOM VIEW
SEE DETAIL "X"
0.10 C
0 . 90 ± 0.1
C
BASE PLANE
SEATING PLANE
0.08 C
( 4. 65 TYP )
( 24X 0 . 50)
(
SIDE VIEW
3. 10)
(28X 0 . 25 )
C
0 . 2 REF
5
0 . 00 MIN.
0 . 05 MAX.
( 28X 0 . 75)
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
FN9094 Rev 7.00
May 4, 2009
Page 26 of 27
ISL6227
ISL6227
Shrink Small Outline Plastic Packages (SSOP)
Quarter Size Outline Plastic Packages (QSOP)
M28.15
N
INDEX
AREA
H
0.25(0.010) M
E
2
SYMBOL
3
0.25
0.010
SEATING PLANE
-A-
INCHES
GAUGE
PLANE
-B1
28 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE
(0.150” WIDE BODY)
B M
A
D
h x 45°
-C-
e
0.17(0.007) M
A2
A1
B
L
C
0.10(0.004)
C A M
B S
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2
of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
MIN
MAX
MILLIMETERS
MIN
MAX
NOTES
A
0.053
0.069
1.35
1.75
-
A1
0.004
0.010
0.10
0.25
-
A2
-
0.061
-
1.54
-
B
0.008
0.012
0.20
0.30
9
C
0.007
0.010
0.18
0.25
-
D
0.386
0.394
9.81
10.00
3
E
0.150
0.157
3.81
3.98
4
e
0.025 BSC
0.635 BSC
-
H
0.228
0.244
5.80
6.19
-
h
0.0099
0.0196
0.26
0.49
5
L
0.016
0.050
0.41
1.27
6
N
28
0°
28
8°
0°
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
7
8°
Rev. 1 6/04
4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch)
per side.
5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “B” does not include dambar protrusion. Allowable dambar protrusion shall be 0.10mm (0.004 inch) total in excess of “B”
dimension at maximum material condition.
10. Controlling dimension: INCHES. Converted millimeter dimensions
are not necessarily exact.
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Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
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Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
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FN9094 Rev 7.00
May 4, 2009
Page 27 of 27
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