DATASHEET
OBSOLETE PRODUCT
NO RECOMMENDED REPLACEMENT
ISL6260C
FN9259
Rev 3.00
June 21, 2010
Multiphase PWM Regulator for IMVP-6+ Mobile CPUs
The ISL6260C is a multiple phase PWM buck regulator for
miroprocessor core power supply. The multiple phase
implementation results in better system performance, superior
thermal management, lower component cost, reduced power
dissipation, and smaller implementation area. The ISL6260C
multiphase controller together with ISL6208 external gate
drivers provide a complete solution to power Intel's mobile
microprocessors. The PWM modulator of ISL6260C is based
on Intersil's Robust Ripple Regulator technology (R3).
Compared with the traditional multiphase buck regulator, the R3
modulator commands variable switching frequency during load
transients, which achieves faster transient response. With the
same modulator, the switching frequency is reduced at light
load conditions resulting higher operation efficiency.
Intel Mobile Voltage Positioning (IMVP) reduces power
dissipation for Intel Pentium processors. The ISL6260C is
designed to be completely compliant with IMVP-6+
specifications. ISL6260C responds to PSI# signal by adding or
dropping PWM2 and adjusting overcurrent protection
accordingly. To reduce audible noise, the DPRSLPVR signal
can be used to reduce output voltage slew rates when entering
and exiting Deeper Sleep State according to Intel specification.
The ISL6260C has several other key features. ISL6260C
reports output power through a power monitor pin. Current
sense can be achieved by using either inductor DCR or
discrete precision resistor. In the case of DCR current
sensing, a single NTC thermistor is used to thermally
compensate the inductor DCR variation with temperature. A
unity gain, differential amplifier is available for remote
voltage sensing. This allows the voltage on the CPU die to
be accurately regulated to meet Intel IMVP-6+
specifications.
Features
• Precision Multiphase Core Voltage Regulation
- 0.5% System Accuracy Over Temperature
- Enhanced Load Line Accuracy
• Microprocessor Voltage Identification Input
- 7-Bit VID Input
- 0.300V to 1.500V in 12.5mV Steps
- Supports VID Changes On-The-Fly
• Multiple Current Sensing Approaches Supported
- Lossless DCR Current Sensing
- Precision Resistive Current Sensing
• Supports PSI# and Narrow VDC for Enhanced Battery Life
(EBL) Initiatives
• Superior Noise Immunity and Transient Response
• Power Monitor and Thermal Monitor
• Differential Remote Voltage Sensing
• High Efficiency Across Entire Load Range
• Programmable 1, 2 or 3 Power Channels
• Excellent Dynamic Current Balance between Channels
• Small Footprint 40 Ld 6x6 QFN Package
• IMVP-6+ Compliant
• Pb-Free (RoHS Compliant)
Applications
• Mobile Laptop Computers
Ordering Information
PART NUMBER
(Note)
PART MARKING
TEMP. RANGE
(°C)
PACKAGE
(Pb-Free)
PKG.
DWG. #
ISL6260CCRZ
ISL6260 CCRZ
-10 to +100
40 Ld 6x6 QFN
L40.6x6
ISL6260CCRZ-T*
ISL6260 CCRZ
-10 to +100
40 Ld 6x6 QFN Tape and Reel
L40.6x6
ISL6260CIRZ
ISL6260 CIRZ
-40 to +100
40 Ld 6x6 QFN
L40.6x6
ISL6260CIRZ-T*
ISL6260 CIRZ
-40 to +100
40 Ld 6x6 QFN Tape and Reel
L40.6x6
*Please refer to TB347 for details on reel specifications.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
FN9259 Rev 3.00
June 21, 2010
Page 1 of 29
ISL6260C
Pinout
OCSET
ISL6260C
(40 LD QFN)
TOP VIEW
PGOOD
3V3
CLK_EN#
DPRSTP#
DPRSLPVR
VR_ON
VID6
VID5
VID4
VID3
Overcurrent set input. A resistor from this pin to VO sets
DROOP voltage limit for OC trip. A 10µA current source is
connected internally to this pin.
40
39
38
37
36
35
34
33
32
31
VW
A resistor from this pin to COMP programs the switching
frequency. (7k gives approximately 300kHz). VW pin
sources current.
PSI# 1
30 VID2
PMON 2
29 VID1
RBIAS 3
28 VID0
VR_TT# 4
27 PWM1
NTC 5
26 PWM2
GND PAD
(BOTTOM)
SOFT 6
25 PWM3
COMP
This pin is the output of the error amplifier.
FB
This pin is the inverting input of error amplifier.
VDIFF
This pin is the output of the differential amplifier.
11
12
13
14
15
16
17
18
19
20
VDD
RTN
VSS
21 ISEN3
VIN
FB 10
VSUM
Remote core voltage sense input. Connect to
microprocessor die.
VO
22 ISEN2
DFB
COMP 9
DROOP
23 ISEN1
RTN
VW 8
VSEN
24 FCCM
VDIFF
OCSET 7
Functional Pin Description
VSEN
Remote voltage sensing return. Connect to ground at
microprocessor die.
DROOP
Output of droop amplifier. Output = VO + DROOP.
DFB
PSI#
Inverting input to droop amplifier.
Low load current indicator input. When asserted low,
indicates a reduced load-current condition. For ISL6260C,
when PSI# is asserted low, PWM2 will be disabled.
VO
PMON
An analog output. PMON sends out an analog signal
proportional to the product of VCCSENSE voltage and the
droop voltage.
An input to the IC that reports the local output voltage.
VSUM
This pin is connected to the current summation junction.
VIN
Battery supply voltage, used for feed forward.
RBIAS
VSS
147k Resistor to VSS sets internal current reference.
Signal ground; Connect to local controller ground.
VR_TT#
VDD
Thermal overload output indicator.
5V bias power.
NTC
ISEN3
Thermistor input to VR_TT# circuit.
Individual current sensing for channel 3.
SOFT
ISEN2
A capacitor from this pin to Vss sets the maximum slew rate
of the output voltage. It affects both soft start and VID
transitioning slew rate. Soft pin is the non-inverting input of
the error amplifier.
Individual current sensing for channel 2.
ISEN1
Individual current sensing for channel 1.
FCCM
Forced Continuous Conduction Mode (FCCM) enable pin to
MOSFET drivers. It will disable diode emulation.
FN9259 Rev 3.00
June 21, 2010
Page 2 of 29
ISL6260C
PWM3
VR_ON
PWM output for channel 3. When PWM3 is pulled to 5V
VDD, PWM3 will be disabled and allow other channels to
operate.
Voltage Regulator enable input. A high level logic signal on
this pin enables the regulator.
PWM2
PWM output for channel 1.
Deeper Sleep Enable signal. At steady state, a high level
logic signal on this pin indicates that the micro-processor is
in Deeper Sleep Mode. Between active and sleep mode
transition, high logic level on this pin programs slow C4 entry
and exit; low logic level on this pin programs large charging
or discharging soft pin current, and therefore fast output
voltage transition slew rate.
VID0, VID1, VID2, VID3, VID4, VID5, VID6
DPRSTP#
VID input with VID0 = LSB and VID6 = MSB.
Deeper Sleep Enable signal. A low level logic signal on this
pin indicates that the micro-processor is in Deeper Sleep
Mode.
PWM output for channel 2. For ISL6260C, PSI# low will
make this output tri-state. When PWM2 is pulled to 5V VDD,
PWM2 will be disabled and allow other channels to operate.
PWM1
CLK_EN#
Digital output to enable System PLL Clock; Goes active after
13 switching cycles after Vcore is within 10% of Boot
Voltage.
DPRSLPVR
PGOOD
Power Good open-drain output. Will be pulled up externally
by a 680 resistor to VCCP or 1.9k to 3.3V.
3V3
3.3V supply voltage for CLK_EN# logic, such an
implementation will improve power consumption from 3.3V
compared to open drain circuit other wise.
FN9259 Rev 3.00
June 21, 2010
Page 3 of 29
ISL6260C
Absolute Maximum Ratings
Thermal Information
Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +7V
Battery Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +25V
Open Drain Outputs, PGOOD, VR_TT# . . . . . . . . . . . . -0.3 to +7V
All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to (VDD + 0.3V)
Thermal Resistance (Notes 1, 2)
JA (°C/W) JC (°C/W)
QFN Package. . . . . . . . . . . . . . . . . . . .
30
5.5
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +100°C
Supply Voltage Range (Typical). . . . . . . . . . . . . . . . . . . . . +5V ±5%
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
2. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
Operating Conditions: VDD = 5V, TA = -40°C to +100°C, unless otherwise noted. Parameters with MIN and/or
MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by
characterization and are not production tested.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
3.6
INPUT POWER SUPPLY
+5V Supply Current
IVDD
4.2
mA
VR_ON = 0V
1
µA
I3V3
No load on CLK_EN#
1
µA
Battery Supply Current
IVIN
VR_ON = 0V
VIN Input Resistance
RVIN
VR_ON = 3.3V
Power-On-Reset Threshold
PORr
VDD rising
PORf
VDD falling
3.95
4.15
V
VDD falling, TA = -10°C to +100°C
4.00
4.15
V
No load; closed loop, active mode range
VID = 0.75V - 1.50V
-0.8
+0.8
%
No load; closed loop, active mode range
VID = 0.75V - 1.50V, TA = -10°C to +100°C
-0.5
+0.5
%
VID = 0.5V - 0.7375V
-10
+10
mV
VID = 0.5V - 0.7375V, TA = -10°C to +100°C
-8
+8
mV
VID = 0.3 - 0.4875V
-18
+18
mV
VID = 0.3 - 0.4875V, TA = -10°C to +100°C
-15
+15
mV
1.224
V
+3.3V Supply Current
VR_ON = 3.3V
1
900
4.35
µA
k
4.5
V
SYSTEM AND REFERENCES
System Accuracy
%Error
(VCC_CORE)
VBOOT
1.176
1.200
Maximum Output Voltage
VCC_CORE(max) VID = [0000000]
1.500
V
Minimum Output Voltage
VCC_CORE(min) VID = [1100000]
0.300
V
0.0
V
VID Off State
VID = [1111111]
RBIAS Voltage
RBIAS = 147k
1.45
1.47
Rfset = 7k, 3 channel operation, VCOMP = 2V
285
300
See Equation 4 RFSET selection
200
1.49
V
CHANNEL FREQUENCY
Nominal Channel Frequency
fSW(nom)
Adjustment Range
315
kHz
500
kHz
+0.3
mV
AMPLIFIERS
Droop Amplifier Offset
Error Amp DC Gain
Error Amp Gain-Bandwidth Product
FN9259 Rev 3.00
June 21, 2010
-0.3
Av0
GBW
(Note 3)
90
dB
CL= 20pF (Note 3)
18
MHz
Page 4 of 29
ISL6260C
Electrical Specifications
Operating Conditions: VDD = 5V, TA = -40°C to +100°C, unless otherwise noted. Parameters with MIN and/or
MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by
characterization and are not production tested. (Continued)
PARAMETER
FB Input Current
SYMBOL
TEST CONDITIONS
MIN
IIN(FB)
TYP
MAX
UNITS
10
150
nA
2
mV
ISEN
Imbalance Voltage
Maximum of ISENs - Minimum of ISENs
Input Bias Current
20
nA
SOFT CURRENT
Soft-start Current
ISS
SOFT Geyserville Current
IGV
|SOFT-VDAC| >100mV
SOFT Deeper Sleep Entry Current
-47
-42
-37
µA
180
205
230
µA
IC4
DPRSLPVR = 3.3V
-47
-42
-37
µA
SOFT Deeper Sleep Exit Current
IC4EA
DPRSLPVR = 3.3V
37
42
47
µA
SOFT Deeper Sleep Exit Current
IC4EB
DPRSLPVR = 0V
180
205
230
µA
0.26
0.4
V
POWER GOOD AND PROTECTION MONITORS
PGOOD Low Voltage
VOL
IPGOOD= 4mA
PGOOD Leakage Current
IOH
PGOOD = 3.3V
-1
1
µA
PGOOD Delay
tpgd
CLK_ENABLE# LOW to PGOOD HIGH
6.3
7.6
8.9
ms
Overvoltage Threshold
OVH
VO rising above setpoint for >1ms
160
200
240
mV
Severe Overvoltage Threshold
OVHS
1.675
1.7
1.725
V
OCSET Reference Current
I(RBIAS) = 10µA
9.8
10
10.2
µA
OC Threshold Offset
DROOP rising above OCSET for >150µs
-2
4
mV
-235
mV
1.0
V
Current Imbalance Threshold
Undervoltage Threshold
(VDIFF/SOFT)
VO rising for >2µs
One ISEN above another ISEN for >1.2ms
UVf
VO falling below setpoint for >1.2ms
9
-355
-295
mV
LOGIC THRESHOLDS
VR_ON and DPRSLPVR Input Low
VIL(3.3V)
VR_ON and DPRSLPVR Input High
VIH(3.3V)
VID0-VID6, PSI#, DPRSTP# Input
Low
VIL(1.0V)
VID0-VID6, PSI#, DPRSTP# Input
High
VIH(1.0V)
2.3
V
0.3
0.7
V
V
PWM
PWM (PWM1-PWM3) Output Low
VOL(5.0V)
Sinking 5mA
FCCM Output Low
VOL_FCCM
Sinking 3mA
PWM (PWM1-PWM3) and FCCM
Output High
VOH(5.0V)
Sourcing 5mA
3.5
PWM = 2.5V
-1
PWM Tri-State Leakage
1.0
1.0
V
V
V
1
µA
THERMAL MONITOR
NTC Source Current
NTC = 1.3V
Over-Temperature Threshold
V (NTC) falling
VR_TT# Low Output Resistance
RTT
I = 20mA
CLK_EN# High Output Voltage
VOH
3V3 = 3.3V, I = -4mA
CLK_EN# Low Output Voltage
VOL
I = 4mA
53
60
67
µA
1.18
1.2
1.22
V
6.5
9
CLK_EN# OUTPUT LEVELS
2.9
3.1
V
0.26
0.4
V
POWER MONITOR
PMON Output Voltage
FN9259 Rev 3.00
June 21, 2010
Vpmon
VSEN = 1.2V, Droop-Vo = 80mV
1.638
1.68
1.722
V
VSEN = 1.0V, Droop-Vo = 20mV
0.308
0.35
0.392
V
Page 5 of 29
ISL6260C
Electrical Specifications
Operating Conditions: VDD = 5V, TA = -40°C to +100°C, unless otherwise noted. Parameters with MIN and/or
MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by
characterization and are not production tested. (Continued)
PARAMETER
PMON Maximum Voltage
PMON Sourcing Current
SYMBOL
TEST CONDITIONS
Vpmonmax
VSEN = 1.0V, Droop-Vo = 50mV
PMON Sinking Current
VSEN = 1.0V, Droop-Vo = 50mV
Maximum Current Sinking Capability
See Figure 36
PMON Impedance
When PMON is within its sourcing/sinking
current range (Note 3)
MIN
TYP
2.8
3
MAX
V
2.0
mA
2.0
Vpmon/
250
UNITS
mA
Vpmon/
180
7
Vpmon/
130
A
3. Limits established by characterization and are not production tested.
FN9259 Rev 3.00
June 21, 2010
Page 6 of 29
ISL6260C
Typical Operating Performance 3 Phase, DCR Sense, (1) 7821, (2) 7832 per phase, 300kHz, 0.5µH
100
1.46
VIN = 8.0V
1.44
VIN = 19.0V
1.42
80
VIN = 12.6V
VOUT (V)
EFFICIENCY (%)
90
VIN = 19.0V
70
1.40
VIN = 8.0V
VIN = 12.6V
1.38
1.36
60
1.34
50
1
1.32
0
100
10
10
20
IOUT (A)
100
1.43
90
1.42
80
VOUT (V)
EFFICIENCY (%)
50
1.44
VIN = 8.0V
VIN = 19.0V
VIN = 12.6V
40
FIGURE 2. ACTIVE MODE LOAD LINE, 3 PHASE, CCM,
PSI# = HIGH VID = 1.435V
FIGURE 1. ACTIVE MODE EFFICIENCY, 3 PHASE, CCM,
PSI# = HIGH, VID = 1.4375V
70
30
IOUT (A)
VIN = 12.6V
1.41
1.40
VIN = 8.0V
VIN = 19.0V
1.39
1.38
60
1.37
50
0.1
1.0
IOUT (A)
FIGURE 3. DEEPER SLEEP MODE EFFICIENCY, 3 PHASE,
DCM OPERATION, PSI# = LOW, VID = 1.4375V
100
VIN = 8.0V
1.36
10
0.76
VIN = 12.6V
70
0.73
0.72
0.71
VIN = 19.0V
0.69
10
FIGURE 5. DEEPER SLEEP MODE EFFICIENCY, 3 PHASE,
DCM OPERATION, PSI# = LOW, VID = 0.75V
FN9259 Rev 3.00
June 21, 2010
30
0.70
VIN = 19.0V
1.0
IOUT (A)
20
VIN = 8.0V
0.74
80
50
0.1
IOUT (A)
VIN = 12.6V
0.75
VOUT (V)
EFFICIENCY (%)
10
FIGURE 4. DEEPER SLEEP MODE LOAD LINE, 3 PHASE,
CCM, PSI# = LOW VID = 1.435V
90
60
0
0.68
0
20
10
IOUT (A)
FIGURE 6. DEEPER SLEEP MODE LOAD LINE, 3 PHASE,
DCM OPERATION, PSI# = LOW, VID = 0.75V
Page 7 of 29
30
ISL6260C
Typical Operating Performance 3 Phase, DCR Sense, (1) 7821, (2) 7832 per phase, 300kHz, 0.5µH (Continued)
100
100
VIN = 8.0V
90
EFFICIENCY (%)
EFFICIENCY (%)
90
80
VIN = 19.0V
VIN = 12.6V
70
60
50
0
10
IOUT (A)
70
VIN = 19.0V
50
0.1
100
1.0
IOUT (A)
10
FIGURE 8. DEEPER SLEEP MODE EFFICIENCY, 2 PHASE,
DCM OPERATION, PSI# = LOW, VID = 1.4375V
1.44
100
90
VIN = 12.6V
VIN = 8.0V
VIN = 12.6V
1.42
1.40
80
70
VOUT (V)
EFFICIENCY (%)
VIN = 12.6V
60
FIGURE 7. ACTIVE MODE EFFICIENCY, 2 PHASE, CCM,
PSI# = HIGH, VID = 1.4375V
VIN = 19.0V
VIN = 8.0V
1.38
1.36
60
1.34
50
0.1
1.0
IOUT (A)
1.32
10
VIN = 19.0V
0
20
10
40
30
50
IOUT (A)
FIGURE 9. DEEPER SLEEP MODE EFFICIENCY, 2 PHASE,
DCM OPERATION, PSI# = LOW, VID = 0.75V
FIGURE 10. ACTIVE MODE LOAD LINE, 2 PHASE, CCM,
PSI# = HIGH, VID = 1.435V
0.76
1.44
VIN = 12.6V
1.43
0.75
VIN = 8.0V
1.42
1.41
1.40
1.39
VIN = 19.0V
1.38
VIN = 12.6V
0.74
VOUT (V)
VOUT (V)
VIN = 8.0V
80
VIN = 8.0V
0.73
0.72
0.71
0.70
VIN = 19.0V
0.69
1.37
0.68
1.36
0
10
20
30
IOUT (A)
FIGURE 11. DEEPER SLEEP MODE LOAD LINE, 2 PHASE,
DCM OPERATION, PSI# = LOW, VID = 1.4375V
FN9259 Rev 3.00
June 21, 2010
0
10
20
30
IOUT (A)
FIGURE 12. DEEPER SLEEP MODE LOAD LINE, 2 PHASE, DCM
OPERATION, PSI# = LOW, VID = 0.75V
Page 8 of 29
ISL6260C
Typical Operating Performance
VSOFT (Green)
VOUT
VOUT (Brown)
PGOOD
CLK_EN#
VR_ON
FIGURE 13. SOFT-START WAVEFORM 0V TO 1.2V (BOOT
VOLTAGE) AND CLK_EN# TIMING
VIN
VR_ON
FIGURE 14. SOFT-START WAVEFORM SHOWING PGOOD
VOUT
VOUT
FIGURE 15. 12V-18V INPUT LINE TRANSIENT RESPONSE
FIGURE 16. SOFT-START INRUSH CURRENT, VIN = 8V
FIGURE 17. 3 PHASE CURRENT BALANCE, FULL LOAD = 50A
FIGURE 18. 2 PHASE CURRENT BALANCE, FULL LOAD = 50A
FN9259 Rev 3.00
June 21, 2010
Page 9 of 29
ISL6260C
Typical Operating Performance (Continued)
VOUT
COMP PIN
FIGURE 19. TRANSIENT LOAD RESPONSE, 40A LOAD STEP
@ 200A/µs, 3 PHASE
FIGURE 20. TRANSIENT LOAD 3 PHASE OPERATION CURRENT BALANCE
FIGURE 21. TRANSIENT LOAD 3 PHASE OPERATION, ZOOM
OF RISING EDGE CURRENT BALANCE
FIGURE 22. TRANSIENT LOAD 3 PHASE OPERATION, ZOOM
OF FALLING EDGE CURRENT BALANCE
VID MSB
VID MSB
VOUT
FIGURE 23. IVID MSB BIT CHANGE FROM 1.4375V TO 0.65V
SHOWING 9mV/µs SLEW RATE, DPRSLPVR = 0,
DPRSTP# = 1
FN9259 Rev 3.00
June 21, 2010
VOUT
FIGURE 24. SLEW RATE ENTERING C4, VID MSB BIT
CHANGE FROM 1.4375V TO 0.65V SHOWING
2mV/µs SLEW RATE, DPRSLPVR = 1, DPRSTP# = 0
Page 10 of 29
ISL6260C
Typical Operating Performance (Continued)
VOUT
VOUT @ 1.7V
PWM
DPRSTP# AND PSI#
VOUT @ 0.85V
DPRSLPVR AND MSB
FIGURE 25. C4 ENTRY AND EXIT SLEW RATES WITH
DPRSLPVR AND DPRSTP#
FIGURE 26. 1.7V OVP SHOWING OUTPUT PULLED LOW TO
0.85V AND PWM TRI_STATE
PWM
PWM
VOUT
IPHASE
PGOOD
VOUT
FIGURE 27. UNDERVOLTAGE RESPONSE SHOWING PWM
TRI-STATE, VOUT < VID - 300mV
PGOOD
FIGURE 28. OCP - RESPONSE
PWM
PSI#
CLK_EN#
IPHASE
VOUT
VOUT
PGOOD
FIGURE 29. WOCP - SHORT CIRCUIT PROTECTION
FN9259 Rev 3.00
June 21, 2010
PHASE 2
FIGURE 30. ISL6260C, PHASE ADDING AND DROPPING IN
ACTIVE MODE, LOAD CURRENT = 15A
Page 11 of 29
ISL6260C
Typical Operating Performance (Continued)
PHASE 3 CURRENT
PSI#
CLK_EN#
PHASE 1 CURRENT
VOUT
PHASE 2
CURRENT
PHASE 2
PHASE 2
FIGURE 31. ISL6260C PHASE ADDING AND DROPPING IN
DEEPER SLEEP MODE, LOAD CURRENT = 4.35A
FIGURE 32. ISL6260C, INDUCTOR CURRENT WAVEFORM
WITH PHASE ADDING AND DROPPING IN DCM
OR DEEPER SLEEP MODE
PHASE 3
CURRENT
PHASE 1 CURRENT
PHASE 2 CURRENT
PHASE 1 CURRENT
PGOOD
PHASE 2 CURRENT
FIGURE 33. ISL6260C, INDUCTOR CURRENT WAVEFORM
WITH PHASE ADDING AND DROPPING IN CCM
OR ACTIVE MODE
FIGURE 34. ISL6260C, OVERCURRENT DUE TO PHASE
DROPPING
1.8
PMON (V)
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
0.0
0.8
19V, 1.15V, 40A
VID = 1.15V, IOUT = 15A
0.7
7
0.6
PMON (V)
1.6
19V, 1.15V, 30A
19V, 1.15V, 20A
0.5
VID = 1.15V, IOUT = 10A
0.4
180
0.3
VID = 1.15V, IOUT = 5A
0.2
19V, 1.15V, 10A
0.1
19V, 1.15V, 5A
1.0
2.0
3.0
4.0
5.0
6.0
CURRENT SOURCING (mA)
7.0
FIGURE 35. POWER MONITOR CURRENT SOURCING
CAPABILITY
FN9259 Rev 3.00
June 21, 2010
0.00
0.0
VID = 1.15V, IOUT = 2.5A
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
CURRENT SINKING (mA)
FIGURE 36. POWER MONITOR CURRENT SINKING
CAPABILITY
Page 12 of 29
ISL6260C
Typical Operating Performance (Continued)
25%
60.0
VIN = 19V
POWER (W)
15%
10%
5%
0%
0.0
50.0
VID = 1.15V
20%
40.0
PMON
30.0
20.0
MEASURED OUTPUT POWER
10.0
10.0
20.0
30.0
40.0
50.0
OUTPUT CURRENT (A)
FIGURE 37. POWER MONITOR ACCURACY
FN9259 Rev 3.00
June 21, 2010
0.0
0.0
10.0
20.0
30.0
40.0
50.0
CURRENT (A)
FIGURE 38. POWER MONITOR vs OUTPUT CURRENT
Page 13 of 29
ISL6260C
Simplified Application Circuit for DCR Current Sensing
the regulator to operate in Diode Emulation for improved
light load efficiency. As shown in the circuit diagram, the
FCCM pin is connected to ISL6260C, which programs the
CCM or DCM mode.
Figure 39 shows a simplified application circuit for the
ISL6260C converter with inductor DCR current sensing. The
ISL6208 MOSFET gate driver has a force-continuousconduction-mode (FCCM) input, that when disabled, allows
V+5 VIN V+3.3
VIN
VDD
VIN
3V3
V+5
RBIAS
VCC
NTC
VR_TT#
PWM1
PWM
ISEN1
VR_TT#
BOOT
LO
UGATE
ISL6208
PHASE
SOFT
7
VID
VIDs
DPRSTP#
RL CL
FCCM
LGATE
GND
ISEN1
DPRSTP#
ISL6260C
DPRSLPVR
DPRSLPVR
PSI#
VIN
PSI#
CLK_ENABLE#
VCC
PWM
PWM2
CLK_EN#
ISEN2
VR_ON
VR_ON
IMVP-6+_PWRGD
VO
V+5
PMON
PWR MONITOR
CO
BOOT
LO
UGATE
ISL6208
PHASE
PGOOD
RL CL
FCCM
LGATE
GND
VSEN
REMOTE SENSE
AT CPU CORE
VO'
VSUM
ISEN2
RTN
Ri
VSUM
FCCM
C3
R3
V+5
VCC
FB
C1
VO'
VIN
VDIFF
BOOT
R1
PWM
PWM3
ISEN3
COMP
C2
LO
UGATE
ISL6208
RFSET
VSUM
VSUM
VW
PHASE
FCCM
LGATE
GND
OCSET
GND
DFB
DROOP
VO
RL CL
ISEN3
VSUM
RN
VO'
CCS
VO'
FIGURE 39. TYPICAL APPLICATION CIRCUIT FOR DCR SENSING
FN9259 Rev 3.00
June 21, 2010
Page 14 of 29
ISL6260C
Simplified Application Circuit for Resistive Current Sensing
stability margin of the channel current balance loop. No NTC
thermistor is needed and the droop circuit is simplified.
Figure 40 shows a simplified application circuit for the
ISL6260C converter with external resistor current sensing. A
capacitor is added in parallel with RL in order to improve the
V+5 V+3.3
VIN
VIN
VDD
3V3
VIN
V+5
RBIAS
VCC
NTC
PWM1
ISEN1
VR_TT#
VR_TT#
PWM
BOOT
LO
UGATE
RSEN
ISL6208
SOFT
7
VID
PHASE
VIDs
VSUM
FCCM
LGATE
GND
DPRSTP#
CL
VO'
ISL6260C
DPRSLPVR
VIN
PSI#
PWR MONITOR
VCC
PWM
PWM2
CLK_EN#
ISEN2
VR_ON
VR_ON
IMVP-6+_PWRGD
VO
V+5
PMON
CLK_ENABLE#
CO
BOOT
LO
UGATE
RSEN
ISL6208
PHASE
PGOOD
VSUM
FCCM
LGATE
GND
VSEN
REMOTE SENSE
AT CPU CORE
ISEN2
RTN
FCCM
C1
R1
CL
VIN
VDIFF
R3
RL
VO'
Ri
C3
RL
ISEN1
V+5
VCC
FB
BOOT
PWM3
PWM
ISEN3
COMP
C2
UGATE
LO
RSEN
ISL6208
RFSET
PHASE
VW
VSUM
VSUM
FCCM
LGATE
GND
OCSET
GND
DFB DROOP
VSUM
ISEN3
RL
CL
VO
VO'
VO'
FIGURE 40. TYPICAL APPLICATION CIRCUIT FOR DISCRETE RESISTOR CURRENT SENSING
FN9259 Rev 3.00
June 21, 2010
Page 15 of 29
RBIAS
PMON
3V3 CLK_EN# VIN
PGOOD
VO
ISEN1 ISEN2 ISEN3
ISL6260C
FN9259 Rev 3.00
June 21, 2010
Functional Block Diagram
VDD
VIN
VID0
POWER
VID1
PROTECTION
VID2
54µA
6µA
CURRENT
BALANCE
LOGIC
MONITOR
DAC
VID3
Dacout
VID4
IBAL
-
VID6
MODE
CONTROL
FCCM
+
NTC
FLT
OC
VDIFF
VID5
FAST_OC OR
WAY-OC
1.20V
OC
MULTIPLIER
VO
VIN
VO
1.24V
VR_TT#
+
2X
VR_ON
FLT
MODULATOR
MODE
PSI#
IBAL
CLK_EN#
GOOD
SOFT
CONTROL
PWM1
DPRSLPVR
VO VSEN
OC
DPRSTP#
VIN
VO
NUMBER OF
PHASES
10µA
GAIN SELECT)
OCSET
FLT
MODULATOR
-
PWM2
OC
+
VSUM
DFB
OC
+
DROOP
-
DROOP
+
1
-
FLT
PWM3
E/A
+
NUMBER OF PHASES
+
1
-
+
CHANNEL
CLOCK
MODE
CONTROL
Page 16 of 29
VIN
VO VSEN RTN
VO
MODULATOR
+
VO
VSEN
VIN
VDIFF
SOFT FB
COMP
VO
VW
FIGURE 41. SIMPLIFIED BLOCK DIAGRAM
GND
SELECT
ISL6260C
Theory of Operation
Operational Description
The ISL6260C is a multiphase regulators implementing
Intel® IMVP-6+ protocol. It can be programmed for one-,
two- or three-channel operation for microprocessor core
applications up to 70A. With ISL6208 gate driver capable of
diode emulation, the ISL6260C provides optimum efficiency
in both heavy and light conditions.
ISL6260C uses Intersil patented R3 (Robust Ripple
Regulator™) modulator. The R3 modulator combines the
best features of fixed frequency PWM and hysteretic PWM
while eliminating many of their shortcomings. The ISL6260C
modulator internally synthesizes analog signals inside the IC
emulating the inductor ripple currents and use hysteretic
comparators on those signals to determine switching pulse
widths. Operating on these large-amplitude, noise-free
synthesized signals allows the ISL6260C to achieve lower
output ripple and lower phase jitter than conventional
hysteretic and fixed PWM mode controllers. Unlike
conventional hysteretic converters, the ISL6260C has an
error amplifier that allows the controller to maintain a 0.5%
output voltage accuracy. At heavy load conditions, the
ISL6260 is switching at a relatively constant switching
frequency similar to fixed frequency PWM controller. At light
load conditions, the ISL6260C is switching at a frequency
proportional to load current similar to hysteretic mode
controller.
ISL6260C disables PWM2 when PSI# is asserted low. And
the power monitor pin provides an analog signal
representing the output power of the converter.
VDD
10mV/µs
2mV/µs
VR_ON
120µs
VBOOT
90%
VID COMMANDED
VOLTAGE
SOFT & VO
13 SWITCHING CYCLES
CLK_EN#
~7ms
IMVP-6+ PGOOD
FIGURE 42. SOFT-START WAVEFORMS USING A 20nF SOFT
CAPACITOR
Static Operation
A) Voltage Regulation at Zero Load Current
After the start sequence, the output voltage will be regulated
to the value set by the VID inputs per Table 1. The entire VID
Table is presented in the Intel IMVP-6+™ specification. The
ISL6260C will control the no-load output voltage to an
accuracy of ±0.5% over the range of 0.75V to 1.5V.
TABLE 1. TRUNCATED VID TABLE FOR INTEL IMVP-6+™
SPECIFICATION
VID6
VID5
VID4
VID3
VID2
VID1
VID0
VOUT
0
0
0
0
0
0
0
1.500V
0
0
0
0
0
0
1
1.4875
Start-up Timing
0
0
0
0
1
0
1
1.4375
With the controller's +5V VDD voltage above the POR
threshold, the start-up sequence begins when VR_ON
exceeds the 3.3V logic HIGH threshold. Approximately
120µs later SOFT and VOUT start ramping up to the boot
voltage of 1.2V. During this interval, the SOFT capacitor is
charged with approximately 40µA. Therefore, if the SOFT
capacitor is selected to be 20nF, the SOFT ramp will be at
about 2mV/µs for a soft-start time of 600µs. Once VOUT
(VDIFF) is within 10% of the boot voltage for 13 PWM cycles
(43µs for frequency = 300kHz), then CLK_EN# is pulled
LOW and the SOFT capacitor is charged up with
approximately 200µA. Therefore, VOUT slews at +10mV/µs
to the voltage set by the VID pins. Approximately 7ms later,
PGOOD is asserted HIGH. A typical start-up timing is shown
in Figure 42. Similar results occur if VR_ON is tied to VDD,
with the soft-start sequence starting 120µs after VDD
crosses the POR threshold.
0
0
0
0
1
1
1
1.4125
0
0
0
1
0
0
0
1.4000
0
0
1
0
0
0
1
1.2875
0
0
1
1
0
0
0
1.2000
0
0
1
1
1
0
0
1.1500
0
1
0
1
0
0
0
1.0000
0
1
0
1
0
1
1
0.9625
0
1
1
1
1
0
0
0.7500
1
0
0
0
1
0
0
0.6500
1
0
1
0
0
0
0
0.5000
1
1
0
0
0
0
0
0.300
1
1
0
0
0
0
1
Off
1
1
0
0
0
1
0
Off
FN9259 Rev 3.00
June 21, 2010
...
Off
1
1
1
1
1
1
0
Off
1
1
1
1
1
1
1
Off
Page 17 of 29
ISL6260C
A differential amplifier allows voltage sensing for precise
voltage regulation at the microprocessor die. The inputs to
the amplifier are the VSEN and RTN pins.
B) Load Line or Droop Accomplishment
As the load current increases from zero, the output voltage
will drop from the VID table value by an amount proportional
to load current to achieve the IMVP-6+ load line. The
ISL6260C provides for current to be sensed using resistors
in series with the channel inductors as shown in the
application circuit of Figure 40 or using the intrinsic series
resistance of the inductors as shown in the application circuit
of Figure 39. In both cases, signals representing the inductor
currents are summed at VSUM which is the non-inverting
input to the DROOP amplifier shown in the block diagram of
Figure 41. The voltage at the DROOP pin minus the output
voltage at VO pin is the total load current multiplied by a gain
factor. This value is used as an input to the differential
amplifier to achieve the IMVP-6+ load line as well as the
input to the overcurrent circuit.
When using inductor DCR current sensing, a single NTC
element is used to compensate the positive temperature
coefficient of the copper winding thus sustaining the load-line
accuracy with reduced cost.
C) Phase Current Balance
In addition to the total current which is used for DROOP and
OCP, the individual channel average currents are also
monitored by the phase node voltage. Channel current
differences are sensed by comparing ISEN1, ISEN2, and
ISEN3 voltage. The IBAL circuit will adjust the channel
pulse-widths up or down relative to the other channels to
cause the voltages presented to the ISEN pins to be equal.
D) Enable and Disable Phases
The ISL6260C controller can be configured for three-, twoor single-channel operation. To disable channel two and/or
channel three, its PWM output pin should be tied to +5V and
the ISEN pins should be grounded. In three-channel
operation, the three channel PWM's are phase shifted by
120°, and in two-channel operation they are phase shifted by
180°.
E) Switching Frequency in CCM/DCM mode
The switching frequency is adjusted by the resistor between
the error amplifier output and the VW pin. When ISL6260C is
in continuous conduction mode (CCM), the switching
frequency may not be as constant as that of a fixed
frequency PWM controllers. However, the switching
frequency variation will be kept small to maintain the output
voltage ripple within SPEC. In general, the switching
frequency will be very close to the set value at high input
voltage and heavy load conditions.
When DPRSLPVR is high and DPRSTP# is low, the FCCM
pin will become low, and discontinuous conduction mode
FN9259 Rev 3.00
June 21, 2010
(DCM) operation will be allowed in the ISL6208 gate drive. In
DCM, ISL6208 turns off the lower FET after its channel
current across zero. As load is further reduced, channel
switching frequency will drop, providing optimized efficiency
at light loading. FCCM logic low is the signal to enable, or to
allow the DCM operation. Only if the inductor current is really
cross zero, does the true DCM occur.
V o ut
10 m V /us
-2 m V /us
2 m V /u s
D P R S TP #
D P R S LP V R
M S B of V ID
FIGURE 43. DEEPER SLEEP TRANSITION SHOWING
DPRSLPVR’s EFFECT ON EXIT SLEW RATE
Dynamic Operation
Refer to Figure 43. The ISL6260C responds to changes in
VID command voltage by slewing to new voltages with a
dV/dt set by the SOFT capacitor and by the state of
DPRSLPVR. With CSOFT = 20nF and DPRSLPVR HIGH,
the output voltage will move at ±2mV/µs for large changes in
voltage. For DPRSLPVR LOW, the large signal dV/dt will be
±10mV/µs. As the output approaches the VID command
voltage, the dV/dt rate moderates to prevent overshoot.
During Geyserville III transitions where there is one LSB VID
step each 5µs, the controller will follow the VID command
with its dV/dt rate of ±2.5mV/µs.
Keeping DPRSLPVR HIGH during VID transitions will result
in reduced dV/dt slew rate and lesser audio noise. For
fastest recovery from Deeper Sleep to Active mode,
DPRSLPVR LOW achieves higher dV/dt as required by
IMVP-6+ DPRSTP# and DPRSLPVR logic SPEC.
Intersil's R3 intrinsically has voltage-feed-forward. The
output voltage is insensitive to a fast slew input voltage
change. Refer to Figure 15 in the “Typical Operating
Performance” on page 9 for Input Transient Performance.
The hysteresis window voltage is constructed with a resistor on
the Vw pin to the error amplifier outputs. The synthesized
inductor current ripple signal compares with the window voltage
and generates PWM signal. At load current step up, the
switching frequency is increased resulting in a faster response
than conventional fixed frequency PWM controllers. As all the
phases shares the same hysteretic window voltage, it also
ensures excellent dynamic current balance between phases.
The individual average phase voltages are monitored and
controlled to achieve steady state current balance among the
phases with current balance loop.
Page 18 of 29
ISL6260C
Modes of Operation Programmed by Logic Signals
The operational modes of ISL6260C are programmed by the
control signals of DPRSLPVR, DPRSTP#, and PSI#.
ISL6260C responds PSI# signal by adding or dropping
PWM2 and adjusting the overcurrent protection level
accordingly. For example, if the ISL6260C is initially used as
three phase controller, the PSI# signal will add or drop
PWM2 and leave PWM1 and PWM3 always in operation.
Meanwhile, after PWM2 is dropped, the phase shift between
the PWM1 and PWM3 is adjusted from 120° to 180° and the
overcurrent and the way-overcurrent protection level will be
adjusted to 2/3 of the initial value. If the ISL6260C is initially
used as two phase operation, it is suggested that PWM1 and
PWM2 pair, not PWM1 and PWM3 pair, should be used such
that the PSI# signal will enable or disable PWM2 with PWM1
in operation always. The overcurrent and way-overcurrent
protection level in two-to-one phase mode operation will be
adjusted as two-to-one as well.
The DCM mode operation is independent of PSI# for
ISL6260C. It responds to the DPRSLPVR and DPRSTP#.
Table 2 shows the operation modes of ISL6260C with
combinations of control logic.
When PSI# is de-asserted low, ISEN2 pin is connected to
the ISEN pins of the operational phases internally to keep
proper current balance and minimize the inductor current
overshoot and undershoot when the disabled phase is
enabled again.
TABLE 2. ISL6260C MODE OF OPERATIONS
DPRSLPVR DPRSTP# PSI#
IMVP-6+
Logic
Other
Logic
MODE OF
OPERATION
CPU
MODE
0
1
1
N phase CCM
Active
0
1
0
N-1 phase CCM Active
1
0
1
N phase DCM
1
0
0
N-1 phase DCM Deeper
sleep
0
0
1
N phase CCM
0
0
0
N-1 phase CCM
1
1
1
N phase CCM
1
1
0
N-1phase CCM
Deeper
sleep
Protection
The ISL6260C provides overcurrent, overvoltage, and
undervoltage protection. Overcurrent protection is related to
the voltage droop which is determined by the load line
requirement. After the load-line is set, the OCSET resistor can
be selected to detect overcurrent at any level of droop voltage.
For overcurrent less that 2.5x the OCSET level, the overload
condition must exist for 120µs in order to trip the OC fault
latch. This is shown in Figure 28.
FN9259 Rev 3.00
June 21, 2010
For overload exceeding 2.5 times the OCSET level, the
PWM outputs will immediately shut off and PGOOD will go
low to maximize protection due to hard short circuit. This
protection was referred to as way-overcurrent or fast over
current, for short-circuit protections.
In addition, excessive phase unbalance due to gate driver
failure will be detected and will shut down the controller. The
phase unbalance is detected by the voltage on the ISEN pin.
If the ISEN pin voltage difference is greater than 9mV for 1ms,
the controller will latch off.
Undervoltage protection is independent of the overcurrent
limit. If the output voltage is less than the VID set value by
300mV or more, a fault will latch after 1ms in that condition.
The PWM outputs will turn off and PGOOD will go low. This
is shown in Figure 27. Note that most practical core voltage
regulators will have the overcurrent set to trip before the
-300mV undervoltage limit.
There are two levels of overvoltage protection with different
response. The first level of overvoltage protection is referred
to as PGOOD overvoltage protection. Basically, for output
voltage exceeding the set value by +200mV for 1ms, a fault
will be declared with PGOOD latched low.
All of the above faults have the same action taken: PGOOD
is latched low and the upper and lower power FETs are
turned off so that inductor current will decay through the FET
body diodes. This condition can be reset by bringing VR_ON
low or by bringing VDD below POR threshold. When these
inputs are returned to their high operating levels, a soft-start
will occur.
The second level of overvoltage protection behaves
differently. If the output exceeds 1.7V, an OV fault is
immediately declared, PGOOD is latched low and the
low-side FETs are turned on. The low-side FETs will remain
on until the output voltage is pulled down below 0.85V at
which time all FETs are turned off. If the output again rises
above 1.7V, the process is repeated. This affords the
maximum amount of protection against a shorted high-side
FET while preventing output ringing below ground. The 1.7V
OVP can not be reset with VR_ON, but requires that VDD be
lowered to reset. The 1.7V OV detector is active at all times
when the controller is enabled including after one of the
other faults occurs. This ensures the processor is protected
against high-side FET leakage while the FETs are
commanded off.
Page 19 of 29
ISL6260C
TABLE 3. SUMMARY OF THE FAULT PROTECTION AND RESET OPERATIONS OF ISL6260C
FAULT DURATION
PRIOR TO
PROTECTION
PROTECTION
ACTIONS
FAULT RESET
Overcurrent
120µs
PWMs tri-state, PGOOD latched low
VR_ON toggle or VDD toggle
Way-Overcurren (2.5X OC)
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