ISL6261
®
Data Sheet
Single-Phase Core Regulator for IMVP-6®
Mobile CPUs
The ISL6261 is a single-phase buck regulator implementing
lntel® IMVP-6® protocol, with embedded gate drivers.
September 27, 2006
FN9251.1
Features
• Precision single-phase CORE voltage regulator
- 0.5% system accuracy over temperature
- Enhanced load line accuracy
The heart of the ISL6261 is the patented R3 Technology™,
Intersil’s Robust Ripple Regulator modulator. Compared with
the traditional multi-phase buck regulator, the R3
Technology™ has faster transient response. This is due to
the R3 modulator commanding variable switching frequency
during a load transient.
• Internal gate driver with 2A driving capability
lntel® Mobile Voltage Positioning (IMVP) is a smart voltage
regulation technology effectively reducing power dissipation
in lntel® Pentium processors. To boost battery life, the
ISL6261 supports DPRSLRVR (deeper sleep) function and
maximizes the efficiency via automatically changing
operation modes. At heavy load in the active mode, the
regulator commands the continuous conduction mode
(CCM) operation. When the CPU enters deeper sleep mode,
the ISL6261 enables diode emulation to maximize the
efficiency at light load. Asserting the FDE pin of the ISL6261
in deeper sleep mode will further decrease the switching
frequency at light load and increase the regulator efficiency.
• Multiple current sensing schemes supported
- Lossless inductor DCR current sensing
- Precision resistive current sensing
A 7-bit digital-to-analog converter (DAC) allows dynamic
adjustment of the core output voltage from 0.300V to 1.500V.
The ISL6261 has 0.5% system voltage accuracy over
temperature.
A unity-gain differential amplifier provides remote voltage
sensing at the CPU die. This allows the voltage on the CPU
die to be accurately measured and regulated per lntel®
IMVP-6 specification. Current sensing can be implemented
through either lossless inductor DCR sensing or precise
resistor sensing. If DCR sensing is used, an NTC thermistor
network will thermally compensates the gain and the time
constant variations caused by the inductor DCR change.
• Microprocessor voltage identification input
- 7-Bit VID input
- 0.300V to 1.500V in 12.5mV steps
- Support VID change on-the-fly
• Thermal monitor
• User programmable switching frequency
• Differential remote voltage sensing at CPU die
• Overvoltage, undervoltage, and overcurrent protection
• Pb-free plus anneal available (RoHS compliant)
Ordering Information
PART NUMBER
(NOTE)
PART
MARKING
TEMP
RANGE
(°C)
PACKAGE PKG.
(Pb-FREE) DWG. #
ISL6261CRZ
ISL6261CRZ
-10 to +100 40 Ld 6x6
QFN
L40.6x6
ISL6261CRZ-T
ISL6261CRZ
-10 to +100 40 Ld 6x6 L40.6x6
QFN, T&R
ISL6261CR7Z
ISL6261CR7Z -10 to +100 48 Ld 7x7
QFN
L48.7x7
ISL6261CR7Z-T ISL6261CR7Z -10 to +100 48 Ld 7x7 L48.7x7
QFN, T&R
ISL6261IRZ
ISL6261IRZ
-40 to +100 40 Ld 6x6
QFN
L40.6x6
ISL6261IRZ-T
ISL6261IRZ
-40 to +100 40 Ld 6x6 L40.6x6
QFN, T&R
ISL6261IR7Z
ISL6261IR7Z
-40 to +100 48 Ld 7x7
QFN
ISL6261IR7Z-T
ISL6261IR7Z
-40 to +100 48 Ld 7x7 L48.7x7
QFN, T&R
L48.7x7
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2006. All Rights Reserved. R3 Technology™ is a trademark of Intersil Americas Inc.
All other trademarks mentioned are the property of their respective owners.
ISL6261
Pinouts
PGOOD
3V3
CLK_EN
DPRSTP#
DPRSLPVR
VR_ON
VID6
VID5
VID4
VID3
ISL6261
(40 LD QFN)
40
39
38
37
36
35
34
33
32
31
FDE
1
30 VID2
PGD_IN
2
29 VID1
RBIAS
3
28 VID0
VR_TT#
4
27 VCCP
NTC
5
SOFT
6
OCSET
7
24 PHASE
VW
8
23 UGATE
COMP
9
22 BOOT
FB
10
21 NC
26 LGATE
DROOP
17
18
19
20
VDD
RTN
16
VSS
VSEN
15
VIN
14
25 VSSP
VSUM
13
VO
12
DFB
11
VDIFF
GND PAD
(BOTTOM)
3V3
CLK_EN#
DPRSTP#
DPRSLPVR
VR_ON
VID6
VID5
VID4
VID3
VID2
VID1
VID0
ISL6261
(48 LD QFN)
48
47
46
45
44
43
42
41
40
39
38
37
PGOOD
1
36 NC
FDE
2
35 NC
PGD_IN
3
34 NC
RBIAS
4
33 NC
VR_TT#
5
32 NC
NTC
6
SOFT
7
OCSET
8
29 VSSP
VW
9
28 PHASE
COMP 10
27 UGATE
31 VCCP
GND PAD
(BOTTOM)
30 LGATE
2
13
14
15
16
17
18
19
20
21
22
23
24
DROOP
DFB
VO
VSUM
VIN
VSS
VDD
NC
NC
25 NC
RTN
NC 12
VSEN
26 BOOT
VDIFF
FB 11
FN9251.1
September 27, 2006
ISL6261
Absolute Maximum Ratings
Thermal Information
Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +7V
Battery Voltage, VIN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+28V
Boot Voltage (BOOT) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +33V
Boot to Phase Voltage (BOOT-PHASE). . . . . . . . . -0.3V to +7V(DC)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +9V(0.5µs
1.675
1.7
1.725
V
10
10.2
µA
3.5
mV
OCSET Reference Current
I(Rbias) = 10µA
9.8
OC Threshold Offset
DROOP rising above OCSET >120µs
-3.5
VO below set point for >1ms
-360
-300
-240
mV
Undervoltage Threshold
(VDIFF-SOFT)
UVf
LOGIC THRESHOLDS
VR_ON, DPRSLPVR and PGD_IN
Input Low
VIL(3.3V)
-
-
1
V
VR_ON, DPRSLPVR and PGD_IN
Input High
VIH(3.3V)
2.3
-
-
V
4
FN9251.1
September 27, 2006
ISL6261
Electrical Specifications
VDD = 5V, TA = -10°C to +100°C, Unless Otherwise Specified. (Continued)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
IIL
Logic input is low
-1
0
-
μA
IIH
Logic input is high
-
0
1
μA
IIL_DPRSLP
DPRSLPVR logic input is low
-1
0
-
μA
IIH_DPRSLP
DPRSLPVR logic input is high
-
0.45
1
μA
Leakage Current on VR_ON and
PGD_IN
Leakage Current on DPRSLPVR
TEST CONDITIONS
DAC(VID0-VID6), PSI# and
DPRSTP# Input Low
VIL(1.0V)
-
-
0.3
V
DAC(VID0-VID6), PSI# and
DPRSTP# Input High
VIH(1.0V)
0.7
-
-
V
Leakage Current of DAC(VID0VID6) and DPRSTP#
IIL
DPRSLPVR logic input is low
-1
0
-
μA
IIH
DPRSLPVR logic input is high
-
0.45
1
μA
53
60
67
µA
1.17
1.2
1.25
V
-
5
9
2.9
3.1
-
V
-
0.18
0.4
V
THERMAL MONITOR
NTC Source Current
NTC = 1.3V
Over-temperature Threshold
V(NTC) falling
VR_TT# Low Output Resistance
RTT
I = 20mA
CLK_EN# High Output Voltage
VOH
3V3 = 3.3V, I = -4mA
CLK_EN# Low Output Voltage
VOL
ICLK_EN# = 4mA
CLK_EN# OUTPUT LEVELS
NOTES:
3. Guaranteed by characterization.
4. Guaranteed by design.
Gate Driver Timing Diagram
PWM
tPDHU
tFU
tRU
1V
UGATE
1V
LGATE
tRL
tFL
tPDHL
5
FN9251.1
September 27, 2006
ISL6261
PGOOD
3V3
CLK_EN
DPRSTP#
DPRSLPVR
VR_ON
VID6
VID5
VID4
VID3
Functional Pin Description
40
39
38
37
36
35
34
33
32
31
FDE
1
30 VID2
PGD_IN
2
29 VID1
RBIAS
3
28 VID0
VR_TT#
4
27 VCCP
NTC
5
SOFT
6
OCSET
7
24 PHASE
VW
8
23 UGATE
COMP
9
22 BOOT
FB
10
21 NC
26 LGATE
15
16
VSEN
RTN
DROOP
DFB
VO
17
18
19
20
VDD
14
VSS
13
VIN
12
25 VSSP
VSUM
11
VDIFF
GND PAD
(BOTTOM)
FDE
VW
Forced diode emulation enable signal. Logic high of FDE
with logic low of DPRSTP# forces the ISL6261 to operate in
diode emulation mode with an increased VW-COMP voltage
window.
A resistor from this pin to COMP programs the switching
frequency (eg. 6.81K = 300kHz).
COMP
The output of the error amplifier.
PGD_IN
Digital Input. Suggest connecting to MCH_PWRGD, which
indicates that VCC_MCH voltage is within regulation.
FB
The inverting input of the error amplifier.
RBIAS
VDIFF
A 147K resistor to VSS sets internal current reference.
The output of the differential amplifier.
VR_TT#
VSEN
Thermal overload output indicator with open-drain output.
Over-temperature pull-down resistance is 10.
Remote core voltage sense input.
NTC
Remote core voltage sense return.
Thermistor input to VR_TT# circuit and a 60µA current
source is connected internally to this pin.
DROOP
SOFT
A capacitor from this pin to GND pin sets the maximum slew
rate of the output voltage. The SOFT pin is the non-inverting
input of the error amplifier.
RTN
The output of the droop amplifier. DROOP-VO voltage is the
droop voltage.
DFB
The inverting input of the droop amplifier.
VO
OCSET
Overcurrent set input. A resistor from this pin to VO sets
DROOP voltage limit for OC trip. A 10µA current source is
connected internally to this pin.
6
An input to the IC that reports the local output voltage.
FN9251.1
September 27, 2006
ISL6261
VSUM
NC
This pin is connected to one terminal of the capacitor in the
current sensing R-C network.
Not connected. Ground this pin in the practical layout.
VIN
VID input with VID0 as the least significant bit (LSB) and
VID6 as the most significant bit (MSB).
Power stage input voltage. It is used for input voltage feed
forward to improve the input line transient performance.
VSS
VID0, VID1, VID2, VID3, VID4, VID5, VID6
VR_ON
Signal ground. Connect to controller local ground.
VR enable pin. A logic high signal on this pin enables the
regulator.
VDD
DPRSLPVR
5V control power supply.
Deeper sleep enable signal. A logic high indicates that the
microprocessor is in Deeper Sleep Mode and also indicates
a slow Vo slew rate with 41μA discharging or charging the
SOFT cap.
BOOT
Upper gate driver supply voltage. An internal bootstrap diode
is connected to the VCCP pin.
DPRSTP#
UGATE
The upper-side MOSFET gate signal.
PHASE
The phase node. This pin should connect to the source of
upper MOSFET.
Deeper sleep slow wake up signal. A logic low signal on this
pin indicates that the microprocessor is in Deeper Sleep
Mode.
CLK_EN#
VSSP
Digital output for system PLL clock. Goes active 20µs after
PGD_IN is active and Vcore is within 10% of boot voltage.
The return path of the lower gate driver.
3V3
LGATE
3.3V supply voltage for CLK_EN#.
The lower-side MOSFET gate signal.
PGOOD
VCCP
Power good open-drain output. Needs to be pulled up
externally by a 680 resistor to VCCP or 1.9k to 3.3V.
5V power supply for the gate driver.
7
FN9251.1
September 27, 2006
8
DROOP
DFB
VSUM
OCSET
VID6
VID5
VID4
VID3
VID2
VID1
VID0
DAC
VO VSEN RTN
VO
10uA
VR_ON
DROOP
RBIAS
DPRSLPVR DPRSTP#
1
1
VO
SOFT
VDIFF SOFT FB
OC
MODE CONTROL
FDE
CLK_EN#
PGOOD
3V3
PGOOD
E/A
COMP
VIN VSOFT
VW
VW
MODULATOR
OC
FAULT AND PGOOD LOGIC
FLT
FLT
60uA
VIN
VIN
DRIVER
LOGIC
VCCP
1.22V
GND
VSS
PGOOD MONITOR AND LOGIC
PGD_IN
VCCP
VDD
VCCP
VCCP
VSSP
LGATE
PHASE
UGATE
BOOT
VR_TT#
NTC
ISL6261
Function Block Diagram
FIGURE 1. SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM OF ISL6261
FN9251.1
September 27, 2006
ISL6261
Simplified Application Circuit for DCR Current Sensing
V+5
V+3.3
Vin
R4
C4
R5
3V3
VDD VCCP
RBIAS
VIN
R6
C8
NTC
C5
UGATE
SOFT
BOOT
Lo
C6
VR_TT#
VR_TT#
PHASE
Vo
VIDs
VID
Co
DPRSTP#
DPRSTP#
DPRSLPVR
DPRSLPVR
LGATE
FDE
PGD_IN
MCH_PWRGD
VSSP
CLK_EN#
CLK_ENABLE#
VR_ON
VR_ON
R8
VSUM
PGOOD
IMVP6_PWRGD
VCC-SENSE
VSEN
VSS-SENSE
RTN
R7
C7
C3
C9
R11
C10
DFB
COMP
R12
FB
C1
VDIFF
R1
R10
OCSET
C2
R3
NTC
Network
VO
ISL6261
VW
R2
R9
DROOP
VSS
FIGURE 2. ISL6261-BASED IMVP-6® SOLUTION WITH INDUCTOR DCR CURRENT SENSING
9
FN9251.1
September 27, 2006
ISL6261
Simplified Application Circuit for Resistive Current Sensing
V+5
V+3.3
Vin
R4
C4
R5
3V3
VDD VCCP
RBIAS
VIN
R6
C8
NTC
C5
UGATE
SOFT
BOOT
Lo
C6
VR_TT#
VR_TT#
R sen
PHASE
VIDs
VID
Vo
Co
DPRSTP#
DPRSTP#
DPRSLPVR
DPRSLPVR
LGATE
FDE
PGD_IN
MCH_PWRGD
VSSP
CLK_EN#
CLK_ENABLE#
VR_ON
VR_ON
IMVP6_PWRGD
PGOOD
VCC-SENSE
R8
VSUM
C9
VSEN
VSS-SENSE
R7
C7
C3
RTN
VO
ISL6261
OCSET
C2
R2
C10
DFB
COMP
R12
FB
C1
R3
VDIFF
R1
R10
R11
VW
DROOP
VSS
FIGURE 3. ISL6261-BASED IMVP-6® SOLUTION WITH RESISTIVE CURRENT SENSING
10
FN9251.1
September 27, 2006
ISL6261
Theory of Operation
The ISL6261 is a single-phase regulator implementing Intel®
IMVP-6® protocol and includes an integrated gate driver for
reduced system cost and board area. The ISL6261 IMVP-6®
solution provides optimum steady state and transient
performance for microprocessor core voltage regulation
applications up to 25A. Implementation of diode emulation
mode (DEM) operation further enhances system efficiency.
VDD
VR_ON
100us
The hysteretic window voltage is with respect to the error
amplifier output. Therefore the load current transient results
in increased switching frequency, which gives the R3™
regulator a faster response than conventional fixed
frequency PWM regulators.
Start-up Timing
With the controller’s VDD pin voltage above the POR
threshold, the start-up sequence begins when VR_ON
exceeds the 3.3V logic HIGH threshold. In approximately
100μs, SOFT and VO start ramping to the boot voltage of
1.2V. At startup, the regulator always operates in continuous
current mode (CCM), regardless of the control signals.
During this interval, the SOFT cap is charged by a 41μA
current source. If the SOFT capacitor is 20nF, the SOFT
ramp will be 2mV/μs for a soft-start time of 600μs. Once VO
is within 10% of the boot voltage and PGD_IN is HIGH for six
PWM cycles (20µs for 300kHz switching frequency),
CLK_EN# is pulled LOW, and the SOFT cap is
charged/discharged by approximate 200µA and VO slews at
10mV/μs to the voltage set by the VID pins. In approximately
7ms, PGOOD is asserted HIGH. Figure 4 shows typical
startup timing.
PGD_IN Latch
It should be noted that PGD_IN going low will cause the
converter to latch off. Toggling PGD_IN won’t clear the latch.
Toggling VR_ON will clear it. This feature allows the
converter to respond to other system voltage outages
immediately.
11
2mV/us Vboot
SOFT &VO
~20us
R3
The heart of the ISL6261 is the patented
Technology™,
Intersil’s Robust Ripple Regulator modulator. The R3™
modulator combines the best features of fixed frequency and
hysteretic PWM controllers while eliminating many of their
shortcomings. The ISL6261 modulator internally synthesizes
an analog of the inductor ripple current and uses hysteretic
comparators on those signals to establish PWM pulses.
Operating on the large-amplitude and noise-free synthesized
signals allows the ISL6261 to achieve lower output ripple
and lower phase jitter than either conventional hysteretic or
fixed frequency PWM controllers. Unlike conventional
hysteretic converters, the ISL6261 has an error amplifier that
allows the controller to maintain 0.5% voltage regulation
accuracy throughout the VID range from 0.75V to 1.5V.
10mV/us
PGD_IN
CLK_EN#
~7ms
IMVP-VI PGOOD
FIGURE 4. SOFT-START WAVEFORMS USING A 20nF SOFT
CAPACITOR
Static Operation
After the startup sequence, the output voltage will be
regulated to the value set by the VID inputs per Table 1,
which is presented in the lntel® IMVP-6® specification. The
ISL6261 regulates the output voltage with ±0.5% accuracy
over the range of 0.7V to 1.5V.
A true differential amplifier remotely senses the core voltage
to precisely control the voltage at the microprocessor die.
VSEN and RTN pins are the inputs to the differential
amplifier.
As the load current increases from zero, the output voltage
droops from the VID value proportionally to achieve the
IMVP-6® load line. The ISL6261 can sense the inductor
current through the intrinsic series resistance of the
inductors, as shown in Figure 2, or through a precise resistor
in series with the inductor, as shown in Figure 3. The
inductor current information is fed to the VSUM pin, which is
the non-inverting input to the droop amplifier. The DROOP
pin is the output of the droop amplifier, and DROOP-VO
voltage is a high-bandwidth analog representation of the
inductor current. This voltage is used as an input to a
differential amplifier to achieve the IMVP-6® load line, and
also as the input to the overcurrent protection circuit.
When using inductor DCR current sensing, an NTC
thermistor is used to compensate the positive temperature
coefficient of the copper winding resistance to maintain the
load-line accuracy.
The switching frequency of the ISL6261 controller is set by
the resistor RFSET between pins VW and COMP, as shown in
Figures 2 and 3.
FN9251.1
September 27, 2006
ISL6261
TABLE 1. VID TABLE FROM INTEL IMVP-6 SPECIFICATION
TABLE 1. VID TABLE FROM INTEL IMVP-6 SPECIFICATION
(Continued)
VID6
VID5
VID4
VID3
VID2
VID1
VID0
Vo (V)
VID6
VID5
VID4
VID3
VID2
VID1
VID0
Vo (V)
0
0
0
0
0
0
0
1.5000
0
1
0
1
0
1
0
0.9750
0
0
0
0
0
0
1
1.4875
0
1
0
1
0
1
1
0.9625
1
0
1
1
0
0
0.9500
0
0
0
0
0
1
0
1.4750
0
0
0
0
0
0
1
1
1.4625
0
1
0
1
1
0
1
0.9375
0
0
0
0
1
0
0
1.4500
0
1
0
1
1
1
0
0.9250
0
0
0
0
1
0
1
1.4375
0
1
0
1
1
1
1
0.9125
1
1
0
0
0
0
0.9000
0
0
0
0
1
1
0
1.4250
0
0
0
0
0
1
1
1
1.4125
0
1
1
0
0
0
1
0.8875
0
0
0
1
0
0
0
1.4000
0
1
1
0
0
1
0
0.8750
0
0
0
1
0
0
1
1.3875
0
1
1
0
0
1
1
0.8625
1
1
0
1
0
0
0.8500
0
0
0
1
0
1
0
1.3750
0
0
0
0
1
0
1
1
1.3625
0
1
1
0
1
0
1
0.8375
0
0
0
1
1
0
0
1.3500
0
1
1
0
1
1
0
0.8250
0
0
0
1
1
0
1
1.3375
0
1
1
0
1
1
1
0.8125
1
1
1
0
0
0
0.8000
0
0
0
1
1
1
0
1.3250
0
0
0
0
1
1
1
1
1.3125
0
1
1
1
0
0
1
0.7875
0
0
1
0
0
0
0
1.3000
0
1
1
1
0
1
0
0.7750
0
0
1
0
0
0
1
1.2875
0
1
1
1
0
1
1
0.7625
1
1
1
1
0
0
0.7500
0
0
1
0
0
1
0
1.2750
0
0
0
1
0
0
1
1
1.2625
0
1
1
1
1
0
1
0.7375
0
0
1
0
1
0
0
1.2500
0
1
1
1
1
1
0
0.7250
0
0
1
0
1
0
1
1.2375
0
1
1
1
1
1
1
0.7125
0
0
0
0
0
0
0.7000
0
0
1
0
1
1
0
1.2250
1
0
0
1
0
1
1
1
1.2125
1
0
0
0
0
0
1
0.6875
0
0
1
1
0
0
0
1.2000
1
0
0
0
0
1
0
0.6750
0
0
1
1
0
0
1
1.1875
1
0
0
0
0
1
1
0.6625
0
0
0
1
0
0
0.6500
0
0
1
1
0
1
0
1.1750
1
0
0
1
1
0
1
1
1.1625
1
0
0
0
1
0
1
0.6375
0
0
1
1
1
0
0
1.1500
1
0
0
0
1
1
0
0.6250
0
0
1
1
1
0
1
1.1375
1
0
0
0
1
1
1
0.6125
0
0
1
0
0
0
0.6000
0
0
1
1
1
1
0
1.1250
1
0
0
1
1
1
1
1
1.1125
1
0
0
1
0
0
1
0.5875
0
1
0
0
0
0
0
1.1000
1
0
0
1
0
1
0
0.5750
0
1
0
0
0
0
1
1.0875
1
0
0
1
0
1
1
0.5625
0
0
1
1
0
0
0.5500
0
1
0
0
0
1
0
1.0750
1
0
1
0
0
0
1
1
1.0625
1
0
0
1
1
0
1
0.5375
0
1
0
0
1
0
0
1.0500
1
0
0
1
1
1
0
0.5250
0
1
0
0
1
0
1
1.0375
1
0
0
1
1
1
1
0.5125
0
1
0
0
0
0
0.5000
0
1
0
0
1
1
0
1.0250
1
0
1
0
0
1
1
1
1.0125
1
0
1
0
0
0
1
0.4875
0
1
0
1
0
0
0
1.0000
1
0
1
0
0
1
0
0.4750
0
1
0
1
0
0
1
0.9875
1
0
1
0
0
1
1
0.4625
12
FN9251.1
September 27, 2006
ISL6261
TABLE 1. VID TABLE FROM INTEL IMVP-6 SPECIFICATION
(Continued)
TABLE 1. VID TABLE FROM INTEL IMVP-6 SPECIFICATION
(Continued)
VID6
VID5
VID4
VID3
VID2
VID1
VID0
Vo (V)
VID6
VID5
VID4
VID3
VID2
VID1
VID0
Vo (V)
1
0
1
0
1
0
0
0.4500
1
1
0
1
0
1
1
0.1625
1
0
1
0
1
0
1
0.4375
1
1
0
1
1
0
0
0.1500
1
0
1
0
1
1
0
0.4250
1
1
0
1
1
0
1
0.1375
1
0
1
0
1
1
1
0.4125
1
1
0
1
1
1
0
0.1250
1
0
1
1
0
0
0
0.4000
1
1
0
1
1
1
1
0.1125
1
0
1
1
0
0
1
0.3875
1
1
1
0
0
0
0
0.1000
1
0
1
1
0
1
0
0.3750
1
1
1
0
0
0
1
0.0875
1
0
1
1
0
1
1
0.3625
1
1
1
0
0
1
0
0.0750
1
0
1
1
1
0
0
0.3500
1
1
1
0
0
1
1
0.0625
1
0
1
1
1
0
1
0.3375
1
1
1
0
1
0
0
0.0500
1
0
1
1
1
1
0
0.3250
1
1
1
0
1
0
1
0.0375
1
0
1
1
1
1
1
0.3125
1
1
1
0
1
1
0
0.0250
1
1
0
0
0
0
0
0.3000
1
1
1
0
1
1
1
0.0125
1
1
0
0
0
0
1
0.2875
1
1
1
1
0
0
0
0.0000
1
1
0
0
0
1
0
0.2750
1
1
1
1
0
0
1
0.0000
1
1
0
0
0
1
1
0.2625
1
1
1
1
0
1
0
0.0000
1
1
0
0
1
0
0
0.2500
1
1
1
1
0
1
1
0.0000
1
1
0
0
1
0
1
0.2375
1
1
1
1
1
0
0
0.0000
1
1
0
0
1
1
0
0.2250
1
1
1
1
1
0
1
0.0000
1
1
0
0
1
1
1
0.2125
1
1
1
1
1
1
0
0.0000
1
1
0
1
0
0
0
0.2000
1
1
1
1
1
1
1
0.0000
1
1
0
1
0
0
1
0.1875
1
1
0
1
0
1
0
0.1750
TABLE 2. CONTROL SIGNAL TRUTH TABLES FOR OPERATIONAL MODES OF ISL6261
Control
Signal
Logic
FDE
DPRSLPVR
0
0
0
Forced CCM
0%
0
0
1
Diode Emulation Mode
0%
0
1
x
Enhanced Diode Emulation Mode
33%
1
x
x
Forced CCM
0%
13
OPERATIONAL MODE
VW-COMP WINDOW
VOLTAGE INCREASE
DPRSTP#
FN9251.1
September 27, 2006
ISL6261
High Efficiency Operation Mode
based on load current. Light-load efficiency is increased in
both active mode and deeper sleep mode.
The operational modes of the ISL6261 depend on the
control signal states of DPRSTP#, FDE, and DPRSLPVR, as
shown in Table 2. These control signals can be tied to lntel®
IMVP-6® control signals to maintain the optimal system
configuration for all IMVP-6® conditions.
CPU mode-transition sequences often occur in concert with
VID changes. The ISL6261 employs carefully designed
mode-transition timing to work in concert with the VID
changes.
DPRSTP# = 0, FDE = 0 and DPRSLPVR = 1 enables the
ISL6261 to operate in diode emulation mode (DEM) by
monitoring the low-side FET current. In diode emulation
mode, when the low-side FET current flows from source to
drain, it turns on as a synchronous FET to reduce the
conduction loss. When the current reverses its direction
trying to flow from drain to source, the ISL6261 turns off the
low-side FET to prevent the output capacitor from
discharging through the inductor, therefore eliminating the
extra conduction loss. When DEM is enabled, the regulator
works in automatic discontinuous conduction mode (DCM),
meaning that the regulator operates in CCM in heavy load,
and operates in DCM in light load. DCM in light load
decreases the switching frequency to increase efficiency.
This mode can be used to support the deeper sleep mode of
the microprocessor.
The ISL6261 is equipped with internal counters to prevent
control signal glitches from triggering unintended mode
transitions. For example: Control signals lasting less than
seven switching periods will not enable the diode emulation
mode.
Dynamic Operation
The ISL6261 responds to VID changes by slewing to new
voltages with a dv/dt set by the SOFT capacitor and the logic
of DPRSLPVR. If CSOFT = 20nF and DPRSLPVR = 0, the
output voltage will move at a maximum dv/dt of ±10mV/μs
for large changes. The maximum dv/dt can be used to
achieve fast recovery from Deeper Sleep to Active mode. If
CSOFT = 20nF and DPRSLPVR = 1, the output voltage will
move at a dv/dt of ±2mV/μs for large changes. The slow
dv/dt into and out of deeper sleep mode will minimize the
audible noise. As the output voltage approaches the VID
command value, the dv/dt moderates to prevent overshoot.
The ISL6261 is IMVP-6® compliant for DPRSTP# and
DPRSLPVR logic.
DPRSTP# = 0 and FDE = 1 enables the enhanced diode
emulation mode (EDEM), which increases the VW-COMP
window voltage by 33%. This further decreases the
switching frequency at light load to boost efficiency in the
deeper sleep mode.
Intersil R3™ has an intrinsic voltage feed forward function.
High-speed input voltage transients have little effect on the
output voltage.
For other combinations of DPRSTP#, FDE, and
DPRSLPVR, the ISL6261 operates in forced CCM.
Intersil R3™ commands variable switching frequency during
transients to achieve fast response. Upon load application,
the ISL6261 will transiently increase the switching frequency
to deliver energy to the output more quickly. Compared with
steady state operation, the PWM pulses during load
application are generated earlier, which effectively increases
the duty cycle and the response speed of the regulator.
Upon load release, the ILS6261 will transiently decrease the
switching frequency to effectively reduce the duty cycle to
achieve fast response.
The ISL6261 operational modes can be set according to
CPU mode signals to achieve the best performance. There
are two options: (1) Tie FDE to DPRSLPVR, and tie
DPRSTP# and DPRSLPVR to the corresponding CPU mode
signals. This configuration enables EDEM in deeper sleep
mode to increase efficiency. (2) Tie FDE to “1” and
DPRSTP# to “0” permanently, and tie DPRSLPVR to the
corresponding CPU mode signal. This configuration sets the
regulator in EDEM all the time. The regulator will enter DCM
TABLE 3. FAULT-PROTECTION SUMMARY OF ISL6261
FAULT TYPE
FAULT DURATION PRIOR
TO PROTECTION
PROTECTION ACTIONS
FAULT RESET
Overcurrent fault
120μs
PWM tri-state, PGOOD latched low
VR_ON toggle or VDD toggle
Way-Overcurrent fault
< 2μs
PWM tri-state, PGOOD latched low
VR_ON toggle or VDD toggle
Overvoltage fault (1.7V)
Immediately
Low-side FET on until Vcore < 0.85V, then PWM tristate, PGOOD latched low (OV-1.7V always)
VDD toggle
Overvoltage fault
(+200mV)
1ms
PWM tri-state, PGOOD latched low
VR_ON toggle or VDD toggle
Undervoltage fault
(-300mV)
1ms
PWM tri-state, PGOOD latched low
VR_ON toggle or VDD toggle
Over-temperature fault
(NTCT2) are two threshold temperatures.
VR_TT# goes low when the temperature is higher than T1
and goes high when the temperature is lower than T2.
VR_TT#
(EQ. 5)
Logic_1
In diode emulation mode, the ISL6261 stretches the
switching period. The switching frequency decreases as the
load becomes lighter. Diode emulation mode reduces the
switching loss at light load, which is important in conserving
battery power.
Voltage Regulator Thermal Throttling
Logic_0
T2
T1
T (oC)
FIGURE 8. VR_TT# TEMPERATURE HYSTERISIS
lntel® IMVP-6® technology supports thermal throttling of the
processor to prevent catastrophic thermal damage to the
voltage regulator. The ISL6261A features a thermal monitor
sensing the voltage across an externally placed negative
temperature coefficient (NTC) thermistor. Proper selection
and placement of the NTC thermistor allows for detection of
a designated temperature rise by the system.
17
FN9251.1
September 27, 2006
ISL6261
The NTC thermistor’s resistance is approximately given by
the following formula:
R
NTC
(T ) = R
NTCTo
1
1
b⋅(
−
)
T
273
To
273
+
+
⋅e
(EQ. 6)
T is the temperature of the NTC thermistor and b is a
constant determined by the thermistor material. To is the
reference temperature at which the approximation is
derived. The most commonly used To is 25°C. For most
commercial NTC thermistors, there is b = 2750k, 2600k,
4500k or 4250k.
From the operation principle of VR_TT#, the NTC resistor
satisfies the following equation group:
R NTC (T1 ) + Rs =
R NTC (T2 ) + Rs =
1.20V
= 20kΩ
60 μA
(EQ. 7)
1.23V
= 22.78kΩ
54 μA
(EQ. 8)
From Equation 7 and Equation 8, the following can be
derived:
RNTC(T2 ) − RNTC(T1 ) = 2.78kΩ
(EQ. 9)
Substitution of Equation 6 into Equation 9 yields the required
nominal NTC resistor value:
2.78kΩ ⋅ e
RNTCTo =
e
1
b⋅(
)
T2 + 273
b⋅(
1
)
To + 273
(EQ. 10)
−e
1
b⋅(
)
T1 + 273
In some cases, the constant b is not accurate enough to
approximate the resistor value; manufacturers provide the
resistor ratio information at different temperatures. The
nominal NTC resistor value may be expressed in another
way as follows:
RNTCTo =
2.78kΩ
Λ
Λ
R NTC (T2 ) − R NTC (T1 )
Once RNTCTo and Rs is designed, the actual NTC resistance
at T2 and the actual T2 temperature can be found in:
RNTC _ T 2 = 2.78kΩ + RNTC _ T 1
T2 _ actual =
1
1 R NTC _ T2
ln(
) + 1 ( 273 + To )
b
R NTCTo
(EQ. 13)
− 273
(EQ. 14)
One example of using Equations 10, 11 and 12 to design a
thermal throttling circuit with the temperature hysteresis
100°C to 105°C is illustrated as follows. Since T1 = 105°C
and T2 = 100°C, if we use a Panasonic NTC with b = 4700,
Equation 9 gives the required NTC nominal resistance as
R NTC_To = 431kΩ
The NTC thermistor datasheet gives the resistance ratio as
0.03956 at 100°C and 0.03322 at 105°C. The b value of
4700k in Panasonic datasheet only covers up to 85°C;
therefore, using Equation 11 is more accurate for 100°C
design and the required NTC nominal resistance at 25°C is
438kΩ. The closest NTC resistor value from manufacturers
is 470kΩ. So Equation 12 gives the series resistance as
follows:
Rs = 20kΩ − R NTC _ 105C = 20kΩ − 15.61kΩ = 4.39kΩ
The closest standard value is 4.42kΩ. Furthermore,
Equation 13 gives the NTC resistance at T2:
RNTC _ T 2 = 2.78kΩ + RNTC _ T 1 = 18.39kΩ
The NTC branch is designed to have a 470k NTC and a
4.42k resistor in series. The part number of the NTC
thermistor is ERTJ0EV474J. It is a 0402 package. The NTC
thermistor should be placed in the spot that gives the best
indication of the temperature of the voltage regulator. The
actual temperature hysteretic window is approximately
105°C to 100°C.
(EQ. 11)
Λ
where R NTC (T ) is the normalized NTC resistance to its
nominal value. The normalized resistor value on most NTC
thermistor datasheets is based on the value at 25°C.
Once the NTC thermistor resistor is determined, the series
resistor can be derived by:
Rs =
1.20V
− R NTC (T1 ) = 20kΩ − R NTC_T1
60 μA
18
(EQ. 12)
FN9251.1
September 27, 2006
ISL6261
10uA
Rocset
OCSET
VO
OC
Rs
VSUM
Internal to
ISL6261
DROOP
DFB
Io DCR
Rpar
Rntc
R drp1
VO
Vdcr
Rseries
Cn
1
R drp2
DROOP
Rn
(Rntc+Rseries) Rpar
Rntc+Rseries+Rpar
FIGURE 9. EQUIVALENT MODEL FOR DROOP CIRCUIT USING DCR SENSING
Static Mode of Operation - Static Droop Using DCR
Sensing
G1, the gain of Vn to VDCR, is also dependent on the
temperature of the NTC thermistor:
The ISL6261 has an internal differential amplifier to
accurately regulate the voltage at the processor die.
G1 (T ) =
Δ
For DCR sensing, the process to compensate the DCR
resistance variation takes several iterative steps. Figure 2
shows the DCR sensing method. Figure 9 shows the
simplified model of the droop circuitry. The inductor DC
current generates a DC voltage drop on the inductor DCR.
Equation 15 gives this relationship.
V DCR = I o × DCR
(EQ. 15)
An R-C network senses the voltage across the inductor to
get the inductor current information. Rn represents the NTC
network consisting of Rntc, Rseries and Rpar. The choice of Rs
will be discussed in the next section.
The first step in droop load line compensation is to choose
Rn and Rs such that the correct droop voltage appears even
at light loads between the VSUM and VO nodes. As a rule of
thumb, the voltage drop across the Rn network, Vn, is set to
be 0.5-0.8 times VDCR. This gain, defined as G1, provides a
fairly reasonable amount of light load signal from which to
derive the droop voltage.
The NTC network resistor value is dependent on the
temperature and is given by:
Rn (T ) =
( Rseries + Rntc ) ⋅ R par
Rseries + Rntc + R par
19
(EQ. 16)
Rn (T )
Rn (T ) + Rs
(EQ. 17)
The inductor DCR is a function of the temperature and is
approximately given by
DCR(T ) = DCR25C ⋅ (1 + 0.00393 * (T − 25))
(EQ. 18)
in which 0.00393 is the temperature coefficient of the copper.
The droop amplifier output voltage divided by the total load
current is given by:
Rdroop = G1(T) ⋅ DCR (T ) ⋅ k droopamp
(EQ. 19)
Rdroop is the actual load line slope. To make Rdroop
independent of the inductor temperature, it is desired to
have:
G1 (T ) ⋅ (1 + 0.00393 * (T − 25)) ≅ G1t arg et
(EQ. 20)
where G1target is the desired ratio of Vn/VDCR. Therefore, the
temperature characteristics G1 is described by:
G 1 (T ) =
G 1 t arg et
(1 + 0.00393* (T − 25)
(EQ. 21)
For different G1 and NTC thermistor preference, Intersil
provides a design spreadsheet to generate the proper value
of Rntc, Rseries, Rpar.
FN9251.1
September 27, 2006
ISL6261
Rdrp1 (R11 in Figure 2) and Rdrp2 (R12 in Figure 2) sets the
droop amplifier gain, according to Equation 22:
k droopamp = 1 +
Rdrp 2
(EQ. 22)
R drp1
After determining Rs and Rn networks, use Equation 23 to
calculate the droop resistances Rdrp1 and Rdrp2.
Rdrp 2 = (
Rdroop
DCR ⋅ G1(25 o C )
− 1) ⋅ Rdrp1
(EQ. 23)
Rdroop is 2.1mV/A per lntel® IMVP-6® specification.
The droop capacitor refers to Cn in Figure 9. If Cn is
designed correctly, its voltage will be a high-bandwidth
analog voltage of the inductor current. If Cn is not designed
correctly, its voltage will be distorted from the actual
waveform of the inductor current and worsen the transient
response. Figure 11 shows the transient response when Cn
is too small. Vcore may sag excessively upon load
application to create a system failure. Figure 12 shows the
transient response when Cn is too large. Vcore is sluggish in
drooping to its final value. There will be excessive overshoot
if a load occurs during this time, which may potentially hurt
the CPU reliability.
The effectiveness of the Rn network is sensitive to the
coupling coefficient between the NTC thermistor and the
inductor. The NTC thermistor should be placed in close
proximity of the inductor.
To verify whether the NTC network successfully compensates
the DCR change over temperature, one can apply full load
current, and wait for the thermal steady state, and see how
much the output voltage deviates from the initial voltage
reading. Good thermal compensation can limit the drift to less
than 2mV. If the output voltage decreases when the
temperature increases, that ratio between the NTC thermistor
value and the rest of the resistor divider network has to be
increased. Following the evaluation board value and layout of
NTC placement will minimize the engineering time.
The current sensing traces should be routed directly to the
inductor pads for accurate DCR voltage drop measurement.
However, due to layout imperfection, the calculated Rdrp2
may still need slight adjustment to achieve optimum load line
slope. It is recommended to adjust Rdrp2 after the system
has achieved thermal equilibrium at full load. For example, if
the max current is 20A, one should apply 20A load current
and look for 42mV output voltage droop. If the voltage droop
is 40mV, the new value of Rdpr2 is calculated by:
R drp 2 _ new =
42 mV
( R drp 1 + R drp 2 ) − R drp 1
40 mV
Vcore
icore
ΔIcore
Vcore
ΔVcore
ΔVcore= ΔIcore×Rdroop
FIGURE 10. DESIRED LOAD TRANSIENT RESPONSE
WAVEFORMS
icore
Vcore
Vcore
FIGURE 11. LOAD TRANSIENT RESPONSE WHEN Cn IS TOO
SMALL
icore
Vcore
Vcore
(EQ. 24)
FIGURE 12. LOAD TRANSIENT RESPONSE WHEN Cn IS TOO
LARGE
For the best accuracy, the effective resistance on the DFB
and VSUM pins should be identical so that the bias current
of the droop amplifier does not cause an offset voltage. The
effective resistance on the VSUM pin is the parallel of Rs and
Rn, and the effective resistance on the DFB pin is the parallel
of Rdrp1 and Rdrp2.
The current sensing network consists of Rn, Rs and Cn. The
effective resistance is the parallel of Rn and Rs. The RC time
constant of the current sensing network needs to match the
L/DCR time constant of the inductor to get correct
representation of the inductor current waveform. Equation 25
shows this equation:
Dynamic Mode of Operation – Droop Capacitor
Design in DCR Sensing
Figure 10 shows the desired waveforms during load
transient response. Vcore needs to be as square as possible
at Icore change. The Vcore response is determined by several
factors, namely the choice of output inductor and output
capacitor, the compensator design, and the droop capacitor
design.
20
⎛ R × Rs ⎞
L
⎟ × Cn
= ⎜⎜ n
DCR ⎝ Rn + Rs ⎟⎠
(EQ. 25)
FN9251.1
September 27, 2006
ISL6261
Solving for Cn yields
L
C n = DCR
Rn × Rs
Rn + Rs
(EQ. 26)
For example: L = 0.45μH, DCR = 1.1mΩ, Rs = 7.68kΩ, and
Rn = 3.4kΩ
0.45μH
0.0011
= 174nF
Cn =
parallel(7.68k ,3.4k )
(EQ. 27)
Since the inductance and the DCR typically have 20% and
7% tolerance respectively, the L/DCR time constant of each
individual inductor may not perfectly match the RC time
constant of the current sensing network. In mass production,
this effect will make the transient response vary a little bit
from board to board. Compared with potential long-term
damage on CPU reliability, an immediate system failure is
worse. So it is desirable to avoid the waveforms shown in
Figure 11. It is recommended to choose the minimum Cn
value based on the maximum inductance so only the
scenarios of Figures 10 and 12 may happen. It should be
noted that, after calculation, fine-tuning of Cn value may still
be needed to account for board parasitics. Cn also needs to
be a high-grade cap like X7R with low tolerance. Another
good option is the NPO/COG (class-I) capacitor, featuring
only 5% tolerance and very good thermal characteristics. But
the NPO/COG caps are only available in small capacitance
values. In order to use such capacitors, the resistors and
thermistors surrounding the droop voltage sensing and
droop amplifier need to be scaled up 10X to reduce the
capacitance by 10X. Attention needs to be paid in balancing
the impedance of droop amplifier.
Dynamic Mode of Operation - Compensation
Parameters
The voltage regulator is equivalent to a voltage source equal
to VID in series with the output impedance. The output
impedance needs to be 2.1mΩ in order to achieve the
2.1mV/A load line. It is highly recommended to design the
compensation such that the regulator output impedance is
2.1mΩ. A type-III compensator is recommended to achieve
the best performance. Intersil provides a spreadsheet to
design the compensator parameters. Figure 13 shows an
example of the spreadsheet. After the user inputs the
parameters in the blue font, the spreadsheet will calculate
the recommended compensator parameters (in the pink
font), and show the loop gain curves and the regulator output
impedance curve. The loop gain curves need to be stable for
regulator stability, and the impedance curve needs to be
equal to or smaller than 2.1mΩ in the entire frequency range
to achieve good transient response.
21
The user can choose the actual resistor and capacitor values
based on the recommendation and input them in the
spreadsheet, then see the actual loop gain curves and the
regulator output impedance curve.
Caution needs to be used in choosing the input resistor to
the FB pin. Excessively high resistance will cause an error to
the output voltage regulation due to the bias current flowing
in the FB pin. It is recommended to keep this resistor below
3k.
Droop using Discrete Resistor Sensing Static/Dynamic Mode of Operation
Figure 3 shows a detailed schematic using discrete resistor
sensing of the inductor current. Figure 14 shows the
equivalent circuit. Since the current sensing resistor voltage
represents the actual inductor current information, Rs and Cn
simply provide noise filtering. The most significant noise
comes from the ESL of the current sensing resistor. A low
low ESL sensing resistor is strongly recommended. The
recommended Rs is 100Ω and the recommended Cn is
220pF. Since the current sensing resistance does not
appreciably change with temperature, the NTC network is
not needed for thermal compensation.
Droop is designed the same way as the DCR sensing
approach. The voltage on the current sensing resistor is
given by the following equation:
Vrsen = Rsen ⋅ I o
(EQ. 28)
Equation 21shows the droop amplifier gain. So the actual
droop is given by
⎛ Rdrp 2 ⎞
⎟
Rdroop = Rsen ⋅ ⎜1 +
⎜ R ⎟
drp1 ⎠
⎝
(EQ. 29)
Solving for Rdrp2 yields:
⎛ Rdroop ⎞
Rdrp 2 = Rdrp1 ⋅ ⎜⎜
− 1⎟⎟
⎠
⎝ Rsen
(EQ. 30)
For example: Rdroop = 2.1mΩ. If Rsen = 1m and Rdrp1 = 1k,
easy calculation gives that Rdrp2 is 1.1k.
The current sensing traces should be routed directly to the
current sensing resistor pads for accurate measurement.
However, due to layout imperfections, the calculated Rdrp2
may still need slight adjustment to achieve optimum load line
slope. It is recommended to adjust Rdrp2 after the system
has achieved thermal equilibrium at full load.
FN9251.1
September 27, 2006
VSS
ISL6261
FIGURE 13. AN EXAMPLE OF ISL6261 COMPENSATION SPREADSHEET
22
FN9251.1
September 27, 2006
ISL6261
10uA
OCSET
Rocset
VO
OC
Rs
VSUM
Internal to
ISL6261
DROOP
DFB
Vrsen
R drp1
VO
I o Rsen
Cn
1
R drp2
DROOP
FIGURE 14. EQUIVALENT MODEL FOR DROOP CIRCUIT USING DISCRETE RESISTOR SENSING
Typical Performance (Data Taken on ISL6261 Eval1 Rev. C Evaluation Board)
FIGURE 15. CCM EFFICIENCY, VID = 1.1V,
VIN1 = 8V, VIN2 = 12.6V AND VIN3 = 19V
FIGURE 16. CCM LOAD LINE AND THE SPEC, VID = 1.1V,
VIN1 = 8V, VIN2 = 12.6V AND VIN3 = 19V
FIGURE 17. DEM EFFICIENCY, VID = 0.7625V,
VIN1 = 8V, VIN2 = 12.6V AND VIN3 = 19V
FIGURE 18. DEM LOAD LINE AND THE SPEC, VID = 0.7625V,
VIN1 = 8V, VIN2 = 12.6V AND VIN3 = 19V
23
FN9251.1
September 27, 2006
ISL6261
Typical Performance (Data Taken on ISL6261 Eval1 Rev. C Evaluation Board) (Continued)
FIGURE 19. ENHANCED DEM EFFICIENCY, VID = 0.7625V,
VIN1 = 8V, VIN2 = 12.6V AND VIN3 = 19V
FIGURE 20. ENHANCED DEM LOAD LINE, VID = 0.7625V,
VIN1 = 8V, VIN2 = 12.6V AND VIN3 = 19V
FIGURE 21. ENHANCED DEM EFFICIENCY, VID = 1.1V,
VIN1 = 8V, VIN2 = 12.6V AND VIN3 = 19V
FIGURE 22. ENHANCED DEM LOAD LINE, VID = 1.1V,
VIN1 = 8V, VIN2 = 12.6V AND VIN3 = 19V
5V/div
0.5V/div
10V/div
FIGURE 23. SOFT-START, VIN = 19V, Io = 0A, VID = 1.5V,
Ch1: VR_ON, Ch2: Vo, Ch4: PHASE
24
FIGURE 24. SOFT-START, VIN = 19V, Io = 0A, VID = 1.1V,
Ch1: VR_ON, Ch2: Vo, Ch4: PHASE
FN9251.1
September 27, 2006
ISL6261
Typical Performance (Data Taken on ISL6261 Eval1 Rev. C Evaluation Board) (Continued)
5V/div
0.2V/div
0.2V/div
5V/div
5V/div
5V/div
10V/div
5V/div
FIGURE 25. VBOOT TO VID, VIN = 19V, Io = 2A, VID = 1.5V,
Ch1: PGD_IN, Ch2: Vo, Ch3: CLK_EN#,
Ch4: PHASE
FIGURE 26. VBOOT TO VID, VIN = 19V, Io = 2A, VID = 0.7625V,
Ch1: PGD_IN, Ch2: Vo, Ch3: PGOOD,
Ch4: CLK_EN
5V/div
0.5V/div
7.5ms
5V/div
10V/div
FIGURE 27. CLK_EN AND PGOOD ASSERTION DELAY,
VIN=19V, Io=2A, VID=1.1V, Ch1: CLK_EN#,
Ch2: Vo, Ch3: PGOOD, Ch4: PHASE
FIGURE 28. SHUT DOWN, VIN = 19V, Io = 0.5A, VID = 1.5V,
Ch1: VR_ON, Ch2: Vo, Ch3: PGOOD,
Ch4: PHASE
FIGURE 29. SOFT START INRUSH CURRENT, VIN = 19V,
Io = 0.5A, VID = 1.1V, Ch1: DROOP-VO
(2.1mV = 1A), Ch2: Vo, Ch3: Vcomp, Ch4: PHASE
FIGURE 30. VIN TRANSIENT TEST, VIN = 8Æ19V, Io = 2A,
VID = 1.1V, Ch1: Vo, Ch3: VIN, Ch4: PHASE
25
FN9251.1
September 27, 2006
ISL6261
Typical Performance (Data Taken on ISL6261 Eval1 Rev. C Evaluation Board) (Continued)
FIGURE 31. C4 ENTRY/EXIT, VIN = 12.6V, Io = 0.7A,
HFM VID = 1.1V, LFM VID = 0.9V, C4
VID = 0.7625V, FDE = DPRSLPVR,
Ch1: DPRSTP#, Ch2: Vo, Ch3: DPRSLPVR/FDE,
Ch4: PHASE
100A/us
FIGURE 32. VID TOGGLING, VIN = 12.6V, Io= 0.7A,
HFM VID = 1.1V, LFM VID = 0.9V,
Ch1: SOFT, Ch2: Vo, Ch3: Vcomp, Ch4: PHASE
50A/us
FIGURE 33. LOAD STEP UP RESPONSE IN CCM,
VIN = 8V, Io = 2AÆ20A at 100A/us, VID = 1.1V,
Ch1: Io, Ch2: Vo, Ch3: Vcomp, Ch4: PHASE
50A/us
100A/us
FIGURE 35. LOAD TRANSIENT RESPONSE IN CCM
VIN = 8V, Io = 2AÅÆ20A, VID = 1.1V,
Ch1: Io, Ch2: Vo, Ch3: Vcomp, Ch4: PHASE
26
FIGURE 34. LOAD STEP DOWN RESPONSE IN CCM
VIN = 8V, Io = 20AÆ2A at 100A/us, VID = 1.1V,
Ch1: Io, Ch2: Vo, Ch3: Vcomp, Ch4: PHASE
100A/us
50A/us
FIGURE 36. LOAD TRANSIENT RESPONSE IN ENHANCED
DEM, VIN = 8V, Io = 2AÅÆ20A, VID = 1.1V,
Ch1: Io, Ch2: Vo, Ch3: Vcomp, Ch4: PHASE
FN9251.1
September 27, 2006
ISL6261
Typical Performance (Data Taken on ISL6261 Eval1 Rev. C Evaluation Board) (Continued)
50A/us
100A/us
FIGURE 37. LOAD TRANSIENT RESPONSE IN ENHANCED
DEM, VIN = 8V, Io = 2AÅÆ20A, VID = 1.1V,
Ch1: Io, Ch2: Vo, Ch3: Vcomp, Ch4: PHASE
FIGURE 38. LOAD TRANSIENT RESPONSE IN ENHANCED
DEM, VIN = 8V, Io = 2AÅÆ20A, VID = 1.1V,
Ch1: Io, Ch2: Vo, Ch3: Vcomp, Ch4: PHASE
120us
FIGURE 39. OVERCURRENT PROTECTION, VIN = 12.6V,
Io = 0AÆ28A, VID = 1.1V, Ch1: DROOP-VO
(2.1mV = 1A), Ch2: Vo, Ch3: PGOOD,
Ch4: PHASE
FIGURE 40. OVERVOLTAGE (>1.7V) PROTECTION,
VIN = 12.6V, Io = 2A, VID = 1.1V,
Ch2: Vo, Ch3: PGOOD, Ch4: PHASE
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
27
FN9251.1
September 27, 2006
A
B
C
GND_POWER
VSSSENSE
IN
IN
IN
8
VCORE
IN
1
VCCSENSE
VCC_PRM
Q5
2N7002
PGOOD
D3
+3.3V
GRN
3 R2 510 J9
1 12 2
1
RED
ON
ON
ON
ON
ON
R4
DROOP
0
R6
0
R5
DNP
6.34K
C3
R3
10
9
8
7
6
DPRSLPVR
PSI#
PGD_IN
DPRSTP#
SD05H0SK
FDE
1
2
3
4
5
10K
3
4
5
P6
VW
OCSET
47PF
C12
7
IN
VSUM
VCC_PRM
330PF
IN
1K
C7
R15
DFB
5.23K
C6
0
C9
150PF
R12
0
R11
COMP
SOFT
DNP R8 DNP
R7
P5
+3.3V1
R103
P7
P4
+3.3V
0
D
P10
P9
2
S1
10K
R10
C8
R9
R19
1000PF
C14
464K
IN
IN
IN
IN
OUT
J8
1 2 2 21
10K
R14
0.015UF
C10
DNP
R13
34
2
C2
R17 DNP R16
6.81K
C13
C11
CLK_EN#
PSI#
FDE
+3.3V
PGOOD
DPRSLPVR
OUT
R23
6
330PF
C18
0
C20
VDIFF1
41
1
2
3
4
5
6
7
8
9
10
1X3
J10
1
2 21
3 3
RTN
3V3
1UF
C24
J15
1 1 2 2
0
R30
DNP
C23
EP
FDE
PGD_IN
RBIAS
VR_TT
NTC
SOFT
OCSET
VW
COMP
FB
5
P23
ISL6261CR
U6
VID2
VID1
VID0
VCCP
LGATE
VSSP
PHASE
UGATE
BOOT
NC
4
R32
P31
0
R35
0
R34
0
R33
LGATE
GND_POWER
PHASE
UGATE
BOOT
VID6
VID5
VID4
VID3
VID2
VID1
VID0
1
OUT
OUT
OUT
OUT
OUT
3
VIN
1 2 2 +5V
J16
IN
IN
IN
IN
IN
IN
IN
10K
R36
IN
J17
2 2 1
+5V
1
4
3
NOTE:
RUN LGATE1 TRACE PARALLEL TO TRACE CONNECTING
PGND1 AND SOURCE OF Q3 AND Q4.
30
29
28
27
26
25
24
23
22
21
P28
P29
5
VR_ON
DPRSLPVR
DPRSTP#
VSEN
PGD_IN
390PF
2.21K
R25
R24
P12
RBIAS
VR_TT
5.49K
FB
1
R1 510
SSL_LXA3025IGC
10UF
P3
10K
R18
DNP
1000PF
1000PF
10K
499
C15
147K
10K
R21
R20
P1
R22
P11
0.1UF
C16
P13
DNP
P2
C17
0.12UF
C19
P16
4.53K
R28
R29
1
0.068UF
C21
P20
P21
DNP
C25
6
P30 DNP
P14
P15
P18
P17
8200PF
R27
P19
3.57K 10K NTC
R31
P24
C26
10K
R37
C28
P27
P26
PGOOD 40
3V3 39
CLK_EN 38
DPRSTP 37
DPRSLPVR 36
VR_ON 35
VID6 34
VID5 33
VID4 32
VID3 31
VDIFF
VSEN
RTN
DROOP
DFB
VO
VSUM
VIN
VSS
VDD
11
12
13
14
15
16
17
18
19
20
P25
0.22UF
10K
R38
P34
0.01UF
7
6
5
4
3
2
1
1
2
3
4
5
6
7
U1
14
13
12
11
10
9
8
+3.3V
MST7_SPST
1X3
J19
1
2 21
3 3
2
ISL6261 EVAL1
CONTROLLER
ENGINEER:
JIA WEI
DRAWN BY:
10K
10K
R45
R44
10K
3
1 S4
+3.3V
R43
5V
VR_ON1
+3.3V
TITLE:
IN
2
J2
10K
J1
7
C30
10K
R40
R39
C29
10K
R41
10
1UF
10K
R42
10UF
P33
P32
C27
P8
1UF
2
8
9
10
11
12
13
14
ON
OFF
10
R46
C31
28
10UF
1
3.3V
100
?
J4
J3
1
DATE:
MAR-14-05
SHEET:
1 OF 5
REV:
VR_ON
R47
8
A
B
C
D
ISL6261
ISL6261 Eval1 Rev. C Evaluation Board Schematic
P22
FN9251.1
September 27, 2006
29
FN9251.1
September 27, 2006
A
B
C
D
BOOT
PHASE
LGATE
IN
IN
IN
8
UGATE
IN
8
0
R48
P36
P35
0.22UF
C1
7
7
Q2
Q4
6
IRF7832
Q3
Q1
IRF7832
IRF7821
IRF7821
VIN
OUT
R49
C33
D2
6
DNP
DNP
2
C32
1UF
1
10UF
DNP
C4
J20 4
10UF C5
10UF C5B
3
R82
5
J21 4
1
2
5
56UF
R83
1
3
1
2
1
56UF
C34
J5
J6
0.1UF
VSSSENSE
VCCSENSE
VSUM
OUT
P37
P38
4
R50
R51
P39
IN
IN
DNP
R52
L1
0.45UH
R53
P40
DNP
R54
R60
BUS WIRE
J22 4
0
3
1
2
3
1
J13
3
C35
4
0
7.68K
VCC_PRM
OUT
P41
0.1UF
C91
0.1UF
C42
C45
C39
C43
22UF
2
C56
C57
22UF
22UF
22UF
C49
330UF
C44
330UF
C55
C90
22UF
C61
330UF
C46
C47
C48
22UF
22UF
22UF
C37
C38
C59
C60
22UF
22UF
C53
C54
22UF
22UF
C36
C40
330UF
330UF
22UF
C41
C52
C89
22UF
22UF
C65
C66
22UF
22UF
22UF
C58
330UF
C64
22UF
C70
1
OUT
OUT
DATE:
MAR-14-05
SHEET:
2 OF 5
1
REV:
1
J14
GND_POWER
22UF
22UF
22UF
C67
22UF
22UF
VCORE
ISL6261 EVAL1
POWER STAGE
ENGINEER:
JIA WEI
DRAWN BY:
22UF
22UF
C68
C69
22UF
2
TITLE:
C50
C51
22UF
C62
C63
22UF
22UF
22UF
C71
22UF
A
B
C
D
ISL6261 Eval1 Rev. C Evaluation Board Schematic
(Continued)
ISL6261
A
B
C
VCORE
IN
OUT
8
A7
A9
A10
A12
A13
A15
A17
A18
A20
B7
B9
B10
B12
B14
B15
B17
B18
B20
C9
C10
C12
C13
C15
C17
C18
D9
D10
D12
D14
D15
D17
D18
E7
E9
E10
E12
E13
E15
E17
E18
E20
F7
F9
F10
F12
F14
F15
F17
F18
F20
AA7
AA9
AA10
AA12
AA13
AA15
AA17
AF7
B26
VCCSENSE
VCCA
VCCSENSE
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
7
AF20
AF18
AF17
AF15
AF14
AF12
AF10
AF9
AE20
AE18
AE17
AE15
AE13
AE12
AE10
AE9
AD18
AD17
AD15
AD14
AD12
AD10
AD9
AD7
AC18
AC17
AC15
AC13
AC12
AC10
AC9
AC7
AB20
AB18
AB17
AB15
AB14
AB12
AB10
AB9
AB7
AA20
AA18
G21
J6
J21
K6
K21
M6
M21
N6
N21
R6
R21
T6
T21
V6
V21
W21
6
A3
A5
A6
A21
A22
A24
A25
B1
B2
B3
B4
B5
B22
B23
B25
C1
C3
C4
C6
C7
C20
C21
C23
C24
C26
D2
D3
D5
D6
D7
D20
D21
D22
D24
D25
E1
E2
E4
E5
E22
E23
E25
E26
F1
F3
F4
F6
F21
F23
F24
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
5
4
PSI#
AE6
OUT
AD26
AE2 VID6
AF2 VID5 OUT
AE3 VID4 OUT
AF4 VID3 OUT
AE5 VID2 OUT
OUT
AF5 VID1 OUT
AD6 VID0 OUT
AF26
AF25
AF23
AF22
AF1
AE25
AE24
AE22
AE21
AD24
AD23
AD21
AD20
AD4
AD3
AD1
AC26
AC25
AC23
AC22
AC20
AC5
AC4
AC2
AC1
AB25
AB24
AB22
AB21
AB6
AB5
AB3
AB2
AA26
AA24
AA23
AA21
AA6
SOCKET1
INTEL_IMPV6
COMP3
COMP1
COMP2
COMP0
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
PSI
GTLREF
VID6
VID5
VID4
VID3
VID2
VID1
VID0
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
D
6
5
4
W22
W6
W5
W3
W2
V26
V24
V23
V4
V3
U25
U23
U22
U5
U4
U2
T25
T24
T22
T5
T3
T2
R24
R23
R4
R3
R1
P26
P25
P23
P22
P5
P4
V1
U26
U1
R26
AA4
AA3
AA1
Y26
Y25
Y23
Y22
Y5
Y4
Y2
Y1
W25
W24
3
3
A4
A8
A11
A14
A16
A19
A23
A26
B6
B8
B11
B13
B16
B19
B21
B24
C2
C5
C8
C11
C14
C16
C19
C22
C25
D1
D4
D8
D11
D13
D16
D19
D23
D26
E3
E6
E8
E11
E14
E16
E19
E21
E24
F2
F5
F8
F11
F13
F16
F19
F22
F25
G1
G4
G23
G26
H3
H6
H21
H24
J2
J5
J22
J25
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
2
ISL6261 EVAL1
SOCKET
ENGINEER:
JIA WEI
DRAWN BY:
TITLE:
GND_POWER
IN
30
K1
K4
K23
K26
L3
L6
L21
L24
M2
M5
M22
M25
N1
N4
N23
N26
AE7
7
SOCKET1
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
INTEL_IMPV6
VSSSENSE
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
F26
G2
G3
G5
G6
G22
G24
G25
H1
H2
H4
H5
H22
H23
H25
H26
J1
J3
J4
J23
J24
J26
K2
K3
K5
K22
K24
K25
L1
L2
L4
L5
L22
L23
L25
L26
M1
M3
M4
M23
M24
M26
N2
N3
N5
N22
N24
N25
P1
P2
AF24
AF21
AF19
AF16
AF13
AF11
AF8
AF6
AF3
AE26
AE23
AE19
AE16
AE14
AE11
AE8
AE4
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
OUT
AE1
AD25
AD22
AD19
AD16
AD13
AD11
AD8
AD5
AD2
AC24
AC21
AC19
AC16
AC14
AC11
AC8
AC6
AC3
AB26
AB23
AB19
AB16
AB13
AB11
AB8
AB4
AB1
AA25
AA22
AA19
AA16
AA14
AA11
AA8
AA5
AA2
Y24
Y21
Y6
Y3
W26
W23
W4
W1
V25
V22
V5
V2
U24
U21
U6
U3
T26
T23
T4
T1
R25
R22
R5
R2
P24
P21
P6
P3
1
DATE:
MAR-14-05
SHEET:
3 OF 5
REV:
1
A
B
C
D
ISL6261 Eval1 Rev. C Evaluation Board Schematic
VSSSENSE
8
ISL6261
(Continued)
INTEL_IMPV6
SOCKET1
FN9251.1
September 27, 2006
1
J11
1
4
3
2
+12V
+12V
1UF
Q14
2N7002
LO
VSS
LI
HI
499
R72
HIP2100
VDD
HB
HO
HS
U5
5
6
7
8
C81
+12V
2
S5 1
ON
3
OFF
249
R73
249
R74
1
2
BAV99
D1
3
IN
1
R75
VCORE
Q15
HUF76129D3S
2
3
0.1
R76
C80
R71
3
2
GND_POWER
1
2
4 J23
ISL6261 Eval1 Rev. C Evaluation Board Schematic
49.9K
0.12
31
J12
GND_POWER
ISL6261
(Continued)
FN9251.1
September 27, 2006
3
10UF
A
B
C
D
7
6
5
4
3
2
1
7
6
5
4
3
2
1
7
6
5
4
3
2
1
2
3
4
5
6
7
1
2
3
4
5
6
7
8
+3.3V
14 14
13 13
12 12
11 11
10 10
9 9
8 8
MST7_SPST
U9
MST7_SPST
14 14
13 13
12 12
11 11
10 10
9 9
8 8
MST7_SPST
U8
R81
14 14
13 13
12 12
11 11
10 10
9 9
8 8
10K
R84
1
7
J24
1 2 2 +3.3V_GEY
10K
R85
10K
R86
10K
R87
10K
R88
10K
R89
10K
R90
10K
R91
10K
R92
10K
R93
10K
R94
10K
R95
10K
R96
10K
R97
10K
R98
10K
10K
R100
10K
R99
10K
10K
10K
R101
U7
1
10
9
8
7
6
5
4
3
2
1
10
9
8
7
6
5
4
3
2
1
10
9
8
7
6
5
4
3
2
Y4
Y5
Y6
Y7
Y8
A5
A6
A7
A8
GND
HC540
Y7
Y8
A8
GND
Y8
GND
10K
10K
10K
10K
R58
R59
R61
R62
6
Y7
A8
10K
Y6
A7
R57
Y5
10K
Y4
A5
A6
R56
Y3
A4
10K
Y2
A3
R55
Y1
A2
HC540
G2
A1
VCC
Y6
A7
G1
Y5
A6
U4
Y3
Y4
Y2
A3
A5
Y1
A2
A4
G2
A1
VCC
Y3
A4
G1
Y2
A3
U3
Y1
A2
VCC
G2
HC540
U2
A1
G1
11
12
13
14
15
16
17
18
19
20
11
12
13
14
15
16
17
18
19
20
11
12
13
14
15
16
17
18
19
20
C72
0.1UF
C74
+3.3V_GEY
0.1UF
C73
+3.3V_GEY
0.1UF
+3.3V_GEY
5
4
7
28
18
31
30
19
20
21
22
23
24
33
34
8
9
10
11
14
15
16
17
S2
EVQPA
J29
1 1 2 2
EVQPA
PSI#
+3.3V_GEY
2
PSI# S7
1
1
J25
1 2 2
EVQPA
LOOP
+3.3V_GEY
2
DPRSLP
S6
1
2
1
MODE TRANS
DNP
0
+3.3V_GEY
+3.3V_GEY
VDD
VDD
RB0
RB1
RB2
RB3
RB4
RB5
RB6
RB7
NC
NC
RA0
RA1
RA2
RA3
RA4
RA5
OSC1
OSC2
MCLR
3
1UF
C78
PIC16F874 +3.3V_GEYR69
R104
10K
RC0
RC1
RC2
RC3
RC4
RC5
RC6
RC7
NC
NC
RD0
RD1
RD2
RD3
RD4
RD5
RD6
RD7
RE0
RE1
RE2
VSS
VSS
CLK_EN# R67
+3.3V_GEY
IN
6
29
25
26
27
38
39
40
41
2
3
4
5
12
13
32
35
36
37
42
43
44
1
U10
3
4
3
4
3
4
3
DNP
R106
10K
R77
1
2
1
1
7
6
5
4
3
2
2
AC04
3
4
6A
6Y
5A
5Y
4A
4Y
Vcc
1UF
C86
+3.3V
2
DIRECT
8
9
10
11
12
13
14
DELAY
DPRSLPVR
1
OUT
2
1
REV:
TITLE:
ISL6261 EVAL1
GEYSERVILLE TRANSITION GEN.
ENGINEER:
DATE:
MAR-14-05
JIA WEI
DRAWN BY:
SHEET:
5 OF 5
3A
3Y
GND
1A
1Y
2A
2Y
EVQPA
J28
1 2 2
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
U12
HCM49
U11
RESETS8
1
PSI#
DPRSTP#
PGD_IN
VR_ON1
VID0
VID1
VID2
VID3
VID4
VID5
VID6
C85
1
2
3
4
5
6
7
4
R105
R68
R82
R83
C87
1
5
0
DNP
J7
15PF
6
R63
C75
R64
C76
BAV99
7
10K
0.1UF
10K
0.1UF
10K
0.1UF
10K
10K
S3
R70 0
R65
C77
R66
R102
C79
3
0.01UF
2
1
C84
15PF
P43
P42
BAV99
R78 0
DNP
1X3
3
R79 0
C88
P45
P44
1
2 21
3 3
S9
2
1
32
R80 0
A
B
C
D
ISL6261 Eval1 Rev. C Evaluation Board Schematic
DNP
8
ISL6261
(Continued)
FN9251.1
September 27, 2006
ISL6261
Package Outline Drawing
L40.6x6
40 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 2, 9/06
4X 4.5
6.00
36X 0.50
A
B
6
PIN 1
INDEX AREA
6
PIN #1 INDEX AREA
40
31
30
1
6.00
4 . 10 ± 0 . 15
21
10
0.15
(4X)
11
20
0.10 M C A B
TOP VIEW
40X 0 . 4 ± 0 . 1
4 0 . 23 +0 . 07 / -0 . 05
BOTTOM VIEW
SEE DETAIL "X"
0.10 C
0 . 90 ± 0 . 1
(
C
BASE PLANE
( 5 . 8 TYP )
SEATING PLANE
0.08 C
SIDE VIEW
4 . 10 )
( 36X 0 . 5 )
C
0 . 2 REF
5
( 40X 0 . 23 )
0 . 00 MIN.
0 . 05 MAX.
( 40X 0 . 6 )
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between .015mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
33
FN9251.1
September 27, 2006
ISL6261
Package Outline Drawing
L48.7x7
48 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 3, 9/06
4X 5.5
7.00
A
44X 0.50
B
37
6
PIN 1
INDEX AREA
6
PIN #1 INDEX AREA
48
1
7.00
36
4. 30 ± 0 . 15
12
25
(4X)
0.15
13
24
0.10 M C A B
48X 0 . 40± 0 . 1
TOP VIEW
4 0.23 +0.07 / -0.05
BOTTOM VIEW
SEE DETAIL "X"
( 6 . 80 TYP )
(
0.10 C
BASE PLANE
0 . 90 ± 0 . 1
4 . 30 )
C
SEATING PLANE
0.08 C
SIDE VIEW
( 44X 0 . 5 )
C
0 . 2 REF
5
( 48X 0 . 23 )
( 48X 0 . 60 )
0 . 00 MIN.
0 . 05 MAX.
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between .015mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
34
FN9251.1
September 27, 2006
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