ISL6323B
®
Data Sheet
March 23, 2009
Monolithic Dual PWM Hybrid Controller
Powering AMD SVI Split-Plane and PVI
Uniplane Processors
Features
The ISL6323B dual PWM controller delivers high efficiency
and tight regulation from two synchronous buck DC/DC
converters. The ISL6323B supports hybrid power control of
AMD processors which operate from either a 6-bit parallel
VID interface (PVI) or a serial VID interface (SVI). The dual
output ISL6323B features a multi-phase controller to support
uniplane VDD core voltage and a single phase controller to
power the Northbridge (VDDNB) in SVI mode. Only the
multi-phase controller is active in PVI mode to support
uniplane VDD only processors.
A precision uniplane core voltage regulation system is
provided by a two-to-four-phase PWM voltage regulator (VR)
controller. The integration of two power MOSFET drivers,
adding flexibility in layout, reduce the number of external
components in the multi-phase section. A single phase PWM
controller with integrated driver provides a second precision
voltage regulation system for the North Bridge portion of the
processor. This monolithic, dual controller with integrated
driver solution provides a cost and space saving power
management solution.
For applications which benefit from load line programming to
reduce bulk output capacitors, the ISL6323B features output
voltage droop. The multi-phase portion also includes
advanced control loop features for optimal transient
response to load apply and removal. One of these features
is highly accurate, fully differential, continuous DCR current
sensing for load line programming and channel current
balance. Dual edge modulation is another unique feature,
allowing for quicker initial response to high di/dt load
transients.
The ISL6323B supports Power Savings Mode by dropping
the number of phases to two when the PSI_L bit is set.
Ordering Information
TEMP.
RANGE
(°C)
• Processor Core Voltage Via Integrated Multi-Phase
Power Conversion
• Configuration Flexibility
- 2-Phase Operation with Internal Drivers
- 3- or 4-Phase Operation with External PWM Drivers
• PSI_L Support with Phase Shedding for Improved
Efficiency at Light Load
• Serial VID Interface Inputs
- Two Wire, Clock and Data, Bus
- Conforms to AMD SVI Specifications
• Parallel VID Interface Inputs
- 6-bit VID input
- 0.775V to 1.55V in 25mV Steps
- 0.375V to 0.7625V in 12.5mV Steps
• Precision Core Voltage Regulation
- Differential Remote Voltage Sensing
- ±0.6% System Accuracy Over-Temperature
- Adjustable Reference-Voltage Offset
• Optimal Processor Core Voltage Transient Response
- Adaptive Phase Alignment (APA)
- Active Pulse Positioning Modulation
• Fully Differential, Continuous DCR Current Sensing
- Accurate Load Line Programming
- Precision Channel Current Balancing
• Variable Gate Drive Bias: 5V to 12V
• Overcurrent Protection
• Multi-tiered Overvoltage Protection
• Selectable Switching Frequency up to 1MHz
• Simultaneous Digital Soft-Start of Both Outputs
• Processor NorthBridge Voltage Via Single Phase
Power Conversion
• Precision Voltage Regulation
- Differential Remote Voltage Sensing
- ±0.6% System Accuracy Over Temperature
ISL6323BCRZ*
ISL6323B CRZ 0 to +70 48 Ld 7x7 QFN L48.7x7
• Serial VID Interface Inputs
- Two Wire, Clock and Data, Bus
- Conforms to AMD SVI Specifications
ISL6323BIRZ*
ISL6323B IRZ -40 to +85 48 Ld 7x7 QFN L48.7x7
• Overcurrent Protection
PART NUMBER
(Note)
PART
MARKING
PACKAGE
(Pb-free)
PKG.
DWG. #
*Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel
specifications.
NOTE: These Intersil Pb-free plastic packaged products employ special
Pb-free material sets, molding compounds/die attach materials, and
100% matte tin plate plus anneal (e3 termination finish, which is RoHS
compliant and compatible with both SnPb and Pb-free soldering
operations). Intersil Pb-free products are MSL classified at Pb-free peak
reflow temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
1
FN6879.0
• Continuous DCR Current Sensing
• Variable Gate Drive Bias: 5V to 12V
• Simultaneous Digital Soft-Start of Both Outputs
• Selectable Switching Frequency up to 1MHz
• Pb-Free (RoHS Compliant)
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2009. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL6323B
Pinout
COMP_NB
ISEN_NB-
ISEN4+
ISEN4-
ISEN3+
ISEN3-
PVCC_NB
LGATE_NB
BOOT_NB
UGATE_NB
PHASE_NB
VDDPWRGD
ISL6323B
(48 LD QFN)
TOP VIEW
48
47
46
45
44
43
42
41
40
39
38
37
FB_NB
1
36
PWM4
ISEN_NB+
2
35
PWM3
RGND_NB
3
34
PWROK
VID0/VFIXEN
4
33
PHASE1
VID1/SEL
5
32
UGATE1
VID2/SVD
6
31
BOOT1
VID3/SVC
7
30
LGATE1
VID4
8
29
PVCC1_2
VID5
9
28
LGATE2
VCC 10
27
BOOT2
FS 11
26
UGATE2
RGND 12
25
PHASE2
13
14
15
16
17
18
19
20
21
22
23
24
VSEN
OFS
DVC
RSET
FB
COMP
APA
ISEN1+
ISEN1-
ISEN2+
ISEN2-
EN
49
GND
Integrated Driver Block Diagram
PVCC
BOOT
UGATE
PWM
20KΩ
SOFT-START
AND
FAULT LOGIC
GATE
CONTROL
LOGIC
SHOOTTHROUGH
PROTECTION
PHASE
10KΩ
LGATE
2
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March 23, 2009
ISL6323B
Controller Block Diagram
RGND_NB
NB_REF
COMP_NB
FB_NB
∑
BOOT_NB
E/A
ISEN_NB+
UV
LOGIC
CURRENT
SENSE
ISEN_NB-
MOSFET
DRIVER
OV
LOGIC
RAMP
UGATE_NB
PHASE_NB
LGATE_NB
VDDPWRGD
EN_12V
PVCC_NB
APA
APA
NB
FAULT
LOGIC
COMP
OFS
ENABLE
LOGIC
EN
VCC
POWER-ON
RESET
OFFSET
PVCC1_2
SOFT-START
AND
FB
FAULT LOGIC
E/A
DVC
RGND
2X
BOOT1
∑
DROOP
CONTROL
LOAD APPLY
TRANSIENT
ENHANCEMENT
PWROK
VID0/VFIXEN
VID1/SEL
VID2/SVD
VID3/SVC
VID4
MOSFET
DRIVER
UGATE1
PHASE1
LGATE1
SVI
SLAVE
BUS
AND
PVI
DAC
CLOCK AND
TRIANGLE WAVE
GENERATOR
FS
VID5
PWM1
∑
NB_REF
BOOT2
OV
LOGIC
PWM2
∑
VSEN
UV
LOGIC
RSET
MOSFET
DRIVER
PWM3
ISEN1-
PHASE2
LGATE2
∑
OC
RESISTOR
MATCHING
PH3/PH4
POR
PWM4
ISEN1+
UGATE2
I_TRIP
CH1
CURRENT
SENSE
I_AVG
∑
EN_12V
CHANNEL
DETECT
ISEN3ISEN4-
ISEN2+
ISEN2ISEN3+
ISEN3-
CH2
CURRENT
SENSE
CHANNEL
CURRENT
BALANCE
ISEN4-
1
N
PWM3
SIGNAL
LOGIC
CH3
CURRENT
SENSE
PWM3
∑
ISEN3-
ISEN4+
I_AVG
CH4
CURRENT
SENSE
PWM4
SIGNAL
LOGIC
PWM4
ISEN4-
GND
3
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March 23, 2009
ISL6323B
Typical Application - SVI Mode
+12V
+12V
FB
COMP
ISEN3+
ISEN3PWM3
VSEN
BOOT1
BOOT1
UGATE1
UGATE1
PHASE1
PHASE1
LGATE1
LGATE1
PWM1
PGND
APA
ISEN1ISEN1+
DVC
ISL6614
+12V
+5V
PVCC1_2
VDD
+12V
VCC
+12V
VCC
BOOT2 PVCC
BOOT2
OFS
UGATE2
FS
PHASE2
+5V
RSET
NC
NC
UGATE2 GND
PHASE2
CPU
LOAD
PWM2
LGATE2
LGATE2
VFIXEN
ISEN2SEL
ISEN2+
SVD
SVC
RGND
VID4
VID5
PWROK
VDDPWRGD ISEN4+
GND
ISEN4PWM4
+12V
ISL6323B
+12V
PVCC_NB
OFF
EN
BOOT_NB
ON
UGATE_NB
PHASE_NB
VDDNB
LGATE_NB
COMP_NB ISEN_NB-
NB
LOAD
ISEN_NB+
FB_NB
4
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March 23, 2009
ISL6323B
Typical Application - PVI Mode
+12V
+12V
FB
COMP
ISEN3+
ISEN3PWM3
VSEN
BOOT1
BOOT1
UGATE1
UGATE1
PHASE1
PHASE1
LGATE1
APA
LGATE1
DVC
ISEN1ISEN1+
ISL6614
+12V
+5V
PWM1
PGND
VDD
+12V
PVCC1_2
VCC
+12V
VCC
BOOT2 PVCC
BOOT2
+5V
OFS
UGATE2
FS
PHASE2
PHASE2
CPU
LOAD
PWM2
LGATE2
LGATE2
RSET
NC
UGATE2GND
VID0
ISEN2VID1/SEL
ISEN2+
VID2
VID3
RGND
VID4
VID5
PWROK
VDDPWRGD ISEN4+
GND
ISEN4PWM4
ISL6323B
+12V
+12V
NORTH BRIDGE REGULATOR
PVCC_NB
OFF
DISABLED IN PVI MODE
EN
BOOT_NB
ON
UGATE_NB
PHASE_NB
VDDNB
LGATE_NB
COMP_NB ISEN_NB-
NB
LOAD
ISEN_NB+
FB_NB
5
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March 23, 2009
ISL6323B
Absolute Maximum Ratings
Thermal Information
Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.2V
Supply Voltage (PVCC) . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +15V
Absolute Boot Voltage (VBOOT). . . . . . . . GND - 0.3V to GND + 36V
Phase Voltage (VPHASE) . . . . . . . . GND - 0.3V to 15V (PVCC = 12)
GND - 8V ( ------------------------------------2 ⋅ π ⋅ C ⋅ ESR
2 ⋅ π ⋅ f 0 ⋅ V P-P ⋅ L
R C = R FB ⋅ ---------------------------------------------0.66 ⋅ V IN ⋅ ESR
0.66 ⋅ V IN ⋅ ESR ⋅ C
C C = ----------------------------------------------------------------2 ⋅ π ⋅ V P-P ⋅ R FB ⋅ f 0 ⋅ L
Compensation Without Loadline Regulation
The non load-line regulated converter is accurately modeled
as a voltage-mode regulator with two poles at the L-C
resonant frequency and a zero at the ESR frequency. A
type III controller, as shown in Figure 23, provides the
necessary compensation.
The first step is to choose the desired bandwidth, f0, of the
compensated system. Choose a frequency high enough to
assure adequate transient performance but not higher than 1/3
of the switching frequency. The type-III compensator has an
extra high-frequency pole, fHF. This pole can be used for added
noise rejection or to assure adequate attenuation at the erroramplifier high-order pole and zero frequencies. A good general
rule is to choose fHF = 10f0, but it can be higher if desired.
Choosing fHF to be lower than 10f0 can cause problems with
too much phase shift below the system bandwidth.
C2
RC
CC
COMP
FB
C1
R1
ISL6323B
RFB
VSEN
FIGURE 23. COMPENSATION CIRCUIT WITHOUT LOAD-LINE
REGULATION
29
FN6879.0
March 23, 2009
ISL6323B
pulsating voltage at the phase nodes. The output filter also
must provide the transient energy until the regulator can
respond. Because it has a low bandwidth compared to the
switching frequency, the output filter limits the system
transient response. The output capacitors must supply or
sink load current while the current in the output inductors
increases or decreases to meet the demand.
.
C ⋅ ESR
R 1 = R FB ⋅ -------------------------------------------L ⋅ C – C ⋅ ESR
L ⋅ C – C ⋅ ESR
C 1 = -------------------------------------------R FB
0.75 ⋅ V IN
C 2 = ---------------------------------------------------------------------------------------------------( 2 ⋅ π ) 2 ⋅ f 0 ⋅ f HF ⋅ ( L ⋅ C ) ⋅ R FB ⋅ V P-P
(EQ. 52)
2
V P-P ⋅ ⎛ 2π⎞ ⋅ f 0 ⋅ f HF ⋅ L ⋅ C ⋅ R FB
⎝ ⎠
R C = ----------------------------------------------------------------------------------------0.75 ⋅ V IN ⋅ ( 2 ⋅ π ⋅ f HF ⋅ L ⋅ C – 1 )
0.75 ⋅ V IN ⋅ ( 2 ⋅ π ⋅ f HF ⋅ L ⋅ C – 1 )
C C = ---------------------------------------------------------------------------------------------------( 2 ⋅ π ) 2 ⋅ f 0 ⋅ f HF ⋅ ( L ⋅ C ) ⋅ R FB ⋅ V P-P
In the solutions to the compensation equations, there is a
single degree of freedom. For the solutions presented in
Equation 53, RFB is selected arbitrarily. The remaining
compensation components are then selected according to
Equation 53.
In Equation 53, L is the per-channel filter inductance divided
by the number of active channels; C is the sum total of all
output capacitors; ESR is the equivalent-series resistance of
the bulk output-filter capacitance; and VPP is the peak-topeak sawtooth signal amplitude as described in Electrical
Specifications on page 6.
Case 1:
(EQ. 54)
2 ⋅ π ⋅ f 0 ⋅ V P-P ⋅ L ⋅ C
R C = R FB ⋅ ---------------------------------------------------------0.66 ⋅ V
The filter capacitor must have sufficiently low ESL and ESR
so that ΔV < ΔVMAX.
0.66 ⋅ V IN
C C = --------------------------------------------------2 ⋅ π ⋅ V PP ⋅ R FB ⋅ f 0
Most capacitor solutions rely on a mixture of high frequency
capacitors with relatively low capacitance in combination
with bulk capacitors having high capacitance but limited
high-frequency performance. Minimizing the ESL of the
high-frequency capacitors allows them to support the output
voltage as the current increases. Minimizing the ESR of the
bulk capacitors allows them to supply the increased current
with less output voltage deviation.
1
1
-------------------------------- ≤ f 0 < -----------------------------------2 ⋅ π ⋅ C ⋅ ESR
2⋅π⋅ L⋅C
V P-P ⋅ ( 2 ⋅ π ) 2 ⋅ f 02 ⋅ L ⋅ C
R C = R FB ⋅ -----------------------------------------------------------------0.66 ⋅ V IN
(EQ. 53)
0.66 ⋅ V IN
C C = ------------------------------------------------------------------------------------( 2 ⋅ π ) 2 ⋅ f 02 ⋅ V PP ⋅ R FB ⋅ L ⋅ C
Case 3:
At the beginning of the load transient, the output capacitors
supply all of the transient current. The output voltage will
initially deviate by an amount approximated by the voltage
drop across the ESL. As the load current increases, the
voltage drop across the ESR increases linearly until the load
current reaches its final value. The capacitors selected must
have sufficiently low ESL and ESR so that the total
output-voltage deviation is less than the allowable maximum.
Neglecting the contribution of inductor current and regulator
response, the output voltage initially deviates by an amount
as shown in Equation 54
di
ΔV ≈ ESL ⋅ ----- + ESR ⋅ ΔI
dt
1
-------------------------------- > f 0
2⋅π⋅ L⋅C
IN
Case 2:
In high-speed converters, the output capacitor bank is usually
the most costly (and often the largest) part of the circuit.
Output filter design begins with minimizing the cost of this part
of the circuit. The critical load parameters in choosing the
output capacitors are the maximum size of the load step, ΔI,
the load-current slew rate, di/dt, and the maximum allowable
output-voltage deviation under transient loading, ΔVMAX.
Capacitors are characterized according to their capacitance,
ESR, and ESL (equivalent series inductance).
1
f 0 > ------------------------------------2 ⋅ π ⋅ C ⋅ ESR
2 ⋅ π ⋅ f 0 ⋅ V P-P ⋅ L
R C = R FB ⋅ ---------------------------------------------0.66 ⋅ V IN ⋅ ESR
0.66 ⋅ V IN ⋅ ESR ⋅ C
C C = ----------------------------------------------------------------2 ⋅ π ⋅ V P-P ⋅ R FB ⋅ f 0 ⋅ L
The ESR of the bulk capacitors also creates the majority of
the output-voltage ripple. As the bulk capacitors sink and
source the inductor AC ripple current (see “Interleaving” on
page 11 and Equation 3), a voltage develops across the bulk
capacitor ESR equal to IC(P-P ) (ESR). Thus, once the output
capacitors are selected, the maximum allowable ripple
voltage, VP-P(MAX), determines the lower limit on the
inductance..
⎛V – N ⋅ V
⎞
OUT⎠ ⋅ V OUT
⎝ IN
L ≥ ESR ⋅ -------------------------------------------------------------------f S ⋅ V IN ⋅ V P-P( MAX )
(EQ. 55)
Output Filter Design
The output inductors and the output capacitor bank together
to form a low-pass filter responsible for smoothing the
30
Since the capacitors are supplying a decreasing portion of
the load current while the regulator recovers from the
FN6879.0
March 23, 2009
ISL6323B
Equation 56 gives the upper limit on L for the cases when
the trailing edge of the current transient causes a greater
output-voltage deviation than the leading edge. Equation 57
addresses the leading edge. Normally, the trailing edge
dictates the selection of L because duty cycles are usually
less than 50%. Nevertheless, both inequalities should be
evaluated, and L should be selected based on the lower of
the two results. In each equation, L is the per-channel
inductance, C is the total output capacitance, and N is the
number of active channels.
2 ⋅ N ⋅ C ⋅ VO
L ≤ --------------------------------- ⋅ ΔV MAX – ( ΔI ⋅ ESR )
( ΔI ) 2
(EQ. 56)
⋅N⋅C
----------------------------- ⋅ ΔV MAX – ( ΔI ⋅ ESR ) ⋅ ⎛ V IN – V O⎞
L ≤ 1.25
⎝
⎠
( ΔI ) 2
(EQ. 57)
Input Capacitor Selection
The input capacitors are responsible for sourcing the AC
component of the input current flowing into the upper
MOSFETs. Their RMS current capacity must be sufficient to
handle the AC component of the current drawn by the upper
MOSFETs which is related to duty cycle and the number of
active phases.
0.3
INPUT-CAPACITOR CURRENT (IRMS/IO)
transient, the capacitor voltage becomes slightly depleted.
The output inductors must be capable of assuming the entire
load current before the output voltage decreases more than
ΔVMAX. This places an upper limit on inductance.
There are a number of variables to consider when choosing
the switching frequency, as there are considerable effects on
the upper MOSFET loss calculation. These effects are
outlined in “MOSFETs” on page 24, and they establish the
upper limit for the switching frequency. The lower limit is
established by the requirement for fast transient response
and small output-voltage ripple as outlined in “Output Filter
Design” on page 30. Choose the lowest switching frequency
that allows the regulator to meet the transient-response
requirements.
Switching frequency is determined by the selection of the
frequency-setting resistor, RT. Figure 24 and Equation 58
are provided to assist in selecting the correct value for RT.
R T = 10
[10.61 – ( 1.035 ⋅ log ( f S ) ) ]
(EQ. 58)
0.1
0
10
10k
100k
1M
SWITCHING FREQUENCY (Hz)
FIGURE 24. RT vs SWITCHING FREQUENCY
31
10M
0.4
0.6
0.8
1.0
FIGURE 25. NORMALIZED INPUT-CAPACITOR RMS CURRENT
vs DUTY CYCLE FOR 4-PHASE CONVERTER
For a four-phase design, use Figure 25 to determine the
input-capacitor RMS current requirement set by the duty
cycle, maximum sustained output current (IO), and the ratio
of the peak-to-peak inductor current (IL(P-P)) to IO. Select a
bulk capacitor with a ripple current rating which will minimize
the total number of input capacitors required to support the
RMS current calculated.
The voltage rating of the capacitors should also be at least
1.25x greater than the maximum input voltage. Figures 26 and
27 provide the same input RMS current information for 3-phase
and two-phase designs respectively. Use the same approach
for selecting the bulk capacitor type and number.
INPUT-CAPACITOR CURRENT (IRMS/IO)
RT (kΩ)
100
0.2
DUTY CYCLE (VO/VIN)
0.3
1k
IL(P-P) = 0.5 IO
IL(P-P) = 0.75 IO
0.2
0
Switching Frequency
IL(P-P) = 0
IL(P-P) = 0.25 IO
IL(P-P) = 0
IL(P-P) = 0.5 IO
IL(P-P) = 0.25 IO
IL(P-P) = 0.75 IO
0.2
0.1
0
0
0.2
0.4
0.6
0.8
1.0
DUTY CYCLE (VIN/VO)
FIGURE 26. NORMALIZED INPUT-CAPACITOR RMS
CURRENT FOR 3-PHASE CONVERTER
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March 23, 2009
ISL6323B
Low capacitance, high-frequency ceramic capacitors are
needed in addition to the input bulk capacitors to suppress
leading and falling edge voltage spikes. The spikes result from
the high current slew rate produced by the upper MOSFET
turn on and off. Select low ESL ceramic capacitors and place
one as close as possible to each upper MOSFET drain to
minimize board parasitics and maximize suppression.
INPUT-CAPACITOR CURRENT (IRMS/IO)
0.3
0.2
IL(P-P) = 0
IL(P-P) = 0.5 IO
IL(P-P) = 0.75 IO
0
0.2
When placing the MOSFETs try to keep the source of the
upper FETs and the drain of the lower FETs as close as
thermally possible. Input high-frequency capacitors, CHF,
should be placed close to the drain of the upper FETs and the
source of the lower FETs. Input bulk capacitors, CBULK, case
size typically limits following the same rule as the
high-frequency input capacitors. Place the input bulk
capacitors as close to the drain of the upper FETs as possible
and minimize the distance to the source of the lower FETs.
Locate the output inductors and output capacitors between the
MOSFETs and the load. The high-frequency output decoupling
capacitors (ceramic) should be placed as close as practicable
to the decoupling target, making use of the shortest connection
paths to any internal planes, such as vias to GND next or on the
capacitor solder pad.
0.1
0
to the CORE and NB power trains it controls through the
integrated drivers helps keep the gate drive traces equally
short, resulting in equal trace impedances and similar drive
capability of all sets of MOSFETs.
0.4
0.6
0.8
1.0
DUTY CYCLE (VIN/VO)
FIGURE 27. NORMALIZED INPUT-CAPACITOR RMS
CURRENT FOR 2-PHASE CONVERTER
Layout Considerations
MOSFETs switch very fast and efficiently. The speed with
which the current transitions from one device to another
causes voltage spikes across the interconnecting
impedances and parasitic circuit elements. These voltage
spikes can degrade efficiency, radiate noise into the circuit
and lead to device overvoltage stress. Careful component
selection, layout, and placement minimizes these voltage
spikes. Consider, as an example, the turnoff transition of the
upper PWM MOSFET. Prior to turnoff, the upper MOSFET
was carrying channel current. During the turnoff, current
stops flowing in the upper MOSFET and is picked up by the
lower MOSFET. Any inductance in the switched current path
generates a large voltage spike during the switching interval.
Careful component selection, tight layout of the critical
components, and short, wide circuit traces minimize the
magnitude of voltage spikes.
There are two sets of critical components in a DC/DC
converter using a ISL6323B controller. The power
components are the most critical because they switch large
amounts of energy. Next are small signal components that
connect to sensitive nodes or supply critical bypassing
current and signal coupling.
The power components should be placed first, which include
the MOSFETs, input and output capacitors, and the inductors. It
is important to have a symmetrical layout for each power train,
preferably with the controller located equidistant from each.
Symmetrical layout allows heat to be dissipated equally
across all power trains. Equidistant placement of the controller
32
The critical small components include the bypass capacitors
(CFILTER) for VCC and PVCC, and many of the components
surrounding the controller including the feedback network
and current sense components. Locate the VCC/PVCC
bypass capacitors as close to the ISL6323B as possible. It is
especially important to locate the components associated
with the feedback circuit close to their respective controller
pins, since they belong to a high-impedance circuit loop,
sensitive to EMI pick-up.
A multi-layer printed circuit board is recommended. Figure 28
shows the connections of the critical components for the
converter. Note that capacitors CIN and COUT could each
represent numerous physical capacitors. Dedicate one solid
layer, usually the one underneath the component side of the
board, for a ground plane and make all critical component
ground connections with vias to this layer. Dedicate another
solid layer as a power plane and break this plane into smaller
islands of common voltage levels. Keep the metal runs from the
PHASE terminal to output inductors short. The power plane
should support the input power and output power nodes. Use
copper filled polygons on the top and bottom circuit layers for
the phase nodes. Use the remaining printed circuit layers for
small signal wiring.
Routing UGATE, LGATE, and PHASE Traces
Great attention should be paid to routing the UGATE, LGATE,
and PHASE traces since they drive the power train MOSFETs
using short, high current pulses. It is important to size them as
large and as short as possible to reduce their overall
impedance and inductance. They should be sized to carry at
least one ampere of current (0.02” to 0.05”). Going between
layers with vias should also be avoided, but if so, use two vias
for interconnection when possible.
Extra care should be given to the LGATE traces in particular
since keeping their impedance and inductance low helps to
FN6879.0
March 23, 2009
ISL6323B
significantly reduce the possibility of shoot-through. It is also
important to route each channels UGATE and PHASE traces
in as close proximity as possible to reduce their inductances.
Current Sense Component Placement and
Trace Routing
One of the most critical aspects of the ISL6323B regulator
layout is the placement of the inductor DCR current sense
components and traces. The R-C current sense components
must be placed as close to their respective ISEN+ and
ISEN- pins on the ISL6323B as possible.
The sense traces that connect the R-C sense components to
each side of the output inductors should be routed on the
bottom of the board, away from the noisy switching
components located on the top of the board. These traces
should be routed side by side, and they should be very thin
traces. It’s important to route these traces as far away from
any other noisy traces or planes as possible. These traces
should pick up as little noise as possible.
Thermal Management
For maximum thermal performance in high current, high
switching frequency applications, connecting the thermal
GND pad of the ISL6323B to the ground plane with multiple
vias is recommended. This heat spreading allows the part to
achieve its full thermal potential. It is also recommended
that the controller be placed in a direct path of airflow if
possible to help thermally manage the part.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
33
FN6879.0
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ISL6323B
RFB
C2
+12V
+12V
CC
RC
FB
CIN
VSEN
R3_2
CBOOT
CBOOT
COMP
C3
BOOT1
ISEN3+
ISEN3-
CIN
BOOT1
R3_1
UGATE1
UGATE1
PWM3
PHASE1
PHASE1
RAPA
R1_1
CAPA
C1
LGATE1
LGATE1
APA
PGND
PWM1
R1_2
ISEN1ISEN1+
DVC
ISL6614
+12V
+12V
V_CORE
+5V
+12V
PVCC1_2
CIN
CFILTER
CFILTER
VCC
CBOOT
BOOT2
ROFS
CBULK
UGATE2
CPU
LOAD
PHASE2
PWM2
C2
C4
R2_2
R4_2
R2_1
R4_1
LGATE2
LGATE2
RSET
VFIXEN
SEL
SVD
ISEN2ISEN2+
SVC
VID4
VID5
PWROK
NC
NC
GND
PHASE2
RFS
RSET
CFILTER
CHF
UGATE2
FS
+5V
CIN
CBOOT
OFS
VCC
PVCC
BOOT2
RGND
VDDPWRGD
ISEN4+
GND
ISEN4-
PWM4
+12V
ISL6323B
REN1
OFF
+12V
KEY
HEAVY TRACE ON CIRCUIT PLANE LAYER
PVCC_NB
CIN
CFILTER
EN
ISLAND ON POWER PLANE LAYER
ISLAND ON CIRCUIT PLANE LAYER
CBOOT_NB
ON
BOOT_NB
REN2
VIA CONNECTION TO GROUND PLANE
UGATE_NB
V_NB
PHASE_NB
R1_NB
LGATE_NB
ISEN_NBISEN_NB+
COMP_NB
FB_NB
C2_NB
RC_NB
CC_NB
C1_NB
CBULK
CHF
R2_NB
RED COMPONENTS:
LOCATE CLOSE TO IC TO
MINIMIZE CONNECTION PATH
NB
LOAD
BLUE COMPONENTS:
LOCATE NEAR LOAD
(MINIMIZE CONNECTION PATH)
MAGENTA COMPONENTS:
LOCATE CLOSE TO SWITCHING TRANSISTORS
(MINIMIZE CONNECTION PATH)
RFB_NB
FIGURE 28. PRINTED CIRCUIT BOARD POWER PLANES AND ISLANDS
34
FN6879.0
March 23, 2009
ISL6323B
Package Outline Drawing
L48.7x7
48 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 4, 10/06
4X 5.5
7.00
A
44X 0.50
B
37
6
PIN 1
INDEX AREA
6
PIN #1 INDEX AREA
48
1
7.00
36
4. 30 ± 0 . 15
12
25
(4X)
0.15
13
24
0.10 M C A B
48X 0 . 40± 0 . 1
TOP VIEW
4 0.23 +0.07 / -0.05
BOTTOM VIEW
SEE DETAIL "X"
( 6 . 80 TYP )
(
0.10 C
BASE PLANE
0 . 90 ± 0 . 1
4 . 30 )
C
SEATING PLANE
0.08 C
SIDE VIEW
( 44X 0 . 5 )
C
0 . 2 REF
5
( 48X 0 . 23 )
( 48X 0 . 60 )
0 . 00 MIN.
0 . 05 MAX.
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
35
FN6879.0
March 23, 2009
