DATASHEET
ISL6328A
Dual PWM Controller For Powering AMD SVI Split-Plane Processors
The ISL6328A dual PWM controller delivers high efficiency
and tight regulation from two synchronous buck DC/DC
converters. The ISL6328A supports power control of AMD
processors, which operate from a serial VID interface (SVI). The
dual output ISL6328A features a multiphase controller to
support the Core voltage (VDD) and a single phase controller to
power the Northbridge (VDDNB).
Features
A precision core voltage regulation system is provided by a
one-to-four-phase PWM voltage regulator (VR) controller. The
integration of two power MOSFET drivers adds flexibility in
layout and reduces the number of external components in the
multiphase section. A single phase PWM controller with
integrated driver provides a second precision voltage
regulation system for the Northbridge portion of the processor.
This monolithic, dual controller with an integrated driver
solution provides a cost and space saving power management
solution.
• PSI_L support
For applications that benefit from load line programming to
reduce bulk output capacitors, the ISL6328A features
temperature compensated output voltage droop. The multiphase
portion also includes advanced control loop features for
optimal transient response to load application and removal.
One of these features is highly accurate, fully differential,
continuous DCR current sensing for load line programming
and channel current balance. Dual edge modulation is another
unique feature, allowing for quicker initial response to high
di/dt load transients.
The ISL6328A supports Power Savings Mode by dropping the
number of phases when the PSI_L bit is set.
FN7986
Rev 1.00
February 13, 2015
• Processor core voltage via integrated multiphase power
conversion
• Configuration flexibility
- 1 or 2-phase operation with internal drivers
- 3 or 4-phase operation with external PWM drivers
- Phase shedding for improved efficiency at light load
- Diode emulation in PSI mode
- Gate voltage optimization
• Precision core voltage regulation
- Differential remote voltage sensing
- ±0.6% system accuracy over-temperature
• Optimal processor core voltage transient response
- Adaptive phase alignment (APA)
- Active pulse positioning modulation
• Fully differential, continuous DCR current sensing
- Accurate load line programming
- Precision channel current balancing
- Temperature compensated
• Serial VID interface handles up to 3.4MHz clock rates
• Two level overcurrent protection allows for high current
throttling (IDD_SPIKE)
• Multitiered overvoltage protection
• Selectable switching frequency up to 1MHz
• Simultaneous digital soft-start of both outputs
FN7986 Rev 1.00
February 13, 2015
Page 1 of 33
ISL6328A
Table of Contents
Integrated Driver Block Diagram. . . . . . . . . . . . . . . . . . . . . . . 3
Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Functional Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . 9
Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Multiphase Power Conversion . . . . . . . . . . . . . . . . . . . . . . . . . 12
Interleaving. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Active Pulse Positioning Modulated PWM Operation . . . . . . 13
Adaptive Phase Alignment (APA) . . . . . . . . . . . . . . . . . . . . . . 13
PWM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Continuous Current Sampling . . . . . . . . . . . . . . . . . . . . . . . . . 14
Temperature Compensated Current Sensing. . . . . . . . . . . . . 15
Channel-current Balance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Serial VID Interface (SVI) . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Pre-PWROK METAL VID. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
SVI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Power Savings Mode: PSI_L . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Voltage Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Load-line (Droop) Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Droop Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Output Voltage Offset Programming. . . . . . . . . . . . . . . . . . . . 19
Dynamic VID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Advanced Adaptive Zero Shoot-through Deadtime Control
(Patent Pending) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Enable Comparator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Phase Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Soft-start Output Voltage Targets . . . . . . . . . . . . . . . . . . . . . .
Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Prebiased Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20
20
20
20
20
20
20
Fault Monitoring and Protection . . . . . . . . . . . . . . . . . . . . .
Power-good Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overvoltage Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pre-POR Overvoltage Protection . . . . . . . . . . . . . . . . . . . . . . .
Undervoltage Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Open Sense Line Protection . . . . . . . . . . . . . . . . . . . . . . . . . .
Overcurrent Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Individual Channel Overcurrent Limiting . . . . . . . . . . . . . . . .
21
21
21
21
22
22
22
23
General Design Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Internal Bootstrap Device . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Gate Drive Voltage Versatility . . . . . . . . . . . . . . . . . . . . . . . . .
Package Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . .
Inductor DCR Current Sensing Component Fine Tuning . . .
Loadline Regulation Resistor . . . . . . . . . . . . . . . . . . . . . . . . .
Compensation With Loadline Regulation . . . . . . . . . . . . . . .
Compensation Without Loadline Regulation . . . . . . . . . . . .
Output Filter Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Switching Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23
23
24
24
24
25
26
26
26
27
28
28
Layout Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Routing UGATE, LGATE, and PHASE Traces. . . . . . . . . . . . . . 30
Current Sense Component Placement and Trace Routing 30
Thermal Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
FN7986 Rev 1.00
February 13, 2015
Page 2 of 33
ISL6328A
Integrated Driver Block Diagram
Channels 1 and 2 Gate Drive
PVCC
GVOT
BOOTn
UGATEn
PWM
20kΩ
SOFT-START
AND
FAULT LOGIC
GATE
CONTROL
LOGIC
SHOOTTHROUGH
PROTECTION
PHASEn
10kΩ
LGATEn
Northbridge Gate Drive
PVCC
BOOT_NB
UGATE_NB
PWM
20kΩ
SOFT-START
AND
FAULT LOGIC
GATE
CONTROL
LOGIC
SHOOTTHROUGH
PROTECTION
PHASE_NB
10kΩ
LGATE_NB
FN7986 Rev 1.00
February 13, 2015
Page 3 of 33
ISL6328A
Controller Block Diagram
COMP_NB
FB_NB
RGND
VSEN_NB
BOOT_NB
E/A
CURRENT
SENSE
ISEN_NB-
DRPCTRL
NB_REF
ISEN_NB+
UV
LOGIC
OV
LOGIC
MOSFET
DRIVER
RAMP
DROOP
CONTROL
EN_12V
OFFSET
COMP
CH3_OFF
PSI
SVC
SVD
VCC
GVOT
SOFT-START
+
FAULT LOGIC
E/A
+
BOOT1
NB_REF
SVI
SLAVE
BUS
MOSFET
DRIVER
LOAD APPLY
TRANSIENT
ENHANCEMENT
DUAL
OCP
OCP
LGATE1
CLOCK AND
TRIANGLE WAVE
GENERATOR
UV
LOGIC
APA
FS
OC
PWM1
I_TRIP
BOOT2
8
N
PWM2
MOSFET
DRIVER
PWM3
TCOMP1
TCOMP2
ISEN1+
ISEN1ISEN2+
ISEN2ISEN3+
ISEN3-
ISEN4-
UGATE2
PHASE2
LGATE2
TEMPERATURE
COMPENSATION
PH3/PH4
POR
PWM4
I_TC_IN
CH1
CURRENT
SENSE
EN_12V
CHANNEL
DETECT
CH2
CURRENT
SENSE
CHANNEL
CURRENT
BALANCE
I_AVG
CH3
CURRENT
SENSE
CH4
CURRENT
SENSE
ISEN2ISEN3ISEN4-
1
N
I_TC_IN
ISEN3ISEN4+
UGATE1
PHASE1
OV
LOGIC
VSEN
APA
EN
AND
RGND
PWROK
ENABLE
LOGIC
POWER-ON
RESET
FB
RGND
PVCC
LDO
NB
FAULT
LOGIC
FB_PSI
PHASE_NB
LGATE_NB
VDDPWRGD
OFS
UGATE_NB
1
8
PWM3
SIGNAL
LOGIC
PWM4
SIGNAL
LOGIC
PWM3
PWM4
ISEN4GND
FN7986 Rev 1.00
February 13, 2015
Page 4 of 33
ISL6328A
Typical Application
VCC
+5V
VCC RSVD
TCOMP1
CS1-
ISEN1-
CS1+
ISEN1+
TCOMP2
CS2-
ISEN2-
PWM3
PWM4
CS2+
ISEN2+
CS3-
ISEN3-
PVCC
CS3+
ISEN3+
GVOT
CS4-
ISEN4-
CS4+
ISEN4+
PWM3
PWM4
+12V
ISL6328A
CS_NB-
ISEN_NB-
CS_NB+
ISEN_NB+
+12V
BOOT1
UGATE1
PHASE1
LGATE1
CS1CS1+
BOOT2
DRPCTRL
OFS
LGATE2
OCP
+12V
SVC
SVD
PWROK
VDDPWRGD
+12V
EN
APA
LGATE1
PVCC
VCC
BOOT2
+12V
GND
UGATE2
PHASE2
CS2CS2+
CS4CS4+
PGND
LGATE2
VSEN
RGND
CORE_FB
BOOT_NB
+12V
CORE
CPU
UGATE_NB
PHASE_NB
LGATE_NB
CS_NBCS_NB+
NORTHBRIDGE
VSEN_NB
CORE_FB
FB_PSI
FB
COMP
FN7986 Rev 1.00
February 13, 2015
CS3CS3+
UGATE2
PHASE2
FS
ENABLE
ISL6614
BOOT1 PWM1
PWM3
PWM2
PWM4
UGATE1
PHASE1
+12V
+12V
FB_NB
COMP_NB
GND
Page 5 of 33
ISL6328A
Pin Configuration
ISEN_NB+
ISEN_NB-
ISEN4+
ISEN4-
ISEN3+
ISEN3-
PVCC
LGATE_NB
BOOT_NB
UGATE_NB
PHASE_NB
PWM3
ISL6328A
(48 LD QFN)
TOP VIEW
48
47
46
45
44
43
42
41
40
39
38
37
COMP_NB
1
36
PWM4
FB_NB
2
35
PWROK
VSEN_NB
3
34
VDDPWRGD
DRPCTRL
4
33
PHASE1
SVC
5
32
UGATE1
SVD
6
31
BOOT1
30
LGATE1
GND
27
BOOT2
TCOMP1
11
26
UGATE2
TCOMP2
12
25
EN
13
14
15
16
17
18
19
20
21
22
23
24
PHASE2
10
ISEN2-
OCP
ISEN2+
LGATE2
ISEN1-
28
ISEN1+
9
APA
OFS
FS
GVOT
COMP
29
FB
8
FB_PSI
RSVD
VSEN
7
RGND
VCC
Functional Pin Descriptions
PIN NAME
PIN NUMBER
COMP_NB
1
Output of the internal error amplifier for the Northbridge regulator.
FB_NB
2
Inverting input to the internal error amplifier for the Northbridge regulator.
VSEN_NB
3
Noninverting input to the Northbridge regulator precision differential remote-sense amplifier. This pin
should be connected to the remote Northbridge sense pin of the processor, VDDNB_SENSE.
DRPCTRL
4
Droop Control for Core and Northbridge. This pin is used to set up one of four user programmable selections
via a resistor: Core Droop On and Northbridge Droop On; Core Droop Off and Northbridge Droop On, Core
Droop On and Northbridge Droop Off; Core Droop Off and Northbridge Droop Off.
If the resistor is tied to ground, the number of active phases in PSI mode is 1. If the resistor is tied to
VCC, the number of active phases in PSI mode is 2.
SVC
5
Serial VID clock input from the AMD processor.
SVD
6
Serial VID data bi-directional signal to and from the master device on AMD processor.
VCC
7
VCC is the bias supply for the ICs small-signal circuitry. Connect this pin to a +5V supply and decouple
using a quality 0.1µF ceramic capacitor.
RSVD
8
RESERVED. Connect this pin directly to the VCC pin.
OFS
9
The OFS pin provides a means to program a DC current for generating an offset voltage across the resistor
between FB and VSEN. The offset current is generated via an external resistor and precision internal
voltage references. The polarity of the offset is selected by connecting the resistor to GND or VCC. For no
offset, the OFS pin should be left unconnected.
FN7986 Rev 1.00
February 13, 2015
DESCRIPTION
Page 6 of 33
ISL6328A
Functional Pin Descriptions (Continued)
PIN NAME
PIN NUMBER
DESCRIPTION
OCP
10
A capacitor from this pin to ground determines the time that the regulator is allowed to service a load
current spike that exceeds the internal OCP trip point.
TCOMP1, TCOMP2
11, 12
RGND
13
Inverting input to the Core and Northbridge regulator precision differential remote-sense amplifiers. This
pin should be connected to the remote ground sense pin of the processor core, VSS_SENSE.
VSEN
14
Non-inverting input to the Core regulator precision differential remote-sense amplifier. This pin should be
connected to the remote Core sense pin of the processor, VDD_SENSE.
FB_PSI
15
In PSI mode this pin is internally shorted to the FB pin to augment the feedback compensation network
for the lower phase count.
FB
16
Inverting input to the internal error amplifier for the Core regulator.
COMP
17
Output of the internal error amplifier for the Core regulator.
FS
18
This is a dual function pin. A resistor, placed from FS to either Ground or VCC sets the switching
frequency of both controllers. Refer to Equation 1 for proper resistor calculation.
These two pins are used to compensate the inductor current sensing for fluctuations due to
temperature.
R T = 10
10.61 – 1.035 log f s
(EQ. 1)
This pin also controls the SVID high and low trip thresholds.
APA
19
Allows for programming of the Auto Phase Alignment threshold. A resistor in parallel with a capacitor
to ground is used to set this threshold.
ISENn+, ISENn-,
ISEN_NB+, ISEN_NB-
20, 21, 22,
23, 43, 44,
45, 46, 47,
48
These pins are used for differentially sensing the corresponding channel output currents. The sensed
currents are used for channel balancing, protection, and core load line regulation.
Connect ISEN- to the node between the RC sense elements surrounding the inductor of the respective
channel. Tie the ISEN+ pin to the other end of the sense capacitor through a resistor, RISEN. The voltage
across the sense capacitor is proportional to the inductor current. The sense current, therefore, is
proportional to the inductor current and scaled by the DCR of the inductor and RISEN.
PHASE1,
PHASE2
33,
24
Connect these pins to the sources of the corresponding upper MOSFETs. These pins are the return path
for the upper MOSFET drives.
GND
-
Bias and reference ground for the IC. The GND connection for the ISL6328A is made with three pins and
through the thermal pad on the bottom of the package.
EN
25
This pin is a threshold-sensitive (approximately 0.85V) system enable input for the controller. Held low, this
pin disables both CORE and NB controller operation. Pulled high, the pin enables both controllers for
operation.
A second function of this pin is to provide driver bias monitor for external drivers. A resistor divider with the
center tap connected to this pin from the drive bias supply prevents enabling the controller before
insufficient bias is provided to external driver. The resistors should be selected such that when the POR-trip
point of the external driver is reached, the voltage at this pin meets the above mentioned threshold level.
UGATE1, UGATE2
32, 26
Connect this pin to the corresponding upper MOSFET gate. This pin provides the PWM-controlled gate
drive for the upper MOSFET and is monitored for shoot-through prevention purposes.
BOOT1, BOOT2
31, 27
This pin provides the bias voltage for the corresponding upper MOSFET drive. Connect this pin to
appropriately-chosen external bootstrap capacitor. The internal bootstrap diode connected to the PVCC
pin provides the necessary bootstrap charge.
LGATE1, LGATE2
30, 28
Connect this pin to the corresponding MOSFET’s gate. This pin provides the PWM-controlled gate drive
for the lower MOSFET. This pin is also monitored by the adaptive shoot-through protection circuitry to
determine when the lower MOSFET has turned off.
GVOT
29
The power supply pin for the multiphase internal MOSFET drivers. In normal operation, this pin is
shorted to the PVCC pin. While in PSI mode, this pin is tied to the output of the internal LDO for Gate
Drive Voltage Optimization. Decouple this pin with a quality 2.2µF ceramic capacitor.
VDDPWRGD
34
During normal operation this pin indicates whether both output voltages are within specified overvoltage
and undervoltage limits. If either output voltage exceeds these limits or a reset event occurs (such as an
overcurrent event), the pin is pulled low. This pin is always low prior to the end of soft-start.
FN7986 Rev 1.00
February 13, 2015
Page 7 of 33
ISL6328A
Functional Pin Descriptions (Continued)
PIN NAME
PIN NUMBER
DESCRIPTION
PWROK
35
System wide Power Good input signal. If this pin is low, the two SVI bits are decoded to determine the
“metal VID”. When pin is high, the SVI is actively running its protocol.
PWM3, PWM4
37, 36
Pulse-width modulation outputs. Connect these pins to the PWM input pins of an Intersil driver IC if
3- or 4-phase operation is desired. Connect the ISEN- pins of the channels not desired to +5V to disable
them. Channels must be disabled in decremental order.
PHASE_NB
38
Connect this pin to the source of the corresponding upper MOSFET. This pin is the return path for the
upper MOSFET drive. This pin is used to monitor the voltage drop across the upper MOSFET for
overcurrent protection.
UGATE_NB
39
Connect this pin to the corresponding upper MOSFET gate. This pin provides the PWM-controlled gate
drive for the upper MOSFET and is monitored for shoot-through prevention purposes.
BOOT_NB
40
This pin provides the bias voltage for the corresponding upper MOSFET drive. Connect this pin to
appropriately-chosen external bootstrap capacitor. The internal bootstrap diode connected to the PVCC
pin provides the necessary bootstrap charge.
LGATE_NB
41
Connect this pin to the corresponding MOSFET’s gate. This pin provides the PWM-controlled gate drive
for the lower MOSFET. This pin is also monitored by the adaptive shoot-through protection circuitry to
determine when the lower MOSFET has turned off.
PVCC
42
The power supply pin for the internal MOSFET drivers. Connect this pin to +12V. This pin is the input to
the internal LDO for GVOT. Decouple this pin with a quality 1.0µF ceramic capacitor.
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
ISL6328ACRZ
PART
MARKING
6328A CRZ
TEMP. RANGE
(°C)
0 to +70
PACKAGE
(RoHS Compliant)
48 Ld 6x6 QFN
PKG.
DWG. #
L48.6x6B
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials and 100% matte tin plate
plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL6328A. For more information on MSL please see techbrief TB363.
FN7986 Rev 1.00
February 13, 2015
Page 8 of 33
ISL6328A
Absolute Maximum Ratings
Thermal Information
Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6V
Supply Voltage (PVCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +15V
Absolute Boot Voltage (VBOOT) . . . . . . . . . . . . . . . GND - 0.3V to GND + 36V
Phase Voltage (VPHASE). . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 24V
(PVCC = 12V) GND - 8V (
