DATASHEET
ISL6329
FN7800
Rev 0.00
April 19, 2011
Dual PWM Controller Powering AMD SVI Split-Plane Processors
The ISL6329 dual PWM controller delivers high efficiency and
tight regulation from two synchronous buck DC/DC converters.
The ISL6329 supports power control of AMD processors, which
operate from a serial VID interface (SVI). The dual output
ISL6329 features a multiphase controller to support the Core
voltage (VDD) and a single phase controller to power the
Northbridge (VDDNB).
A precision core voltage regulation system is provided by a
one-to-six-phase PWM voltage regulator (VR) controller. The
integration of two power MOSFET drivers adds flexibility in
layout and reduces the number of external components in the
multi-phase section. A single phase PWM controller with
integrated driver provides a second precision voltage
regulation system for the Northbridge portion of the processor.
This monolithic, dual controller with integrated driver solution
provides a cost and space saving power management solution.
For applications that benefit from load line programming to
reduce bulk output capacitors, the ISL6329 features temperature
compensated output voltage droop. The multiphase portion also
includes advanced control loop features for optimal transient
response to load application and removal. One of these
features is highly accurate, fully differential, continuous DCR
current sensing for load line programming and channel current
balance. Dual edge modulation is another unique feature,
allowing for quicker initial response to high di/dt load
transients.
The ISL6329 supports Power Savings Mode by dropping the
number of phases to one or two when the PSI_L bit is set. For
even greater power efficiency, diode emulation and gate
voltage optimization are implemented in PSI mode.
Features
• Processor Core Voltage Via Integrated Multiphase Power
Conversion
• Configuration Flexibility
- 1 or 2-Phase Operation with Internal Drivers
- 3,4,5 or 6-Phase Operation with External PWM Drivers
• PSI_L Support
- Phase Shedding for Improved Efficiency at Light Load
- Diode Emulation in PSI mode
- Gate Voltage Optimization
• I2C Interface with 8 Selectable Addresses
• Precision Core Voltage Regulation
- Differential Remote Voltage Sensing
- 0.6% System Accuracy Over-Temperature
• Optimal Processor Core Voltage Transient Response
- Adaptive Phase Alignment (APA)
- Active Pulse Positioning Modulation
• Fully Differential, Continuous DCR Current Sensing
- Accurate Load Line Programming
- Precision Channel Current Balancing
- Temperature Compensated
• Serial VID Interface Handles up to 3.4MHz Clock Rates
• Two Level Overcurrent Protection Allows for High Current
Throttling (IDD_SPIKE)
• Multi-tiered Overvoltage Protection
• Selectable Switching Frequency up to 1MHz
• Simultaneous Digital Soft-Start of Both Outputs
• Pb-Free (RoHS Compliant)
FN7800 Rev 0.00
April 19, 2011
Page 1 of 38
ISL6329
Integrated Driver Block Diagram
Channels 1 and 2 Gate Drive
PVCC
GVOT
BOOT
UGATE
PWM
20kΩ
SOFT-START
AND
FAULT LOGIC
GATE
CONTROL
LOGIC
SHOOTTHROUGH
PROTECTION
PHASE
10kΩ
LGATE
Northbridge Gate Drive
PVCC
BOOT
UGATE
PWM
20kΩ
SOFT-START
AND
FAULT LOGIC
GATE
CONTROL
LOGIC
SHOOTTHROUGH
PROTECTION
PHASE
10kΩ
LGATE
FN7800 Rev 0.00
April 19, 2011
Page 2 of 38
ISL6329
Controller Block Diagram
COMP_NB
FB_NB
RGND
VSEN_NB
NB_REF
ISEN_NB+
ISEN_NB-
BOOT_NB
E/A
CURRENT
SENSE
UV
LOGIC
OV
LOGIC
MOSFET
DRIVER
RAMP
I2C
I2C_ADDR
SCL
EN_12V
ENABLE
LOGIC
OFFSET
CH3_OFF
PSI
VCC
GVOT
SOFT-START
AND
FB
+
RGND
FAULT LOGIC
E/A
RGND
PWROK
VDDIO
SVC
SVD
EN
POWER-ON
RESET
COMP
FB_PSI
PVCC
LDO
NB
FAULT
LOGIC
VDDPWRGD
OFS
+
BOOT1
NB_REF
DROOP
CONTROL
SVI
SLAVE
BUS
MOSFET
DRIVER
LOAD APPLY
TRANSIENT
ENHANCEMENT
LGATE1
DRPCTRL
CLOCK AND
TRIANGLE WAVE
GENERATOR
VSEN
UV
LOGIC
FS
OC
APA
PWM1
BOOT2
I_TRIP
DUAL
OCP
OCP
PWM2
8
N
MOSFET
DRIVER
PWM3
PWM4
TCOMP2
ISEN1+
ISEN1ISEN2+
ISEN2ISEN3+
ISEN3-
CH1 CURRENT
SENSE
PWM6
I_AVG
ISEN2-
ISEN3CH4 CURRENT
SENSE
ISEN5+
CH5 CURRENT
SENSE
ISEN6+
ISEN6-
CH3 CURRENT
SENSE
CHANNEL
CURRENT
BALANCE
1
N
I_TC_IN
ISEN4-
ISEN5-
PH3/PH4/PH5/PH6
POR
CH2 CURRENT
SENSE
ISEN4+
ISEN4-
ISEN5-
PWM5
I_TC_IN
1
8
CH6 CURRENT
SENSE
ISEN6-
PHASE2
EN_12V
TEMPERATURE
COMPENSATION
UGATE2
LGATE2
TCOMP1
UGATE1
PHASE1
OV
LOGIC
APA
PHASE_NB
LGATE_NB
DAC_OFS
NB_OVP
CORE_OVP
VDDPWRGD_TRIP
GVOT_LDO
NUM_PHASES_PSI
NUM_CYCLES_PSI
SDA
UGATE_NB
CHANNEL
DETECT
ISEN2ISEN3ISEN4ISEN5ISEN6-
PWM3
SIGNAL
LOGIC
PWM3
PWM4
SIGNAL
LOGIC
PWM4
PWM5
SIGNAL
LOGIC
PWM5
PWM6
SIGNAL
LOGIC
PWM6
GND
FN7800 Rev 0.00
April 19, 2011
Page 3 of 38
ISL6329
Typical Application
VCC
+5V
ISL6614
BOOT1 PWM1
PWM2
+12V
CS1-
ISEN1-
CS1+
ISEN1+
CS2-
ISEN2-
CS2+
ISEN2+
CS3-
ISEN3-
CS3+
ISEN3+
VCC RSVD
TCOMP2
PWM3
PWM4
PWM5
PWM6
PVCC
ISEN4ISEN4+
BOOT1
CS5-
ISEN5-
CS5+
ISEN5+
UGATE1
PHASE1
CS6+
ISEN6+
CS_NB-
ISEN_NB-
CS_NB+
ISEN_NB+
GND
UGATE2
PHASE2
CS4CS4+
PGND
LGATE2
ISL6614
BOOT1 PWM1
PWM2
+12V
UGATE1
PHASE1
CS1CS1+
CS5CS5+
LGATE1
PWM5
PWM6
+12V
PVCC
VCC
+12V
BOOT2
+12V
GND
UGATE2
PHASE2
LGATE2
FS
UGATE2
PHASE2
CS2CS2+
CS6CS6+
VSEN
RGND
OFS
BOOT_NB
VDDIO
SVC
SVD
SCL
SDA
PWROK
VDDPWRGD
EN
APA
+12V
UGATE_NB
PHASE_NB
LGATE_NB
PGND
LGATE2
KELVIN
SENSE
LINES
CORE_FB
OCP
ENABLE
+12V
+12V
BOOT2
I2C_ADDR
+12V
PVCC
BOOT2
+12V
LGATE1
LGATE1
+12V
VCC
PWM3
PWM4
PWM5
PWM6
ISL6329
CS4+
ISEN6-
CS3CS3+
GVOT
CS4-
CS6-
UGATE1
PHASE1
TCOMP1
PWM3
PWM4
CORE
CPU
CS_NBCS_NB+
NORTHBRIDGE
KELVIN
SENSE
LINE
VSEN_NB
DRPCTRL
FB_NB
COMP_NB
CORE_FB
FB_PSI
FB
COMP
GND
FN7800 Rev 0.00
April 19, 2011
Page 4 of 38
ISL6329
Pin Configuration
ISEN_NB+
ISEN_NB-
ISEN5+
ISEN5-
ISEN4+
ISEN4-
ISEN3+
ISEN3-
I2C_ADDR
PVCC
LGATE_NB
BOOT_NB
UGATE_NB
PHASE_NB
PWM3
ISL6329
(60 LD QFN)
TOP VIEW
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
COMP_NB 1
45 PWM4
FB_NB 2
44 PWM5
VSEN_NB 3
43 PWM6
DRPCTRL 4
42 PWROK
SVC 5
41 VDDPWRGD
SVD 6
40 PHASE1
VDDIO 7
39 UGATE1
61
GND
SCL 8
38 BOOT1
SDA 9
37 LGATE1
VCC 10
36 GVOT
RSVD 11
35 LGATE2
OFS 12
34 BOOT2
OCP 13
33 UGATE2
20
21
22
23
24
25
26
COMP
FS
APA
ISEN6+
ISEN6-
ISEN1+
ISEN1-
27
28
29
30
GND
19
PHASE2
18
ISEN2-
17
ISEN2+
16
FB
31 EN
FB_PSI
TCOMP2 15
VSEN
32 GND
RGND
TCOMP1 14
Functional Pin Descriptions
PIN NAME
PIN NUMBER
COMP_NB
1
Output of the internal error amplifier for the Northbridge regulator.
FB_NB
2
Inverting input to the internal error amplifier for the Northbridge regulator.
VSEN_NB
3
Non-inverting input to the Northbridge regulator precision differential remote-sense amplifier. This pin
should be connected to the remote Northbridge sense pin of the processor, VDDNB_SENSE.
DRPCTRL
4
Droop Control for Core and Northbridge. This pin is used to set up one of four user programmable selections
via a resistor tied to ground: Core Droop On and Northbridge Droop On; Core Droop Off and Northbridge Droop
On, Core Droop On and Northbridge Droop Off; Core Droop Off and Northbridge Droop Off.
SVC
5
Serial VID clock input from the AMD processor.
SVD
6
Serial VID data bi-directional signal to and from the master device on AMD processor.
VDDIO
7
Reference voltage for the SVI communication bus. Connect this pin to the system VDDIO and decouple
using a quality 0.1F ceramic capacitor.
SCL
8
Connect this pin to the clock signal for the I2C bus, which is a logic level input signal. The clock signal
tells the controller when data is available on the I2C bus.
FN7800 Rev 0.00
April 19, 2011
DESCRIPTION
Page 5 of 38
ISL6329
Functional Pin Descriptions (Continued)
PIN NAME
PIN NUMBER
DESCRIPTION
SDA
9
Connect this pin to the bidirectional data line of the I2C bus, which is a logic level input/output signal.
All I2C data is sent over this line, including the address of the device the bus is trying to communicate
with and what functions the device should perform.
VCC
10
VCC is the bias supply for the ICs small-signal circuitry. Connect this pin to a +5V supply and decouple
using a quality 0.1µF ceramic capacitor.
RSVD
11
RESERVED. Connect this pin directly to the VCC pin.
OFS
12
The OFS pin provides a means to program a DC current for generating an offset voltage across the resistor
between FB and VSEN. The offset current is generated via an external resistor and precision internal
voltage references. The polarity of the offset is selected by connecting the resistor to GND or VCC. For no
offset, the OFS pin should be left unconnected.
OCP
13
A capacitor from this pin to ground determines the time that the regulator is allowed to service a load
current spike that exceeds the internal OCP trip point.
TCOMP1, TCOMP2
14, 15
RGND
16
Inverting input to the Core and Northbridge regulator precision differential remote-sense amplifiers. This
pin should be connected to the remote ground sense pin of the processor core, VSS_SENSE.
VSEN
17
Non-inverting input to the Core regulator precision differential remote-sense amplifier. This pin should be
connected to the remote Core sense pin of the processor, VDD_SENSE.
FB_PSI
18
In PSI mode this pin is internally shorted to the FB pin to augment the feedback compensation network
for the lower phase count.
FB
19
Inverting input to the internal error amplifier for the Core regulator.
COMP
20
Output of the internal error amplifier for the Core regulator.
FS
21
This is a dual function pin. A resistor, placed from FS to either Ground or VCC sets the switching
frequency of both controllers. Refer to Equation 1 for proper resistor calculation.
These two pins are used to compensate the inductor current sensing for fluctuations due to
temperature.
R T = 10
10.61 – 1.035 log f s
(EQ. 1)
If the resistor is tied to ground, the number of active phases in PSI mode is 1. If the resistor is tied to
VCC, the number of active phases in PSI mode is 2.
APA
22
Allows for programming of the Auto Phase Alignment threshold. A resistor in parallel with a capacitor
to ground is used to set this threshold.
ISENn+, ISENn-,
ISEN_NB+, ISEN_NB-
23, 24, 25, 26,
27, 28, 53, 54,
55, 56, 57, 58,
59, 60
These pins are used for differentially sensing the corresponding channel output currents. The sensed
currents are used for channel balancing, protection, and core load line regulation.
Connect ISEN- to the node between the RC sense elements surrounding the inductor of the respective
channel. Tie the ISEN+ pin to the other end of the sense capacitor through a resistor, RISEN. The voltage
across the sense capacitor is proportional to the inductor current. The sense current, therefore, is
proportional to the inductor current and scaled by the DCR of the inductor and RISEN.
PHASE1, PHASE2
40, 29
Connect these pins to the sources of the corresponding upper MOSFETs. These pins are the return path
for the upper MOSFET drives.
GND
30, 32, 61
Bias and reference ground for the IC. The GND connection for the ISL6329 is made with three pins and
through the thermal pad on the bottom of the package.
EN
31
This pin is a threshold-sensitive (approximately 0.85V) system enable input for the controller. Held low, this
pin disables both CORE and NB controller operation. Pulled high, the pin enables both controllers for
operation.
A second function of this pin is to provide driver bias monitor for external drivers. A resistor divider with the
center tap connected to this pin from the drive bias supply prevents enabling the controller before
insufficient bias is provided to external driver. The resistors should be selected such that when the PORtrip point of the external driver is reached, the voltage at this pin meets the above mentioned threshold
level.
UGATE1, UGATE2
39, 33
Connect this pin to the corresponding upper MOSFET gate. This pin provides the PWM-controlled gate
drive for the upper MOSFET and is monitored for shoot-through prevention purposes.
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April 19, 2011
Page 6 of 38
ISL6329
Functional Pin Descriptions (Continued)
PIN NAME
PIN NUMBER
DESCRIPTION
BOOT1, BOOT2
38, 34
This pin provides the bias voltage for the corresponding upper MOSFET drive. Connect this pin to
appropriately-chosen external bootstrap capacitor. The internal bootstrap diode connected to the PVCC
pin provides the necessary bootstrap charge.
LGATE1, LGATE2
37, 35
Connect this pin to the corresponding MOSFET’s gate. This pin provides the PWM-controlled gate drive
for the lower MOSFET. This pin is also monitored by the adaptive shoot-through protection circuitry to
determine when the lower MOSFET has turned off.
GVOT
36
The power supply pin for the multiphase internal MOSFET drivers. In normal operation, this pin is
shorted to the PVCC pin. While in PSI mode, this pin is tied to the output of the internal LDO for Gate
Drive Voltage Optimization. Decouple this pin with a quality 2.2F ceramic capacitor.
VDDPWRGD
41
During normal operation, this pin indicates whether both output voltages are within specified overvoltage
and undervoltage limits. If either output voltage exceeds these limits or a reset event occurs (such as an
overcurrent event), the pin is pulled low. This pin is always low prior to the end of soft-start.
PWROK
42
System wide Power Good input signal. If this pin is low, the two SVI bits are decoded to determine the
“metal VID”. When pin is high, the SVI is actively running its protocol.
PWM3, PWM4, PWM5,
PWM6
46, 45, 44, 43
Pulse-width modulation outputs. Connect these pins to the PWM input pins of an Intersil driver IC if 3,
4, 5, or 6-phase operation is desired. Connect the ISEN- pins of the channels not desired to +5V to
disable them. Channels must be disabled in decremental order.
PHASE_NB
47
Connect this pin to the source of the corresponding upper MOSFET. This pin is the return path for the
upper MOSFET drive. This pin is used to monitor the voltage drop across the upper MOSFET for
overcurrent protection.
UGATE_NB
48
Connect this pin to the corresponding upper MOSFET gate. This pin provides the PWM-controlled gate
drive for the upper MOSFET and is monitored for shoot-through prevention purposes.
BOOT_NB
49
This pin provides the bias voltage for the corresponding upper MOSFET drive. Connect this pin to
appropriately-chosen external bootstrap capacitor. The internal bootstrap diode connected to the PVCC
pin provides the necessary bootstrap charge.
LGATE_NB
50
Connect this pin to the corresponding MOSFET’s gate. This pin provides the PWM-controlled gate drive
for the lower MOSFET. This pin is also monitored by the adaptive shoot-through protection circuitry to
determine when the lower MOSFET has turned off.
PVCC
51
The power supply pin for the internal MOSFET drivers. Connect this pin to +12V. This pin is the input to
the internal LDO for GVOT. Decouple this pin with a quality 1.0F ceramic capacitor.
I2C_ADDR
52
A resistor tied from this pin to either ground or VCC will set the I2C address. There are eight I2C
programmable addresses.
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
TEMP.
(°C)
PACKAGE
(Pb-free)
PKG.
DWG. #
ISL6329CRZ
ISL6329 CRZ
0 to +70
60 Ld 7x7 QFN
L60.7x7
ISL6329IRZ
ISL6329 IRZ
-40 to +85
60 Ld 7x7 QFN
L60.7x7
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate
plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL6329. For more information on MSL please see techbrief TB363.
FN7800 Rev 0.00
April 19, 2011
Page 7 of 38
ISL6329
Table of Contents
Absolute Maximum Ratings.............................................................. 9
Undervoltage Detection............................................................. 22
Overcurrent Protection .............................................................. 22
Individual Channel Overcurrent Limiting ................................ 23
Thermal Information .......................................................................... 9
I2C Bus Interface .............................................................................. 23
Recommended Operating Conditions ............................................. 9
Data Validity ................................................................................
START and STOP Conditions.....................................................
Byte Format.................................................................................
Acknowledge...............................................................................
ISL6329 I2C Slave Address.......................................................
Communicating Over the I2C Bus ............................................
Writing to the Internal Registers..............................................
Reading from the Internal Registers .......................................
Resetting the Internal Registers ..............................................
I2C Read and Write Protocol ....................................................
Register Bit Definitions..............................................................
Electrical Specifications ....................................................................9
Timing Diagram ................................................................................ 12
Operation ........................................................................................... 12
Multiphase Power Conversion .................................................. 12
Interleaving.................................................................................. 12
Active Pulse Positioning Modulated PWM Operation ........... 13
Adaptive Phase Alignment (APA)............................................. 13
PWM Operation........................................................................... 13
Continuous Current Sampling................................................... 14
Temperature Compensated Current Sensing......................... 15
Channel-Current Balance........................................................... 15
Serial VID Interface (SVI) ................................................................. 15
Pre-PWROK METAL VID ............................................................. 15
SVI Mode ...................................................................................... 16
Power Savings Mode: PSI_L...................................................... 17
Voltage Regulation ..................................................................... 18
Load-Line (Droop) Regulation ................................................... 18
Droop Control .............................................................................. 18
Output-Voltage Offset Programming ....................................... 19
Dynamic VID ................................................................................ 19
Advanced Adaptive Zero Shoot-Through Deadtime Control
(Patent Pending) .......................................................................... 19
Initialization....................................................................................... 20
Power-On Reset .......................................................................... 20
Enable Comparator .................................................................... 20
Phase Detection.......................................................................... 20
Soft-Start Output Voltage Targets ............................................ 20
Soft-Start...................................................................................... 20
Pre-Biased Soft-Start.................................................................. 21
General Design Guide ...................................................................... 28
Power Stages ..............................................................................
Internal Bootstrap Device..........................................................
Gate Drive Voltage Versatility ...................................................
Package Power Dissipation ......................................................
Inductor DCR Current Sensing Component Fine Tuning .....
Loadline Regulation Resistor ...................................................
Compensation With Loadline Regulation...............................
Compensation Without Loadline Regulation .........................
Output Filter Design ...................................................................
Switching Frequency ..................................................................
Input Capacitor Selection..........................................................
28
29
29
29
30
31
31
32
32
33
33
Layout Considerations ..................................................................... 34
Routing UGATE, LGATE, and PHASE Traces............................ 35
Current Sense Component Placement and Trace Routing ....... 35
Thermal Management ............................................................... 35
Revision History ................................................................................ 37
Products ............................................................................................. 37
Package Outline Drawing ............................................................... 38
Fault Monitoring and Protection..................................................... 21
Power Good Signal ..................................................................... 21
Overvoltage Protection .............................................................. 21
Pre-POR Overvoltage Protection............................................... 21
FN7800 Rev 0.00
April 19, 2011
23
23
24
24
24
24
24
25
25
26
26
Page 8 of 38
ISL6329
Absolute Maximum Ratings
Thermal Information
Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V
Supply Voltage (PVCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +15V
Absolute Boot Voltage (VBOOT) . . . . . . . . . . . . . . . GND - 0.3V to GND + 36V
Phase Voltage (VPHASE). . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 30V
(PVCC = 12V) GND - 8V ( f 0
2 LC
C2
Case 1:
RC
CC
0.66 V IN
C C = --------------------------------------------------2 V PP R FB f 0
COMP
FB
C1
1
1
-------------------------------- f 0 < -----------------------------------2 C ESR
2 LC
ISL6329
RFB
R1
2 f 0 V pp L C
R C = R FB -------------------------------------------------------0.66 V IN
Case 2:
V PP 2 2 f 02 L C
R C = R FB ----------------------------------------------------------------0.66 V
(EQ. 38)
IN
VSEN
0.66 V IN
C C = ------------------------------------------------------------------------------------2
2
2 f 0 V PP R FB L C
FIGURE 24. COMPENSATION CIRCUIT WITHOUT LOAD-LINE
REGULATION
The first step is to choose the desired bandwidth, f0, of the
compensated system. Choose a frequency high enough to assure
adequate transient performance but not higher than 1/3 of the
switching frequency. The type-III compensator has an extra
high-frequency pole, fHF. This pole can be used for added noise
rejection or to assure adequate attenuation at the error-amplifier
high-order pole and zero frequencies. A good general rule is to
choose fHF = 10f0, but it can be higher if desired. Choosing fHF to
be lower than 10f0 can cause problems with too much phase shift
below the system bandwidth.
C ESR
R 1 = R FB -------------------------------------------L C – C ESR
L C – C ESR
C 1 = -------------------------------------------R FB
0.75 V IN
C 2 = -------------------------------------------------------------------------------------------------- 2 2 f 0 f HF L C R FB V PP
(EQ. 37)
2
V PP 2 f 0 f HF L C R FB
R C = ---------------------------------------------------------------------------------------0.75 V IN 2 f HF L C – 1
0.75 V IN 2 f HF L C – 1
C C = -------------------------------------------------------------------------------------------------- 2 2 f 0 f HF L C R FB V PP
In the solutions to the compensation equations, there is a single
degree of freedom. For the solutions presented in Equation 38,
RFB is selected arbitrarily. The remaining compensation
components are then selected according to Equation 38.
In Equation 38, L is the per-channel filter inductance divided by
the number of active channels; C is the sum total of all output
capacitors; ESR is the equivalent-series resistance of the bulk
output-filter capacitance; and VPP is the peak-to-peak sawtooth
signal amplitude as described in “Electrical Specifications” on
page 9.
1
f 0 > ------------------------------------2 C ESR
Case 3:
2 f 0 V pp L
R C = R FB --------------------------------------------0.66 V IN ESR
0.66 V IN ESR C
C C = ---------------------------------------------------------------2 V PP R FB f 0 L
Output Filter Design
The output inductors and the output capacitor bank together to
form a low-pass filter responsible for smoothing the pulsating
voltage at the phase nodes. The output filter also must provide
the transient energy until the regulator can respond. Because it
has a low bandwidth compared to the switching frequency, the
output filter limits the system transient response. The output
capacitors must supply or sink load current while the current in
the output inductors increases or decreases to meet the
demand.
In high-speed converters, the output capacitor bank is usually the
most costly (and often the largest) part of the circuit. Output filter
design begins with minimizing the cost of this part of the circuit.
The critical load parameters in choosing the output capacitors are
the maximum size of the load step, I, the load-current slew rate,
di/dt, and the maximum allowable output-voltage deviation under
transient loading, VMAX. Capacitors are characterized according
to their capacitance, ESR, and ESL (equivalent series inductance).
At the beginning of the load transient, the output capacitors
supply all of the transient current. The output voltage will initially
deviate by an amount approximated by the voltage drop across
the ESL. As the load current increases, the voltage drop across
the ESR increases linearly until the load current reaches its final
value. The capacitors selected must have sufficiently low ESL and
ESR so that the total output-voltage deviation is less than the
allowable maximum. Neglecting the contribution of inductor
current and regulator response, the output voltage initially
deviates by an amount:
di
V ESL ----- + ESR I
dt
(EQ. 39)
The filter capacitor must have sufficiently low ESL and ESR so
that V < VMAX.
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Page 32 of 38
ISL6329
Most capacitor solutions rely on a mixture of high frequency
capacitors with relatively low capacitance in combination with
bulk capacitors having high capacitance but limited
high-frequency performance. Minimizing the ESL of the
high-frequency capacitors allows them to support the output
voltage as the current increases. Minimizing the ESR of the bulk
capacitors allows them to supply the increased current with less
output voltage deviation.
RT (k)
1k
The ESR of the bulk capacitors also creates the majority of the
output-voltage ripple. As the bulk capacitors sink and source the
inductor AC ripple current (see “Interleaving” on page 12 and
Equation 3), a voltage develops across the bulk capacitor ESR
equal to IC,PP (ESR). Thus, once the output capacitors are
selected, the maximum allowable ripple voltage, VPP(MAX),
determines the lower limit on the inductance.
(EQ. 40)
Since the capacitors are supplying a decreasing portion of the
load current while the regulator recovers from the transient, the
capacitor voltage becomes slightly depleted. The output
inductors must be capable of assuming the entire load current
before the output voltage decreases more than VMAX. This
places an upper limit on inductance.
Equation 41 gives the upper limit on L for the cases when the
trailing edge of the current transient causes a greater
output-voltage deviation than the leading edge. Equation 42
addresses the leading edge. Normally, the trailing edge dictates
the selection of L because duty cycles are usually less than 50%.
Nevertheless, both inequalities should be evaluated, and L
should be selected based on the lower of the two results. In each
equation, L is the per-channel inductance, C is the total output
capacitance, and N is the number of active channels.
2 N C VO
L --------------------------------- V MAX – I ESR
I 2
(EQ. 41)
1.25 N C- V
L ---------------------------MAX – I ESR V IN – V O
I 2
(EQ. 42)
10
10k
100k
1M
10M
SWITCHING FREQUENCY (Hz)
FIGURE 25. R T vs SWITCHING FREQUENCY
Input Capacitor Selection
The input capacitors are responsible for sourcing the AC
component of the input current flowing into the upper MOSFETs.
Their RMS current capacity must be sufficient to handle the AC
component of the current drawn by the upper MOSFETs which is
related to duty cycle and the number of active phases.
0.3
INPUT-CAPACITOR CURRENT (IRMS/IO)
V – N V
OUT V OUT
IN
L ESR -------------------------------------------------------------------f S V IN V PP MAX
100
IL,PP = 0
IL,PP = 0.25 IO
IL,PP = 0.5 IO
IL,PP = 0.75 IO
0.2
0.1
0
0
0.2
0.4
0.6
0.8
1.0
DUTY CYCLE (VO/VIN)
Switching Frequency
There are a number of variables to consider when choosing the
switching frequency, as there are considerable effects on the
upper MOSFET loss calculation. These effects are outlined in
“MOSFETs” on page 28, and they establish the upper limit for the
switching frequency. The lower limit is established by the
requirement for fast transient response and small output-voltage
ripple as outlined in “Output Filter Design” on page 32. Choose
the lowest switching frequency that allows the regulator to meet
the transient-response requirements.
Switching frequency is determined by the selection of the
frequency-setting resistor, RT. Figure 25 and Equation 43 are
provided to assist in selecting the correct value for RT.
R T = 10
10.61 – 1.035 log f S
FN7800 Rev 0.00
April 19, 2011
FIGURE 26. NORMALIZED INPUT-CAPACITOR RMS CURRENT vs DUTY
CYCLE FOR 4-PHASE CONVERTER
For a four-phase design, use Figure 26 to determine the inputcapacitor RMS current requirement set by the duty cycle, maximum
sustained output current (IO), and the ratio of the peak-to-peak
inductor current (IL,PP) to IO. Select a bulk capacitor with a ripple
current rating which will minimize the total number of input
capacitors required to support the RMS current calculated.
The voltage rating of the capacitors should also be at least 1.25
times greater than the maximum input voltage. Figures 27 and 28
provide the same input RMS current information for three-phase
and two-phase designs respectively. Use the same approach for
selecting the bulk capacitor type and number.
(EQ. 43)
Page 33 of 38
ISL6329
INPUT-CAPACITOR CURRENT (IRMS/IO)
0.3
IL,PP = 0
IL,PP = 0.5 IO
IL,PP = 0.25 IO
IL,PP = 0.75 IO
Careful component selection, tight layout of the critical
components, and short, wide circuit traces minimize the
magnitude of voltage spikes.
There are two sets of critical components in a DC/DC converter
using a ISL6329 controller. The power components are the most
critical because they switch large amounts of energy. Next are
small signal components that connect to sensitive nodes or
supply critical bypassing current and signal coupling.
0.2
0.1
0
0
0.2
0.4
0.6
0.8
1.0
DUTY CYCLE (VIN/VO)
FIGURE 27. NORMALIZED INPUT-CAPACITOR RMS CURRENT FOR
3-PHASE CONVERTER
Low capacitance, high-frequency ceramic capacitors are needed in
addition to the input bulk capacitors to suppress leading and
falling edge voltage spikes. The spikes result from the high current
slew rate produced by the upper MOSFET turn on and off. Select
low ESL ceramic capacitors and place one as close as possible to
each upper MOSFET drain to minimize board parasitics and
maximize suppression.
INPUT-CAPACITOR CURRENT (IRMS/IO)
0.3
When placing the MOSFETs, try to keep the source of the upper
FETs and the drain of the lower FETs as close as thermally possible.
Input high-frequency capacitors, CHF, should be placed close to the
drain of the upper FETs and the source of the lower FETs. Input
bulk capacitors, CBULK, case size typically limits following the
same rule as the high-frequency input capacitors. Place the input
bulk capacitors as close to the drain of the upper FETs as possible
and minimize the distance to the source of the lower FETs.
Locate the output inductors and output capacitors between the
MOSFETs and the load. The high-frequency output decoupling
capacitors (ceramic) should be placed as close as practicable to the
decoupling target, making use of the shortest connection paths to
any internal planes, such as vias to GND next or on the capacitor
solder pad.
0.2
0.1
IL,PP = 0
IL,PP = 0.5 IO
IL,PP = 0.75 IO
0
The power components should be placed first, which include the
MOSFETs, input and output capacitors, and the inductors. It is
important to have a symmetrical layout for each power train,
preferably with the controller located equidistant from each.
Symmetrical layout allows heat to be dissipated equally across all
power trains. Equidistant placement of the controller to the CORE
and NB power trains it controls through the integrated drivers
helps keep the gate drive traces equally short, resulting in equal
trace impedances and similar drive capability of all sets of
MOSFETs.
0
0.2
0.4
0.6
0.8
1.0
DUTY CYCLE (VIN/VO)
FIGURE 28. NORMALIZED INPUT-CAPACITOR RMS
CURRENT FOR 2-PHASE CONVERTER
Layout Considerations
MOSFETs switch very fast and efficiently. The speed with which
the current transitions from one device to another causes voltage
spikes across the interconnecting impedances and parasitic
circuit elements. These voltage spikes can degrade efficiency,
radiate noise into the circuit and lead to device overvoltage
stress. Careful component selection, layout, and placement
minimizes these voltage spikes. Consider, as an example, the
turnoff transition of the upper PWM MOSFET. Prior to turnoff, the
upper MOSFET was carrying channel current. During the turnoff,
current stops flowing in the upper MOSFET and is picked up by
the lower MOSFET. Any inductance in the switched current path
generates a large voltage spike during the switching interval.
FN7800 Rev 0.00
April 19, 2011
The critical small components include the bypass capacitors
(CFILTER) for VCC and PVCC, and many of the components
surrounding the controller including the feedback network and
current sense components. Locate the VCC/PVCC bypass
capacitors as close to the ISL6329 as possible. It is especially
important to locate the components associated with the
feedback circuit close to their respective controller pins, since
they belong to a high-impedance circuit loop, sensitive to EMI
pick-up.
A multi-layer printed circuit board is recommended. Figure 29 shows
the connections of the critical components for the converter. Note
that capacitors CIN and COUT could each represent numerous
physical capacitors. Dedicate one solid layer, usually the one
underneath the component side of the board, for a ground plane
and make all critical component ground connections with vias to
this layer. Dedicate another solid layer as a power plane and break
this plane into smaller islands of common voltage levels. Keep the
metal runs from the PHASE terminal to output inductors short. The
power plane should support the input power and output power
nodes. Use copper filled polygons on the top and bottom circuit
layers for the phase nodes. Use the remaining printed circuit layers
for small signal wiring.
Page 34 of 38
ISL6329
Routing UGATE, LGATE, and PHASE Traces
Great attention should be paid to routing the UGATE, LGATE, and
PHASE traces since they drive the power train MOSFETs using
short, high current pulses. It is important to size them as large and
as short as possible to reduce their overall impedance and
inductance. They should be sized to carry at least one ampere of
current (0.02” to 0.05”). Going between layers with vias should also
be avoided, but if so, use two vias for interconnection when possible.
Extra care should be given to the LGATE traces in particular since
keeping their impedance and inductance low helps to significantly
reduce the possibility of shoot-through. It is also important to route
each channels UGATE and PHASE traces in as close proximity as
possible to reduce their inductances.
Current Sense Component Placement and
Trace Routing
One of the most critical aspects of the ISL6329 regulator layout
is the placement of the inductor DCR current sense components
and traces. The R-C current sense components must be placed
as close to their respective ISEN+ and ISEN- pins on the ISL6329
as possible.
The sense traces that connect the R-C sense components to each
side of the output inductors should be routed on the bottom of
the board, away from the noisy switching components located on
the top of the board. These traces should be routed side by side,
and they should be very thin traces. It’s important to route these
traces as far away from any other noisy traces or planes as
possible. These traces should pick up as little noise as possible.
Thermal Management
For maximum thermal performance in high current, high
switching frequency applications, connecting the thermal GND
pad of the ISL6329 to the ground plane with multiple vias is
recommended. This heat spreading allows the part to achieve
its full thermal potential. It is also recommended that the
controller be placed in a direct path of airflow if possible to help
thermally manage the part.
FN7800 Rev 0.00
April 19, 2011
Page 35 of 38
ISL6329
VCC
+5V
ISL6614
BOOT1 PWM1
PWM2
+12V
CS1-
ISEN1- VCC RSVD TCOMP1
CS1+
ISEN1+
CS2-
ISEN2-
CS2+
ISEN2+
CS3-
ISEN3-
CS3+
ISEN3+
CS4-
ISEN4-
CS4+
ISEN4+
CS5-
ISEN5-
CS5+
ISEN5+
CS6-
ISEN6-
CS6+
ISEN6+
CS_NB-
TCOMP2
PWM3
PWM4
PWM5
PWM6
PVCC
GND
UGATE2
PHASE2
+12V
CS4CS4+
+12V
PGND
LGATE2
ISL6614
BOOT1 PWM1
PWM2
+12V
RNTC*
UGATE1
PHASE1
UGATE1
PHASE1
CS1CS1+
CS5CS5+
LGATE1
PWM5
PWM6
+12V
PVCC
VCC
BOOT2
BOOT2
+12V
+12V
GND
UGATE2
PHASE2
LGATE2
I2C_ADDR
FS
UGATE2
PHASE2
CS2CS2+
CS6CS6+
PGND
LGATE2
VSEN
RGND
OFS
CORE_FB
OCP
ENABLE
PVCC
BOOT2
+12V
BOOT1
LGATE1
LGATE1
+12V
VCC
PWM3
PWM4
PWM5
PWM6
ISL6329
ISEN_NB+
+12V
CS3CS3+
GVOT
ISEN_NB-
CS_NB+
UGATE1
PHASE1
PWM3
PWM4
BOOT_NB
VDDIO
SVC
SVD
SCL
SDA
PWROK
VDDPWRGD
CORE
+12V
UGATE_NB
PHASE_NB
LGATE_NB
EN
APA
DRPCTRL
CPU
CS_NBCS_NB+
NORTHBRIDGE
VSEN_NB
FB_NB
RED COMPONENTS:
LOCATE CLOSE TO IC TO
MINIMIZE CONNECTION PATH
BLUE COMPONENTS:
LOCATE NEAR LOAD
(MINIMIZE CONNECTION PATH)
COMP_NB
CORE_FB
FB_PSI
FB
MAGENTA COMPONENTS:
LOCATE CLOSE TO SWITCHING TRANSISTORS
(MINIMIZE CONNECTION PATH)
COMP
GND
KEY
HEAVY TRACE ON CIRCUIT PLANE LAYER
ISLAND ON POWER PLANE LAYER
ISLAND ON CIRCUIT PLANE LAYER
KELVIN TYPE TRACE/SENSE LINE
(Keep these traces away from any switching nodes)
VIA CONNECTION TO GROUND PLANE
*LOCATE NTC RESISTOR CLOSE TO PHASE1 INDUCTOR
FIGURE 29. PRINTED CIRCUIT BOARD POWER PLANES AND ISLANDS
FN7800 Rev 0.00
April 19, 2011
Page 36 of 38
ISL6329
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make
sure you have the latest Rev.
DATE
REVISION
4/19/11
FN7800.0
CHANGE
Initial release.
Products
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address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks.
Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a
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*For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page
on intersil.com: ISL6329
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FITs are available from our website at http://rel.intersil.com/reports/search.php
© Copyright Intersil Americas LLC 2011. All Rights Reserved.
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Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
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Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
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otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN7800 Rev 0.00
April 19, 2011
Page 37 of 38
ISL6329
Package Outline Drawing
L60.7x7
60 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 1, 2/10
4X 5.6
7.00
A
6
PIN #1 INDEX AREA
56X 0.40
B
46
6
60
1
45
PIN 1
INDEX AREA
7.00
5. 60
31
(4X)
15
0.15
16
30
60X 0 . 40
TOP VIEW
0.10 M C A B
0.1672
4 0.20
BOTTOM VIEW
( 60X 0 . 60)
0.2818
SEE DETAIL "X"
( 60X 0 . 20 )
0.10 C C
SEATING PLANE
0.08 C
1.00 MAX
( 6 . 8 TYP )
SIDE VIEW
(
5 . 60 )
( 56X 0 . 4 )
C
0.1672
0 . 2 REF
5
0 . 00 MIN.
0 . 05 MAX.
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
0.4818
NOTES:
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to ASME Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.10
Angular ±2.50°
4.
Dimension applies to the metallized terminal and is measured
between 0.015mm and 0.30mm from the terminal tip.
5.
Tiebar shown (if present) is a non-functional feature.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
FN7800 Rev 0.00
April 19, 2011
Page 38 of 38
