ISL6564IRZ

ISL6564 ® Data Sheet December 27, 2004 Multi-Phase PWM Controller with Linear 6-bit DAC Capable of Precision rDS(ON) or DCR Differential Current Sensing The ISL6564 is a Multi-phase PWM controller which controls microprocessor core voltage regulation by driving up to 4 synchronous-rectified buck channels. It features a high bandwidth control loop to provide optimal response to the load transients. With switching frequency up to 1.5MHz per phase, the ISL6564 based voltage regulator requires minimum components and PCB area in DC/DC converter application. The ISL6564 senses current by utilizing patented techniques to measure the voltage across the on resistance, rDS(on), of the lower MOSFETs or DCR of the output inductor during their conduction intervals. Current sensing provides the needed signals for precision droop, channel-current balancing, and overcurrent protection. A unity gain, differential amplifier is provided for remote voltage sensing. Any potential difference between remote and local grounds can be completely eliminated using the remote-sense amplifier. Eliminating ground differences improves regulation and protection accuracy. The thresholdsensitive enable input is available to accurately coordinate the start up of the ISL6564 with any other voltage rail. Dynamic-VID™ technology allows seamless on-the-fly VID changes. The offset pin allows accurate voltage offset settings that are independent of VID setting. The ISL6564 uses a 5V bias and has a built-in shunt regulator to allow 12V bias using only a small external limiting resistor. Ordering Information PART NUMBER TEMP. (°C) PACKAGE PKG. DWG. # ISL6564CR 0 to 70 40 Ld 6x6 QFN L40.6x6 ISL6564CR-T 0 to 70 40 Ld 6x6 QFN L40.6x6 ISL6564CRZ (Note) 0 to70 40 Ld 6x6 QFN L40.6x6 (Pb-free) ISL6564CRZ-T (Note) 0 to 70 40 Ld 6x6 QFN L40.6x6 (Pb-free) ISL6564IR -40 to 85 40 Ld 6x6 QFN L40.6x6 ISL6564IR-T -40 to 85 40 Ld 6x6 QFN L40.6x6 ISL6564IRZ (Note) -40 to 85 40 Ld 6x6 QFN L40.6x6 (Pb-free) ISL6564IRZ-T (Note) -40 to 85 40 Ld 6x6 QFN L40.6x6 (Pb-free) FN9156.2 Features • Precision Multi-Phase Core Voltage Regulation - Differential Remote Voltage Sensing - ±0.5% System Accuracy - Adjustable Reference-Voltage Offset • Precision rDS(ON) or DCR Current Sensing - Accurate Load-Line Programming - Accurate Channel-Current Balancing - Differential Current Sense - Low-Cost, Lossless Current Sensing • Internal Shunt Regulator for 5V or 12V Biasing • Microprocessor Voltage Identification Input - Self clocked Dynamic VID™ control technology - 6-Bit VID Input - 0.525V to 1.300V in 12.5mV Steps • Threshold-Sensitive Enable Function for power sequencing control • Overcurrent Protection • Overvoltage Protection - No Additional External Components Needed - OVP Pin to drive Crowbar Device • 1, 2, 3, or 4 Phase Operation • Up to 1.5MHz per phase Operation (>6MHz Ripple) • QFN Package - Compliant to JEDEC PUB95 MO-220 QFN - Quad Flat No Leads - Product Outline - QFN Near Chip Scale Package Footprint; Improves PCB Efficiency, Thinner in Profile • Pb-Free Available (RoHS Compliant) NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2004. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL6564 Pinout 2 GND PGOOD OVP GND FS DRVEN ENLL EN VCC PWM4 ISL6564 (40-PIN QFN) TOP VIEW 40 39 38 37 36 35 34 33 32 31 VID5 1 30 ISEN4+ VID4 2 29 ISEN4- VID3 3 28 ISEN2- VID2 4 27 ISEN2+ VID1 5 26 PWM2 GND 9 22 ISEN3- DAC 10 21 ISEN3+ 11 12 13 14 15 16 17 18 19 20 PWM3 IOUT GND 23 ISEN1- RGND 8 VSEN OFS VDIFF 24 ISEN1+ COMP 7 IDROOP GND FB 25 PWM1 GND 6 REF VID0 FN9156.2 December 27, 2004 ISL6564 ISL6564CR Block Diagram OVP VDIFF PGOOD RGND S x1 OVP LATCH VSEN R ENLL VCC DRVEN 1.29V POWER-ON RESET (POR) EN Q THREE-STATE SOFT START AND FAULT LOGIC OVP CLOCK AND SAWTOOTH GENERATOR ∑ +200mV OFS FS PWM1 PWM ∑ OFFSET PWM2 PWM ∑ REF PWM3 PWM DAC ∑ VID5 VID4 PWM4 PWM VID3 DYNAMIC VID VID2 D/A E/A VID1 CHANNEL CURRENT BALANCE VID0 CHANNEL DETECT COMP ISEN1+ I_TRIP FB OC IDROOP ISEN1- ∑ SAMPLE & HOLD CHANNEL ISEN2+ CURRENT ISEN2- SENSE I_TOT ISEN3+ ISEN3- IOUT ISEN4+ ISEN4- GND 3 FN9156.2 December 27, 2004 ISL6564 Typical Application for Voltage Regulation without Droop Using rDS(ON) Sensing +12V VIN VCC BOOT UGATE PVCC PHASE ISL6612 DRIVER PWM LGATE GND +5V FB COMP REF IDROOP VDIFF VSEN ENLL PGOOD OVP VCC BOOT VIN VCC RGND VIDPGOOD +12V DAC UGATE EN ISL6564 VID5 ISEN1+ ISEN1- VID4 PWM1 PVCC PWM PHASE ISL6612 DRIVER PWM2 VID3 LGATE GND ISEN2+ VID2 ISEN2- VID1 PWM3 VID0 ISEN3+ DRVEN ISEN3OFS VIN VCC PWM4 FS IOUT +12V GND ISEN4+ ISEN4- µP LOAD BOOT UGATE PVCC PWM PHASE ISL6612 DRIVER LGATE GND NTC NETWORK +12V VOLTAGE PROPOTIONAL TO LOAD CURRENT VCC VIN BOOT UGATE PVCC PWM PHASE ISL6612 DRIVER LGATE GND 4 FN9156.2 December 27, 2004 ISL6564 Typical Application for Voltage Regulation without Droop Using DCR Sensing +12V VIN VCC BOOT UGATE PVCC PHASE ISL6612 DRIVER PWM LGATE GND +5V FB COMP REF IDROOP VDIFF VSEN ENLL PGOOD OVP VCC BOOT VIN VCC RGND VIDPGOOD +12V DAC UGATE EN ISL6564 VID5 ISEN1+ ISEN1- VID4 PWM1 PVCC PWM PHASE ISL6612 DRIVER PWM2 VID3 LGATE GND ISEN2+ VID2 ISEN2- VID1 PWM3 VID0 ISEN3+ DRVEN ISEN3OFS VIN VCC PWM4 FS IOUT +12V GND ISEN4+ ISEN4- µP LOAD BOOT UGATE PVCC PWM PHASE ISL6612 DRIVER LGATE NTC NETWORK GND VOLTAGE PROPOTIONAL TO LOAD CURRENT +12V VIN VCC BOOT UGATE PVCC PWM PHASE ISL6612 DRIVER LGATE GND 5 FN9156.2 December 27, 2004 ISL6564 Typical Application for Load Line Regulation Using rDS(ON) Sensing and External NTC +12V VIN VCC BOOT UGATE PVCC PHASE ISL6612 DRIVER PWM LGATE FB IDROOP COMP REF VSEN VCC BOOT UGATE ENLL PGOOD PVCC ISL6564 OVP VIN VCC RGND VIDPGOOD +12V DAC VDIFF NTC THERMISTOR GND +5V VID4 ISEN1+ ISEN1- VID3 PWM1 PWM PHASE ISL6612 DRIVER PWM2 VID2 LGATE GND ISEN2+ VID1 ISEN2- VID0 PWM3 VID12.5 ISEN3+ DRVEN ISEN3OFS PWM4 FS ISEN4+ ISEN4- IOUT GND +12V VIN VCC µP LOAD BOOT UGATE PVCC EN PWM +12V PHASE ISL6612 DRIVER LGATE GND NTC NETWORK +12V VCC VIN BOOT VOLTAGE PROPOTIONAL TO LOAD CURRENT UGATE PVCC PWM PHASE ISL6612 DRIVER LGATE GND 6 FN9156.2 December 27, 2004 ISL6564 Typical Application for Load Line Regulation using DCR Sensing and External NTC +12V VCC BOOT VIN UGATE PVCC PHASE ISL6612 PWM DRIVER GND +5V FB IDROOP COMP REF VSEN VCC BOOT UGATE ENLL PGOOD OVP VIN VCC RGND VIDPGOOD NTC THERMISTOR +12V DAC VDIFF LGATE PVCC ISL6564 VID4 ISEN1+ ISEN1- VID3 PWM1 VID2 PWM2 VID1 ISEN2+ ISEN2- VID0 PWM ISEN3+ DRVEN ISEN3OFS PWM4 FS ISEN4+ ISEN4GND IOUT DRIVER LGATE GND +12V PWM3 VID12.5 PHASE ISL6612 VIN VCC µP LOAD BOOT UGATE PVCC EN +12V PWM PHASE ISL6612 DRIVER LGATE GND NTC NETWORK +12V VIN VCC BOOT VOLTAGE PROPOTIONAL TO LOAD CURRENT UGATE PVCC PWM PHASE ISL6612 DRIVER LGATE GND 7 FN9156.2 December 27, 2004 ISL6564 Absolute Maximum Ratings Thermal Information Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7V Input and Output Voltage (except OVP). . GND -0.3V to VCC + 0.3V OVP Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+15V ESD (Human body model) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>4kV ESD (Machine model) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>300V ESD (Charged device model) . . . . . . . . . . . . . . . . . . . . . . . . . .>2kV Thermal Resistance θJA (°C/W) θJC (°C/W) QFN Package (Notes 1, 2). . . . . . . . . . 32 3.5 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150°C Maximum Storage Temperature Range . . . . . . . . . . - 65°C to 150°C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C Operating Conditions Supply Voltage, VCC (5V bias mode, Note 2) . . . . . . . . . . +5V ±5% Ambient Temperature (ISL6564CR, ISL6564CRZ) . . . . 0°C to 70°C Ambient Temperature (ISL6564IR, ISL6564IRZ) . . . . .-40°C to 85°C CAUTION: Stress above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. NOTES: 1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 2. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside. Electrical Specifications Operating Conditions: VCC = 5V or ICC < 25mA (Note 3). Unless Otherwise Specified. PARAMETER TEST CONDITIONS MIN TYP MAX UNITS VCC SUPPLY CURRENT Nominal Supply VCC = 5VDC; EN = 5VDC; RT = 100kΩ, ISEN1 = ISEN2 = ISEN3 = ISEN4 = -70µA - 14 18 mA Shutdown Supply VCC = 5VDC; EN = 0VDC; RT = 100 kΩ - 10 14 mA VCC Voltage VCC tied to 12VDC thru 300Ω resistor, RT = 100kΩ 5 5.9 6.5 V VCC Sink Current VCC tied to 12VDC thru 300Ω resistor, RT = 100kΩ - - 25 mA VCC Rising 4.20 4.31 4.50 V VCC Falling 3.60 3.80 4.00 V EN Rising 1.26 1.29 1.32 V Hysteresis 110 125 135 mV Fault Reset 1.12 1.16 1.20 V ENLL Input Logic Low Level - - 0.4 V ENLL input Logic High Level 0.8 - - V - - 1 µA (Note 3) -0.5 - 0.5 %VID System Accuracy (VID = 0.525V-0.9875V) (Note 3) -0.9 - 0.9 %VID VID Pull Up -55 -45 -35 µA VID Input Low Level - - 0.4 V VID Input High Level 0.8 - - V -200 - 200 µA VID Input Voltage when Floated 1.0 1.15 1.30 V REF Source/Sink Current -50 - 50 µA SHUNT REGULATOR POWER-ON RESET AND ENABLE POR Threshold ENABLE Threshold ENLL Leakage Current ENLL = 5V REFERENCE VOLTAGE AND DAC System Accuracy (VID = 1.V-1.3V) DAC Source/Sink Current VID = 010100 8 FN9156.2 December 27, 2004 ISL6564 Electrical Specifications Operating Conditions: VCC = 5V or ICC < 25mA (Note 3). Unless Otherwise Specified. (Continued) PARAMETER TEST CONDITIONS MIN TYP MAX UNITS Offset resistor connected to ground 388 400 412 mV VCC = 5.000V, offset resistor connected to VCC 2.91 3.0 3.09 V - - 50 µA 260 300 345 kHz 0.08 - 1.5 MHz Sawtooth Amplitude - 2 - V Max Duty Cycle - 66.7 - % PIN-ADJUSTABLE OFFSET Voltage at OFS pin Maximum OFS Source and Sink Current OSCILLATOR Accuracy RT = 100kΩ Adjustment Range ERROR AMPLIFIER Open-Loop Gain RL = 10kΩ to ground - 80 - dB Open-Loop Bandwidth CL = 100pF, RL = 10kΩ to ground - 18 - MHz Maximum Output Voltage 4.0 4.3 - V Output High Voltage @ 2mA 3.7 - - V Output Low Voltage @ 2mA - - 1.35 V - 20 - MHz 2.485 2.500 2.515 V REMOTE-SENSE AMPLIFIER Bandwidth Output Voltage @ 1mA load VSEN - RGND = 2.5V PWM OUTPUT PWM Output Voltage LOW Iload = ±500µA - - 0.3 V PWM Output Voltage HIGH Iload = ±500µA 4.0 - - V DRIVER ENABLE OUTPUT DRVEN Output Voltage LOW Iload = ±1mA - - 0.3 V DRVEN Output Voltage HIGH Iload = ±1mA 4.0 - - V SENSE CURRENT OUTPUT Sensed Current Accuracy ISEN1 = ISEN2 = ISEN3 = ISEN4 = 80µA Overcurrent Trip Level Maximum voltage at IDROOP and IOUT 77 86 95 µA 90 105 120 µA - - 2 V - - 0.3 V POWER GOOD AND PROTECTION MONITORS PGOOD Low Voltage IPGOOD = 4mA Undervoltage Offset From VID VSEN Falling 70 75 80 %VID Overvoltage Threshold Voltage above VID, After Soft Start (Note 4) 180 200 230 mV Before Enable 1.45 1.5 1.55 V VCC < POR Threshold 1.7 1.8 1.87 V VCC ≥ POR Threshold, VSEN Falling - 0.6 - V VCC < POR Threshold - 1.5 - V 3.0 3.6 5.0 V Overvoltage Reset Voltage OVP Drive Voltage IOVP = -10mA, VCC = 5V NOTES: 3. When using the internal shunt regulator, VCC is clamped to 6.2V (max). Current must be limited to 25mA or less. 4. These parts are designed and adjusted for accuracy with all errors in the voltage loop included. 5. During soft-start, VDAC rises from 0 to VID. The overvoltage trip level is the higher of 1.5V and VDAC + 0.2V. 9 FN9156.2 December 27, 2004 ISL6564 Functional Pin Description FB and COMP Supplies all the power necessary to operate the chip. The controller starts to operate when the voltage on this pin exceeds the rising POR threshold and shuts down when the voltage on this pin drops below the falling POR threshold. Connect this pin directly to a +5V supply or through a series 300Ω resistor to a +12V supply. Inverting input and output of the error amplifier, respectively. FB is connected to VDIFF through a resistor. A negative current, proportional to output current is present on the FB pin. A properly sized resistor between VDIFF and FB sets the load line (droop). The droop scale factor is set by the ratio of the ISEN resistors and the lower MOSFET rDS(ON). COMP is tied back to FB through an external R-C network with no DC connection to compensate the regulator. GND DAC and REF Bias and reference ground for the IC. The DAC output pin is the output of the precision internal DAC reference. The REF input pin is the positive input of the Error Amp. In typical applications, a 1kΩ, 1% resistor is used between DAC and REF to generate a precise offset voltage. This voltage is proportional to the offset current determined by the offset resistor from OFS to ground or VCC. A capacitor is used between REF and ground to smooth the voltage transition during Dynamic VID™ operations. VCC EN This pin is a threshold-sensitive enable input for the controller. Connecting the 12V supply to EN through an appropriate resistor divider provides a means to synchronize power-up of the controller and the MOSFET driver ICs. When EN is driven above 1.29V, the ISL6564 is active depending on status of ENLL, the internal POR, and pending fault states. Driving EN below 1.16V will clear all fault states and prime the ISL6564 to soft-start when re-enabled. ENLL This pin is a logic-level enable input for the controller. When asserted to a logic high, the ISL6564 is active depending on status of EN, the internal POR, VID inputs and pending fault states. Deasserting ENLL will clear all fault states and prime the ISL6564 to soft-start when re-enabled. When floating, ENLL pin will be pulled to high internally with a typical voltage as 1.15V. FS A resistor, RT, placed from FS to ground will set the switching frequency. There is an inverse relationship between the value of the resistor and the switching frequency. See Figure 15 and Equation 29. VID5, VID4, VID3, VID2, VID1, and VID0 These are the inputs to the internal DAC that provides the reference voltage for output regulation. Connect these pins either to open-drain outputs with or without external pull-up resistors or to active-pull-up outputs. VID5-VID0 have 45µA internal pull-up current sources that diminish to zero as the voltage rises above the logic-high level. These inputs can be pulled up as high as VCC plus 0.3V. VDIFF, VSEN, and RGND VSEN and RGND form the precision differential remotesense amplifier. This amplifier converts the differential voltage of the remote output to a single-ended voltage referenced to local ground. VDIFF is the amplifier’s output and the input to the regulation and protection circuitry. Connect VSEN and RGND to the sense pins of the remote load. 10 PWM1, PWM2, PWM3, PWM4 Pulse-width modulation outputs. Connect these pins to the PWM input pins of the Intersil driver IC. The number of active channels is determined by the state of PWM3 and PWM4. Leave PWM4 unconnected and tie PWM3 to VCC to configure for 2-phase operation. Tie PWM4 to VCC to configure for 3-phase operation. Tie both PWM4 and PWM3 to high for 1-phase operation. ISEN1+, ISEN1-; ISEN2+, ISEN2-; ISEN3+, ISEN3-; ISEN4+, ISEN4The ISEN+ and ISEN- pins are current sense inputs to individual differential amplifiers. The sensed current is used as a reference for channel balancing, protection, and regulation. Inactive channels should have their respective sense inputs left open (for example, for 3-phase operation open ISEN4+). For DCR sensing, connect each ISEN- pin to the node between the RC sense elements. Tie the ISEN+ pin to the other end of the sense capacitor through a resistor, RISEN. The voltage across the sense capacitor is proportional to the inductor current. The sensed current is proportional to the output current, and scaled by the DCR of the inductor, divided by RISEN. When configured for rDS(ON) current sensing, the ISEN1-, ISEN2-, ISEN3-, and ISEN4- pins are grounded at the lower MOSFET sources. The ISEN1+, ISEN2+, ISEN3+, and ISEN4+ pins are then held at a virtual ground, such that a resistor connected between them, and the drain terminal of the associated lower MOSFET, will carry a current proportional to the current flowing through that channel. The current is determined by the negative voltage developed across the lower MOSFET’s rDS(ON), which is the channel current scaled by rDS(ON). FN9156.2 December 27, 2004 ISL6564 PGOOD PGOOD is used as an indication of the end of soft-start per the microprocessor specification. It is an open-drain logic output that is low impedance until the soft-start is completed. It will be pulled low again once the undervoltage point is reached. IL1 + IL2 + IL3, 7A/DIV IL3, 7A/DIV PWM3, 5V/DIV OFS The OFS pin provides a means to program a dc offset current for generating a dc offset voltage at the REF input. The offset current is generated via an external resistor and precision internal voltage references. The polarity of the offset is selected by connecting the resistor to GND or VCC. For no offset, the OFS pin should be left unterminated. IL2, 7A/DIV PWM2, 5V/DIV IL1, 7A/DIV PWM1, 5V/DIV OVP 1µs/DIV Overvoltage protection pin. This pin pulls to VCC and is latched when an overvoltage condition is detected. Connect this pin to the gate of an SCR or MOSFET tied from VIN or VOUT to ground to prevent damage to the load. This pin may be pulled above VCC as high as 15V to ground with an external resistor. However, it is only capable of pulling low when VCC is above 2V. DRVEN Driver enable pin. This pin can be used to enable the drivers which have enable pins such as ISL6605 or ISL6608. If ISL6564 is used with Intersil ISL6612 drivers, it’s not necessary to use this pin. IDROOP and IOUT IDROOP and IOUT are the output pins of sensed average channel current which is proportional to load current. They are designed for flexible application purposes. In the application which does not require loadline, leave IDROOP pin open. In the application which requires load line, connect IDROOP pin to FB so that the sensed average current will flow through the resistor between FB and VDIFF to create a voltage drop which is proportional to load current. IOUT is typically used for load current indication. Operation Multi-Phase Power Conversion Microprocessor load current profiles have changed to the point that the advantages of multi-phase power conversion are impossible to ignore. The technical challenges associated with producing a single-phase converter which is both cost-effective and thermally viable have forced a change to the cost-saving approach of multi-phase. The ISL6564 controller helps reduce the complexity of implementation by integrating vital functions and requiring minimal output components. The block diagrams on pages 3, 4, 5 and 6 provide top level views of multi-phase power conversion using the ISL6564 controller. 11 FIGURE 1. PWM AND INDUCTOR-CURRENT WAVEFORMS FOR 3-PHASE CONVERTER Interleaving The switching of each channel in a multi-phase converter is timed to be symmetrically out of phase with each of the other channels. In a 3-phase converter, each channel switches 1/3 cycle after the previous channel and 1/3 cycle before the following channel. As a result, the three-phase converter has a combined ripple frequency three times greater than the ripple frequency of any one phase. In addition, the peak-topeak amplitude of the combined inductor currents is reduced in proportion to the number of phases (Equations 1 and 2). Increased ripple frequency and lower ripple amplitude mean that the designer can use less per-channel inductance and lower total output capacitance for any performance specification. Figure 1 illustrates the multiplicative effect on output ripple frequency. The three channel currents (IL1, IL2, and IL3) combine to form the AC ripple current and the DC load current. The ripple component has three times the ripple frequency of each individual channel current. Each PWM pulse is terminated 1/3 of a cycle after the PWM pulse of the previous phase. The peak-to-peak current for each phase is about 7A, and the dc components of the inductor currents combine to feed the load. To understand the reduction of ripple current amplitude in the multi-phase circuit, examine the equation representing an individual channel’s peak-to-peak inductor current. ( V IN – V OUT ) V OUT I PP = ----------------------------------------------------L fS V (EQ. 1) IN In Equation 1, VIN and VOUT are the input and output voltages respectively, L is the single-channel inductor value, and fS is the switching frequency. FN9156.2 December 27, 2004 ISL6564 PWM Operation INPUT-CAPACITOR CURRENT, 10A/DIV CHANNEL 3 INPUT CURRENT 10A/DIV CHANNEL 2 INPUT CURRENT 10A/DIV CHANNEL 1 INPUT CURRENT 10A/DIV 1µs/DIV FIGURE 2. CHANNEL INPUT CURRENTS AND INPUTCAPACITOR RMS CURRENT FOR 3-PHASE CONVERTER The output capacitors conduct the ripple component of the inductor current. In the case of multi-phase converters, the capacitor current is the sum of the ripple currents from each of the individual channels. Compare Equation 1 to the expression for the peak-to-peak current after the summation of N symmetrically phase-shifted inductor currents in Equation 2. Peak-to-peak ripple current decreases by an amount proportional to the number of channels. Outputvoltage ripple is a function of capacitance, capacitor equivalent series resistance (ESR), and inductor ripple current. Reducing the inductor ripple current allows the designer to use fewer or less costly output capacitors. ( V IN – N V OUT ) V OUT I C, PP = ----------------------------------------------------------L fS V (EQ. 2) IN Another benefit of interleaving is to reduce input ripple current. Input capacitance is determined in part by the maximum input ripple current. Multi-phase topologies can improve overall system cost and size by lowering input ripple current and allowing the designer to reduce the cost of input capacitance. The example in Figure 2 illustrates input currents from a three-phase converter combining to reduce the total input ripple current. The converter depicted in Figure 2 delivers 36A to a 1.5V load from a 12V input. The RMS input capacitor current is 5.9A. Compare this to a single-phase converter also stepping down 12V to 1.5V at 36A. The single-phase converter has 11.9A RMS input capacitor current. The single-phase converter must use an input capacitor bank with twice the RMS current capacity as the equivalent three-phase converter. Figures 21, 22 and 23 in the section entitled Input Capacitor Selection can be used to determine the input-capacitor RMS current based on load current, duty cycle, and the number of channels. They are provided as aids in determining the optimal input capacitor solution. Figure 24 shows the single phase input-capacitor RMS current for comparison. 12 The timing of each converter leg is set by the number of active channels. The default channel setting for the ISL6564 is four. One switching cycle is defined as the time between PWM1 pulse termination signals. The pulse termination signal is an internally generated clock signal which triggers the falling edge of PWM1. The cycle time of the pulse termination signal is the inverse of the switching frequency set by the resistor between the FS pin and ground. Each cycle begins when the clock signal commands the channel-1 PWM output to go low. The PWM1 transition signals the channel-1 MOSFET driver to turn off the channel-1 upper MOSFET and turn on the channel-1 synchronous MOSFET. In the default channel configuration, the PWM2 pulse terminates 1/4 of a cycle after PWM1. The PWM3 output follows another 1/4 of a cycle after PWM2. PWM4 terminates another 1/4 of a cycle after PWM3. If PWM3 is connected to VCC, two channel operation is selected and the PWM2 pulse terminates 1/2 of a cycle later. Connecting PWM4 to VCC selects three channel operation and the pulse-termination times are spaced in 1/3 cycle increments. Connecting both PWM3 and PWM4 to VCC selects single-channel operation. Once a PWM signal transitions low, it is held low for a minimum of 1/3 cycle. This forced off time is required to ensure an accurate current sample. Current sensing is described in the next section. After the forced off time expires, the PWM output is enabled. The PWM output state is driven by the position of the error amplifier output signal, VCOMP, minus the current correction signal relative to the sawtooth ramp as illustrated in Figure 4. When the modified VCOMP voltage crosses the sawtooth ramp, the PWM output transitions high. The MOSFET driver detects the change in state of the PWM signal and turns off the synchronous MOSFET and turns on the upper MOSFET. The PWM signal will remain high until the pulse termination signal marks the beginning of the next cycle by triggering the PWM signal low. Current Sampling During the forced off-time following a PWM transition low, the associated channel current sense amplifier uses the ISEN inputs to reproduce a signal proportional to the inductor current, IL. No matter the current sense method, the sense current, ISEN, is simply a scaled version of the inductor current. Coincident with the falling edge of the PWM signal, the sample and hold circuitry samples ISEN, as illustrated in Figure 3. The sample window hold time, tHOLD, is fixed and equal to 1/3 of the switching period, tSW. t SW 1 t HOLD = --------- = -----------------3 3 ⋅ f SW (EQ. 3) Therefore, the sample current, In, is proportional to the output current and held for one switching cycle. The sample current is used for current balance, load-line regulation, and overcurrent protection. FN9156.2 December 27, 2004 ISL6564 VIN I (s) L IL L ISL6207 DCR INDUCTOR + + VC(s) R ISEN PWM(n) COUT - VL - PWM VOUT C ISL6564 INTERNAL CIRCUIT tHOLD SAMPLE CURRENT, In RISEN(n) (PTC) In SWITCHING PERIOD SAMPLE & HOLD TIME ISEN-(n) + FIGURE 3. SAMPLE AND HOLD TIMING - ISEN+(n) Current Sensing The ISL6564 supports inductor DCR sensing, MOSFET rDS(ON) sensing, or resistive sensing techniques. The internal circuitry, shown in Figures 4, 5, and 6, represents channel n of an N-channel converter. This circuitry is repeated for each channel in the converter, but may not be active depending on the status of the PWM3 and PWM4 pins, as described in the PWM Operation section. INDUCTOR DCR SENSING An inductor’s winding is characteristic of a distributed resistance as measured by the DCR (Direct Current Resistance) parameter. Consider the inductor DCR as a separate lumped quantity, as shown in Figure 4. The channel current IL, flowing through the inductor, will also pass through the DCR. Equation 4 shows the s-domain equivalent voltage across the inductor VL. V L = I L ⋅ ( s ⋅ L + DCR ) (EQ. 4) DCR I SEN = I ----------------LR ISEN FIGURE 4. DCR SENSING CONFIGURATION The capacitor voltage VC, is then replicated across the sense resistor RISEN. The current through the sense resistor is proportional to the inductor current. Equation 6 shows the proportion between the channel current and the sensed current ISEN, is driven by the value of the sense resistor chosen and the DCR of the inductor. DCR I SEN = I L ⋅ -----------------R ISEN (EQ. 6) DCR varies with temperature, so a Positive Temperature Coefficient (PTC) resistor should be selected for the sense resistor RISEN. RESISTIVE SENSING A simple R-C network across the inductor extracts the DCR voltage, as shown in Figure 4. The voltage on the capacitor VC, can be shown to be proportional to the channel current IL, see Equation 5. L  s ⋅ ------------+ 1 ⋅ ( DCR ⋅ I L )  DCR  V C = --------------------------------------------------------------------( s ⋅ RC + 1 ) If DCR sensing is not utilized, independent current-sense resistors in series with each output inductor can serve as the sense element (see Figure 5). This technique is more accurate, but reduces overall converter efficiency due to the addition of a lossy element directly in the output path. (EQ. 5) If the R-C network components are selected such that the RC time constant matches the inductor L/DCR time constant, then VC is equal to the voltage drop across the DCR. 13 FN9156.2 December 27, 2004 ISL6564 I L Channel-Current Balance L RSENSE VOUT COUT ISL6564 INTERNAL CIRCUIT RISEN(n) In SAMPLE & HOLD ISEN-(n) + - ISEN+(n) I R SENSE SEN = I L ------------------------R ISEN FIGURE 5. SENSE RESISTOR IN SERIES WITH INDUCTORS The sampled currents In, from each active channel are summed together and divided by the number of active channels. The resulting cycle average current IAVG, provides a measure of the total load current demand on the converter during each switching cycle. Channel current balance is achieved by comparing the sampled current of each channel to the cycle average current, and making an appropriate adjustment to each channel pulse width based on the error. Intersil’s patented current-balance method is illustrated in Figure 7, with error correction for channel 1 represented. In the figure, the cycle average current combines with the channel 1 sample, I1, to create an error signal IER. The filtered error signal modifies the pulse width commanded by VCOMP to correct any unbalance and force IER toward zero. The same method for error signal correction is applied to each active channel. MOSFET rDS(ON) SENSING The controller can also sense the channel load current by sampling the voltage across the lower MOSFET rDS(ON) (see Figure 6). The amplifier is ground-reference by connecting the ISEN- input to the source of the lower MOSFET. ISEN+ connects to the PHASE node through a resistor RISEN. The voltage across RISEN is equivalent to the voltage drop across the rDS(ON) of the lower MOSFET while it is conducting. The resulting current into the ISEN+ pin is proportional to the channel current IL. The ISEN current is then sampled and held after sufficient settling time. The sampled current In, is used for channel-current balance, load-line regulation, and overcurrent protection. From Figure 6, Equation 7 for ISEN is derived. VIN r DS ( ON ) I SEN = I ------------------------L R ISEN In IL SAMPLE & HOLD ISEN+(n) RISEN (PTC) - ISEN-(n) I r L DS ( ON ) + + N-CHANNEL MOSFETs ISL6564 INTERNAL CIRCUIT EXTERNAL CIRCUIT FIGURE 6. MOSFET rDS(ON) CURRENT-SENSING CIRCUIT r DS ( ON ) I SEN = I L ---------------------R ISEN (EQ. 7) where IL is the channel current. Since MOSFET rDS(ON) increases with temperature, a PTC resistor should be chosen for RISEN to compensate for this change. 14 VCOMP + + - FILTER PWM1 SAWTOOTH SIGNAL f(jω) I4 * IER IAVG - + ÷N Σ I3 * I2 I1 NOTE: *Channels 3 and 4 are optional. FIGURE 7. CHANNEL-1 PWM FUNCTION AND CURRENTBALANCE ADJUSTMENT Channel current balance is essential in realizing the thermal advantage of multi-phase operation. The heat generated in down converting is dissipated over multiple devices and a greater area. The designer avoids the complexity of driving multiple parallel MOSFETs, and the expense of using heat sinks and nonstandard magnetic materials. Voltage Regulation The integrating compensation network shown in Figure 8 assures that the steady-state error in the output voltage is limited only to the error in the reference voltage (output of the DAC) and offset errors in the OFS current source, remote-sense and error amplifiers. Intersil specifies the guaranteed tolerance of the ISL6564 to include the combined tolerances of each of these elements. The output of the error amplifier, VCOMP, is compared to the sawtooth waveform to generate the PWM signals. The PWM signals control the timing of the Intersil MOSFET drivers and regulate the converter output to the specified reference voltage. The internal and external circuitry which control voltage regulation is illustrated in Figure 8. FN9156.2 December 27, 2004 ISL6564 EXTERNAL CIRCUIT RC CC COMP RREF VID5 VID4 VID3 VID2 VID1 VID0 DAC 400 mV 200 mV 100 mV 50 mv 25 mV 12.5 mV REF 1 1 1 1 1 1 OFF 1 1 1 1 1 0 1.3000V 1 1 1 1 0 1 1.2875V 1 1 1 1 0 0 1.2750V 1 1 1 0 1 1 1.2625V 1 1 1 0 1 0 1.2500V 1 1 1 0 0 1 1.2375V 1 1 1 0 0 0 1.2250V 1 1 0 1 1 1 1.2125V 1 1 0 1 1 0 1.2000V 1 1 0 1 0 1 1.1875V 1 1 0 1 0 0 1.1750V 1 1 0 0 1 1 1.1625V 1 1 0 0 1 0 1.1500V 1 1 0 0 0 1 1.1375V 1 1 0 0 0 0 1.1250v 1 0 1 1 1 1 1.1125V 1 0 1 1 1 0 1.1000V 1 0 1 1 0 1 1.0875V 1 0 1 1 0 0 1.0750V 1 0 1 0 1 1 1.0625V 1 0 1 0 1 0 1.0500V 1 0 1 0 0 1 1.0375V 1 0 1 0 0 0 1.0250V 1 0 0 1 1 1 1.0125V 1 0 0 1 1 0 1.0000V 1 0 0 1 0 1 0.9875V 1 0 0 1 0 0 0.9750V 1 0 0 0 1 1 0.9625V 1 0 0 0 1 0 0.9500V 1 0 0 0 0 1 0.9375V 1 0 0 0 0 0 0.9250V 0 1 1 1 1 1 0.9125V 0 1 1 1 1 0 0.9000V 0 1 1 1 0 1 0.8875V 0 1 1 1 0 0 0.8750V CREF + - FB RFB IDROOP + VDROOP VDIFF VOUT+ VOUT- TABLE 1. VOLTAGE IDENTIFICATION (VID) CODES ISL6564 INTERNAL CIRCUIT IAVG VCOMP ERROR AMPLIFIER VSEN + - RGND DIFFERENTIAL REMOTE-SENSE AMPLIFIER FIGURE 8. OUTPUT VOLTAGE AND LOAD-LINE REGULATION WITH OFFSET ADJUSTMENT The ISL6564 incorporates an internal differential remotesense amplifier in the feedback path. The amplifier removes the voltage error encountered when measuring the output voltage relative to the local controller ground reference point resulting in a more accurate means of sensing output voltage. Connect the microprocessor sense pins to the noninverting input, VSEN, and inverting input, RGND, of the remote-sense amplifier. The remote-sense output, VDIFF, is connected to the inverting input of the error amplifier through an external resistor. A digital to analog converter (DAC) generates a reference voltage based on the state of logic signals at pins VID4 through VID12.5. The DAC decodes the a 6-bit logic signal (VID) into one of the discrete voltages shown in Table 1. Each VID input offers a 45µA pull-up to an internal 2.5V source for use with open-drain outputs. The pull-up current diminishes to zero above the logic threshold to protect voltage-sensitive output devices. External pull-up resistors can augment the pull-up current sources if case leakage into the driving device is greater than 45µA. Load-Line Regulation Some microprocessor manufacturers require a preciselycontrolled output resistance. This dependence of output voltage on load current is often termed “droop” or “load line” regulation. By adding a well controlled output impedance, the output voltage can effectively be level shifted in a direction which works to achieve the load-line regulation required by these manufacturers. 15 VDAC FN9156.2 December 27, 2004 ISL6564 TABLE 1. VOLTAGE IDENTIFICATION (VID) CODES (Continued) VID5 VID4 VID3 VID2 VID1 VID0 VDAC 0 1 1 0 1 1 0.8625V 0 1 1 0 1 0 0.8500V 0 1 1 0 0 1 0.8375V 0 1 1 0 0 0 0.8250V 0 1 0 1 1 1 0.8125V 0 1 0 1 1 0 0.8000V 0 1 0 1 0 1 0.7875V 0 1 0 1 0 0 0.7750V 0 1 0 0 1 1 0.7625V 0 1 0 0 1 0 0.7500V 0 1 0 0 0 1 0.7375V 0 1 0 0 0 0 0.7250V 0 0 1 1 1 1 0.7125V 0 0 1 1 1 0 0.7000V 0 0 1 1 0 1 0.6875V 0 0 1 1 0 0 0.6750V 0 0 1 0 1 1 0.6625V 0 0 1 0 1 0 0.6500V 0 0 1 0 0 1 0.6375V 0 0 1 0 0 0 0.6250V 0 0 0 1 1 1 0.6125V 0 0 0 1 1 0 0.6000V 0 0 0 1 0 1 0.5875V 0 0 0 1 0 0 0.5750V 0 0 0 0 1 1 0.5625V 0 0 0 0 1 0 0.5500V 0 0 0 0 0 1 0.5375V 0 0 0 0 0 0 0.525V In other cases, the designer may determine that a more cost-effective solution can be achieved by adding droop. Droop can help to reduce the output-voltage spike that results from fast load-current demand changes. The magnitude of the spike is dictated by the ESR and ESL of the output capacitors selected. By positioning the no-load voltage level near the upper specification limit, a larger negative spike can be sustained without crossing the lower limit. By adding a well controlled output impedance, the output voltage under load can effectively be level shifted down so that a larger positive spike can be sustained without crossing the upper specification limit. 16 As shown in Figure 8, a current proportional to the average current in all active channels, IAVG, flows from FB through a load-line regulation resistor, RFB. The resulting voltage drop across RFB is proportional to the output current, effectively creating an output voltage droop with a steady-state value defined as V DROOP = I AVG R FB (EQ. 8) The regulated output voltage is reduced by the droop voltage VDROOP. The output voltage as a function of load current is derived by combining Equation 8 with the appropriate sample current expression defined by the current sense method employed.  I OUT R X  - ------------------ R FB V OUT = V REF – V OFFSET –  -----------4 R   ISEN (EQ. 9) Where VREF is the reference voltage, VOFS is the programmed offset voltage, IOUT is the total output current of the converter, RISEN is the sense resistor in the ISEN line, and RFB is the feedback resistor. RX has a value of DCR, rDS(ON), or RSENSE depending on the sensing method. Output-Voltage Offset Programming The ISL6564 allows the designer to accurately adjust the offset voltage. When a resistor, ROFS, is connected between OFS to VCC, the voltage across it is regulated to 2.0V. This causes a proportional current (IOFS) to flow into OFS. If ROFS is connected to ground, the voltage across it is regulated to 0.5V, and IOFS flows out of OFS. A resistor between DAC and REF, RREF, is selected so that the product (IOFS x ROFS) is equal to the desired offset voltage. These functions are shown in Figure 9. As it may be noticed in Figure 9, the OFSOUT pin must be connected to the REF pin for this current injection to function in ISL6564CR. The current flow through RREF creates an offset at the REF pin, which is ultimately duplicated at the output of the regulator. Once the desired output offset voltage has been determined, use the following formulas to set ROFS: For Positive Offset (connect ROFS to VCC): 2 × R REF R OFS = -------------------------V OFFSET (EQ. 10) For Negative Offset (connect ROFS to GND): 0.5 × R REF R OFS = ----------------------------V OFFSET (EQ. 11) FN9156.2 December 27, 2004 ISL6564 Assuming the microprocessor controls the VID change at 1 bit every TVID, the relationship between the time constant of RREF and CREF network and TVID is given by Equation 12. FB DYNAMIC VID D/A DAC RREF E/A REF C REF R REF = k T VID (EQ. 12) Where, TVID = 4µs, k is the number of the internal VID change cycle. If Typically RREF is selected to be 1kΩ, the allowable delay time for VR to respond to new VID code is 5 VID change cycles (totally 20µs), the value of CREF should be 22nF based on Equation 12. Operation Initialization VCC OR GND 2.0V - ROFS + + 0.5V VCC - ISL6564CR OFS GND FIGURE 9. OUTPUT VOLTAGE OFFSET PROGRAMMING WITH ISL6564CR Prior to converter initialization, proper conditions must exist on the enable inputs and VCC. When the conditions are met, the controller begins soft-start. Once the output voltage is within the proper window of operation, PGOOD asserts logic 1. Enable and Disable While in shutdown mode, the PWM outputs are held in a high-impedance state to assure the drivers remain off. The following input conditions must be met before the ISL6564 is released from shutdown mode. ISL6564 INTERNAL CIRCUIT Dynamic VID Modern microprocessors need to make changes to their core voltage as part of normal operation. They direct the core-voltage regulator to do this by making changes to the VID inputs during regulator operation. The power management solution is required to monitor the DAC inputs and respond to on-the-fly VID changes in a controlled manner. Supervising the safe output voltage transition within the DAC range of the processor without discontinuity or disruption is a necessary function of the core-voltage regulator. The ISL6564 checks the VID inputs at the three edges of 16MHz clock. If the VID code is found to have changed, the controller waits half of a complete cycle before executing a 12.5mV change. If during the half-cycle wait period, the difference between DAC level and the new VID code changes sign, no change is made. If the VID code is more than 1 bit higher or lower than the DAC (not recommended), the controller will execute step-up and step down VID change at a speed of 12.5mV every 4µs until VID and DAC are equal. In order to ensure the smooth transition of output voltage during VID change, a VID step change smoothing network composed of RREF and CREF is required for an ISL6564 based voltage regulator. The selection of RREF is based on the desired offset as detailed above in Output-Voltage Offset Programming. The selection of CREF is based on the time duration for 1 bit VID change and the allowable delay time. 17 EXTERNAL CIRCUIT +12V VCC POR CIRCUIT 10.7kΩ ENABLE COMPARATOR EN + - 1.40kΩ 1.23V ENLL SOFT START AND FAULT LOGIC FIGURE 10. POWER SEQUENCING USING THRESHOLDSENSITIVE ENABLE (EN) FUNCTION 1. The bias voltage applied at VCC must reach the internal power-on reset (POR) rising threshold. Once this threshold is reached, proper operation of all aspects of the ISL6564 is guaranteed. Hysteresis between the rising and falling thresholds assure that once enabled, the ISL6564 will not inadvertently turn off unless the bias voltage drops substantially (see Electrical Specifications). FN9156.2 December 27, 2004 ISL6564 2. The ISL6564 features an enable input (EN) for power sequencing between the controller bias voltage and another voltage rail. The enable comparator holds the ISL6564 in shutdown until the voltage at EN rises above 1.29V. The enable comparator has about 125mV of hysteresis to prevent bounce. It is important that the driver ICs reach their POR level before the ISL6564 becomes enabled. The schematic in Figure 10 demonstrates sequencing the ISL6564 with the ISL66Xx family of Intersil MOSFET drivers, which require 12V bias. VOUT, 500mV/DIV EN, 5V/DIV 3. The voltage on ENLL must be logic high to enable the controller. This pin is typically connected to the VID_PGOOD. 4. The VID code must not be 111111. This code signals the controller that no load is present. The controller will enter shut-down mode after receiving this code and will execute soft-start upon receiving any other code. This code can be used to enable or disable the controller but it is not recommended. After receiving this code, the controller executes a 2-cycle delay before changing the overvoltage trip level to the shut-down level and disabling PWM. Overvoltage shutdown can not be reset using this code. To enable the controller, VCC must be greater than the POR threshold; the voltage on EN must be greater than 1.29V; For ISL6564CR, ENLL must be logic high; and VID cannot be equal to 111111. When each of these conditions is true, the controller immediately begins the soft-start sequence. 500µs/DIV FIGURE 11. SOFT-START WAVEFORMS WITH AN UN-BIASED OUTPUT Fault Monitoring and Protection The ISL6564 actively monitors output voltage and current to detect fault conditions. Fault monitors trigger protective measures to prevent damage to a microprocessor load. One common power good indicator is provided for linking to external system monitors. The schematic in Figure 12 outlines the interaction between the fault monitors and the power good signal. Power Good Signal Soft-Start During soft-start, the DAC voltage ramps linearly from zero to the programmed VID level as shown in Figure 11. The PWM signals remain in the high-impedance state until the controller detects that the ramping DAC level has reached the pre-bias output-voltage level. This protects the system against the large, negative inductor currents that would otherwise occur when starting with a pre-existing charge on the output as the controller attempted to regulate to zero volts at the beginning of the soft-start cycle. The soft-start time, tSS, begins with a delay period equal to 64 switching cycles followed by a linear ramp with a fixed rate at a speed of 12.5mV/32µs. t SS = ( 2560 )VID The power good pin (PGOOD) is an open-drain logic output indication that the converter is operating after soft-start. PGOOD pulls low during shutdown and releases high after a successful soft-start. PGOOD will only transition low when an undervoltage condition is detected or the controller is disabled by a reset from EN, ENLL, POR, or one of the noCPU VID codes. After an undervoltage event, PGOOD will return high unless the controller has been disabled. PGOOD does not automatically transition low upon detection of an overvoltage condition. (EQ. 13) Equation 13 can be used to calculate the soft-start time. For example, when VID is set to 1.2V, the soft-start time will be 3.072ms. A 100mV offset exists on the remote-sense amplifier at the beginning of soft-start and ramps to zero during the first 640 cycles of soft-start (704 cycles following enable). This prevents the large inrush current that would otherwise occur should the output voltage start out with a slight negative bias. 18 FN9156.2 December 27, 2004 ISL6564 PGOOD - 110µA + I1 OC - + UV REPEAT FOR EACH CHANNEL 75% DAC REFERENCE VDIFF SOFT START, FAULT AND CONTROL LOGIC + - 110µA + IAVG OC OVP OV VID + 0.2V FIGURE 12. POWER GOOD AND PROTECTION CIRCUITRY Undervoltage Detection The undervoltage threshold is set at 75% of the VID code. When the output voltage at VSEN is below the undervoltage threshold, PGOOD gets pulled low. Overvoltage Protection When VCC is above 1.4V, but otherwise not valid as defined under Power on Reset in Electrical Specifications, the overvoltage trip circuit is active using auxiliary circuitry. In this state, an overvoltage trip occurs if the voltage at VSEN exceeds 1.8V. With valid VCC, the overvoltage circuit is sensitive to the voltage at VDIFF. In this state, the trip level is 1.7V prior to valid enable conditions being met as described in Enable and Disable. The only exception to this is when the IC has been disabled by an overvoltage trip. In that case the overvoltage trip point is VID plus 200mV. During soft-start, the overvoltage trip level is the higher of 1.5V or VID plus 200mV. Upon successful soft-start, the overvoltage trip level is 200mV above VID. Two actions are taken by the ISL6564 to protect the microprocessor load when an overvoltage condition occurs. At the inception of an overvoltage event, all PWM outputs are commanded low instantly (less than 20ns) until the voltage at VSEN falls below 0.6V with valid VCC or 1.5V otherwise. This causes the Intersil drivers to turn on the lower MOSFETs and pull the output voltage below a level that might cause damage to the load. The PWM outputs remain low until VDIFF falls to the programmed DAC level when they enter a high-impedance state. The Intersil drivers respond to the high-impedance input by turning off both upper and lower MOSFETs. If the overvoltage condition 19 reoccurs, the ISL6564 will again command the lower MOSFETs to turn on. The ISL6564 will continue to protect the load in this fashion as long as the overvoltage condition recurs. Simultaneous to the protective action of the PWM outputs, the OVP pin pulls to VCC delivering up to 100mA to the gate of a crowbar MOSFET or SCR placed either on the input rail or the output rail. Turning on the MOSFET or SCR collapses the power rail and causes a fuse placed further up stream to blow. The fuse must be sized such that the MOSFET or SCR will not overheat before the fuse blows. The OVP pin is tolerant to 12V (see Absolute Maximum Ratings), so an external resistor pull up can be used to augment the driving capability. If using a pull up resistor in conjunction with the internal overvoltage protection function, care must be taken to avoid nuisance trips that could occur when VCC is below 2V. In that case, the controller is incapable of holding OVP low. Once an overvoltage condition is detected, normal PWM operation ceases until the ISL6564 is reset. Cycling the voltage on EN or ENLL or VCC below the POR-falling threshold will reset the controller. Cycling the VID codes will not reset the controller. Overcurrent Protection ISL6564 has two levels of overcurrent protection. Each phase is protected from a sustained overcurrent condition on a delayed basis, while the combined phase currents are protected on an instantaneous basis. In instantaneous protection mode, the ISL6564 takes advantage of the proportionality between the load current and the average current, IAVG, to detect an overcurrent condition. See the Channel-Current Balance section for more detail on how the average current is measured. The average current is continually compared with a constant 110µA reference current as shown in Figure 10. Once the average current exceeds the reference current, a comparator triggers the converter to shutdown. In individual overcurrent protection mode, the ISL6564 continuously compares the current of each channel with the same 110µA reference current. If any channel current exceeds the reference current continuously for eight consecutive cycles, the comparator triggers the converter to shutdown. FN9156.2 December 27, 2004 ISL6564 In normal operation, DRVEN remains low until ISL6564 begins soft-start ramp and then changes to high (Figure 14). When an overcurrent event occurs, DRVEN is pulled to low instantly (less than 20ns) to disable the driver so that both upper and lower FETs be turned off (Figure 15). During an overvoltage condition, DRVEN remains high to allow the driver turn on the lower FETs based on the PWM input to discharge the energy stored in the output inductor. Once the Output voltage is reduced to 0.6V, DRVEN is pulled to low as shown in Figure 16. OUTPUT CURRENT, 50A/DIV 0A OUTPUT VOLTAGE, 500mV/DIV DRVEN, 5V/DIV 0V 0V 2ms/DIV OUTPUT CURRENT, 50A/DIV FIGURE 13. OVERCURRENT BEHAVIOR IN HICCUP MODE. FSW = 500kHz At the beginning of overcurrent shutdown, the controller places all PWM signals in a high-impedance state within 20ns commanding the Intersil MOSFET driver ICs to turn off both upper and lower MOSFETs. The system remains in this state a period of 4096 switching cycles. If the controller is still enabled at the end of this wait period, it will attempt a softstart. If the fault remains, the trip-retry cycles will continue indefinitely (as shown in Figure 13) until either controller is disabled or the fault is cleared. Note that the energy delivered during trip-retry cycling is much less than during full-load operation, so there, there is no thermal hazard during this kind of operation. 0A OUTPUT VOLTAGE, 500mV/DIV 0V 2ms/DIV FIGURE 15. DRVEN DURING OVERCURRENT OPERATION DRVEN, 5V/DIV DRVEN, 5V/DIV OUTPUT VOLTAGE, 500mV/DIV VOUT, 1V/DIV EN, 5V/DIV 2ms/DIV FIGURE 16. DRVEN DURING OVERCURRENT OPERATION 500µs/DIV FIGURE 14. DRVEN WAVEFORM AT STARTUP There’s no need to use DRVEN when ISL6564 is used to work with Intersil’s drivers such as ISL6612 and ISL6605. Driver Enable Output Current Sense Output The ISL6564 has a driver enable output pin DRVEN. The DRVEN is designed for the application where ISL6564 needs to work with drivers that can not recognize three-state PWM input. The ISL6564 has 2 current sense output pins IDROOP and IOUT. They are identical. In typical application, IDROOP pin is connected to FB pin for the application where load line is required. IOUT pin was designed for load current measurement. As shown in typical application schematics 20 FN9156.2 December 27, 2004 ISL6564 on pages 4 to 7, load current information can be obtained by measuring the voltage between IOUT to ground when a NTC network from IOUT pin to the ground is placed. The output current at IOUT pin is proportional to load current as shown in Figure 17. current range. If through-hole MOSFETs and inductors can be used, higher per-phase currents are possible. In cases where board space is the limiting constraint, current can be pushed as high as 40A per phase, but these designs require heat sinks and forced air to cool the MOSFETs, inductors and heat-dissipating surfaces. MOSFETs The choice of MOSFETs depends on the current each MOSFET will be required to conduct; the switching frequency; the capability of the MOSFETs to dissipate heat; and the availability and nature of heat sinking and air flow. V_IOUT, 200mV/DIV LOWER MOSFET POWER CALCULATION 0A 50A 100A FIGURE 17. VOLTAGE AT IOUT PIN WITH A NTC NETWORK PLACED BETWEEN IOUT TO GROUND WHEN LOAD CURRENT CHANGES When selecting the equivalent resistor network components values, it is important to ensure the voltage at IOUT pin not exceed 2V. When ISL6564 is operated at single phase mode (both PWM3 and PWM4 connected to VCC and PWM2 unconnected). The output current at IOUT and IDROOP is half of the sensed phase current. General Design Guide This design guide is intended to provide a high-level explanation of the steps necessary to create a multi-phase power converter. It is assumed that the reader is familiar with many of the basic skills and techniques referenced below. In addition to this guide, Intersil provides complete reference designs that include schematics, bills of materials, and example board layouts for all common microprocessor applications. Power Stages The first step in designing a multi-phase converter is to determine the number of phases. This determination depends heavily on the cost analysis which in turn depends on system constraints that differ from one design to the next. Principally, the designer will be concerned with whether components can be mounted on both sides of the circuit board; whether through-hole components are permitted; and the total board space available for power-supply circuitry. Generally speaking, the most economical solutions are those in which each phase handles between 15 and 20A. All surface-mount designs will tend toward the lower end of this 21 The calculation for heat dissipated in the lower MOSFET is simple, since virtually all of the heat loss in the lower MOSFET is due to current conducted through the channel resistance (rDS(ON)). In Equation 14, IM is the maximum continuous output current; IPP is the peak-to-peak inductor current (see Equation 1); d is the duty cycle (VOUT/VIN); and L is the per-channel inductance. I L, 2PP ( 1 – d )  I M 2 P LOW, 1 = r DS ( ON )  ----- ( 1 – d ) + -------------------------------12  N (EQ. 14) An additional term can be added to the lower-MOSFET loss equation to account for additional loss accrued during the dead time when inductor current is flowing through the lower-MOSFET body diode. This term is dependent on the diode forward voltage at IM, VD(ON); the switching frequency, fS; and the length of dead times, td1 and td2, at the beginning and the end of the lower-MOSFET conduction interval respectively. I  I M I PP M I PP t P LOW, 2 = V D ( ON ) f S  ----- t d1 +  ----- – --------- d2  N- + -------2  N 2  (EQ. 15) Thus the total maximum power dissipated in each lower MOSFET is approximated by the summation of PLOW,1 and PLOW,2. UPPER MOSFET POWER CALCULATION In addition to rDS(ON) losses, a large portion of the upperMOSFET losses are due to currents conducted across the input voltage (VIN) during switching. Since a substantially higher portion of the upper-MOSFET losses are dependent on switching frequency, the power calculation is more complex. Upper MOSFET losses can be divided into separate components involving the upper-MOSFET switching times; the lower-MOSFET body-diode reverserecovery charge, Qrr; and the upper MOSFET rDS(ON) conduction loss. When the upper MOSFET turns off, the lower MOSFET does not conduct any portion of the inductor current until the voltage at the phase node falls below ground. Once the lower MOSFET begins conducting, the current in the upper MOSFET falls to zero as the current in the lower MOSFET FN9156.2 December 27, 2004 ISL6564 ramps up to assume the full inductor current. In Equation 16, the required time for this commutation is t1 and the approximated associated power loss is PUP,1. I M I PP  t 1  P UP,1 ≈ V IN  -----  ----  f  N- + -------2  2 S (EQ. 16) At turn on, the upper MOSFET begins to conduct and this transition occurs over a time t2. In Equation 17, the approximate power loss is PUP,2.  I M I PP  t 2  P UP, 2 ≈ V IN  ----- – ---------  ----  f S 2  2 N (EQ. 17) A third component involves the lower MOSFET’s reverserecovery charge, Qrr. Since the inductor current has fully commutated to the upper MOSFET before the lowerMOSFET’s body diode can draw all of Qrr, it is conducted through the upper MOSFET across VIN. The power dissipated as a result is PUP,3 and is approximately P UP,3 = V IN Q rr f S (EQ. 18) Finally, the resistive part of the upper MOSFET’s is given in Equation 18 as PUP,4. The total power dissipated by the upper MOSFET at full load can now be approximated as the summation of the results from Equations 16, 17, 18 and 19. Since the power equations depend on MOSFET parameters, choosing the correct MOSFETs can be an iterative process involving 2  I M I PP2 P UP,4 ≈ r DS ( ON )  ----- d + ---------12  N (EQ. 19) Current Sensing Resistor The resistors connected between these pins and the respective phase nodes determine the gains in the load-line regulation loop and the channel-current balance loop as well as setting the overcurrent trip point. Select values for these resistors based on the room temperature rDS(ON) of the lower MOSFETs, DCR of inductor or additional resistor; the full-load operating current, IFL; and the number of phases, N using Equation 20. I FL -------N (EQ. 20) In certain circumstances, it may be necessary to adjust the value of one or more ISEN resistor. When the components of one or more channels are inhibited from effectively dissipating their heat so that the affected channels run hotter than desired, choose new, smaller values of RISEN for the affected phases (see the section entitled Channel-Current Balance). Choose RISEN,2 in proportion to the desired 22 ∆T R ISEN ,2 = R ISEN ----------2 ∆T 1 (EQ. 21) In Equation 21, make sure that ∆T2 is the desired temperature rise above the ambient temperature, and ∆T1 is the measured temperature rise above the ambient temperature. While a single adjustment according to Equation 21 is usually sufficient, it may occasionally be necessary to adjust RISEN two or more times to achieve optimal thermal balance between all channels. Load-Line Regulation Resistor The load-line regulation resistor is labeled RFB in Figure 8. Its value depends on the desired full-load droop voltage (VDROOP in Figure 8). If Equation 20 is used to select each ISEN resistor, the load-line regulation resistor is as shown in Equation 22. V DROOP R FB = -----------------------–6 70 ×10 (EQ. 22) If one or more of the ISEN resistors is adjusted for thermal balance, as in Equation 21, the load-line regulation resistor should be selected according to Equation 23 where IFL is the full-load operating current and RISEN(n) is the ISEN resistor connected to the nth ISEN pin. V DROOP R FB = -------------------------------I FL r DS ( ON ) ∑ RISEN ( n ) (EQ. 23) n Compensation The two opposing goals of compensating the voltage regulator are stability and speed. Depending on whether the regulator employs the optional load-line regulation as described in Load-Line Regulation, there are two distinct methods for achieving these goals. repetitive solutions to the loss equations for different MOSFETs and different switching frequencies. RX R ISEN = ---------------------70 ×10 – 6 decrease in temperature rise in order to cause proportionally less current to flow in the hotter phase. COMPENSATING LOAD-LINE REGULATED CONVERTER The load-line regulated converter behaves in a similar manner to a peak-current mode controller because the two poles at the output-filter L-C resonant frequency split with the introduction of current information into the control loop. The final location of these poles is determined by the system function, the gain of the current signal, and the value of the compensation components, RC and CC. Since the system poles and zero are affected by the values of the components that are meant to compensate them, the solution to the system equation becomes fairly complicated. Fortunately there is a simple approximation that comes very close to an optimal solution. Treating the system as though it were a voltage-mode regulator by compensating the L-C poles and the ESR zero of the voltage-mode approximation yields a solution that is always stable with very close to ideal transient performance. FN9156.2 December 27, 2004 ISL6564 C2 C2 (OPTIONAL) RC CC COMP IDROOP C1 ISL6564 + VDROOP R1 - FIGURE 18. COMPENSATION CONFIGURATION FOR LOAD-LINE REGULATED ISL6564 CIRCUIT The feedback resistor, RFB, has already been chosen as outlined in Load-Line Regulation Resistor. Select a target bandwidth for the compensated system, f0. The target bandwidth must be large enough to assure adequate transient performance, but smaller than 1/3 of the perchannel switching frequency. The values of the compensation components depend on the relationships of f0 to the L-C pole frequency and the ESR zero frequency. For each of the three cases which follow, there is a separate set of equations for the compensation components. 1 ------------------- > f 0 2π LC 2πf 0 V pp LC R C = R FB ----------------------------------0.75V IN 0.75V IN C C = ----------------------------------2πV PP R FB f 0 Case 2: (EQ. 24) IN 0.75V IN C C = -----------------------------------------------------------( 2π ) 2 f 02 V PP R FB LC Case 3: 1 f 0 > -----------------------------2πC ( ESR ) 2π f 0 V pp L R C = R FB ----------------------------------------0.75 V IN ( ESR ) 0.75V IN ( ESR ) C C C = -----------------------------------------------2πV PP R FB f 0 L In Equations 25, L is the per-channel filter inductance divided by the number of active channels; C is the sum total of all output capacitors; ESR is the equivalent-series 23 IDROOP FIGURE 19. COMPENSATION CIRCUIT FOR ISL6564 BASED CONVERTER WITHOUT LOAD-LINE REGULATION resistance of the bulk output-filter capacitance; and VPP is the peak-to-peak sawtooth signal amplitude as described in Figure 6 and Electrical Specifications. The optional capacitor C2, is sometimes needed to bypass noise away from the PWM comparator (see Figure 21). Keep a position available for C2, and be prepared to install a highfrequency capacitor of between 22pF and 150pF in case any leading-edge jitter problem is noted. Once selected, the compensation values in Equations 23 assure a stable converter with reasonable transient performance. In most cases, transient performance can be improved by making adjustments to RC. Slowly increase the value of RC while observing the transient performance on an oscilloscope until no further improvement is noted. Normally, CC will not need adjustment. Keep the value of CC from Equations 23 unless some performance issue is noted. COMPENSATION WITHOUT LOAD-LINE REGULATION 1 1 ------------------- ≤ f 0 < ----------------------------2πC ( ESR ) 2π LC V PP ( 2π ) 2 f 02 LC R C = R FB -------------------------------------------0.75 V RFB VDIFF VDIFF Case 1: COMP FB FB RFB CC ISL6564 RC The non load-line regulated converter is accurately modeled as a voltage-mode regulator with two poles at the L-C resonant frequency and a zero at the ESR frequency. A type III controller, as shown in Figure 22, provides the necessary compensation. The first step is to choose the desired bandwidth, f0, of the compensated system. Choose a frequency high enough to assure adequate transient performance but not higher than 1/3 of the switching frequency. The type-III compensator has an extra high-frequency pole, fHF. This pole can be used for added noise rejection or to assure adequate attenuation at the error-amplifier high-order pole and zero frequencies. A good general rule is to choose fHF = 10f0, but it can be higher if desired. Choosing fHF to be lower than 10f0 can cause problems with too much phase shift below the system bandwidth. In the solutions to the compensation equations, there is a single degree of freedom. For the solutions presented in Equations 26, RFB is selected arbitrarily. The remaining FN9156.2 December 27, 2004 ISL6564 compensation components are then selected according to Equations 26. C ( ESR ) R 1 = R FB ----------------------------------------LC – C ( ESR ) voltage deviation is less than the allowable maximum. Neglecting the contribution of inductor current and regulator response, the output voltage initially deviates by an amount di ∆V ≈ ( ESL ) ----- + ( ESR ) ∆I dt LC – C ( ESR ) C 1 = ----------------------------------------R FB (EQ. 26) The filter capacitor must have sufficiently low ESL and ESR so that ∆V < ∆VMAX. 0.75V IN C 2 = -----------------------------------------------------------------( 2π ) 2 f 0 f HF LCR FB V PP Most capacitor solutions rely on a mixture of high-frequency capacitors with relatively low capacitance in combination with bulk capacitors having high capacitance but limited high-frequency performance. Minimizing the ESL of the high-frequency capacitors allows them to support the output voltage as the current increases. Minimizing the ESR of the bulk capacitors allows them to supply the increased current with less output voltage deviation. 2 V PP  2π f 0 f HF LCR FB   R C = -------------------------------------------------------------------  0.75 V IN 2πf HF LC – 1  0.75V IN 2πf  HF LC – 1 C C = ------------------------------------------------------------------( 2π ) 2 f 0 f HF LCR FB V PP (EQ. 25) In Equations 26, L is the per-channel filter inductance divided by the number of active channels; C is the sum total of all output capacitors; ESR is the equivalent-series resistance of the bulk output-filter capacitance; and VPP is the peak-to-peak sawtooth signal amplitude as described in Figure 6 and Electrical Specifications. Output Filter Design The output inductors and the output capacitor bank together to form a low-pass filter responsible for smoothing the pulsating voltage at the phase nodes. The output filter also must provide the transient energy until the regulator can respond. Because it has a low bandwidth compared to the switching frequency, the output filter necessarily limits the system transient response. The output capacitor must supply or sink load current while the current in the output inductors increases or decreases to meet the demand. In high-speed converters, the output capacitor bank is usually the most costly (and often the largest) part of the circuit. Output filter design begins with minimizing the cost of this part of the circuit. The critical load parameters in choosing the output capacitors are the maximum size of the load step, ∆I; the load-current slew rate, di/dt; and the maximum allowable output-voltage deviation under transient loading, ∆VMAX. Capacitors are characterized according to their capacitance, ESR, and ESL (equivalent series inductance). At the beginning of the load transient, the output capacitors supply all of the transient current. The output voltage will initially deviate by an amount approximated by the voltage drop across the ESL. As the load current increases, the voltage drop across the ESR increases linearly until the load current reaches its final value. The capacitors selected must have sufficiently low ESL and ESR so that the total output- 24 The ESR of the bulk capacitors also creates the majority of the output-voltage ripple. As the bulk capacitors sink and source the inductor ac ripple current (see Interleaving and Equation 2), a voltage develops across the bulk-capacitor ESR equal to IC,PP (ESR). Thus, once the output capacitors are selected, the maximum allowable ripple voltage, VPP(MAX), determines the lower limit on the inductance. V – N V  OUT V OUT  IN L ≥ ( ESR ) -----------------------------------------------------------f S V IN V PP( MAX ) (EQ. 27) Since the capacitors are supplying a decreasing portion of the load current while the regulator recovers from the transient, the capacitor voltage becomes slightly depleted. The output inductors must be capable of assuming the entire load current before the output voltage decreases more than ∆VMAX. This places an upper limit on inductance. Equation 29 gives the upper limit on L for the cases when the trailing edge of the current transient causes a greater output-voltage deviation than the leading edge. Equation 30 addresses the leading edge. Normally, the trailing edge dictates the selection of L because duty cycles are usually 2NCVO - ∆V MAX – ∆I ( ESR ) L ≤ -------------------( ∆I ) 2 ( 1.25 ) NC L ≤ -------------------------- ∆V MAX – ∆I ( ESR )  V IN – V O   ( ∆I ) 2 (EQ. 28) (EQ. 29) less than 50%. Nevertheless, both inequalities should be evaluated, and L should be selected based on the lower of the two results. In each equation, L is the per-channel inductance, C is the total output capacitance, and N is the number of active channels. FN9156.2 December 27, 2004 ISL6564 Input Supply Voltage Selection There are a number of variables to consider when choosing the switching frequency, as there are considerable effects on the upper-MOSFET loss calculation. These effects are outlined in MOSFETs, and they establish the upper limit for the switching frequency. The lower limit is established by the requirement for fast transient response and small outputvoltage ripple as outlined in Output Filter Design. Choose the lowest switching frequency that allows the regulator to meet the transient-response requirements. Switching frequency is determined by the selection of the frequency-setting resistor, RT (see the figures labeled Typical Application on pages 4, 5, 6 and 7). Figure 23 and Equation 31 are provided to assist in selecting the correct value for RT. RT (kΩ) 1000 100 0.2 0.1 IL,PP = 0 IL,PP = 0.5 IO IL,PP = 0.75 IO 0 0 0.2 0.4 0.6 0.8 1.0 DUTY CYCLE (VO/VIN) FIGURE 21. NORMALIZED INPUT-CAPACITOR RMS CURRENT vs DUTY CYCLE FOR 2-PHASE CONVERTER 0.3 INPUT-CAPACITOR CURRENT (IRMS/IO) Switching Frequency INPUT-CAPACITOR CURRENT (IRMS/IO) 0.3 The VCC input of the ISL6564 can be connected either directly to a +5V supply or through a current limiting resistor to a +12V supply. An integrated 5.8V shunt regulator maintains the voltage on the VCC pin when a +12V supply is used. A 300Ω resistor is suggested for limiting the current into the VCC pin to a worst-case maximum of approximately 25mA. IL,PP = 0 IL,PP = 0.5 IO IL,PP = 0.25 IO IL,PP = 0.75 IO 0.2 0.1 0 0 0.2 0.4 0.6 0.8 1.0 DUTY CYCLE (VO/VIN) FIGURE 22. NORMALIZED INPUT-CAPACITOR RMS CURRENT vs DUTY CYCLE FOR 3-PHASE CONVERTER 10 10 100 1000 SWITCHING FREQUENCY (kHz) 10000 FIGURE 20. RT vs SWITCHING FREQUENCY R T = 10 [10.886 – 1.0792 log ( f S ) ] (EQ. 30) Input Capacitor Selection The input capacitors are responsible for sourcing the ac component of the input current flowing into the upper MOSFETs. Their RMS current capacity must be sufficient to handle the ac component of the current drawn by the upper MOSFETs which is related to duty cycle and the number of active phases. 25 For a two phase design, use Figure 24 to determine the input-capacitor RMS current requirement given the duty cycle, maximum sustained output current (IO), and the ratio of the per-phase peak-to-peak inductor current (IL,PP) to IO. Select a bulk capacitor with a ripple current rating which will minimize the total number of input capacitors required to support the RMS current calculated. The voltage rating of the capacitors should also be at least 1.25 times greater than the maximum input voltage. Figures 24 and 25 provide the same input RMS current information for three and four phase designs respectively. Use the same approach to selecting the bulk capacitor type and number as described above. Low capacitance, high-frequency ceramic capacitors are needed in addition to the bulk capacitors to suppress leading and falling edge voltage spikes. The result from the high current slew rates produced by the upper MOSFETs turn on FN9156.2 December 27, 2004 ISL6564 and off. Select low ESL ceramic capacitors and place one as close as possible to each upper MOSFET drain to minimize board parasitic impedances and maximize suppression. INPUT-CAPACITOR CURRENT (IRMS/IO) 0.3 IL,PP = 0 IL,PP = 0.25 IO IL,PP = 0.5 IO IL,PP = 0.75 IO 0.1 0 0.2 0.4 0.6 0.8 1.0 DUTY CYCLE (VO/VIN) FIGURE 23. NORMALIZED INPUT-CAPACITOR RMS CURRENT vs DUTY CYCLE FOR 4-PHASE CONVERTER MULTI-PHASE RMS IMPROVEMENT Figure 24 is provided as a reference to demonstrate the dramatic reductions in input-capacitor RMS current upon the implementation of the multi-phase topology. For example, compare the input rms current requirements of a two-phase converter versus that of a single phase. Assume both converters have a duty cycle of 0.25, maximum sustained output current of 40A, and a ratio of IL,PP to IO of 0.5. The single phase converter would require 17.3 Arms current capacity while the two-phase converter would only require 10.9 Arms. The advantages become even more pronounced when output current is increased and additional phases are added to keep the component cost down relative to the single phase approach. 0.6 INPUT-CAPACITOR CURRENT (IRMS/IO) The following layout strategies are intended to minimize the impact of board parasitic impedances on converter performance and to optimize the heat-dissipating capabilities of the printed-circuit board. These sections highlight some important practices which should not be overlooked during the layout process. Component Placement 0.2 0 Layout Considerations Within the allotted implementation area, orient the switching components first. The switching components are the most critical because they carry large amounts of energy and tend to generate high levels of noise. Switching component placement should take into account power dissipation. Align the output inductors and MOSFETs such that space between the components is minimized while creating the PHASE plane. Place the Intersil MOSFET driver IC as close as possible to the MOSFETs they control to reduce the parasitic impedances due to trace length between critical driver input and output signals. If possible, duplicate the same placement of these components for each phase. Next, place the input and output capacitors. Position one high-frequency ceramic input capacitor next to each upper MOSFET drain. Place the bulk input capacitors as close to the upper MOSFET drains as dictated by the component size and dimensions. Long distances between input capacitors and MOSFET drains result in too much trace inductance and a reduction in capacitor performance. Locate the output capacitors between the inductors and the load, while keeping them in close proximity to the microprocessor socket. The ISL6564 can be placed off to one side or centered relative to the individual phase switching components. Routing of sense lines and PWM signals will guide final placement. Critical small signal components to place close to the controller include the ISEN resistors, RT resistor, feedback resistor, and compensation components. Bypass capacitors for the ISL6564 and ISL66XX driver bias supplies must be placed next to their respective pins. Trace parasitic impedances will reduce their effectiveness. 0.4 Plane Allocation and Routing Dedicate one solid layer, usually a middle layer, for a ground plane. Make all critical component ground connections with vias to this plane. Dedicate one additional layer for power planes; breaking the plane up into smaller islands of common voltage. Use the remaining layers for signal wiring. 0.2 IL,PP = 0 IL,PP = 0.5 IO IL,PP = 0.75 IO 0 0 0.2 0.4 0.6 0.8 1.0 DUTY CYCLE (VO/VIN) FIGURE 24. NORMALIZED INPUT-CAPACITOR RMS CURRENT vs DUTY CYCLE FOR SINGLE-PHASE CONVERTER 26 Route phase planes of copper filled polygons on the top and bottom once the switching component placement is set. Size the trace width between the driver gate pins and the MOSFET gates to carry 4A of current. When routing components in the switching path, use short wide traces to reduce the associated parasitic impedances. FN9156.2 December 27, 2004 ISL6564 Quad Flat No-Lead Plastic Package (QFN) Micro Lead Frame Plastic Package (MLFP) 2X L40.6x6 40 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220VJJD-2 ISSUE C) 0.15 C A MILLIMETERS D A 9 D/2 D1 D1/2 2X N 6 INDEX AREA 0.15 C B SYMBOL MIN NOMINAL E1/2 E/2 E1 A 0.80 0.90 1.00 - - - 0.05 - A2 - - 1.00 9 b D2 2X 0.15 C B 0.15 C A B TOP VIEW A C 0.08 C SEATING PLANE A1 A3 SIDE VIEW 9 5 NX b 0.10 M C A B 4X P D2 (DATUM B) 8 7 NX k D2 2 N 4X P 0.30 - 5.75 BSC 3.95 4.10 9 4.25 6.00 BSC - 5.75 BSC 9 3.95 4.10 4.25 - k 0.25 - - - L 0.30 0.40 0.50 8 L1 - - 0.15 10 N 40 2 Nd 10 3 Ne 10 3 P - - 0.60 9 θ - - 12 9 NOTES: (Ne-1)Xe REF. E2 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 7 N e 8 2. N is the number of terminals. E2/2 NX L 8 3. Nd and Ne refer to the number of terminals on each D and E. 4. All dimensions are in millimeters. Angles are in degrees. 9 CORNER OPTION 4X (Nd-1)Xe REF. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. BOTTOM VIEW 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. A1 NX b 5 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. SECTION "C-C" C L 7, 8 0.50 BSC Rev. 1 10/02 2 3 6 INDEX AREA 7, 8 E 1 (DATUM A) 5, 8 6.00 BSC e / / 0.10 C 0.23 9 E1 E2 A2 0 4X 0.18 D1 9 2X 0.20 REF D E NOTES A1 A3 1 2 3 MAX 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. C L L1 10 L L1 e 10 L e C C TERMINAL TIP FOR ODD TERMINAL/SIDE 9. Features and dimensions A2, A3, D1, E1, P & θ are present when Anvil singulation method is used and not present for saw singulation. 10. Depending on the method of lead termination at the edge of the package, a maximum 0.15mm pull back (L1) maybe present. L minus L1 to be equal to or greater than 0.3mm. FOR EVEN TERMINAL/SIDE All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 27 FN9156.2 December 27, 2004