DATASHEET
ISL76322
FN7611
Rev 3.00
May 6, 2015
16-Bit Long-Reach Video Automotive Grade SERDES
The ISL76322 is a serializer/deserializer of LVCMOS parallel
video data. The video data presented to the serializer on the
parallel LVCMOS bus is serialized into a high-speed differential
signal. This differential signal is converted back to parallel
video at the remote end by the deserializer. The fully featured
register set is programmed through the industry standard I2C.
Related Literature
• See FN6827, ISL34341 Data Sheet “WSVGA 24-Bit
Long-Reach Video SERDES with Bi-directional Side-Channel”
Features
• 16-bit RGB Transport Over a Single Differential Pair
• 6MHz to 50MHz Pixel Clock Rates
• AEC-Q100 Qualified Component
• Hot-plugging with Automatic Resynchronization Every
HSYNC
• Selectable Clock Edge for Parallel Data Output
• DC-balanced with Industry Standard 8b/10b Line Code
Allows AC-coupling, Providing Immunity Against Ground
Shifts
• 16 Programmable Settings Each for Transmitter Amplitude
Boost and Pre-emphasis and Receiver Equalization, Allow
for Longer Cable Lengths and Higher Data Rates
• Slew Rate Control and Spread Spectrum Capability on
Outputs Reduce the Potential for EMI
• Same Device for Serializer and Deserializer Simplifies
Inventory
Applications
• Video Entertainment Systems
• Remote Cameras
27nF
27nF
VSYNC
HSYNC
VIDEO
TARGET
DE
VDD_CR
VDD_CDR
VDD_P
TEST_EN
PCLK_IN
VIDEO_TX
PCLK_OUT
REF_RES
REF_CLK
ISL76322
DESERIALIZER
I2CA1
I2CA0
SERION
GND_CR
GND_AN
GND_P
GND_TX
GND_CDR
GND_IO
VIDEO_TX
VDD_IO
SERIOP
SERION
I2CA1
I2CA0
TEST_EN
16
RGB
3.16k
3.16k
REF_RES
ISL76322
SERIALIZER
1.8V VDD_IO
RSTB/PDB
27nF
VDD_AN
VDD_TX
27nF
SERIOP
GND_CR
GND_AN
GND_P
GND_TX
GND_CDR
GND_IO
VSYNC
HSYNC
DE
PCLK_IN
RSTB/PDB
VDD_CR
VDD_CDR
RGB
VIDEO
SOURCE
3.3V
1.8V VDD_IO
VDD_P
VDD_IO
VDD_TX
16
VDD_AN
3.3V
VDD_IO
FIGURE 1. TYPICAL APPLICATION
FN7611 Rev 3.00
May 6, 2015
Page 1 of 14
ISL76322
Block Diagram
SCL
I2C
SDA
VCM
GENERATOR
RAM
SERIOP
PREEMPHASIS
TX
3
V/H/DE
TDM
8b/10b
RGB
SERION
MUX
DEMUX
16
RX
EQ
VIDEO_TX
(HI)
CDR
PCLK_IN
(REF_CLK WHEN
VIDEO_TX IS LO)
x20
PCLK_ OUT
x20
FN7611 Rev 3.00
May 6, 2015
Page 2 of 14
ISL76322
Pin Configuration
GND_IO
RGBA7
RGBA6
RGBA5
RGBA4
RGBA3
RGBA2
RGBA1
RGBA0
PCLK_OUT
VDD_IO
GND_IO
ISL76322
(48 LD QFN)
TOP VIEW
48
47
46
45
44
43
42
41
40
39
38
37
VDD_IO
1
36 VDD_CDR
RGBC0
2
35 GND_CDR
RGBC1
3
34 VDD_TX
RGBC2
4
33 SERIOP
RGBC3
5
32 SERION
RGBC4
6
31 GND_TX
PAD
RGBC5
7
30 VDD_AN
RGBC6
8
29 GND_AN
RGBC7
9
28 REF_RES
STATUS 10
27 MASTER
16
17
18
19
20
21
VSYNC
VHSYNCPOL
VIDEO_TX
PCLK_IN
GND_P
22
23
24
SDA
15
SCL
14
VDD_P
13
HSYNC
25 I2CA1
DATAEN
RSTB/PDB 12
VDD_CR
26 I2CA0
GND_CR
TEST_EN 11
Pin Descriptions
DESCRIPTION
PIN NUMBER
PIN NAME
47, 46
45, 44
43, 42
41, 40
9, 8
7, 6
5, 4
3, 2
RGBA7, RGBA6
RGBA5, RGBA4
RGBA3, RGBA2
RGBA1, RGBA0
RGBC7, RGBC6
RGBC5, RGBC4
RGBC3, RGBC2
RGBC1, RGBC0
Parallel video data LVCMOS inputs with Hysteresis Parallel video data LVCMOS outputs
16
HSYNC
Horizontal (line) Sync LVCMOS input with Hysteresis Horizontal (line) Sync LVCMOS output
17
VSYNC
Vertical (frame) Sync LVCMOS input with Hysteresis Vertical (frame) Sync LVCMOS output
15
DATAEN
Video Data Enable LVCMOS input with Hysteresis
Video Data Enable LVCMOS output
20
PCLK_IN
Pixel clock LVCMOS input
PLL reference clock LVCMOS input
39
PCLK_OUT
Default; not used
Recovered clock LVCMOS output
33, 32
SERIOP, SERION
High-speed differential serial I/O
High speed differential serial I/O
FN7611 Rev 3.00
May 6, 2015
SERIALIZER
DESERIALIZER
Page 3 of 14
ISL76322
Pin Descriptions (Continued)
DESCRIPTION
PIN NUMBER
PIN NAME
SERIALIZER
18
VHSYNCPOL
19
VIDEO_TX
24, 23
SDA, SCL (Note 1)
I2C Interface Pins (I2C DATA, I2C CLK), weak internal pullup
25, 26
I2CA[1:0] (Note 1)
I2C Device Address
27
MASTER
12
RSTB/PDB
10
STATUS
28
REF_RES
21
GND_P (Note 2)
PLL Ground
37, 48
GND_IO (Note 2)
Digital (Parallel and Control) Ground
35
GND_CDR (Note 2)
31
GND_TX (Note 2)
Analog (Serial) Output Ground
29
GND_AN (Note 2)
Analog Bias Ground
13
GND_CR (Note 2)
Core Logic Ground
14
VDD_CR
Core Logic VDD
34
VDD_TX
Analog (Serial) Output VDD
30
VDD_AN
Analog Bias VDD
36
VDD_CDR
1, 38
VDD_IO (Note 1)
22
VDD_P
11
TEST_EN
Exposed Pad
PAD
DESERIALIZER
CMOS input for HSYNC and VSYNC Polarity
1: HSYNC & VSYNC active low
0: HSYNC & VSYNC active high
CMOS input for video flow direction
1: Video serializer
0: Video deserializer
I2C Master Mode
1: Master
0: Slave
CMOS input for Reset and Power-down. For normal operation, this pin should be driven high. When this
pin is taken low, the device will be reset. If this pin stays low, the device will be in PD mode.
CMOS output for Receiver Status:
1: Valid 8b/10b data received
0: No valid data detected
Note: serializer and deserializer switch roles during side-channel reverse traffic
Analog bias setting resistor connection; use 3.16k ±1% to ground
Analog (Serial) Data Recovery Ground
Analog (Serial) Data Recovery VDD
Digital (Parallel and Control) VDD
PLL VDD
Must be connected to ground
Must be connected to ground, not an electrical connection
NOTES:
1. Pins with the same name are internally connected together. However, this connection must NOT be used for connecting together external components
or features.
2. The various differently-named Ground pins are internally weakly connected. They must be tied together externally. The different names are provided
to assist in minimizing the current loops involved in bypassing the associated supply VDD pins. In particular, for ESD testing, they should be
considered a common connection.
FN7611 Rev 3.00
May 6, 2015
Page 4 of 14
ISL76322
Ordering Information
PART NUMBER
(Notes 3, 4, 5)
ISL76322ARZ
PART
MARKING
ISL76322 ARZ
TEMP. RANGE
(°C)
-40 to +105
PACKAGE
(RoHS Compliant)
48 Ld QFN
PKG.
DWG. #
L48.7x7C
NOTES:
3. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
4. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pbfree products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
5. For Moisture Sensitivity Level (MSL), please see device information page for ISL76322. For more information on MSL please see techbrief TB363.
FN7611 Rev 3.00
May 6, 2015
Page 5 of 14
ISL76322
Absolute Maximum Ratings
Thermal Information
Supply Voltage
VDD_P to GND_P, VDD_TX to GND_TX, VDD_IO to GND_IO . . . -0.5V to 4.6V
VDD_CDR to GND_CDR, VDD_CR to GND_CR. . . . . . . . . . . -0.5V to 2.5V
Between any pair of GND_P, GND_TX, GND_IO, GND_CDR,
GND_CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.1V to 0.1V
3.3V Tolerant LVTTL/LVCMOS
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VDD_IO +0.3V
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . .-0.3V to VDD_IO + 0.3V
Differential Output Current . . . . . . . . . . . . . . . . . . . . Short Circuit Protected
LVTTL/LVCMOS Outputs. . . . . . . . . . . . . . . . . . . . . . . Short Circuit Protected
ESD Rating
Human Body Model (Tested per JESD22-A114E)
All pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4kV
SERIOP/N
(All VDD Connected, all GND Connected) . . . . . . . . . . . . . . . . . . . . 8kV
Machine Model (Tested per JESD-A115-A) . . . . . . . . . . . . . . . . . . . . 200V
Charge Device Model (Tested per AEC-Q100-011-B) . . . . . . . . . . . . . 2000V
Latch-up (Tested per JESD-78B; Class2, Level A) . . . . . . . . . . . . . . . 100mA
Thermal Resistance (Typical)
JA
JC (°C/W)
QFN Package (Notes 6, 7) . . . . . . . . . . . . . .
32
3.7
Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327mW
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+125°C
Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C
Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
Recommended Operating Conditions
Operating Temperature Range . . . . . . . . . . . . . . . . . . . . . .-40°C to +105°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
6. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
7. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
Unless otherwise indicated, all data is for: VDD_CDR = VDD_CR = 1.8V, VDD_IO = 3.3V,
VDD_TX = VDD_P = VDD_AN = 3.3V, TA = +25°C, Ref_Res = 3.16k, High-speed AC-coupling capacitor = 27nF. Boldface limits apply over the operating
temperature range, -40°C to +105°C.
MIN
(Note 10)
TYP
MAX
(Note 10)
UNIT
VDD_CDR, VDD_CR
1.7
1.8
1.9
V
VDD_TX, VDD_P, VDD_AN, VDD_IO
3.0
3.3
3.6
V
PARAMETER
SYMBOL
TEST CONDITIONS
POWER SUPPLY VOLTAGE
SERIALIZER POWER SUPPLY CURRENTS
Total 1.8V Supply Current
PCLK_IN = 45MHz
62
80
mA
Total 3.3V Supply Current
(Note 8)
40
52
mA
Total 1.8V Supply Current
PCLK_IN = 45MHz
66
76
mA
Total 3.3V Supply Current
(Note 8)
50
63
mA
RSTB = GND
10
mA
0.5
mA
DESERIALIZER POWER SUPPLY CURRENTS
POWER-DOWN SUPPLY CURRENT
Total 1.8V Power-Down Supply Current
Total 3.3V Power-Down Supply Current
PARALLEL INTERFACE
High Level Input Voltage
VIH
Low Level Input Voltage
VIL
Input Leakage Current
IIN
High Level Output Voltage
VOH
IOH = -4.0mA, VDD_IO = 3.0V
Low Level Output Voltage
VOL
IOL = 4.0mA, VDD_IO = 3.6V
Output Short Circuit Current
IOSC
FN7611 Rev 3.00
May 6, 2015
2.0
-1
V
±0.01
0.8
V
1
µA
2.6
V
0.4
V
35
mA
Page 6 of 14
ISL76322
Electrical Specifications
Unless otherwise indicated, all data is for: VDD_CDR = VDD_CR = 1.8V, VDD_IO = 3.3V,
VDD_TX = VDD_P = VDD_AN = 3.3V, TA = +25°C, Ref_Res = 3.16k, High-speed AC-coupling capacitor = 27nF. Boldface limits apply over the operating
temperature range, -40°C to +105°C. (Continued)
PARAMETER
Output Rise and Fall Times
SYMBOL
tOR/tOF
TEST CONDITIONS
MIN
(Note 10)
TYP
MAX
(Note 10)
UNIT
Slew rate control set to min
CL = 8pF
1
ns
Slew rate control set to max, CL = 8pF
4
ns
SERIALIZER PARALLEL INTERFACE
PCLK_IN Frequency
fIN
6
PCLK_IN Duty Cycle
tIDC
40
Parallel Input Setup Time
tIS
3.5
ns
Parallel Input Hold Time
tIH
1.0
ns
PCLK_OUT Frequency
fOUT
6
PCLK_OUT Duty Cycle
tODC
50
50
MHz
60
%
DESERIALIZER PARALLEL INTERFACE
PCLK_OUT Period Jitter (rms)
PCLK_OUT Spread Width
50
MHz
50
%
tOJ
Clock randomizer off
0.5
%tPCLK
tOSPRD
Clock randomizer on
±20
%tPCLK
PCLK_OUT to Parallel Data Outputs
(includes Sync and DE pins)
tDV
Relative to PCLK_OUT,
(Note 9)
-1.0
Deserializer Output Latency
tCPD
Inherent in the design
4
9
5.5
ns
14
PCLK
DESERIALIZER REFERENCE CLOCK (REF_CLK IS FED INTO PCLK_IN)
REF_CLK Lock Time
tPLL
REF_CLK to PCLK_OUT Maximum Frequency Offset
100
µs
ppm
PCLK_OUT is the
recovered clock
1500
5000
TXCN = 0x00
650
800
HIGH-SPEED TRANSMITTER
HS Differential Output Voltage, Transition Bit
HS Differential Output Voltage, Non-Transition Bit
VODTR
VODNTR
900
mVP-P
TXCN = 0x0F
900
mVP-P
TXCN = 0xF0
1100
mVP-P
TXCN = 0xFF
1300
mVP-P
TXCN = 0x00
650
800
900
mVP-P
TXCN = 0x0F
900
mVP-P
TXCN = 0xF0
430
mVP-P
TXCN = 0xFF
600
mVP-P
V
HS Generated Output Common Mode Voltage
VOCM
2.35
HS Common Mode Serializer-Deserializer Voltage
Difference
VCM
10
20
mV
HS Differential Output Impedance
ROUT
80
100
120
Ω
HS Output Latency
tLPD
Inherent in the design
4
7
10
PCLK
HS Output Rise and Fall Times
tR/tF
20% to 80%
HS Differential Skew
tSKEW
150
ps
