DATASHEET
ISL78201
FN8615
Rev 2.00
August 15, 2016
40V 2.5A Regulator with Integrated High-Side MOSFET for Synchronous Buck or
Boost Buck Converter
The ISL78201 is an AEC-Q100 qualified 40V, 2.5A synchronous
buck or boost buck controller with a high-side MOSFET and
low-side driver integrated. In Buck mode, the ISL78201
supports a wide input range of 3V to 40V. In Boost-Buck mode,
the input range can be extended down to 2.5V and output
regulation can be maintained when VIN drops below VOUT,
enabling sensitive electronics to remain on during
cold-cranking and start-stop applications.
The ISL78201 has a flexible selection of operation modes
including forced PWM mode and an optional switch to PFM
mode for light loads. In PFM mode, the quiescent input current
is as low as 300µA and can be further reduced to 180µA with
AUXVCC connected to VOUT under 12V VIN and 5V VOUT
application. The load boundary between PFM and PWM can be
programmed to cover wide applications.
The low-side driver can be either used to drive an external
low-side MOSFET for a synchronous buck, or left unused for a
standard non-synchronous buck. The low-side driver can also
be used to drive a boost converter as a preregulator that
greatly expands the operating input voltage range down to
2.5V or lower (refer to “Typical Application Schematic III - Boost
Buck Converters” on page 5).
The ISL78201 offers the most robust current protections. It
uses peak current mode control with cycle-by-cycle current
limiting. It is implemented with frequency foldback
undercurrent limit condition; in addition, the hiccup
overcurrent mode is also implemented to guarantee reliable
operations under harsh short conditions. The ISL78201 has
comprehensive protections against various faults including
overvoltage and over-temperature protections, etc.
Features
• Buck mode: input voltage range 3V to 40V (refer to “Input
Voltage” on page 14 for more details)
• Boost mode expands operating input voltage lower than
2.5V (refer to “Input Voltage” on page 14 for more details)
• Selectable forced PWM mode or PFM mode
• 300µA IC quiescent current (PFM, no load); 180µA input
quiescent current (PFM, no load, VOUT tied to AUXVCC)
• Less than 5µA (MAX) shutdown input current (IC disabled)
• Operational topologies
- Synchronous buck
- Non-synchronous buck
- Two-stage boost buck
- Noninverting single inductor buck boost
• Programmable frequency from 200kHz to 2.2MHz and
frequency synchronization capability
• ±1% Tight voltage regulation accuracy
• Reliable cycle-by-cycle overcurrent protection
- Temperature compensated current sense
- Programmable OC limit
- Frequency foldback and hiccup mode protection
• 20 Ld HTSSOP package
• AEC-Q100 qualified
• Pb-free (RoHS compliant)
Applications
• Automotive applications
• General purpose power regulator
• 24V Bus power
• Battery power
• Embedded processor and I/O supplies
100
VIN
SYNC
AUXVCC
VCC
VIN
BOOT
ISL78201
ILIMIT
PHASE
LGATE
SS
EXT_BOOST
FS
SGND
PGND
FB
COMP
V OUT
EFFICIENCY (%)
95
PGOOD
EN
MODE
6V VIN
90
85
12V VIN
80
75
24V VIN
70
40V VIN
65
60
55
50
0.1m
1m
10m
100m
1
2.5
LOAD CURRENT (A)
FIGURE 1. TYPICAL APPLICATION
FN8615 Rev 2.00
August 15, 2016
FIGURE 2. EFFICIENCY, SYNCHRONOUS BUCK, PFM MODE,
VOUT 5V, TA = +25°C
Page 1 of 23
ISL78201
Pin Configuration
ISL78201
(20 LD HTSSOP)
TOP VIEW
PGND 1
20 LGATE
BOOT 2
19 SYNC
VIN 3
18 EXT_BOOST
VIN 4
17 PHASE
SGND 5
VCC 6
21
PAD
16 PHASE
15 PGOOD
AUXVCC 7
14 MODE
EN 8
13 ILIMIT
FS 9
12 COMP
SS 10
11 FB
Functional Pin Description
PIN NAME
PIN #
PGND
1
This pin is used as the ground connection of the power flow including driver.
BOOT
2
This pin provides bias voltage to the high-side MOSFET driver. A bootstrap circuit is used to create a voltage suitable to
drive the internal N-channel MOSFET. The boot charge circuitries are integrated inside the IC. No external boot diode is
needed. A 1µF ceramic capacitor is recommended to be used between BOOT and PHASE pin.
VIN
3, 4
Connect the input rail to these pins that are connected to the drain of the integrated high-side MOSFET, as well as the
source for the internal linear regulator that provides the bias of the IC. Range: 3V to 40V.
With the part switching, the operating input voltage applied to the VIN pins must be under 40V. This recommendation
allows for short voltage ringing spikes (within a couple of ns time range) due to switching while not exceeding absolute
maximum ratings.
SGND
5
This pin provides the return path for the control and monitor portions of the IC.
VCC
6
This pin is the output of the internal linear regulator that supplies the bias for the IC including the driver. A minimum
4.7µF decoupling ceramic capacitor is recommended between VCC to ground.
AUXVCC
7
This pin is the input of the auxiliary internal linear regulator, which can be supplied by the regulator output after powerup. With such a configuration, the power dissipation inside the IC is reduced. The input range for this LDO is 3V to 20V.
In Boost mode operation, this pin works as boost output overvoltage detection pin. It detects the boost output through a
resistor divider. When the voltage on this pin is above 0.8V, the boost PWM is disabled; and when voltage on this pin is
below 0.8V minus the hysteresis, the boost PWM is enabled. Range: 3V to 20V.
EN
8
The controller is enabled when this pin is pulled HIGH or left floating. The IC is disabled when this pin is pulled LOW.
Range: 0V to 5.5V.
FS
9
To connect this pin to VCC, or GND, or left open will force the IC to have 500kHz switching frequency. The oscillator
switching frequency can also be programmed by adjusting the resistor from this pin to GND.
SS
10
Connect a capacitor from this pin to ground. This capacitor, along with an internal 5µA current source, sets the soft-start
interval of the converter. Also this pin can be used to track a ramp on this pin.
FB
11
This pin is the inverting input of the voltage feedback error amplifier. With a properly selected resistor divider connected
from VOUT to FB, the output voltage can be set to any voltage between the input rail (reduced by maximum duty cycle
and voltage drop) and the 0.8V reference. Loop compensation is achieved by connecting an RC network across COMP
and FB. The FB pin is also monitored for overvoltage events.
COMP
12
Output of the voltage feedback error amplifier.
ILIMIT
13
Programmable current limit pin. With this pin connected to the VCC pin, or to GND, or left open, the current limit threshold
is set to default 3.6A; the current limit threshold can be programmed with a resistor from this pin to GND.
MODE
14
Mode selection pin. Pull this pin to GND for forced PWM mode; to have it floating or connected to VCC will enable PFM
mode when the peak inductor current is below the default threshold of 700mA. The current boundary threshold between
PFM and PWM can also be programmed with a resistor at this pin to ground. For more details on PFM mode operation
refer to the “Functional Description” on page 13.
FN8615 Rev 2.00
August 15, 2016
DESCRIPTION
Page 2 of 23
ISL78201
Functional Pin Description (Continued)
PIN NAME
PIN #
DESCRIPTION
PGOOD
15
PGOOD is an open-drain output and pull-up this pin with a resistor to VCC for proper function. PGOOD will be pulled low
under the events when the output is out of regulation (OV or UV) or EN pin is pulled low. PGOOD rising has a fixed 128
cycles delay.
PHASE
16, 17
These pins are the PHASE nodes that should be connected to the output inductor. These pins are connected to the source
of the high-side N channel MOSFET.
EXT_BOOST
18
This pin is used to set Boost mode and monitor the battery voltage that is the input of the boost converter. After VCC POR,
the controller will detect the voltage on this pin, if voltage on this pin is below 200mV, the controller is set in
Synchronous/Non-synchronous Buck mode and latch in this state unless VCC is below the POR falling threshold; if the
voltage on this pin after VCC POR is above 200mV, the controller is set in Boost mode and latch in this state.
In Boost mode, this pin is used to monitor input voltage through a resistor divider. By setting the resistor divider, the high
threshold and hysteresis can be programmed. When voltage on this pin is above 0.8V, the PWM output (LGATE) for the
boost converter is disabled, and when voltage on this pin is below 0.8V minus the hysteresis, the boost PWM is enabled.
In Boost mode operation, PFM is disabled when boost PWM is enabled. Check Boost mode operation in the “Functional
Description” on page 13 for more details.
SYNC
19
This pin can be used to synchronize two or more ISL78201 controllers. Multiple ISL78201s can be synchronized with
their SYNC pins connected together. An 180° phase shift is automatically generated between the master and slave ICs.
The internal oscillator can also lock to an external frequency source applied on this pin with square pulse waveform (with
frequency 10% higher than the IC’s local frequency, and pulse width higher than 150ns).
This pin should be left floating if not used. Range: 0V to 5.5V.
LGATE
20
In Synchronous Buck mode, this pin is used to drive the lower side MOSFET to improve efficiency. A 5.1k or smaller value
resistor has to be added to connect LGATE to ground to avoid a false turn-on of the LGATE caused by coupling noise.
In Non-synchronous Buck mode when a diode is used as the bottom-side power device, this pin should be connected to
VCC through a resistor (less than 5k) before VCC start-up to have low-side driver (LGATE) disabled.
In Boost mode, it can be used to drive the boost power MOSFET. The boost control PWM is the same with the buck control
PWM.
PAD
21
Bottom thermal pad. It is not connected to any electrical potential of the IC. In layout it must be connected to PCB ground
copper plane with an area as large as possible to effectively reduce the thermal impedance.
Ordering Information
PART
NUMBER
(Notes 1, 2, 3)
ISL78201AVEZ
PART
MARKING
TEMP. RANGE
(°C)
78201 AVEZ
PACKAGE
(RoHS COMPLIANT)
-40 to +105
20 Ld HTSSOP
PKG.
DWG. #
M20.173A
NOTES:
1. Add “-T” suffix for 2.5k unit or “-T7A” suffix for 250 unit Tape and Reel options. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL78201. For more information on MSL please see techbrief TB363.
TABLE 1. KEY DIFFERENCES BETWEEN FAMILY OF PARTS
PART NUMBER
TOPOLOGY
BOOST
AUXVCC
PFM
PACKAGE
ISL78201
Boost Buck with Internal
High-Side MOSFET
Yes
Yes
Yes
20 Ld HTSSOP
ISL78206
Buck with Internal High-Side
MOSFET
No
No
No
20 Ld HTSSOP
FN8615 Rev 2.00
August 15, 2016
Page 3 of 23
AUXVCC
VCC
PGOOD
ISL78201
FN8615 Rev 2.00
August 15, 2016
Block Diagram
VIN (x2)
VIN
CURRENT
MONITOR
AUXILARY LDO
BIAS LDO
ILIMIT
POWER-ON
RESET
SGND
VCC
BOOT
OCP, OVP, OTP
PFM LOGIC
BOOST MODE CONTROL
EN
EXT_BOOST
MODE
PFM/FPWM
PHASE (x2)
GATE DRIVE
VOLTAGE
MONITOR
SYNC
FS
SLOPE
COMPENSATION
OSCILLATOR
+
SOFT-START
LOGIC
VCC
5 µA
BOOT REFRESH
0.8V
REFERENCE
COMPARATOR
EA
SS
+
LGATE
FB
COMP
FIGURE 3. BLOCK DIAGRAM
PGND
Page 4 of 23
ISL78201
Typical Application Schematic I
T
PGOOD
EN
MODE
SYNC
AUXVCC
VCC
PGOOD
EN
MODE
VIN
VIN
SYNC
AUXVCC
BOOT
ISL78201
V OUT
PHASE
ILIMIT
ISL78201
LGATE
PGND
EXT_BOOST
FS
SGND
FB
COMP
V OUT
PHASE
SS
PGND
EXT_BOOST
FS
SGND
BOOT
ILIMIT
LGATE
SS
VCC
VIN
VIN
FB
COMP
FIGURE 4A. SYNCHRONOUS BUCK
FIGURE 4B. NON-SYNCHRONOUS BUCK
FIGURE 4. SYNCHRONOUS AND NON-SYNCHRONOUS BUCK SCHEMATICS
Typical Application Schematic II - VCC Switchover to VOUT
PGOOD
EN
MODE
SYNC
AUXVCC
VCC
PGOOD
EN
MODE
VIN
VIN
SYNC
AUXVCC
BOOT
ISL78201
VCC
V OUT
PHASE
ILIMIT
ISL78201
LGATE
PGND
EXT_BOOST
FS
SGND
FB
COMP
V OUT
PHASE
SS
PGND
EXT_BOOST
FS
SGND
BOOT
ILIMIT
LGATE
SS
VIN
VIN
FB
COMP
FIGURE 5A. SYNCHRONOUS BUCK
FIGURE 5B. NON-SYNCHRONOUS BUCK
FIGURE 5. VCC SWITCHOVER TO VOUT SCHEMATICS
Typical Application Schematic III - Boost Buck Converters
Battery
+
+
R1
R2
PGOOD
EN
MODE
EXT_BOOST
LGATE
AUXVCC
SYNC
VCC
ILIMIT
100k
1M
FS
BOOT
PGND
SGND
R4
SYNC
VIN
ISL78201
PHASE
SS
R3
PGOOD
EN
COMP
FB
VCC
V OUT
ILIMIT
EXT_BOOST
VCC
15k
130k
AUXVCC
VIN
ISL78201
BOOT
PHASE
VIN
V OUT
SS
PGND
FS
SGND
LGATE
COMP
FB
FIGURE 6B. NON-INVERTING SINGLE INDUCTOR BUCK BOOST
FIGURE 6A. 2-STAGE BOOST BUCK
FIGURE 6. BOOST-BUCK CONVERTER SCHEMATICS
FN8615 Rev 2.00
August 15, 2016
Page 5 of 23
ISL78201
Absolute Maximum Ratings
Thermal Information
VIN, PHASE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(GND - 0.3V) to +44V
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (GND - 0.3V) to +6.0V
AUXVCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(GND - 0.3V) to +22V
Absolute Boot Voltage, VBOOT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +50.0V
Upper Driver Supply Voltage, VBOOT - VPHASE . . . . . . . . . . . . . . . . . . . +6.0V
All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . (GND - 0.3V) to VCC + 0.3V
ESD Rating
Human Body Model (Tested per AEC Q100-002D). . . . . . . . . . . . . . . 2kV
Machine Model (Tested per JESD22-A115C) . . . . . . . . . . . . . . . . . . 250V
Charged Device Model (Tested per AEC-Q100-011C1) . . . . . . . . . . . 1kV
Latch-Up Rating (Tested per AEC Q100-004D; Class II, Level A) . . 100mA
Thermal Resistance
JA (°C/W) JC (°C/W)
HTSSOP Package (Notes 4, 5) . . . . . . . . . .
35
3.5
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . . . . +150°C
Maximum Storage Temperature Range. . . . . . . . . . . . . . . . . -65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
Recommended Operating Conditions
Supply Voltage on VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3V to 40V
AUXVCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .)GND - 0.3V) to +20V
Ambient Temperature Range (Automotive). . . . . . . . . . . . . . .-40°C to +105°C
Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
5. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications Refer to “Block Diagram” on page 4 and Typical Application Schematics (beginning on page 5). Operating
conditions unless otherwise noted: VIN = 12V, or VCC = 4.5V, TA = -40°C to +105°C. Typicals are at TA = +25°C. Boldface limits apply across the operating
temperature range, -40°C to +105°C.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6)
UNIT
VIN SUPPLY
VIN Pin Voltage Range
Operating Supply Current
Shutdown Supply Current
IQ
IIN_SD
VIN pin
3.05
40
V
VIN connected to VCC
3.05
5.50
V
MODE = VCC/FLOATING (PFM), no load at the
output
300
µA
MODE = GND (Forced PWM), VIN = 12V,
IC Operating, not including driving current
1.3
mA
EN connected to GND, VIN = 12V
2.8
4.5
µA
INTERNAL MAIN LINEAR REGULATOR
MAIN LDO VCC Voltage
MAIN LDO Dropout Voltage
VCC
VIN > 5V
4.2
VDROPOUT_MAIN VIN = 4.2V, IVCC = 35mA
VIN = 3V, IVCC = 25mA
VCC Current Limit of MAIN LDO
4.5
4.8
V
0.30
0.52
V
0.25
0.42
60
V
mA
INTERNAL AUXILIARY LINEAR REGULATOR
AUXVCC Input Voltage Range
VAUXVCC
AUX LDO VCC Voltage
VCC
LDO Dropout Voltage
VDROPOUT_AUX
3
VAUXVCC > 5V
4.2
20
V
4.5
4.8
V
VAUXVCC = 4.2V, IVCC = 35mA
0.30
0.52
V
VAUXVCC = 3V, IVCC = 25mA
0.25
0.42
Current Limit of AUX LDO
60
V
mA
AUX LDO Switchover Rising Threshold
VAUXVCC_RISE
AUXVCC voltage rise, switch to auxiliary LDO
2.97
3.10
3.20
V
AUX LDO Switchover Falling Threshold
VAUXVCC_FALL
AUXVCC voltage fall, switch back to main BIAS
LDO
2.73
2.87
2.97
V
AUX LDO Switchover Hysteresis
VAUXVCC_HYS
AUXVCC switchover hysteresis
0.2
V
POWER-ON RESET
Rising VCC POR Threshold
VPORH_RISE
Falling VCC POR Threshold
VCC POR Hysteresis
FN8615 Rev 2.00
August 15, 2016
2.82
2.90
3.05
VPORL_FALL
2.6
2.8
VPORL_HYS
0.3
Page 6 of 23
V
V
V
ISL78201
Electrical Specifications Refer to “Block Diagram” on page 4 and Typical Application Schematics (beginning on page 5). Operating
conditions unless otherwise noted: VIN = 12V, or VCC = 4.5V, TA = -40°C to +105°C. Typicals are at TA = +25°C. Boldface limits apply across the operating
temperature range, -40°C to +105°C. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6)
UNIT
ENABLE
Required Enable On Voltage
Required Enable Off Voltage
EN Pull-Up Current
1.7
VENH
V
1
VENL
IEN_PULLUP
V
VEN = 1.2V, VIN = 24V
1.5
µA
VEN = 1.2V, VIN = 12V
1.2
µA
VEN = 1.2V, VIN = 5V
0.9
µA
OSCILLATOR
PWM Frequency
FOSC
RT = 665kΩ
160
200
240
kHz
RT = 51.1kΩ
1870
2200
2530
kHz
FS pin connected to VCC or floating or GND
450
500
550
kHz
MIN ON Time
tMIN_ON
130
225
ns
MIN OFF Time
tMIN_OFF
210
330
ns
Input High Threshold
VIH
2
Input Low Threshold
VIL
SYNCHRONIZATION
V
0.5
V
Input Minimum Pulse Width
25
ns
Input Impedance
100
kΩ
Input Minimum Frequency Divided by Free
Running Frequency
1.1
N/A
Input Maximum Frequency Divided by Free
Running Frequency
1.6
N/A
CSYNC = 100pF
100
ns
RLOAD = 1kΩ
VCC 0.25
V
GND
V
Output Pulse Width
Output Pulse High
VOH
Output Pulse Low
VOL
REFERENCE VOLTAGE
Reference Voltage
0.8
VREF
System Accuracy
-1.0
FB Pin Source Current
V
1.0
%
5
nA
SOFT-START
Soft-Start Current
3
ISS
5
7
µA
ERROR AMPLIFIER
Unity Gain-Bandwidth
CLOAD = 50pF
10
MHz
DC Gain
CLOAD = 50pF
88
dB
Maximum Output Voltage
3.6
V
Minimum Output Voltage
0.5
V
5
V/µs
MODE = VCC or floating
700
mA
(Note 7) Limits apply for +25°C
127
LGATE Source Resistance
100mA source current
3.5
Ω
LGATE Sink Resistance
100mA sink current
2.8
Ω
Slew Rate
SR
CLOAD = 50pF
PFM MODE CONTROL
Default PFM Current Threshold
INTERNAL HIGH-SIDE MOSFET
Upper MOSFET rDS(ON)
rDS(ON)_UP
140
mΩ
LOW-SIDE MOSFET GATE DRIVER
FN8615 Rev 2.00
August 15, 2016
Page 7 of 23
ISL78201
Electrical Specifications Refer to “Block Diagram” on page 4 and Typical Application Schematics (beginning on page 5). Operating
conditions unless otherwise noted: VIN = 12V, or VCC = 4.5V, TA = -40°C to +105°C. Typicals are at TA = +25°C. Boldface limits apply across the operating
temperature range, -40°C to +105°C. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6)
UNIT
0.74
0.8
0.86
V
BOOST CONVERTER CONTROL
EXT_BOOST Boost_Turn-Off Threshold Voltage
EXT_BOOST Hysteresis Sink Current
IEXT_BOOST_HYS
AUXVCC Boost Turn-Off Threshold Voltage
AUXVCC Hysteresis Sink Current
IAUXVCC_HYS
2.1
3.2
4.2
µA
0.74
0.8
0.86
V
2.1
3.2
4.2
µA
104
110
116
%
POWER GOOD MONITOR
Overvoltage Rising Trip Point
VFB/VREF
Percentage of reference point
Overvoltage Rising Hysteresis
VFB/VOVTRIP
Percentage below OV trip point
Undervoltage Falling Trip Point
VFB/VREF
Percentage of reference point
Undervoltage Falling Hysteresis
VFB/VUVTRIP
Percentage above UV trip point
3
84
90
%
96
%
3
%
128
cycle
PGOOD HIGH, VPGOOD = 4.5V
10
nA
VPGOOD
PGOOD LOW, IPGOOD = 0.2mA
0.10
V
Default Cycle-by-Cycle Current Limit Threshold
IOC_1
ILIMIT = GND or VCC or floating
Hiccup Current Limit Threshold
IOC_2
Hiccup, IOC_2/IOC_1
115
%
OV 120% Trip Point
Active in and after soft-start
Percentage of Reference Point
LG = UG = LOW
120
%
OV 120% Release Point
Active in and after soft-start
Percentage of reference point
102.5
%
OV 110% Trip Point
Active after soft-start done
Percentage of reference point
LG = UG = LOW
110
%
OV 110% Release Point
Active after soft-start done
Percentage of reference point
102.5
%
PGOOD Rising Delay
tPGOODR_DELAY
PGOOD Leakage Current
PGOOD Low Voltage
OVERCURRENT PROTECTION
3
3.6
4.2
A
OVERVOLTAGE PROTECTION
OVER-TEMPERATURE PROTECTION
Over-Temperature Trip Point
160
°C
Over-Temperature Recovery Threshold
140
°C
NOTES:
6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
7. Wire bonds included.
FN8615 Rev 2.00
August 15, 2016
Page 8 of 23
ISL78201
100
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
0.0
95
24V VIN
12V VIN
6V VIN
90
40V VIN
EFFICIENCY (%)
EFFICIENCY (%)
Performance Curves
6V VIN
12V VIN
85
80
40V VIN
75
24V VIN
70
65
60
55
0.5
1.0
1.5
50
0.1m
2.5
2.0
1m
LOAD CURRENT (A)
FIGURE 7. EFFICIENCY, SYNCHRONOUS BUCK, FORCED PWM
MODE, 500kHz, VOUT 5V, TA = +25°C
4.970
4.968
4.968
4.966
4.966
1
2.5
4.964
IO = 0A
4.962
4.960
VOUT (V)
VOUT (V)
4.964
IO = 2A
4.958
4.956
4.962
4.958
4.954
4.954
4.952
4.952
5
10
6V VIN
40V VIN
4.956
IO = 1A
0
24V VIN
4.960
15
20
25
30
35
40
45
12V VIN
4.950
0.0
50
0.5
FIGURE 9. LINE REGULATION, VOUT 5V, TA = +25°C
1.5
2.0
2.5
FIGURE 10. LOAD REGULATION, VOUT 5V, TA = +25°C
100
95
90
12V VIN
85
24V VIN
EFFICIENCY (%)
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
0.0
1.0
LOAD CURRENT (A)
INPUT VOLTAGE (V)
EFFICIENCY (%)
100m
FIGURE 8. EFFICIENCY, SYNCHRONOUS BUCK, PFM MODE,
VOUT 5V, TA = +25°C
4.970
4.950
10m
LOAD CURRENT (A)
40V VIN
6V VIN
6V VIN
12V VIN
80
40V VIN
75
24V VIN
70
65
60
55
50
45
0.5
1.0
1.5
2.0
LOAD CURRENT (A)
FIGURE 11. EFFICIENCY, SYNCHRONOUS BUCK, FORCED PWM
MODE, 500kHz, VOUT 3.3V, TA = +25°C
FN8615 Rev 2.00
August 15, 2016
2.5
40
0.1m
1m
10m
100m
LOAD CURRENT (A)
1
FIGURE 12. EFFICIENCY, SYNCHRONOUS BUCK, PFM MODE,
VOUT 3.3V, TA = +25°C
Page 9 of 23
2.5
ISL78201
Performance Curves
(Continued)
150
200
180
IC DIE TEMPERATURE (°C)
160
INPUT CURRENT (µA)
145
VIN = 12V
140
120
VIN = 24V
100
80
VIN = 40V
60
40
140
135
130
125
120
115
110
20
0
-50
-25
0
25
50
75
100
105
0
125
5
10
15
20
25
85
85
80
80
75
75
70
60
55
VOUT = 9V
VOUT = 20V
VOUT = 12V
50
45
VOUT = 5V
40
35
30
25
0
5
10
15
20
25
30
35
35
40
45
40
45
70
65
60
55
50
VIN = 40V
45
40
30
25
1.0
50
VIN = 12V
VIN = 24V
35
1.5
2.0
VIN (V)
IOUT (A)
FIGURE 15. IC DIE TEMPERATURE UNDER +25°C AMBIENT
TEMPERATURE, STILL AIR, 500kHz, IO = 2A
FIGURE 16. IC DIE TEMPERATURE UNDER +25°C AMBIENT
TEMPERATURE, STILL AIR, 500kHz, VOUT = 9V
180
170
160
150
140
130
120
130
110
120
90
100
80
70
60
50
40
30
20
0
10
-10
-20
-50
-30
110
-40
UPPER MOSFET rDS(ON) (mΩ)
190
100
DIE TEMPERATURE (°C)
FIGURE 17. UPPER MOSFET rDS(ON) (mΩ) OVER-TEMPERATURE
FN8615 Rev 2.00
August 15, 2016
50
FIGURE 14. IC DIE TEMPERATURE UNDER +105°C AMBIENT
TEMPERATURE, 100 CFM, 500kHz, VOUT = 5V, IO = 2A
IC DIE TEMPERATURE (°C)
IC DIE TEMPERATURE (°C)
FIGURE 13. INPUT QUIESCENT CURRENT UNDER NO LOAD,
PFM MODE, AUXVCC CONNECTED TO VOUT, VOUT = 5V
65
30
VIN (V)
AMBIENT TEMPERATURE (°C)
Page 10 of 23
2.5
ISL78201
Performance Curves
(Continued)
VOUT 2V/DIV
VOUT 2V/DIV
PHASE 20V/DIV
PHASE 20V/DIV
2ms/DIV
FIGURE 18. SYNCHRONOUS BUCK MODE, VIN 36V, IO 2A,
ENABLE ON
2ms/DIV
FIGURE 19. SYNCHRONOUS BUCK MODE, VIN 36V, IO 2A,
ENABLE OFF
VOUT 20mV/DIV (5V OFFSET)
VOUT 2V/DIV
PHASE 20V/DIV
PHASE 20V/DIV
5µs/DIV
2ms/DIV
FIGURE 20. VIN 36V, PREBIASED START-UP
VOUT 100mV/DIV (5V OFFSET)
FIGURE 21. SYNCHRONOUS BUCK WITH FORCE PWM MODE,
VIN 36V, IO 2A
VOUT 70mV/DIV (5V OFFSET)
VOUT 1V/DIV
LGATE 5V/DIV
IOUT 1A/DIV
PHASE 20V/DIV
PHASE 20V/DIV
1ms/DIV
100µs/DIV
FIGURE 22. VIN 24V, 0 TO 2A STEP LOAD, FORCE PWM MODE
FIGURE 23. VIN 24V, 80mA LOAD, PFM MODE
FN8615 Rev 2.00
August 15, 2016
Page 11 of 23
ISL78201
Performance Curves
(Continued)
VOUT 200mV/DIV (5V OFFSET)
LGATE 5V/DIV
IOUT 1A/DIV
VOUT 10mV/DIV (5V OFFSET)
PHASE 5V/DIV
PHASE 20V/DIV
1ms/DIV
FIGURE 24. VIN 24V, 0 TO 2A STEP LOAD, PFM MODE
20µs/DIV
FIGURE 25. NON-SYNCHRONOUS BUCK, FORCE PWM MODE,
VIN 12V, NO LOAD
VOUT 1V/DIV
VOUT 10mV/DIV (5V OFFSET)
PHASE 10V/DIV
VIN_BOOST 5V/DIV
5µs/DIV
FIGURE 26. NON-SYNCHRONOUS BUCK, FORCE PWM MODE,
VIN 12V, 2A
20ms/DIV
FIGURE 27. BOOST BUCK MODE, BOOST INPUT STEP FROM
40V TO 3V
VOUT 5V/DIV
VOUT 1V/DIV
IL_BOOST 2A/DIV
PHASE_BOOST 20V/DIV
VIN_BOOST 5V/DIV
20ms/DIV
FIGURE 28. BOOST BUCK MODE, BOOST INPUT STEP FROM
3V TO 40V
FN8615 Rev 2.00
August 15, 2016
PHASE_BUCK 20V/DIV
10ms/DIV
FIGURE 29. BOOST BUCK MODE, VO = 9V, IO = 1.8A, BOOST INPUT
DROPS FROM 16V TO 9V DC
Page 12 of 23
ISL78201
Performance Curves
(Continued)
95
90
15V VIN
EFFICIENCY (%)
85
80
6V VIN
75
9V VIN
70
5V VIN
65
30V VIN
60
BOOST BUCK, VO = 12V
55
50
0.0 0.2
0.4
0.6 0.8
1.0
1.2 1.4 1.6
1.8
2.0 2.2
2.4
LOAD CURRENT (A)
FIGURE 30. EFFICIENCY, BOOST BUCK, 500kHz, VOUT 12V, TA = +25°C
PWM Control
Functional Description
Initialization
Initially, the ISL78201 continually monitors the voltage at the EN
pin. When the voltage on the EN pin exceeds its rising threshold,
the internal LDO will start-up to build up VCC. After Power-On
Reset (POR) circuits detect that the VCC voltage has exceeded the
POR threshold, the soft-start will be initiated.
Soft-Start
The Soft-Start (SS) ramp is built up in the external capacitor on
the SS pin that is charged by an internal 5µA current source.
C SS F = 6.5 t SS S
(EQ. 1)
The SS ramp starts from 0V to a voltage above 0.8V. Once SS
reaches 0.8V, the bandgap reference takes over and the IC goes
into steady-state operation. The soft-start time is referring to the
duration for SS pin ramps from 0 to 0.8V while output voltage
ramps up with the same rate from 0 to target regulated voltage.
The required capacitance at the SS pin can be calculated from
Equation 1.
The SS plays a vital role in the Hiccup mode of operation. The IC
works as a cycle-by-cycle peak current limiting at overload
condition. When a harsh condition occurs and the current in the
upper side MOSFET reaches the second overcurrent threshold,
the SS pin is pulled to ground and a dummy soft-start cycle is
initiated. At the dummy SS cycle, the current to charge the
soft-start capacitor is cut down to 1/5 of its normal value.
Therefore, a dummy SS cycle takes 5 times that of the regular SS
cycle. During the dummy SS period, the control loop is disabled
and has no PWM output. At the end of this cycle, it will start the
normal SS. The Hiccup mode persists until the second
overcurrent threshold is no longer reached.
The ISL78201 is capable of start-up with prebiased output.
FN8615 Rev 2.00
August 15, 2016
Pulling the MODE pin to GND will set the IC in forced PWM mode.
The ISL78201 employs the peak current mode PWM control for
fast transient response and cycle-by-cycle current limiting. See
“Block Diagram” on page 4.
The PWM operation is initialized by the clock from the oscillator.
The upper MOSFET is turned on by the clock at the beginning of a
PWM cycle and the current in the MOSFET starts to ramp up.
When the sum of the current sense signal and the slope
compensation signal reaches the error amplifier output voltage
level, the PWM comparator is triggered to shut down the PWM
logic to turn off the high-side MOSFET. The high-side MOSFET
stays off until the next clock signal comes for the next cycle.
The output voltage is sensed by a resistor divider from VOUT to the
FB pin. The difference between the FB voltage and 0.8V
reference is amplified and compensated to generate the error
voltage signal at the COMP pin. Then the COMP pin signal is
compared with the current ramp signal to shut down the PWM.
PFM Mode Operation
To pull the MODE pin HIGH (>2.5V) or leave the MODE pin floating
will set the IC to have Pulse Frequency Modulation (PFM)
operation in light load. In PFM mode, the switching frequency is
dramatically reduced to minimize the switching loss. The
ISL78201 enters PFM mode when the MOSFET peak current is
lower than the PWM/PFM boundary current threshold. This
threshold is 700mA as default when there is no programming
resistor at MODE pin. It can also be programmed by a resistor at
the MODE pin to ground (see Equation 2).
118500
R MODE = -----------------------------IPFM + 0.2
(EQ. 2)
Where IPFM is the desired PWM/PFM boundary current
threshold and RMODE is the programming resistor. The usable
resistor value range to program PFM current threshold is 150kΩ
to 200kΩ. The RMODE value out of this range is not
recommended.
Page 13 of 23
ISL78201
voltage ringing spikes (within a couple of ns time range) due to
part switching while not exceeding an absolute maximum rating
of 44V.
200
RMODE (kΩ)
190
180
170
160
150
0.3
0.4
0.5
IPFM (A)
0.6
0.7
FIGURE 31. RMODE vs IPFM
Synchronous and Non-Synchronous Buck
The ISL78201 supports both synchronous and non-synchronous
buck operations.
In synchronous buck configuration, a 5.1k or smaller value resistor
has to be added to connect LGATE to ground to avoid a false turn-on
of the LGATE caused by coupling noise.
For a non-synchronous buck operation when a power diode is
used as the low-side power device, the LGATE driver can be
disabled with LGATE connected to VCC (before IC start-up). For
non-synchronous buck, the phase node will show oscillations
after high-side turns off (as shown in Figure 24 - blue trace). This
is normal due to the oscillations among the parasitic capacitors
at phase node and output inductor. A RC snubber (typically 200Ω
and 2.2nF) at phase node can reduce this ringing.
AUXVCC Switchover
The ISL78201 has an auxiliary LDO integrated as shown in the
block diagram on page 4. It is used to replace the internal MAIN
LDO function after the IC start-up. “Typical Application Schematic
II - VCC Switchover to VOUT” on page 5 shows its basic application
setup with output voltage connected to AUXVCC. After the IC
soft-start is complete and the output voltage is built up to a
steady state, (once the AUXVCC pin voltage is over the AUX LDO
Switchover Rising Threshold) the MAIN LDO is shut off and the
AUXILIARY LDO is activated to bias VCC. Since the AUXVCC pin
voltage is lower than the input voltage VIN, the internal LDO
dropout voltage and consequent power loss is reduced. This
feature brings substantial efficiency improvements in light load
range especially at high input voltage applications.
When the voltage at AUXVCC falls below the AUX LDO Switchover
Falling Threshold, the AUXILIARY LDO is shut off and the MAIN
LDO is reactivated to bias VCC. At the OV/UV fault events, the IC
will switchover from AUXILIARY LDO to MAIN LDO.
The AUXVCC switchover function is offered in buck configuration.
It is not offered in boost configuration when the AUXVCC pin is
used to monitor the boost output voltage for OVP.
Input Voltage
With the part switching, the operating ISL78201 input voltage
must be under 40V. This recommendation allows for short
FN8615 Rev 2.00
August 15, 2016
The lowest IC operating input voltage (VIN pin) depends on VCC
voltage and the rising and falling VCC POR threshold in the
Electrical Specifications table on page 6. At IC start-up when VCC
is just over rising POR threshold, switching does not occur until
soft-start begins. Thus, the IC minimum start-up voltage on the
VIN pin is 3.05V (Maximum of Rising VCC POR). When the
soft-start is initiated, the regulator is switching and the dropout
voltage across the internal LDO increases due to driving current.
Thus, the IC VIN pin shutdown voltage is related to driving current
and VCC POR falling threshold. The internal upper side MOSFET
has typical 10nC gate drive. For a typical example of synchronous
buck with 4nC lower MOSFET gate drive and 500kHz switching
frequency, the driving current is 7mA total causing a 70mV drop
across internal LDO under 3V VIN. Then the IC shutdown voltage
on the VIN pin is 2.87V (2.8V + 0.07V). In practical design, extra
room should be taken into account with concerns of voltage
spikes at VIN.
With boost buck configuration, the input voltage range can be
expanded further down to 2.5V or lower depending on the boost
stage voltage drop upon maximum duty cycle. Since the boost
output voltage is connected to the VIN pin as the buck inputs,
after the IC starts up, the IC will keep operating and switching as
long as the boost output voltage can keep the VCC voltage higher
than falling threshold. Refer to “Boost Converter Operation” on
page 15 for more details.
Output Voltage
The output voltage can be programmed down to 0.8V by a
resistor divider from VOUT to FB. For Buck, the maximum
achievable voltage is (VIN * DMAX - VDROP), where VDROP is the
voltage drop in the power path including mainly the MOSFET
rDS(ON) and inductor DCR. The maximum duty cycle DMAX is
decided by (1 - fSW * tMIN(OFF)).
Output Current
With the high-side MOSFET integrated, the maximum current the
ISL78201 can support is decided by the package and many
operating conditions including input voltage, output voltage, duty
cycle, switching frequency and temperature, etc. From the
thermal perspective, the die temperature should not be above
+125°C with the power loss dissipated inside of the IC.
Figures 14 through 16 show the thermal performance of this
part operating in buck at different conditions. The part can
output 2.5A under typical buck application condition VIN 8~36V,
VOUT 5V, 500kHz, still air and +85°C ambient conditions. The
output current should be derated under any conditions causing
the die temperature to exceed +125°C.
Figure 14 shows a 5V, 2A output application over VIN range
under +105°C ambient temperature with 100 CFM air flow.
Figure 15 shows 2A applications under +25°C still air conditions.
Different VOUT (5V, 9V, 12V, 20V) applications thermal data are
shown over VIN range at +25°C and still air. The temperature rise
data in this figure can be used to estimate the die temperature at
different ambient temperatures under various operating
conditions. Note: More temperature rise is expected at higher
Page 14 of 23
ISL78201
ambient temperatures due to more conduction loss caused by
rDS(ON) increase.
Equation 3 to calculate the upper resistor RUP (R1 in Figure 32)
for a desired hysteresis VHYS at boost input voltage.
Figure 16 shows thermal performance under various output
currents and input voltages. It shows the temperature rise trend
with load and VIN changes.
VHYS
R UP M = ----------------3 A
Basically, the die temperature equals the sum of ambient
temperature and the temperature rise resulting from power
dissipated from the IC package with a certain junction to
ambient thermal impedance JA. The power dissipated in the IC
is related to the MOSFET switching loss, conduction loss and the
internal LDO loss. Besides the load, these losses are also related
to input voltage, output voltage, duty cycle, switching frequency
and temperature. With the exposed pad at the bottom, the heat
of the IC mainly goes through the bottom pad and JA is greatly
reduced. The JA is highly related to layout and air flow
conditions. In layout, multiple vias (20) are strongly
recommended in the IC bottom pad. In addition, the bottom pad
with its vias should be placed in ground copper plane with an
area as large as possible connected through multiple layers.
The JA can be reduced further with air flow.
For applications with high output current and bad operating
conditions (compact board size, high ambient temperature, etc.),
synchronous buck is highly recommended since the external
low-side MOSFET generates smaller heat than the external
low-side power diode. This helps to reduce PCB temperature rise
around the ISL78201 and less junction temperature rise.
Boost Converter Operation
The Typical Application Schematic III on page 5 shows the
circuits where the boost works as a prestage to provide input to
the following Buck stage. This is for applications when the input
voltage could drop to a very low voltage in some constants (in
some battery powered systems as an example), causing the
output voltage drops out of regulation. The boost converter can
be enabled to boost the input voltage up to keep the output
voltage in regulation. When the system input voltage recovers
back to normal, the boost stage is disabled while only the buck
stage is switching.
The EXT_BOOST pin is used to set Boost mode and monitor the
boost input voltage. At IC start-up before soft-start, the controller
will latch in Boost mode when the voltage on this pin is above
200mV; it will latch in Synchronous Buck mode if voltage on this
pin is below 200mV. In Boost mode, the low-side driver output
PWM has the same PWM signal with the buck regulator.
In Boost mode, the EXT_BOOST pin is used to monitor the boost
input voltage to turn on and turn off the boost PWM. The AUXVCC
pin is used to monitor the boost output voltage to turn on and
turn off the boost PWM.
Referring to Figure 32, a resistor divider from the boost input
voltage to the EXT_BOOST pin is used to detect the boost input
voltage. When the voltage on the EXT_BOOST pin is below 0.8V,
the boost PWM is enabled with a fixed 500µs soft-start when the
boost duty cycle increases from tMINON*fSW to ~50% and a 3µA
sinking current is enabled at the EXT_BOOST pin for hysteresis
purposes. When the voltage on the EXT_BOOST pin recovers to
above 0.8V, the boost PWM is disabled immediately. Use
FN8615 Rev 2.00
August 15, 2016
(EQ. 3)
Use Equation 4 to calculate the lower resistor RLOW (R2 in
Figure 32) according to a desired boost enable threshold.
R UP 0.8
R LOW = ------------------------------VFTH – 0.8
(EQ. 4)
Where VFTH is the desired falling threshold on boost input
voltage to turn on the boost, 3µA is the hysteresis current, and
0.8V is the reference voltage to be compared.
Note the boost start-up threshold has to be selected in a way that
the buck is operating well at close loop before boost start-up.
Otherwise, large inrush current at boost start-up could occur at
boost input due to the buck loop saturation. The boost start-up
input voltage threshold should be set high enough to cover the
DC voltage drop of boost inductor and diode, also the buck’s
maximum duty cycle and voltage conduction drop. This ensures
buck is not reaching maximum duty cycle before boost start-up.
Similarly, a resistor divider from boost output voltage to the
AUXVCC pin is used to detect the boost output voltage. When the
voltage on the AUXVCC pin is below 0.8V, the boost PWM is
enabled with a fixed 500µs soft-start and a 3µA sinking current
is enabled at the AUXVCC pin for hysteresis purpose. When the
voltage on the AUXVCC pin recovers to above 0.8V, the boost
PWM is disabled immediately. Use Equation 3 to calculate the
upper resistor RUP (R3 in Figure 32 on page 16) according to a
desired hysteresis VHY at boost output voltage. Use Equation 4 to
calculate the lower resistor RLOW (R4 in Figure 32) according to a
desired boost enable threshold at boost output.
Assuming VBAT is the boost input voltage, VOUTBST is the boost
output voltage and VOUT is the buck output voltage, the steady
state transfer functions are:
1
V OUTBST = ------------- V BAT
1–D
(EQ. 5)
D
V OUT = D V OUTBST = ------------- V BAT
1–D
(EQ. 6)
From Equations 5 and 6, Equation 7 can be derived to estimate
the steady state boost output voltage as a function of VBAT and
VOUT:
V OUTBST = V BAT + V OUT
(EQ. 7)
After the IC starts up, the boost buck converters can keep
working when the battery voltage drops extremely low because
the IC’s bias (VCC) LDO is powered by the boost output. For an
example of 3.3V output application, when the battery drops to
2V, the VIN pin voltage is powered by the boost output voltage
that is 5.2V (Equation 7), meaning the VIN pin (buck input) still
needs 5.2V to keep the IC working.
Page 15 of 23
ISL78201
BATTERY
V OUTBST
+
R1
+
EXT_BOOST
0.8V
R2
I_HYS = 3µA
LOGIC
R3
LGATE
AUXVCC
R4
PWM
0.8V
LGATE
DRIVE
I_HYS = 3µA
FIGURE 32. BOOST CONVERTER CONTROL
Note in the previous mentioned case, the boost input current
could be high because the input voltage is very low
(VIN *IIN = VOUT * IOUT / Efficiency). If the design is to achieve the
low input operation with full load, the inductor and MOSFET have
to be selected to have enough current ratings to handle the high
current appearing at boost input. The boost inductor current are
the same with the boost input current, which can be estimated in
Equation 8, where POUT is the output power, VBAT is the boost
input voltage, and EFF is the estimated efficiency of the whole
boost and buck stages.
P OUT
IL IN = -------------------------------V BAT EFF
(EQ. 8)
Based on the same concerns of boost input current, the start-up
sequence must follow the rule that the IC is enabled after the
boost input voltage rises above a certain level. The shutdown
sequence must follow the rule that the IC is disabled first before
the boost input power source is turned off. At Boost mode
applications where there is no external control signal to
enable/disable the IC, an external input UVLO circuit must be
implemented for the start-up and shutdown sequence.
PFM is not available in Boost mode.
Noninverting Single Inductor Buck Boost
Converter Operation
Figure 6B on page 5 in “Typical Application Schematic III - Boost
Buck Converters” shows a noninverting single inductor buck
boost configuration. The recommended setting is to connect a
resistor divider 100kΩ (1%) and 15kΩ (1%) from VCC pin to both
EXT_BOOST and AUXVCC pins (EXT_BOOST and AUXVCC pins are
directly connected) as shown in Figure 6B on page 5. In this way,
the EXT_BOOST pin voltage is set with a voltage higher than the
Boost mode detection threshold 0.2V (Typical) at start-up, which
sets the IC in Boost mode. During and after soft-start, the
EXT_BOOST and AUXVCC pins' voltages have voltages lower than
the boost switching-disable threshold 800mV to keep boost
constantly PWM switching.
FN8615 Rev 2.00
August 15, 2016
Just like in the 2-stage Boost Buck mode, LGATE is switching ON
with the same phase of upper FETs switching ON, meaning both
upper and lower-side FETs are ON and OFF at the same time with
the same duty cycle. When both FETs are ON, the input voltage
charges the inductor current ramping up for duration of DT; when
both FETs are OFF, inductor current is free wheeling through the 2
power diodes to output, and output voltage discharge the
inductor current ramping down for (1 - D)T (in CCM mode). The
steady state DC transfer function is shown in Equation 9:
D
V OUT = ------------------ V IN
1–D
(EQ. 9)
Where VIN is the input voltage, VOUT is the buck-boost output
voltage, D is duty cycle.
Another useful equation is to calculate the inductor DC current as
shown in Equation 10:
1
IL DC = ------------------ I OUT
1–D
(EQ. 10)
Where ILDC is the inductor DC current and IOUT is the output DC
current.
Equation 10 says the inductor current is charging output only
during (1-D)T, which means inductor current has larger DC
current than output load current. Thus, for this part with high-side
FET integrated, the noninverting buck-boost configuration has
less load current capability compared with buck and 2-stage
boost-buck configurations. Its load current capability depends
mainly on the duty cycle and inductor current.
Inductor ripple current is calculated using Equation 11
V OUT 1 – D T
IL RIPPLE = ----------------------------------------------------L
(EQ. 11)
The inductor peak current is,
1
IL PEAK = IL DC + ---- IL RIPPLE
2
(EQ. 12)
Page 16 of 23
ISL78201
In power stage DC calculations, use Equation 9 to calculate D,
then use Equation 10 to calculate ILDC. D and ILDC are useful
information to estimate the high-side FETs power losses and
check if the part can meet the load current requirements.
1200
1000
RFS (kΩ)
800
600
400
In the case when the PGOOD pin is pulled up by external bias
supply instead of VCC of itself, when the part is disabled, the
internal PGOOD open-drain transistor is off, the external bias
supply can charge PGOOD pin HIGH. This should be known as
false PGOOD reporting. At start-up when VCC rises from 0,
PGOOD will be pulled low when VCC reaches 1V. After EN pulled
low and VCC falling, PGOOD internal open-drain transistor will
open with high impedance when VCC falls below 1V. The time
between EN pulled low and PGOOD OPEN depends on the VCC
falling time to 1V.
Fault Protection
200
0
within OV/UV window (90%REF
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