ISL78229EV1Z

DATASHEET ISL78229 FN8656 Rev.6.00 Jul 13, 2018 2-Phase Boost Controller with Drivers and I2C/PMBus The ISL78229 is an automotive grade (AEC-Q100 Grade 1), 2-phase 55V synchronous boost controller that simplifies the design of high power boost applications. It integrates strong half-bridge drivers, an analog/digital tracking input, comprehensive protection functions, and a PMBus interface for added control and telemetry. The ISL78229 enables a simple, modular design for systems requiring power and thermal scalability. It offers peak-current mode control for fast line response and simple compensation. Its synchronous 2-phase architecture enables it to support higher current while reducing the size of input and output capacitors. The integrated drivers feature programmable adaptive dead time control, offering flexibility in power stage design. The ISL78229 offers a 90° output clock and supports 1-, 2-, and 4-phases. The ISL78229 offers a highly robust solution for the most demanding environments. Its unique soft-start control prevents large negative current even in extreme cases, such as a restart under high output pre-bias on high volume capacitances. It also offers two levels of cycle-by-cycle OCP, average current limiting, input OVP, output UVP/OVP, and internal OTP. A thermistor input provides external OTP for the power-stage elements. In the event of a fault, the ISL78229 offers individually programmable latch-off or hiccup recovery for each fault type. Also integrated are several functions that ease system design. A unique tracking input controls the output voltage, allowing it to track either a digital duty cycle (PWM) signal or an analog reference. The ISL78229 provides input average current limiting so the system can deliver transient bursts of high load current while limiting the average current to avoid overheating. The ISL78229 PMBus interface provides fault reporting, telemetry, and system control to support functional safety qualification. Related Literature For a full list of related documents, visit our website • ISL78229 product page ISL78229 EN_IC EN SDA SCL SALERT PGOOD TRACK CLOCK_OUT • Peak current mode control with adjustable slope compensation • Secondary average current control loop • Integrated 5V 2A sourcing/3A sinking N-channel MOSFET drivers • Switching frequency: 50kHz to 1.1MHz per phase • External synchronization • Programmable minimum duty cycle • Programmable adaptive dead time control • Optional diode emulation and phase dropping • PWM and analog track function • Forced PWM operation with negative current limiting and protection • Comprehensive protection/fault reporting • Selectable hiccup or latch-off fault response • I2C/PMBus compatible digital interface • AEC-Q100 qualified, Grade 1: -40°C to +125°C • 6mmx6mm 40 Ld WFQFN (Wettable Flank QFN) package Applications • Automotive power systems (for example, 12V to 24V, 12V to 48V, etc.) - Trunk audio amplifiers - Start-stop systems - Automotive boost applications • Industrial and telecommunication power supplies PVCC UG1 PH1 RSEN1 CLKOUT SS COMP ISEN1N ISEN1P BOOT2 UG2 PH2 100 VOUT BOOT1 LG1 POWERGOOD • Supports synchronous or standard boost topology VIN NTC PMBus { • Input/output voltage range: 5V to 55V, withstands 60V transients RSEN2 LG2 ISEN2N ISEN2P FB VIN 95 EFFICIENCY (%) VIN Features 90 VO = 18V 85 80 VO = 24V 75 VO = 36V 70 65 60 55 50 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 LOAD CURRENT (A) NOTE: (See Typical Application in Figure 4 on page 8.) FIGURE 1. SIMPLIFIED APPLICATION SCHEMATIC, 2-PHASE SYNCHRONOUS BOOST FN8656 Rev.6.00 Jul 13, 2018 FIGURE 2. EFFICIENCY CURVES, VIN = 12V, TA = +25°C Page 1 of 72 ISL78229 Table of Contents Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Typical Application - 2-Phase Synchronous Boost . . . . . . . . 8 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . 9 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Operation Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Synchronous Boost . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 PWM Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Multiphase Power Conversion . . . . . . . . . . . . . . . . . . . . . . . . . 27 Oscillator and Synchronization. . . . . . . . . . . . . . . . . . . . . . . . . 29 Operation Initialization and Soft-Start. . . . . . . . . . . . . . . . . . . 30 Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Soft-Start. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 PGOOD Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Current Sense. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Adjustable Slope Compensation . . . . . . . . . . . . . . . . . . . . . . . 33 Light-Load Efficiency Enhancement . . . . . . . . . . . . . . . . . . . . 33 Fault Protections/Indications. . . . . . . . . . . . . . . . . . . . . . . . . . 34 Internal 5.2V LDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Voltage Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Switching Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Inductor Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Capacitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bootstrap Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Loop Compensation Design . . . . . . . . . . . . . . . . . . . . . . . . . . VCC Input Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Current Sense Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration to Support Single Phase Boost. . . . . . . . . . . . Layout Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 PMBus User Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Monitor Operating Parameters Through PMBus . . . . . . . . . . 40 Monitor Faults and Configure Fault Responses . . . . . . . . . . . 40 Set Operation/Fault Thresholds via PMBus . . . . . . . . . . . . . . 40 Accessible Timing for PMBus Registers Status . . . . . . . . . . . 41 Device Identification Address and Read/Write . . . . . . . . . . . 42 PMBus Data Formats Used in ISL78229 . . . . . . . . . . . . . . . . 42 PMBus Command Summary . . . . . . . . . . . . . . . . . . . . . . . . . .43 PMBus Command Detail . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 OPERATION (01h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 CLEAR_FAULTS (03h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 WRITE_PROTECT (10h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 CAPABILITY (19h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 VOUT_COMMAND (21h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 VOUT_TRANSITION_RATE (27h) . . . . . . . . . . . . . . . . . . . . . . . . 49 OT_NTC_FAULT_LIMIT (4Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 OT_NTC_WARN_LIMIT (51h) . . . . . . . . . . . . . . . . . . . . . . . . . . 51 READ_VIN (88h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 READ_VOUT (89h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 READ_IIN (8Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 READ_TEMPERATURE (8Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . 55 PMBUS_REVISION (98h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 IC_DEVICE_ID (ADh). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 IC_DEVICE_REV (AEh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 FAULT_STATUS (D0h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 FAULT_MASK (D1h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 SET_FAULT_RESPONSE (D2h) . . . . . . . . . . . . . . . . . . . . . . . . . 60 VOUT_OV_FAULT_LIMIT (D3h) . . . . . . . . . . . . . . . . . . . . . . . . . 61 VOUT_UV_FAULT_LIMIT (D4h) . . . . . . . . . . . . . . . . . . . . . . . . . 62 CC_LIMIT (D5h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 OC_AVG_FAULT_LIMIT (D6h) . . . . . . . . . . . . . . . . . . . . . . . . . . 64 FN8656 Rev.6.00 Jul 13, 2018 65 65 65 65 65 66 66 66 66 68 68 68 Page 2 of 72 ISL78229 Pin Configuration VCC RDT ATRK/DTRK HIC/LATCH NC ISEN2P ISEN2N ISEN1P ISEN1N VIN 40 LD 6x6 WFQFN TOP VIEW 40 39 38 37 36 35 34 33 32 31 SLOPE 1 30 BOOT1 FB 2 29 UG1 COMP 3 28 PH1 SS 4 27 LG1 PAD 8 23 PH2 PGOOD 9 22 UG2 FSYNC 10 21 BOOT2 11 12 13 14 15 16 17 18 19 20 CLKOUT ADDR2 EN 24 LG2 PLLCOMP 7 RBLANK ADDR1 DE/PHDRP 25 PGND NTC 6 SALERT TRACK SCL 26 PVCC SDA 5 SGND IMON Functional Pin Description PIN NAME PIN # DESCRIPTION SLOPE 1 Programs the slope of the internal slope compensation. A resistor should be connected from the SLOPE pin to GND. Refer to “Adjustable Slope Compensation” on page 33 for information about how to select this resistor value. FB 2 The inverting input of the error amplifier for the voltage regulation loop. A resistor network must be placed between the FB pin and the output rail to set the boost converter’s output voltage. Refer to “Output Voltage Setting” on page 65 for more details. This pin also has output overvoltage and undervoltage comparators. Refer to “Output Undervoltage Fault” on page 36 and “Output Overvoltage Fault” on page 36 for more details. COMP 3 The output of the transconductance error amplifier (Gm1) for the output voltage regulation loop. Place the compensation network between the COMP pin and ground. Refer to “Output Voltage Regulation Loop” on page 26 for more details. The COMP pin voltage can also be controlled by the constant current control loop error amplifier (Gm2) output through a diode (DCC) when the constant current control loop is used to control the input average current. Refer to “Constant Current Control (CC)” on page 37 for more details. SS 4 A capacitor placed from SS to ground sets up the soft-start ramp rate and in turn, determines the soft-start time. Refer to “Soft-Start” on page 31 for more details. IMON 5 The average current monitor pin for the sum of the two phases’ inductor currents. It is used for average current limiting and average current protection functions. The sourcing current from the IMON pin is the sum of the two CSA’s outputs plus a fixed 17µA offset current. With each CSA sensing individual phase’s inductor current, the IMON signal represents the sum of the two phases’ inductor currents and is the input current for the boost. Place a resistor in parallel with a capacitor from IMON to ground. The IMON pin output current signal builds up the average voltage signal representing the average current sense signals. A constant average current limiting function and an average current protection are implemented based on the IMON signal. • Constant Average Current Limiting: A Constant Current (CC) control loop is implemented to limit the IMON average current signal using a 1.6V reference, which ultimately limits the total input average current to a constant level. • Average Current Protection: If the IMON pin voltage is higher than 2V, the part goes into either Hiccup or Latch-off fault protection as described in “Fault Response Register SET_FAULT_RESPONSE (D2h)” on page 35. Refer to “Average Current Sense for 2 Phases - IMON” on page 32 for more details. FN8656 Rev.6.00 Jul 13, 2018 Page 3 of 72 ISL78229 Functional Pin Description (Continued) PIN NAME PIN # DESCRIPTION TRACK 6 External reference input pin for the IC output voltage regulation loop to follow. The input reference signal can be either a digital or analog signal selected by the ATRK/DTRK pin configuration. If the TRACK function is not used, connect the TRACK pin to VCC and the internal VREF_DAC works as the reference. Refer to “Digital/Analog TRACK Function” on page 26 for more details. ADDR1 7 ADDR1, a logic input in combination with ADDR2, selects one of four bus addresses. Refer to “Device Identification Address and Read/Write” on page 42 for more details. ADDR2 8 ADDR2, a logic input in combination with ADDR1, selects one of four bus addresses. Refer to “Device Identification Address and Read/Write” on page 42 for more details. PGOOD 9 Provides an open-drain power-good signal. Pull up this pin with a resistor to this IC’s VCC for proper function. When the output voltage is within OV/UV thresholds and soft-start is completed, the internal PGOOD open-drain transistor is open and PGOOD is pulled HIGH. It is pulled low when output UV/OV or input OV conditions are detected. Refer to “PGOOD Signal” on page 31 for more details. FSYNC 10 A dual-function pin for switching frequency setting and synchronization defined as follows: • The PWM switching frequency can be programmed by a resistor RFSYNC from this pin to ground. The PWM frequency refers to a single-phase switching frequency in this datasheet. The typical programmable frequency range is 50kHz to 1.1MHz. • The PWM switching frequency can also be synchronized to an external clock applied on the FSYNC pin. The FSYNC pin detects the input clock signal’s rising edge to be synchronized with. The typical detectable minimum pulse width of the input clock is 20ns. The rising edge of LG1 is delayed by 35ns from the rising edge of the input clock signal at the FSYNC pin. When the internal clock is locked to the external clock, it latches to the external clock. If the external clock on the FSYNC pin is removed, the switching frequency oscillator shuts down. The part then detects a PLL_LOCK fault and goes to either Hiccup mode or Latch-off mode as described in “Fault Response Register SET_FAULT_RESPONSE (D2h)” on page 35. If the part is set in Hiccup mode, the part restarts with the frequency set by RFSYNC. SGND 11 Signal ground pin that the internal sensitive analog circuits refer to. Connect this pin to a large copper ground plane free from large noisy signals. In layout power flow planning, avoid having the noisy high frequency pulse current flowing through the ground area around the IC. SDA 12 Serial bus data input/output. Requires pull-up. SCL 13 Serial bus clock input. Requires pull-up. SALERT 14 PMBus Alert Output. An open-drain output that is pulled low when a fault condition is detected. Requires pull-up. Refer to “Fault Flag Register FAULT_STATUS (D0h) and SALERT Signal” on page 34 for more details. NTC 15 External temperature sensor input. An NTC resistor from this pin to GND can be used as the external temperature sensing component. A 20µA current sources out of this pin. The voltage at this pin is 20µA times the NTC resistor, which represents the temperature. The voltage on this pin is converted by the internal ADC and stored in the NTC register which can be read over the PMBus. Refer to “External Temperature Monitoring and Protection (NTC Pin)” on page 38 for more details. DE/PHDRP 16 Used to select Diode Emulation mode (DE), Phase Dropping (PH_DROP) mode, or Continuous Conduction Mode (CCM). There are 3 configurable modes: 1. DE mode; 2. DE plus PH_DROP mode; 3. CCM mode. Refer to Table 2 on page 34 for the three configurable options. The phase dropping mode is not allowed with external synchronization. RBLANK 17 A resistor from this pin to ground programs the blanking time for current sensing after the PWM is ON (LG is ON). This blanking time is also called tMINON time, meaning the minimum ON-time when a PWM pulse is ON. Refer to “Minimum On-Time (Blank Time) Consideration” on page 30 for information about RBLANK. PLLCOMP 18 The compensation node for the switching frequency clock’s Phase Lock Loop (PLL). A second order passive loop filter connected between this pin and ground compensates the PLL. Refer to “Oscillator and Synchronization” on page 29 for more details. EN 19 A threshold-sensitive enable input for the controller. When the EN pin is driven above 1.2V, the ISL78229 is enabled and the internal LDO is activated to power up PVCC followed by a start-up procedure. Driving the EN pin below 0.95V disables the IC and clears all fault states. Refer to “Enable” on page 31 for more details. CLKOUT 20 Outputs a clock signal with same frequency to one phase’s switching frequency. The rising edge signal on the CLKOUT pin is delayed by 90° from the rising edge of LG1 of the same IC. With CLKOUT connected to the FSYNC pin of the second ISL78229, a 4-phase interleaving operation can be achieved. Refer to “Oscillator and Synchronization” on page 29 for more details. FN8656 Rev.6.00 Jul 13, 2018 Page 4 of 72 ISL78229 Functional Pin Description (Continued) PIN NAME PIN # DESCRIPTION BOOT2 21 Provides bias voltage to the Phase 2 high-side MOSFET driver. A bootstrap circuit creates a voltage suitable to drive the external N-channel MOSFET. A 0.47µF ceramic capacitor in series with a 1.5Ω resistor are recommended between the BOOT2 and PH2 pins. In the typical configuration, PVCC provides the bias to BOOT2 through a fast switching diode. In applications in which a high-side driver is not needed (for example, a standard boost application), BOOT2 is recommended to be connected to ground. The ISL78229 IC can detect BOOT2 being grounded during start-up and both the Phase 1 and Phase 2 high-side drivers are disabled. In addition, PH1 and PH2 should also be tied to ground. UG2 22 Phase 2 high-side gate driver output. Disable this output by tying either BOOT1 and PH1 to ground or BOOT2 and PH2 to ground. PH2 23 This pin represents the return path for the Phase 2 high-side gate drive. Connect this pin to the source of the Phase 2 high-side MOSFETs and the drain of the low-side MOSFETs. LG2 24 Phase 2 low-side gate driver output. It should be connected to the Phase 2 low-side MOSFETs’ gates. PGND 25 Provides the return path for the low-side MOSFET drivers. This pin carries a noisy driving current, so the traces connecting from this pin to the low-side MOSFET source and PVCC decoupling capacitor ground pad should be as short as possible. All the sensitive analog signal traces should not share common traces with this driver return path. Connect this pin to the ground copper plane (wiring away from the IC instead of connecting through the IC bottom PAD) through several vias as close as possible to the IC. PVCC 26 Output of the internal linear regulator that provides bias for the low-side driver, high-side driver (PVCC connected to BOOTx through diodes) and VCC bias (PVCC and VCC are typically connected through a small resistor like 10Ω or smaller, which helps to filter out the noises from PVCC to VCC). The PVCC operating range is 4.75V to 5.5V. A minimum 10µF decoupling ceramic capacitor should be used between PVCC and PGND. Refer to “Internal 5.2V LDO” on page 39 for more details. LG1 27 Phase 1 low-side gate driver output. It should be connected to the Phase 1 low-side MOSFETs’ gates. PH1 28 Connect this pin to the source of the Phase 1 high-side MOSFETs and the drain of the low-side MOSFETs. This pin represents the return path for the Phase 1 high-side gate drive. UG1 29 Phase 1 high-side MOSFET gate drive output. Disable this output by tying either BOOT1 and PH1 to ground or BOOT2 and PH2 to ground. BOOT1 30 Provides bias voltage to the Phase 1 high-side MOSFET driver. A bootstrap circuit creates a voltage suitable to drive the external N-channel MOSFET. A 0.47µF ceramic capacitor in series with a 1.5Ω resistor are recommended between BOOT1 and PH1 pins. In a typical configuration, PVCC provides the bias to BOOT1 through a fast switching diode. In applications in which a high-side driver is not needed (for example, standard boost application), the BOOT1 is recommended to be connected to ground. The ISL78229 IC can detect BOOT1 being grounded during start-up and both the Phase 1 and Phase 2 high-side drivers are disabled. In addition, PH1 and PH2 should also be tied to ground. VIN 31 Connect the supply rail to this pin. Typically, connect the boost input voltage to this pin. The VIN pin can also be supplied by a separate input source independent from the boost power stage input source. This pin is connected to the input of the internal linear regulator, generating the power necessary to operate the chip. The DC voltage applied to the VIN should not exceed 55V during normal operation. VIN can withstand transients up to 60V, but in this case, the device's overvoltage protection stops it from switching to protect itself. Refer to “Input Overvoltage Fault” on page 35 for more details. ISEN1N 32 The negative potential input to the Phase 1 current sense amplifier. This amplifier continuously senses the Phase 1 inductor current through a power current sense resistor in series with the inductor. The sensed current signal is used for current mode control, peak current limiting, average current limiting, and diode emulation. ISEN1P 33 The positive potential input to the Phase 1 current sense amplifier. ISEN2N 34 The negative potential input to the Phase 2 current sense amplifier. This amplifier continuously senses the Phase 2 inductor current through a power current sense resistor in series with the inductor. The sensed current signal is used for current mode control, peak current limiting, average current limiting, and diode emulation. ISEN2P 35 The positive phase input to the Phase 2 current sense amplifier. NC 36 Not connected. This pin is not electrically connected internally. HIC/LATCH 37 Selects either the Hiccup or Latch-off response to faults, including output overvoltage (monitoring the FB pin), output undervoltage (monitoring the FB pin, default inactive), VIN overvoltage (monitoring the FB pin), peak overcurrent protection (OC2), average current protection (monitoring the IMON pin), and over-temperature protection (monitoring the NTC pin), etc. Set HIC/LATCH = HIGH to activate the Hiccup fault response. Set HIC/LATCH = LOW to activate the Latch-off fault response. Either toggling the EN pin or recycling VCC POR resets the IC from Latch-off status. Refer to “Fault Response Register SET_FAULT_RESPONSE (D2h)” on page 35 and Table 3 on page 41 for more details. FN8656 Rev.6.00 Jul 13, 2018 Page 5 of 72 ISL78229 Functional Pin Description (Continued) PIN NAME PIN # DESCRIPTION ATRK/DTRK 38 The logic input pin to select the input signal format options for the TRACK pin. Pull this pin HIGH for the TRACK pin to accept analog input signals. Pull this pin LOW for the TRACK pin to accept digital input signals. Refer to “Digital/Analog TRACK Function” on page 26 for more details. RDT 39 A resistor connected from this pin to ground programs the dead times between UGx OFF to LGx ON and LGx OFF to UGx ON to prevent shoot-through. Refer to “Driver Configuration” on page 25 for the selection of RDT. VCC 40 IC bias power input pin for the internal analog circuitry. A minimum 1µF ceramic capacitor should be used between VCC and ground for noise decoupling purposes. VCC is typically biased by PVCC or an external bias supply with voltage ranging from 4.75V to 5.5V. Because PVCC provides the pulsing drive current, a small resistor (10Ω or smaller) between PVCC and VCC can help filter out the noises from PVCC to VCC. PAD - Bottom thermal pad. It is not used as an electrical connection to the IC. In layout it must be connected to a PCB large ground copper plane that does not contain noisy power flows. Put multiple vias (as many as possible) in this pad connecting to the ground copper plane to help reduce the IC’s JA. Ordering Information PART NUMBER (Notes 2, 3) PART MARKING TEMP. RANGE (°C) TAPE AND REEL (UNITS) (Note 1) PACKAGE (RoHS COMPLIANT) PKG. DWG. # ISL78229ARZ ISL7822 9ARZ -40 to +125 - 40 Ld 6x6 WFQFN L40.6x6C ISL78229ARZ-T ISL7822 9ARZ -40 to +125 4k 40 Ld 6x6 WFQFN L40.6x6C ISL78229ARZ-T7A ISL7822 9ARZ -40 to +125 250 40 Ld 6x6 WFQFN L40.6x6C ISL78229EV1Z Evaluation Board NOTES: 1. Refer to TB347 for details about reel specifications. 2. These Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu-Ag plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), refer to the ISL78229 product information page. For more information about MSL, refer to TB363. TABLE 1. KEY DIFFERENCES BETWEEN FAMILY OF PARTS PART NUMBER TOPOLOGY PMBus NTC TRACK FUNCTION ISL78229 2-Phase Boost Controller Yes Yes Yes 40 Ld 6x6 WFQFN ISL78227 2-Phase Boost Controller No No Yes 32 Ld 5x5 WFQFN FN8656 Rev.6.00 Jul 13, 2018 PACKAGE Page 6 of 72 VIN EN EN HIC/LATCH VIN_OV 1.21V 1.2V 5.2V LDO PVCC POR OTP PLL DEFAULT SELECTION 3 bits [2:0] D4h HICCUP /LATCH-OFF EN EN_HICCP HICCUP RETRY DELAY INITIALIZATION DELAY 5µA EN_LATCHOFF M U X VOUT_OV ADDR1 ADDR2 SDA 10-BIT ADC EN I2C/PMBus INTERFACE VIN_OV VFB D2h VNTC VIN/48 VFB VIMON 1.2*VREF_DAC 3 bits [2:0] (DEFAULT) VREF_ D3h VOUTOV VCC NTC 20µA VIN/48 ÷ 48 PGOOD ISL78229 FN8656 Rev.6.00 Jul 13, 2018 Block Diagram VOUT_OV SCL VOUT_UV VREF_ VOUTUV OC_AVG RISING DELAY VOUT_UV OC2_PEAK_PH1 OC2_PEAK_PH2 0.8*VREF_DAC (DEFAULT) SALERT LOGIC AND REGISTERS OT_NTC_FAULT LATCH-OFF LOGIC CLOCK FAULT FSYNC PLLCOMP CLKOUT VCO PLL OT_NTC_WARN PLLCOMP_SHORT PLL_LOCK SLOPE COMPENSATION EN_SS SLOPE SOFT-START DELAY AND LOGIC SS_DONE 3.47V SS SS TRACK 0.3V VREF_TRK ATRAK/ DTRK ATRK/DTRK 112µA ISEN1 VRAMP 1k PWM COMPARATOR SS M U X LP FILTER Gm1 FB COMP -48µA ZCD_PH1 8-BIT DAC ISEN1 ISEN1 R2 R1 1.6V (DEFAULT) CLOCK DCC VREF_CC UG1 Q PWM CONTROL S PH1 PROGRAMMABLE ADAPTIVE DEAD TIME PVCC LG1 Gm2 CMP_PD 1.1V VIMON IOUT CMP_OCAVG Page 7 of 72 OC_AVG VREF_ OCAVG   ÷8 2V (DEFAULT) PGND PGND RDT RBLANK DROP_PHASE2 PHASE_DROP ÷8 3 bits [2:0] D6h BOOT1 ISEN1 DUPLICATE FOR EACH PHASE IMON IBIAS 112µA 2µA FAULT 3 bits [2:0] D5h 80µA OC_NEG_PH1 VFB 8 bits [7:0] 21h 105µA OC1_PH1 VREF_TRK VREF_DAC (1.6V DEFAULT) ISEN1N ISEN1 OC2_PH1 VREF_2.5V ISEN1P CSA ISEN1 (PH1) PHASE DROP CONTROL 17µA ISEN2 (PH2) EN_DE EN_PHASE_DROP DE MODE AND PHASE DROP MODE SELECTION DE/PHDRP N.C. SGND FIGURE 3. BLOCK DIAGRAM PAD ISL78229 Typical Application - 2-Phase Synchronous Boost RVCC 10  SGND VIN VIN EN_IC EN CPLL1 6.8nF Q2 LG1 ISEN1N RBIAS1B TRACK SS CPLL2 1nF RFS RSLOPE RBLANK RDT RBIAS1A RSET1B DBOOT2 PVCC_BT BOOT2 RSET1A COUT CBOOT2 0.47µF UG2 Q3 L2 PH2 Q4 LG2 ISEN2N SLOPE ISEN2P RBLANK IMON RDT VCC ATRK/DTRK HIC/LATCH VCC DE/PHDRP RSEN2 1m PLLCOMP FSYNC VIN CIN CISEN1 220pF ISEN1P RPLL 3.3k  RSEN1 1m  CLKOUT CSS L1 ADDR1 ISL78229 CLOCK_OUT COUT Q1 PH1 PGOOD RPG CBOOT1 0.47µF UG1 SDA SCL SALERT VCC VOUT BOOT1 ADDR2 POWER-GOOD RPVCCBT 5.1 PVCC_BT DBOOT1 NTC PMBus CPVCC 10µF PGND RNTC RP_NTC PVCC PVCC VCC CVCC 1µF RBIAS2B CIN RBIAS2A CISEN2 220pF RSET2B RSET2A CIMON RIMON FB CCP1 RCP COMP RFB2 RFB1 CCP2 ATRK/DTRK: = VCC to track analog signal = GND to track digital signal Q1, Q2, Q3, Q4: 2 BUK9Y6R0-60E in parallel HIC/LATCH: = VCC for HICCUP mode = GND for LATCHOFF mode DE/PHDRP: = VCC for DE mode = FLOAT for DE and Phase-Drop mode = GND for CCM mode FIGURE 4. TYPICAL APPLICATION - 2-PHASE SYNCHRONOUS BOOST FN8656 Rev.6.00 Jul 13, 2018 Page 8 of 72 ISL78229 Absolute Maximum Ratings Thermal Information VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3V to +60V PH1, PH2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3V to +60V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-10V(1.15V, Phase 2 is added back immediately to support the increased load demand. Because the IMON pin normally has large RC filter and VIMON is average current signal, this mechanism has a slow response and is intended for slow load transients. The second mechanism is intended to handle the case when load increases quickly. If the quick load increase triggers OC1 (ISENx >80µA) in either of the 2 phases, Phase 2 is added back immediately. After Phase 2 is added, the phase dropping function is disabled for 1.5ms. After this 1.5ms expires, the phase dropping circuit is activated again and Phase 2 can be dropped automatically as usual. DIODE EMULATION AT LIGHT LOAD CONDITION When the Diode Emulation mode (DE) is selected to be enabled (Mode 1 and 2 in Table 2), the ISL78229 has cycle-by-cycle diode emulation operation at light load achieving Discontinuous Conduction Mode (DCM) operation. With DE mode operation, negative current is prevented and the conduction loss is reduced, so high efficiency can be achieved at light load conditions. Diode emulation occurs during t5-t8 (on Figure 67 on page 30), regardless of the DE/PHDRP operating modes (Table 2). PULSE SKIPPING AT DEEP LIGHT-LOAD CONDITION If the converter enters DE mode and the load is still reducing, eventually pulse skipping occurs to increase the deep light-load efficiency. Either Phase 1 or Phase 2, or both, are pulse skipping at these deep light-load conditions. When load current drops and VIMON falls below 1.1V, Phase 2 is disabled. For better transient response during phase dropping, the ISL78229 gradually reduces the duty cycle of the phase from steady state to zero, typically within 8 to 10 switching cycles. This gradual dropping scheme helps smooth the change of the PWM signal and stabilize the system when phase dropping happens. Fault Protections/Indications From Equations 13 and 14, the phase dropping current threshold level for the total 2-phase boost input current can be calculated by Equation 16. Table 3 on page 41 summarizes the types of faults and warnings accessible from PMBus and the three related registers to monitor the fault status, enable/disable fault protecting reactions and program the desired type of fault responses (Hiccup or Latch-off). Refer to section “PMBus User Guide” starting on page 40 for more details of the commands related to fault management. –6 1.1  ------------------ – 17  10   8  R SET R  IMON I INphDRP = ----------------------------------------------------------------------------------  A  R SEN (EQ. 16) The phase adding is decided by two mechanisms listed as follows. Phase 2 is added immediately if either of the two following conditions are met. 1. VIMON >1.15V, the IMON pin voltage is higher than phase adding threshold 1.15V. The phase adding current threshold level for the total 2-phase boost input current can be calculated by Equation 17. (EQ. 17) 2. ISENx >80µA (OC1), individual phase current triggers OC1. FN8656 Rev.6.00 Jul 13, 2018 FAULTS/WARNINGS MANAGEABLE VIA PMBUS Fault Flag Register FAULT_STATUS (D0h) and SALERT Signal Phase Adding –6 1.15  ------------------ – 17  10   8  R SET R  IMON I INphADD = ----------------------------------------------------------------------------------  A  R SEN The ISL78229 is implemented with comprehensive fault protections, the majority of which can be monitored and programmed using PMBus. When any of the faults in Table 3 on page 41 occurs, the corresponding bit of FAULT_STATUS register (“FAULT_STATUS (D0h)” on page 58) is set to 1 and the SALERT pin is pulled low, regardless if that type of fault is masked by the corresponding bit in the FAULT_MASK register. The bits of the FAULT_STATUS register status are kept unchanged as long as PVCC/VCC and EN are HIGH. Even when the fault conditions are gone, the bit = 1 status is not automatically cleared/reset to 0 by the device itself. Each individual bit or multiple bits can be cleared/reset to 0, but only by a Write command, a CLEAR_FAULTS command from the PMBus, or EN/POR recycling. Page 34 of 72 ISL78229 Refer to “FAULT_STATUS (D0h)” on page 58 for more details of this PMBus command, and Table 3 on page 41 for a fault-related registers summary. SALERT Pin The SALERT pin is an open-drain logic output and should be connected to VCC through a typical 10k resistor. When any bit of FAULT_STATUS register is set to 1, the SALERT pin is pulled low, regardless if that type of fault is masked by the corresponding bit in the FAULT_MASK register. The host is interrupted by SALERT signal and then inquires the ISL78229 using PMBus for information about the faults/warnings recorded in the FAULT_STATUS register, or any others to diagnose. After the ISL78229 is enabled, during the part initializing time t1 - t4 (refer to Figure 67 on page 30) before soft-start, the SALERT pin is kept pulled low. If no faults (listed in Table 4 on page 41) occur during t1 - t4, the SALERT pin open-drain transistor is open at t4 when soft-start begins and the pin voltage is pulled high by the external pull-up circuits. If any fault in Table 4 on page 41 occurs after the beginning of soft-start, the corresponding bit of the FAULT_STATUS register is set to 1 and the SALERT pin is pulled low. The SALERT pin can be released to be pulled HIGH only when all the FAULT_STATUS register bits are 0. Fault Mask Register FAULT_MASK (D1h) “SET_FAULT_RESPONSE (D2h)” on page 60 and Table 3 on page 41). • When bit = 1, the fault protection response is Hiccup mode • When bit = 0, the fault protection response is Latch-off mode The default bit values are determined by the HIC/LATCH pin configuration as listed below. Each bit value can be changed using PMBus to set the respective bit of the fault response register (SET_FAULT_RESPONSE) at default: • When the HIC/LATCH pin is pulled high (VCC), the fault response is Hiccup mode. • When the HIC/LATCH pin is pulled low (GND), the fault response is Latch-off mode. In Hiccup mode, the device stops switching when a fault condition is detected, and restarts from soft-start after 500ms (typical). This operation is repeated until fault conditions are completely removed. In Latch-off mode, the device stops switching when a fault condition is detected, and PWM switching is kept off even after fault conditions are removed. In Latch-off status, the internal LDO is alive to keep PVCC, and PMBus interface is available for the user to monitor the type of fault triggered or other parameters. Toggle the EN pin or cycle VCC/PVCC below the POR threshold to restart the system. When any of the faults in Table 4 on page 41 are detected, the device responds with either protecting actions (Hiccup or Latch-off) or by ignoring this fault depending on the corresponding bit setting of the FAULT_MASK register (“FAULT_MASK (D1h)” on page 59). Refer to the PMBus command “SET_FAULT_RESPONSE (D2h)” on page 60 for details and Table 3 on page 41 for a fault-related registers summary. Each bit of this register controls one specific fault condition to be ignored or not (refer to the list in Table 4 on page 41). The bit values are defined as follows: As shown in Figure 3 on page 7, the ISL78229 monitors the VIN pin voltage divided by 48 (VIN/48) as the input voltage information. This fault detection is active at the beginning of soft-start (t5 as shown in Figure 67 on page 30). • Bit = 1 means to ignore, no protection action taken for the triggered fault, and the ISL78229 keeps its normal PWM switching and operations. • Bit = 0 means to respond with protecting action to enter either Hiccup or Latch-off as the fault response as described in “Fault Response Register SET_FAULT_RESPONSE (D2h)”. The register FAULT_MASK has a default setting and can be programmed using the PMBus command “FAULT_MASK (D1h)” on page 59 to set a specific fault’s protection response to be ignored or not. At default, the VOUT_UV fault is ignored with Bit [6] set to 1 as default. Refer to PMBus command “FAULT_MASK (D1h)” on page 59 for details and Table 3 on page 41 for a fault related registers summary. Fault Response Register SET_FAULT_RESPONSE (D2h) The fault response for each type of fault protection (listed in Table 4 on page 41) can be programmed to be either Hiccup or Latch-off by setting the corresponding bit of the register SET_FAULT_RESPONSE (refer to PMBus command INPUT OVERVOLTAGE FAULT The VIN_OV comparator compares VIN/48 to 1.21V reference to detect if VIN_OV fault is triggered. Equivalently, when VIN >58V (for 5µs), the VIN_OV fault event is triggered. The PGOOD pin is pulled low and the corresponding bit (VIN_OV, Bit [2]) in the FAULT_STATUS register (“Fault Flag Register FAULT_STATUS (D0h) and SALERT Signal” on page 34 and Table 3 on page 41) is set to 1 and the SALERT pin is pulled low. At the same time the VIN_OV fault condition is triggered, because the VIN_OV fault protection response is enabled by default as the VOIN_OV bit (Bit [2]) is set 0 by default in the FAULT_MASK register (refer to “Fault Mask Register FAULT_MASK (D1h)” on page 35 and Table 3 on page 41), the ISL78229 responds with fault protection actions to shut down the PWM switching and enters either Hiccup or Latch-off mode as described in “Fault Response Register SET_FAULT_RESPONSE (D2h)” on page 35 and Table 3 on page 41. The VIN_OV fault protection can be disabled by setting the VIN_OV bit (Bit [2]) in “Fault Mask Register FAULT_MASK (D1h)” on page 35 to 1 via PMBus. If disabled, there are no fault protection actions when VIN_OV fault is triggered, and the ISL78229 keeps PWM switching and normal operation. Under the selection of VIN_OV fault protection activated with Hiccup response, when the output voltage falls down to be lower FN8656 Rev.6.00 Jul 13, 2018 Page 35 of 72 ISL78229 than the VIN_OV threshold 58V, the device returns to normal switching through Hiccup soft-start. PGOOD is released to be pulled HIGH after a 0.5ms delay. As described in “Fault Flag Register FAULT_STATUS (D0h) and SALERT Signal” on page 34, the bit = 1 status in the FAULT_STATUS register is not automatically cleared/reset to 0 by the device itself and the SALERT pin is kept low. The bits in the FAULT_STATUS register can only be cleared to 0 by a Write command, or CLEAR_FAULTS command via PMBus, or EN/POR recycling. When all the bits in the FAULT_STATUS register are 0, the SALERT pin is released to be pulled HIGH. OUTPUT UNDERVOLTAGE FAULT The ISL78229 monitors the FB pin voltage to detect if an output undervoltage fault (VOUT_UV) occurs. If the FB pin voltage is lower than 80% (default) of the voltage regulation reference VREF_DAC, the VOUT_UV comparator is triggered to indicate VOUT_UV fault and the PGOOD pin is pulled low. Also, corresponding bit (VOUT_UV, Bit [6]) in the FAULT_STATUS register (“Fault Flag Register FAULT_STATUS (D0h) and SALERT Signal” on page 34 and Table 3 on page 41) is set to 1 and the SALERT pin is pulled low. When the output voltage rises back to be above the VOUT_UV threshold 80% VREF_DAC plus 4% hysteresis, PGOOD is released to be pulled HIGH after a 0.5ms delay. However, as described in the “Fault Flag Register FAULT_STATUS (D0h) and SALERT Signal” on page 34, the bit = 1 status in the FAULT_STATUS register is not automatically cleared/reset to 0 by the device itself and the SALERT pin is kept low. The bits in the FAULT_STATUS register can only be cleared to 0 by a Write command, a CLEAR_FAULTS command from PMBus, or EN/POR recycling. When all the bits in the FAULT_STATUS register are 0, the SALERT pin is released to be pulled HIGH. The VOUT_UV fault protection response is disabled (ignored) by default as the VOUT_UV bit (Bit [6]) is set to 1 by default in the FAULT_MASK register (refer to “Fault Mask Register FAULT_MASK (D1h)” on page 35 and Table 3 on page 41), which means the ISL78229 keeps the PWM switching and normal operation when VOUT_UV fault occurs. VOUT_UV fault protection can be enabled by setting set this VOUT_UV bit (Bit [6]) to 0 in the “Fault Mask Register FAULT_MASK (D1h)” on page 35. If enabled, the fault response can be programmed to be either Hiccup or Latch-off as described in “Fault Response Register SET_FAULT_RESPONSE (D2h)” on page 35 and Table 3 on page 41. The VOUT_UV threshold values can be set to eight options based on percentage of the reference VREF_DAC via PMBus command “VOUT_UV_FAULT_LIMIT (D4h)” on page 62. OUTPUT OVERVOLTAGE FAULT The ISL78229 monitors the FB pin voltage to detect if an output overvoltage fault (VOUT_OV) occurs. This fault detection is active at the beginning of soft-start (t5 as shown in the Figure 67 on page 30). If the FB pin voltage is higher than 120% (default) of the voltage regulation reference VREF_DAC, the VOUT_OV comparator is triggered to indicate a VOUT_OV fault, and the PGOOD pin is pulled low. The corresponding bit (VOUT_OV, Bit [7]) in the FAULT_STATUS register (“Fault Flag Register FAULT_STATUS (D0h) FN8656 Rev.6.00 Jul 13, 2018 and SALERT Signal” on page 34 and Table 3 on page 41) is set to 1 and the SALERT pin is pulled low. At the same time, when a VOUT_OV fault condition is triggered, because the VOUT_OV fault protection response is enabled by default as the VOUT_OV bit (Bit [7]) is set 0 by default in the FAULT_MASK register (refer to “Fault Mask Register FAULT_MASK (D1h)” on page 35 and Table 3 on page 41), the ISL78229 responds with fault protection actions to shut down the PWM switching and enters either Hiccup or Latch-off mode as described in “Fault Response Register SET_FAULT_RESPONSE (D2h)” on page 35 and Table 3 on page 41. The VOUT_OV fault protection can be disabled by setting the VOUT_OV bit (Bit [7]) in “Fault Mask Register FAULT_MASK (D1h)” on page 35 to 1 via PMBus. If disabled, there are no fault protection actions when VOUT_OV fault is triggered, and the ISL78229 keeps PWM switching and normal operation. Under the selection of VOUT_OV fault protection activated with Hiccup response, when the output voltage falls down to be lower than the VOUT_OV threshold 120% VREF_DAC minus 4% hysteresis, the device returns to normal switching through Hiccup soft-start. The PGOOD pin is released to be pulled HIGH after 0.5ms delay. However, as described in the “Fault Flag Register FAULT_STATUS (D0h) and SALERT Signal” on page 34, the bit = 1 status in the FAULT_STATUS register is not automatically cleared/reset to 0 by the device itself and the SALERT pin is kept low. The bits in the FAULT_STATUS register can only be cleared to 0 by a Write command, a CLEAR_FAULTS command from PMBus, or EN/POR recycling. When all the bits in the FAULT_STATUS register are 0, the SALERT pin is released to be pulled HIGH. The VOUT_OV threshold values can be set to eight options based on percentage of the reference VREF_DAC using PMBus command “VOUT_OV_FAULT_LIMIT (D3h)” on page 61. OVERCURRENT LIMITING AND FAULT PROTECTION The ISL78229 has multiple levels of overcurrent protection. Each phase is protected from an overcurrent condition by limiting its peak current and the combined total current is protected on an average basis. Also, each phase is implemented with cycle-by-cycle negative current limiting (OC_NEG_TH = -48µA). Peak Current Cycle-by-Cycle Limiting (OC1) Each individual phase’s inductor peak current is protected with cycle-by-cycle peak current limiting (OC1) without triggering Hiccup or Latch-off shutdown of the IC. The controller continuously compares the CSA output current sense signal ISENx (calculated by Equation 11 on page 32) to an overcurrent limiting threshold (OC1_TH = 80µA) in every cycle. When ISENx reaches 80µA, the respective phase’s LGx is turned off to stop inductor current further ramping up. In this way, peak current cycle-by-cycle limiting is achieved. The equivalent cycle-by-cycle peak inductor current limiting for OC1 can be calculated using Equation 18: I OC1x = 80  10 – 6 R SETx  -------------------  A  R SENx (EQ. 18) Page 36 of 72 ISL78229 Negative Current Cycle-by-Cycle Limiting (OC_NEG) Each individual phase’s inductor current is protected with cycle-by-cycle negative current limiting (OC_NEG) without triggering Hiccup or Latch-off shutdown of the IC. The controller continuously compares the CSA output current sense signal ISENx (calculated by Equation 11 on page 32) to a negative current limiting threshold (OC_NEG_TH = -48µA) in every cycle. When ISENx falls below -48µA, the respective phase’s UGx is turned off to stop the inductor current further ramping down. In this way, negative current cycle-by-cycle limiting is achieved. The equivalent negative inductor current limiting level can be calculated using Equation 19: I OCNEGx = – 48  10 – 6 R SETx  -------------------  A  R SENx (EQ. 19) Peak Overcurrent Fault (OC2_PEAK) If either of the two individual phase’s current sense signal ISENx (calculated by Equation 11 on page 32) reaches 105µA (OC2_TH = 105µA) for three consecutive switching cycles, the Peak Overcurrent fault (OC2_PEAK) event is triggered. This fault protection protects the device by shutdown (Hiccup or Latch-off) from a worst case condition where OC1 cannot limit the inductor peak current. This fault detection is active at the beginning of soft-start (t5 as shown in the Figure 67 on page 30). When an OC2_PEAK fault event is triggered, the corresponding bit (OC2_PEAK, Bit [5]) in the FAULT_STATUS register (“Fault Flag Register FAULT_STATUS (D0h) and SALERT Signal” on page 34 and Table 3 on page 41) is set to 1 and the SALERT pin is pulled low. At the same time, when an OC2_PEAK fault event is triggered, because the OC2_PEAK fault protection response is enabled by default as the OC2_PEAK bit (Bit [5]) is set 0 by default in the FAULT_MASK register (refer to “Fault Mask Register FAULT_MASK (D1h)” on page 35 and Table 3 on page 41), the ISL78229 responds with fault protection actions to shut down the PWM switching and enters either Hiccup or Latch-off mode as described in “Fault Response Register SET_FAULT_RESPONSE (D2h)” on page 35 and Table 3 on page 41. The OC2_PEAK fault protection can be disabled by setting the OC2_PEAK bit (Bit [5]) in “Fault Mask Register FAULT_MASK (D1h)” on page 35 to 1 via PMBus. If disabled, there are no fault protection actions when OC2_PEAK fault is triggered, and the ISL78229 keeps PWM switching and normal operation. Under the selection of OC2_PEAK fault protection activated with Hiccup response, when both phases’ peak current sense signal ISENx no longer trip the OC2_PEAK thresholds (105µA), the device returns to normal switching and regulation through Hiccup soft-start. However, as described in the “Fault Flag Register FAULT_STATUS (D0h) and SALERT Signal” on page 34, the bit = 1 status in the FAULT_STATUS register is not automatically cleared/reset to 0 by the device itself and the SALERT pin is kept low. The bits in the FAULT_STATUS register can only be cleared to 0 by a Write command, a CLEAR_FAULTS command using PMBus, or EN/POR recycling. When all the bits in the FAULT_STATUS register are 0, the SALERT pin is released to be pulled HIGH. FN8656 Rev.6.00 Jul 13, 2018 The equivalent inductor peak current threshold for the OC2_PEAK fault protection can be calculated by Equation 20: I OC2x = 105  10 – 6 R SETx  -------------------  A  R SENx (EQ. 20) Constant Current Control (CC) A dedicated constant average Current Control (CC) loop is implemented in the ISL78229 to control the input current to be constant at overload conditions, which means constant input power limiting under a constant input voltage. As shown in Figure 3 on page 7, the VIMON represents the average input current and is sent to the error amplifier Gm2 input to be compared with the internal CC reference VREF_CC (which is 1.6V as default and can be programmed to different values using the PMBus command “CC_LIMIT (D5h)” on page 63). The Gm2 output drives the COMP voltage through a diode DCC. Thus, the COMP voltage can be controlled by either Gm1 output or Gm2 output through DCC. At normal operation without overloading, VIMON is lower than the VREF_CC (1.6V at default). Therefore, Gm2 output is HIGH and DCC is blocked and not forward conducting. The COMP voltage is now controlled by the voltage loop error amplifier Gm1’s output to have output voltage regulated. In the input average current overloading case, when VIMON reaches VREF_CC (1.6V at default), the Gm2 output falls and DCC is forward conducting, and the Gm2 output overrides the Gm1 output to drive COMP. In this way, the CC loop overrides the voltage loop, meaning VIMON is controlled to be constant achieving average constant current operation. Under certain input voltages, the input CC makes input power constant for the boost converter. Compared to peak current limiting schemes, the average constant current control is more accurate to control the average current to be constant, which is beneficial for the user to accurately control the maximum average power for the converter to handle. The CC current threshold should be set lower than the OC1 peak current threshold with margin. Generally, the OC1 peak current threshold (per phase) is set 1.5 to 2 times higher than the CC current threshold (referred to as per-phase average current). This matches with the physics of the power devices that normally have higher transient peak current rating and lower average current ratings. The OC1 provides protection against the transient peak current, which can be higher than the power devices can handle. The CC controls the average current with slower response, but with much more accurate control of the maximum power the system has to handle at overloading conditions. 1. When fast changing overloading occurs, because VIMON has sensing delay of RIMON*CIMON, CC does not trip at the initial transient load current until it reaches the CC reference 1.6V (default). OC1 is triggered first to limit the inductor peak current cycle-by-cycle. 2. After the delay of RIMON*CIMON, when VIMON reaches the CC reference 1.6V (default), the CC control starts to work and limit duty cycles to reduce the inductor current and keep the sum of the two phases’ inductor currents being constant. The time constant of the RIMON*CIMON is typically on the order of 10 times slower than the voltage loop bandwidth so that the two loops do not interfere with each other. Page 37 of 72 ISL78229 The CC threshold values can be set to eight options using the PMBus command “CC_LIMIT (D5h)” on page 63, which ranges from 1.25V to 1.6V with a default setting of 1.6V. Average Overcurrent Fault (OC_AVG) The ISL78229 monitors the IMON pin voltage (which represents the average current signal) to detect if an Average Overcurrent (OC_AVG) fault occurs. As shown in Figure 3 on page 7, the comparator CMP_OCAVG compares VIMON to 2V (as default) threshold. This fault detection is active at the beginning of soft-start (t5 as shown in Figure 67 on page 30). When VIMON is higher than 2V, the OC_AVG fault is triggered. The corresponding bit (OC_AVG, Bit [4]) in the FAULT_STATUS register (“Fault Flag Register FAULT_STATUS (D0h) and SALERT Signal” on page 34 and Table 3 on page 41) is set to 1 and the SALERT pin is pulled low. The fault response at default is either Hiccup or Latch-off (as described in “Fault Response Register SET_FAULT_RESPONSE (D2h)” on page 35). At the same time an OC_AVG fault condition is triggered, because the OC_AVG fault protection response is enabled by default as the OC_AVG bit (Bit [4]) is set 0 by default in the FAULT_MASK register (refer to “Fault Mask Register FAULT_MASK (D1h)” on page 35 and Table 3 on page 41), the ISL78229 responds with fault protection actions to shut down the PWM switching and enters either Hiccup or Latch-off mode as described in “Fault Response Register SET_FAULT_RESPONSE (D2h)” on page 35 and Table 3 on page 41. The OC_AVG fault protection can be disabled by setting the OC_AVG bit (Bit [4]) in “Fault Mask Register FAULT_MASK (D1h)” on page 35 to 1 using PMBus. If disabled, there are no fault protection actions when OC_AVG fault is triggered and the device keeps PWM switching and normal operation. Under the selection of OC_AVG fault protection activated with Hiccup response, when the IMON voltage falls below the 2V (default) threshold, the device returns to normal switching through Hiccup soft-start. As described in the “Fault Flag Register FAULT_STATUS (D0h) and SALERT Signal” on page 34, the bit = 1 status in the FAULT_STATUS register is not automatically cleared/reset to 0 by the device itself and the SALERT pin is kept low. The bits in the FAULT_STATUS register can only be cleared to 0 by a Write command, or CLEAR_FAULTS command via PMBus, or EN/POR recycling. When all the bits in the FAULT_STATUS register are 0, the SALERT pin is released to be pulled HIGH. The OC_AVG fault threshold can be set to eight options using the PMBus command “OC_AVG_FAULT_LIMIT (D6h)” on page 64. Because the Constant Current Loop uses the same IMON signal and has a lower threshold (1.6V default), which is lower than the OC_AVG threshold (2V default), the OC_AVG can be tripped. The CC loop limits the IMON signal around 1.6V and below 2V. Generally, OC_AVG functions as worst-case backup protection. EXTERNAL TEMPERATURE MONITORING AND PROTECTION (NTC PIN) The NTC pin allows temperature monitoring with a Negative Temperature Coefficient (NTC) thermistor connected from this pin to ground. An accurate 20µA current sourcing out of the NTC pin develops a voltage across the NTC thermistor, which can be converted to temperature in degrees Celsius due to the NTC thermistor characteristic. A precision resistor (100k, 0.1% for example) can be put in parallel with the NTC thermistor to linearize the voltage versus temperature ratio in certain ranges. As an example, Figure 71 shows the curve of the NTC pin voltage versus the temperature for a 100k resistor in parallel with an NTC thermistor NTCS0805E3474FXT on the NTC pin. The user can read the NTC pin voltage over PMBus and convert the voltage to temperature using the curve in the chart. In the board layout, the NTC resistor should be placed in the area that needs the temperature to be monitored. Typically the NTC is placed close to the power devices like MOSFETs to monitor the board temperature close to them. The voltage on the NTC pin is monitored for over-temperature warnings (OT_NTC_WARN) and over-temperature faults (OT_NTC_FAULT), both flagged by SALERT. The default threshold for OT warnings is 450mV and the default threshold for OT faults is 300mV. Both thresholds can be changed to different values using the PMBus commands “OT_NTC_WARN_LIMIT (51h)” on page 51 and “OT_NTC_FAULT_LIMIT (4Fh)” on page 50. If the NTC function is not used, the NTC pin should be connected to VCC. VNTC (V) CC loop is active at the beginning of soft-start. 2 1.9 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110120 13 014 0150 TEMPERATURE (°C) FIGURE 71. NTC VOLTAGE vs TEMPERATURE External Over-Temperature Warning (OT_NTC_WARN) If VNTC is lower than 450mV (default as determined by OT_NTC_WARN_LIMIT register), the OT_NTC_WARN warning event is triggered. The corresponding bit (OT_NTC_WARN, Bit [1]) in the FAULT_STATUS register (“Fault Flag Register FAULT_STATUS (D0h) and SALERT Signal” on page 34 and Table 3 on page 41) is set to 1 and the SALERT pin is pulled low to deliver a warning to the host. The ISL78229 continues switching and regulating normally. There is no fault protection response when an OT_NTC_WARN event is triggered. When the temperature drops and VNTC rises above 450mV (default), the OT_NTC_WARN is no longer tripped. However, as described in the “Fault Flag Register FAULT_STATUS (D0h) and FN8656 Rev.6.00 Jul 13, 2018 Page 38 of 72 ISL78229 The OT_NTC_WARN threshold OT_NTC_WARN_LIMIT values can be set to different values via PMBus command “OT_NTC_WARN_LIMIT (51h)” on page 51. This warning detection is active at the beginning of soft-start (t5 as shown in Figure 67 on page 30). External Over-Temperature Fault (OT_NTC_FAULT) If VNTC is lower than 300mV (default as determined by OT_NTC_FAULT_LIMIT register), the OT_NTC_FAULT fault event is triggered. The corresponding bit (OC_NTC_FAULT, Bit [3]) in the FAULT_STATUS register (“Fault Flag Register FAULT_STATUS (D0h) and SALERT Signal” on page 34 and Table 3 on page 41) is set to 1 and the SALERT pin is pulled low to deliver a warning to the host. When the OT_NTC_FAULT fault condition is triggered, because the OT_NTC_FAULT fault protection response is disabled by default as the OT_NTC_FAULT bit (Bit [3]) is set to 1 by default in the FAULT_MASK register (refer to “Fault Mask Register FAULT_MASK (D1h)” on page 35 and Table 3 on page 41), the ISL78229 does not respond with fault protection actions and continues switching and regulating normally. The OT_NTC_FAULT fault protection can be enabled by setting the OT_NTC_FAULT bit (Bit [3]) in “Fault Mask Register FAULT_MASK (D1h)” on page 35 to 0 via PMBus. If enabled, the ISL78229 responds with fault protection actions to shut down the PWM switching and enters either Hiccup or Latch-off mode as described in “Fault Response Register SET_FAULT_RESPONSE (D2h)” on page 35 and Table 3 on page 41. Under the selection of OT_NTC_FAULT fault protection activated with a Hiccup response, when the temperature drops and VNTC rises back to be above 300mV (default), the OT_NTC_FAULT is no longer tripped, and the device returns to normal switching through Hiccup soft-start. However, as described in the “Fault Flag Register FAULT_STATUS (D0h) and SALERT Signal” on page 34, the bit = 1 status in the FAULT_STATUS register is not automatically cleared/reset to 0 by the device itself and the SALERT pin is kept low. The bits in the FAULT_STATUS register can only be cleared to 0 by a Write command, a CLEAR_FAULTS command using PMBus, or EN/POR recycling. When all the bits in the FAULT_STATUS register are 0, the SALERT pin is released to be pulled HIGH. The OT_NTC_FAULT threshold values can be set to different values using the PMBus command “OT_NTC_FAULT_LIMIT (4Fh)” on page 50. This warning detection is active at the beginning of soft-start (t5 as shown in the Figure 67 on page 30). INTERNAL DIE OVER-TEMPERATURE PROTECTION The ISL78229 PWM is disabled if the junction temperature reaches +160°C (typical) while the internal LDO is alive to keep FN8656 Rev.6.00 Jul 13, 2018 PVCC/VCC biased (VCC connected to PVCC). A +15°C hysteresis ensures that the device restarts with soft-start when the junction temperature falls below +145°C (typical). Internal 5.2V LDO The ISL78229 has an internal LDO with an input at VIN and a fixed 5.2V/100mA output at PVCC. The internal LDO tolerates an input supply range of VIN up to 55V (60V absolute maximum). A 10µF, 10V or higher X7R type of ceramic capacitor is recommended between PVCC to GND. At low VIN operation when the internal LDO is saturated, the dropout voltage from the VIN pin to the PVCC pin is typically 0.3V under 80mA load at PVCC as shown in the “Electrical Specifications” table on page 9. This is one of the constraints to estimate the required minimum VIN voltage. The output of this LDO is mainly used as the bias supply for the gate drivers. With VCC connected to PVCC as in the typical application, PVCC also supplies other internal circuitry. To provide a quiet power rail to the internal analog circuitry, it is recommended to place an RC filter between PVCC and VCC. A minimum of 1µF ceramic capacitor from VCC to ground should be used for noise decoupling purpose. Because PVCC provides noisy drive current, a small resistor (10Ω or smaller) between the PVCC and VCC helps to prevent the noises interfering from PVCC to VCC. Figure 72 shows the internal LDO’s output voltage (PVCC) regulation versus its output current. The PVCC drops to 4.5V (typical) when the load is 195mA (typical) because of the LDO current limiting circuits. When the load current further increases, the voltage drops further and finally enters current foldback mode where the output current is clamped to 100mA (typical). At the worst case when LDO output is shorted to ground, the LDO output is clamped to 100mA. 5.5 5.0 4.5 4.0 V_PVCC (V) SALERT Signal” on page 34, the bit = 1 status in the FAULT_STATUS register is not automatically cleared/reset to 0 by the device itself and the SALERT pin is kept low. The bits in the FAULT_STATUS register can only be cleared to 0 by a Write command, a CLEAR_FAULTS command from PMBus, or EN/POR recycling. When all the bits in the FAULT_STATUS register are 0, the SALERT pin is released to be pulled HIGH. 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0.00 0.05 0.10 0.15 IOUT_PVCC (A) 0.20 0.25 FIGURE 72. INTERNAL LDO OUTPUT VOLTAGE vs LOAD Based on the junction to ambient thermal resistance RJA of the package, the maximum junction temperature should be kept below +125°C. However, the power losses at the LDO need to be considered, especially when the gate drivers are driving external MOSFETs with large gate charges. At high VIN, the LDO has significant power dissipation that may raise the junction temperature where the thermal shutdown occurs. With an external PNP transistor as shown in Figure 73 on page 40, the power dissipation of the internal LDO can be moved from the ISL78229 to the external transistor. Choose RS to be Page 39 of 72 ISL78229 68Ω so that the LDO delivers about 10mA when the external transistor begins to turn on. The external circuit increases the minimum input voltage to approximately 6.5V. VIN Monitor Operating Parameters Through PMBus A system controller can monitor several ISL78229 operating parameters through the PMBus interface including: • Input voltage (monitors the VIN Pin) RS • Output voltage (monitors the FB Pin) • Input current (monitors the IMON Pin) • External temperature (monitors the NTC Pin) VIN ISL78229 PVCC PVCC FIGURE 73. SUPPLEMENTING LDO CURRENT PMBus User Guide The ISL78229 is implemented with a PMBus digital interface for the user to monitor and change a few operating parameters, allowing smart control of the regulator. The Power Management Bus (PMBus) is an open-standard digital power management protocol. It uses SMBus as its physical communication layer and includes support for the SMBus Alert (SALERT). In much the same way as SMBus defines the general means to manage portable power, PMBus defines the means to manage power subsystems. PMBus and SMBus are I2C derived bus standards that are generally electrically compatible with I2C. They are more robust (Timeouts Force Bus Reset) and offer more features than I2C, like SMBALERT(SALERT) line for interrupts, Packet Error Checking (PEC), and Host Notify Protocol. The ISL78229 is compliant with the PMBus Power System Management Protocol Specification Part I and II version 1.2. These specification documents may be obtained from the website http://PMBus.org. These are required reading for complete understanding of the PMBus implementation. • Specification Part I – General Requirements Transport and Electrical Interface - Includes the general requirements, as well as defines the transport and electrical interface and timing requirements of hardwired signals. • Specification Part II – Command Language - Describes the operation of commands, data formats, and fault management, as well as defines the command language used with the PMBus. Monitor Faults and Configure Fault Responses When any of the 10 fault conditions in Table 4 on page 41 occur, the corresponding bit of the FAULT_STATUS register is set to 1 and the SALERT pin is pulled low, regardless whether that type of fault is masked by the FAULT_MASK register. The PMBus host controller is interrupted by monitoring the SALERT pin and responds as follows: • ISL78229 device pulls SALERT low. • PMBus Host detects that SALERT is low, then performs transmission with Alert Response Address to find which device is pulling SALERT low. • PMBus Host communicates with the device that is pulling SALERT low. The actions that the host performs next are up to the system designer. Each individual bit of the FAULT_STATUS register can only be cleared to 0 by writing to that register using PMBus, by a CLEAR_FAULTS command, or POR recycle. When all the bits of FAULT_STATUS register are reset to 0, the SALERT pin is released to be pulled HIGH. Table 4 on page 41 lists the 10 types of faults that can be accessed through PMBus to: • Monitor or reset/clear each individual bit of the FAULT_STATUS Register (D0h) for its corresponding fault's status. • Configure the FAULT_MASK Register (D1h) to ignore or respond to each individual fault's protection. • Configure the SET_FAULT_RESPONSE Register (D2h) to set each individual fault response to Hiccup or Latch-off. Refer to “PMBus Command Detail” starting on page 46 for details on each specific PMBus command. Set Operation/Fault Thresholds via PMBus A system controller can change the ISL78229 operating parameters through the PMBus interface. Some of the commands include, but are not limited to: • Enable or disable the PWM operation and regulation • Set output voltage • Set output voltage changing slew rate • Set output overvoltage thresholds • Set output undervoltage thresholds • Set input constant current control thresholds FN8656 Rev.6.00 Jul 13, 2018 Page 40 of 72 ISL78229 Accessible Timing for PMBus Registers Status When the part is in Latch-off status or Hiccup mode triggered by any fault in Table 4 on page 41, the internal LDO is still enabled and keeps PVCC/VCC HIGH. All the PMBus register values are accessible using PMBus, and the FAULT_STATUS register values are accessible for the host to diagnose the type of fault. All PMBus command registers are set to default values during the part initialization period during t2 - t3 in Figure 67 on page 30. All the PMBus registers (commands) are ready to be accessed after this part initialization period. After part start-up, as long as EN and PVCC/VCC is kept HIGH, all the PMBus registers values are accessible via the PMBus. Either EN low or PVCC/VCC falling below POR disables the ISL78229. All the registers are reset and are not accessible from PMBus. TABLE 3. REGISTERS TO MONITOR FAULT STATUS AND CONFIGURE FAULT RESPONSE COMMAND CODE REGISTER NAME FORMAT ACCESS DEFAULT VALUE DESCRIPTIONS REFER TO PAGE D0h FAULT_STATUS Bit Field R/W 0: No fault 1: Fault occurred See Table 4 Page 58 D1h FAULT_MASK Bit Field R/W 0: Hiccup or Latch-off fault response 1: Ignore fault with no protection response See Table 4 Page 59 D2h SET_FAULT_RESPONSE Bit Field R/W 0: Latch-off 1: Hiccup See Table 4 Page 60 TABLE 4. FAULT NAMES LIST FOR THE REGISTERS (WITH DEFAULT VALUES) IN Table 3 D2h DEFAULT VALUE SET BY HIC/LATCH PIN HIC/LATCH = GND: BITS [9:0] = 00000000 HIC/LATCH = VCC: BITS [9:0] = 11111111 BIT NUMBER D0h DEFAULT VALUE D1h DEFAULT VALUE CML 0 0 1 Set by the HIC/LATCH pin Communications warning (for unsupported command, PEC error) OT_NTC_WARN 1 0 0 Set by the HIC/LATCH pin External over-temperature warning (NTC_PIN58V) OT_NTC_FAULT 3 0 1 Set by the HIC/LATCH pin External over-temperature fault (NTC_PIN 2V) OC2_PEAK 5 0 0 Set by the HIC/LATCH pin Peak overcurrent fault (ISENx >105µA) VOUT_UV 6 0 1 Set by the HIC/LATCH pin Output undervoltage fault (FB_PIN 120% VREF_DAC as default, threshold programmable) PLLCOMP_SHORT 8 0 0 Set by the HIC/LATCH pin PLLCOMP PIN shorted to high potential voltages (PLLCOMP_PIN >1.7V) PLL_LOCK 9 0 0 Set by the HIC/LATCH pin PLL fault due to reaching minimum frequency (Detect the minimum frequency of 37kHz as typical) FAULT NAME FN8656 Rev.6.00 Jul 13, 2018 RELATED FAULT TO BE MONITORED/CONTROLLED Page 41 of 72 ISL78229 Device Identification Address and Read/Write Write/Read the 16Lu Data as the 8-Bit DAC Input The ISL78229 serves as a slave device on the PMBus. The 7-bit physical slave address can be set by the ADDR1 and ADDR2 pin configurations to have four address options. Table 5 defines the four available 7-bit addresses for the ISL78229 where Bits [7:3] are fixed and Bits [2:1] are determined by the ADDR1 and ADDR2 pin configurations. Bit [0] is a R/W bit to define the command to perform Read (Bit = 1) or Write (Bit = 0). TABLE 5. SLAVE ADDRESS SET BY THE ADDR1 AND ADDR2 PIN CONFIGURATIONS ADDR1 R/W BIT BIT 0 DEVICE IDENTIFICATION -SLAVE ADDRESS BITS 7-1 ADDR1/ADDR2 SETTING ADDR2 BIT FIELD 7 6 5 4 3 2 1 0 GND GND 1 0 0 1 1 0 0 Write: 0 Read: 1 GND VCC 1 0 0 1 1 1 0 Write: 0 Read: 1 VCC GND 1 0 0 1 1 0 1 Write: 0 Read: 1 VCC VCC 1 0 0 1 1 1 1 Write: 0 Read: 1 PMBus Data Formats Used in ISL78229 The 16Lu data format is used in the command “VOUT_COMMAND (21h)” on page 48 to set or read the 8-bit DAC input binary unsigned integer data which changes the DAC output voltage. The DAC output voltage is VREF_DAC, which is the reference to the output voltage regulation. In this command, the 8-bit [7:0] unsigned binary integer value are used and equal to the 8-bit DAC output binary integer value. The DAC has 8mV for 1 LSB. So the 16Lu data can set VREF_DAC voltage range of 0V to 2.04V (8mV*(28-1)). Use Equation 22 to convert the 16Lu data written/read by the VOUT_COMMAND to DAC output voltage, where COMMAND is the 8-bit [7:0] unsigned binary integer value in the command: V DACOUT = 0.008  COMMAND = V REFDAC Write/Read the 16Lu Data to Set NTC Threshold The 16Lu data format is used in command “OT_NTC_FAULT_LIMIT (4Fh)” on page 50 and “OT_NTC_WARN_LIMIT (51h)” on page 51 to set the OT_NTC_WARN and OT_NTC_FAULT thresholds. The 10-bit [9:0] unsigned binary integer values are used and the 1 LSB represents 2mV. Use Equation 23 to convert the 16Lu data in the OT_NTC_FAULT_LIMIT and OT_NTC_WARN_LIMIT commands to the voltage thresholds for the NTC pin, where COMMAND is the 10-bit [9:0] unsigned binary integer value in the command: V OTNTC = 0.002  COMMAND The data formats used in the ISL78229 are listed below. 16-BIT LINEAR UNSIGNED (16LU) 16-bit Linear Unsigned (16Lu) data format is a two byte (16-bit) unsigned binary integer. For the ISL78229, the 16Lu data format performs the following actions: (EQ. 22) (EQ. 23) BIT FIELD (BIT) The Bit Field is explained in “PMBus Command Detail” starting on page 46. Read the 16Lu Data to Report the 10-Bit ADC Input Voltage CUSTOM (CUS) The 16Lu data format is used in some commands to report the binary unsigned integer data at the 10-bit ADC output, where Bits [15:10] are not used. Bits [9:0] are used as equals to the 10-bit ADC output unsigned binary integer value. The input of the ADC is alternatively connected to voltages of NTC, FB, VIN/48, and IMON pins for monitoring. The Custom data format is explained in “PMBus Command Detail” starting on page 46. A combination of Bit Field and integer are common types of Custom data formats. The ADC has 2mV for 1 LSB, so the 16Lu data can report voltage ranges of 0V to 2.046V (2mV*(210-1)). Equation 21 can be used to convert the 16Lu data reported by the commands to ADC input voltage, where COMMAND is the 10-bit [9:0] unsigned binary integer value: V ADCIN = 0.002  COMMAND (EQ. 21) The 10-bit ADC accuracy from output to input has typical tolerances of -15mV to +25mV over the ADC input range of 0V to 2.046V. FN8656 Rev.6.00 Jul 13, 2018 Page 42 of 72 ISL78229 PMBus Command Summary Table 6 lists all the command sets available for the ISL78229. Refer to “PMBus Command Detail” starting on page 46 for details about each specific PMBus command. TABLE 6. PMBus COMMAND SUMMARY COMMAND CODE COMMAND NAME ACCESS NUMBER OF DATA DATA BYTES FORMAT DEFAULT SETTING REFER TO PAGE DESCRIPTIONS 01h OPERATION Read/Write Byte 1 BIT 80h Enable/disable 03h CLEAR_FAULTS Send Byte 0 N/A N/A Clears any fault bits in the Fault_Status register that page 46 have been set 10h WRITE_PROTECT Read/Write Byte 1 BIT 00h Protects against accidental changes 19h CAPABILITY Read Byte 1 BIT B0h page 47 Provides the way for a host system to determine some key capabilities of the ISL78229 as a PMBus device 21h VOUT_COMMAND Read/Write Word 2 16Lu 00C8h Sets the nominal reference voltage for the VOUT set-point, VREF_DAC = 1.6V as default page 48 27h VOUT_TRANSITION_RATE Read/Write Word 2 BIT 0004h Sets the VOUT transition rate during VOUT_COMMAND commands to change VOUT page 49 4Fh OT_NTC_FAULT_LIMIT Read/Write Word 2 16Lu 0096h Sets the over-temperature fault limit, NTC_PIN 1.7V) 9 PLL_LOCK 0 PLL fault due to reaching the minimum frequency (detects the minimum frequency of 37kHz as typical) 15:10 FN8656 Rev.6.00 Jul 13, 2018 Not used 000000 Not used Page 58 of 72 ISL78229 FAULT_MASK (D1h) Definition: Renesas defined register. Sets any specific fault protection to be masked (ignored) or not. Each bit controls one specific fault condition (listed in the table below) to be ignored or not. With any bit’s value setting to 1, the corresponding fault is masked (ignored), which means there is no fault protecting action taken by the device when that fault is triggered, and the ISL78229 keeps its normal PWM switching and operations. The bit values meanings are defined as follows: • Bit = 1 means to ignore, no action taken as fault response. • Bit = 0 means to respond with protecting action, with part enter either hiccup or latch-off as fault response as described in the “Fault Response Register SET_FAULT_RESPONSE (D2h)” on page 35. Bits [9:2] control total of eight fault conditions. Bits [15:10] and Bits [1:0] are not used. At default, the VOUT_UV fault is ignored with Bit [6] setting to 1 as default. Also, refer to Table 3 on page 41 for fault related registers summary. Data Length in Bytes: 2 Data Format: Bit Field Type: R/W Protectable: Yes Default Value: 0049h Units: N/A COMMAND FAULT_MASK (D1h) Format Bit Field Bit Position 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0 0 1 0 0 1 Function Default Value BIT NUMBER See following table 0 0 0 FAULT NAME 0 0 0 0 DEFAULT VALUE 0 0 1 MEANING 0 N/A 1 Reserved 1 N/A 0 Reserved 2 VIN_OV 0 Ignore input overvoltage fault (VIN_PIN >58V) 3 OT_NTC_FAULT 1 Ignore external over-temperature fault (NTC_PIN 2V) 5 OC2_PEAK 0 Ignore peak overcurrent fault (ISENx >105µA) 6 VOUT_UV 1 Ignore output undervoltage fault (FB_PIN 120% VREF_DAC as default, threshold programmable) 8 PLLCOMP_SHORT 0 Ignore PLLCOMP pin shorted to high potential voltages (PLLCOMP_PIN >1.7V) 9 PLL_LOCK 0 Ignore PLL fault due to reaching the minimum frequency (detects the minimum frequency of 37kHz as typical) 15:10 FN8656 Rev.6.00 Jul 13, 2018 Not used 000000 Not used Page 59 of 72 ISL78229 SET_FAULT_RESPONSE (D2h) Definition: Sets/reads the fault protection response which is either Hiccup or Latch-off determined by the corresponding bit of SET_FAULT_RESPONSE register. The default value of the SET_FAULT_RESPONSE register is determined by the HIC/LATCH pin configurations. • When HIC/LATCH pin is pulled high (VCC), each of Bits [9:0] is set to 1 as default • When the HIC/LATCH pin is pulled low (GND), each of Bits [9:0] is set to 0 as default • When bit = 1, the fault protection response is Hiccup mode • When bit = 0, the fault protection response is Latch-off mode In Hiccup mode, the device stops switching when a fault condition is detected, and restarts from soft-start after 500ms (typical). This operation is repeated until fault conditions are completely removed. In Latch-off mode, the device stops switching when a fault condition is detected and PWM switching disabled even after fault conditions are removed. In Latch-off status, the internal LDO is active to maintain PVCC voltage, and PMBus interface is accessible for user to monitor the type of fault triggered or other parameters. By either toggling the EN pin or cycling VCC/PVCC below the POR threshold restarts the system. For related descriptions, refer to “Fault Response Register SET_FAULT_RESPONSE (D2h)” on page 35, and Table 3 on page 41 for some fault related registers summary. Data Length in Bytes: 2 Data Format: Bit Field Type: R/W Protectable: Yes Default Value: Set by the HIC/LATCH pin. 03FFh when HIC/LATCH = VCC; 0000h when HIC/LATCH = GND. Units: N/A COMMAND SET_FAULT_RESPOSE (D2h) Format Bit Field Bit Position 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Function See following table Default Value (HIC/LATCH = VCC) 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 Default Value (HIC/LATCH = GND) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIT NUMBER FAULT NAME DEFAULT VALUE MEANING 0 Not used Set by the HIC/LATCH pin Not used 1 Not used Set by the HIC/LATCH pin Not used 2 VIN_OV Set by the HIC/LATCH pin Input overvoltage fault (VIN_PIN >58V) protection response is Hiccup when bit = 1, and Latch-off when bit = 0 3 OT_NTC_FAULT Set by the HIC/LATCH pin NTC over-temperature fault (NTC_PIN 2V) protection response is Hiccup when bit = 1, and Latch-off when bit = 0 5 OC2_PEAK Set by the HIC/LATCH pin Peak overcurrent fault (ISENx >105µA) protection response is Hiccup when bit = 1, and Latch-off when bit = 0 6 VOUT_UV Set by the HIC/LATCH pin Output undervoltage fault (FB_PIN 120% VREF_DAC as default, threshold programmable) protection response is Hiccup when bit = 1, and Latch-off when bit = 0 FN8656 Rev.6.00 Jul 13, 2018 Page 60 of 72 ISL78229 BIT NUMBER FAULT NAME DEFAULT VALUE MEANING 8 PLLCOMP_SHORT Set by the HIC/LATCH pin PLLCOMP_SHORT fault (PLLCOMP_PIN >1.7V) protection response is Hiccup when bit = 1, and Latch-off when bit = 0 9 PLL_LOCK Set by the HIC/LATCH pin PLL loop fault (detect the minimum frequency of 37kHz as typical) protection response is Hiccup when bit = 1, and Latch-off when bit = 0 15:10 Not used 000000 Not used VOUT_OV_FAULT_LIMIT (D3h) Definition: Sets/reads the output overvoltage fault threshold. The output overvoltage fault is generated by a comparator comparing the FB pin voltage with VOUT_OV threshold which has setting options based on percentage of the VREF_DAC reference voltage. This command set OV threshold with eight options ranging from 105% to 125% of the reference voltage VREF_DAC. The default is set at 120% of VREF_DAC. Equivalently the VOUT overvoltage threshold is set at the same percentage of VOUT target voltage (set by VREF_DAC) because the device uses the same FB voltage to regulate the output voltage with the same resistor divider between VOUT and the FB pin. For example, at default, the VOUT overvoltage threshold is set at 120% of VOUT_TARGET. According to Equation 2 on page 26, the default VOUT overvoltage threshold can be calculated using Equation 31. Other threshold options can be calculated using Equation 31 with 1.2 replaced with other percentage options. R FB2  VOUT OVdefault = 1.2  V REFDAC   1 + --------------- R FB1  (EQ. 31) This fault detection is active at the beginning of soft-start (t5 as shown in Figure 67 on page 30). When an OV fault occurs, the corresponding bit in the FAULT_STATUS register is set to 1 and the SALERT pin is pulled low. The OV fault protection response is by default active and the fault response is either Hiccup or Latch-off determined by the corresponding bit of FAULT_RESPONSE register of which default value is determined by the HIC/LATCH pin. For related description, refer to “Output Overvoltage Fault” on page 36, Table 3 on page 41 and the “PMBus Command Summary” on page 43 to deactivate this fault and configure the fault response. Data Length in Bytes: 1 Data Format: Bit Field Type: R/W Protectable: Yes Default Value: 06h, which equals to 0000_0110b, meaning 120% of VREF_DAC Units: % COMMAND OVP_SET (D3h) Format Bit Field Bit Position 7 6 5 4 3 2 1 0 Access R/W R/W R/W R/W R/W R/W R/W R/W 1 1 0 Function Default Value See following table 0 0 0 0 0 BITS 7:3 (NOT USED) BITS 2:0 PERCENTAGE OF VREF_DAC (%) Not Used 000 105 Not Used 001 107.5 Not Used 010 110 Not Used 011 112.5 Not Used 100 115 Not Used 101 117.5 Not Used 110 120 Not Used 111 125 FN8656 Rev.6.00 Jul 13, 2018 Page 61 of 72 ISL78229 VOUT_UV_FAULT_LIMIT (D4h) Definition: Sets/reads the output undervoltage fault threshold. The output undervoltage fault is generated by a comparator comparing the FB pin voltage with VOUT_UV threshold which has setting options based on percentage of the VREF_DAC reference voltage. This command sets the UV threshold with eight options ranging from 75% to 95% of the reference voltage VREF_DAC. The default is set at 80% of VREF_DAC. Equivalently, the VOUT undervoltage threshold is set at the same percentage of VOUT target voltage (set by VREF_DAC) because the device uses the same FB voltage to regulate the output voltage with the same resistor divider between VOUT and the FB pin. For example, at default, the VOUT undervoltage threshold is set at 80% of VOUT_TARGET. According to Equation 2 on page 26, the default VOUT undervoltage threshold can be calculated using Equation 32. Other threshold options can be calculated using Equation 32 with 0.8 replaced with other percentage options. R FB2  VOUT UV = COMMAND  V REFDAC   1 + --------------- R FB1  (EQ. 32) This fault is masked before soft-start completes (t9 as shown in Figure 67 on page 30), or when the device is disabled. During normal operation after soft-start completes and part is enabled, when a UV fault occurs, the corresponding bit in FAULT_STATUS register is set to 1 and the SALERT pin is pulled low. However, this UV fault protection response is masked by the FAULT_MASK register by default. For related descriptions and command details, refer to “Output Undervoltage Fault” on page 36, Table 3 on page 41 and “PMBus Command Summary” on page 43. Data Length in Bytes: 1 Data Format: Bit Field Type: R/W Protectable: Yes Default Value: 01h, which equals to 0000_0001b, meaning 80% of VREF_DAC Units: V (referred for the VOUT_UV threshold VOUT_UV calculated by Equation 32) COMMAND UVP_SET (D4h) Format Bit Field Bit Position 7 6 5 4 3 2 1 0 Access R/W R/W R/W R/W R/W R/W R/W R/W 0 0 1 Function Default Value See following table 0 0 0 0 0 BITS 7:3 (NOT USED) BITS 2:0 PERCENTAGE OF VREF_DAC (%) Not Used 000 75 Not Used 001 80 Not Used 010 82.5 Not Used 011 85 Not Used 100 87.5 Not Used 101 90 Not Used 110 92.5 Not Used 111 95 FN8656 Rev.6.00 Jul 13, 2018 Page 62 of 72 ISL78229 CC_LIMIT (D5h) Definition: Sets/reads the reference voltage VREF_CC for constant current control loop described in “Constant Current Control (CC)” on page 37. At overloading condition when constant current control loop is working, the VIMON is controlled to be equal to the 1.6V reference (VREF_CC) by default. Because VIMON represents the boost total input average current IIN as described in “Average Current Sense for 2 Phases - IMON” on page 32, the IIN is controlled to be constant by the CC loop. This command can set CC reference to 8 options ranging from 1.25V to 1.6V with default setting of 1.6V. From Equations 13 and 14, Equation 33 can be derived to convert the eight CC reference options in below table (as VIMON in the equation) to the actual total boost input current thresholds for CC, where COMMAND in the equation is the voltage options (CC_LIMIT Reference Voltage) in the command table shown in following. – 6 R SET COMMAND I IN =  ---------------------------------- – 17  10   ----------------  8  R  R IMON SEN (EQ. 33) For related descriptions, refer to “Constant Current Control (CC)” on page 37. Data Length in Bytes: 1 Data Format: Bit Field Type: R/W Protectable: Yes Default Value: 07h, which equals to 0000_0111b, meaning VREF_CC = 1.6V (per table) for VIMON to follow at CC control. Units: V (referred for the reference voltage VREF_CC for VIMON to follow); A (referred for the boost average input current converted by Equation 33) COMMAND CC_LIMIT (D5h) Format Bit Field Bit Position 7 6 5 4 3 2 1 0 Access R/W R/W R/W R/W R/W R/W R/W R/W 1 1 1 Function Default Value See following table 0 0 0 0 0 BITS 7:3 (NOT USED) BITS 2:0 CC REFERENCE VOLTAGE VREF_CC (V) Not Used 000 1.25 Not Used 001 1.3 Not Used 010 1.35 Not Used 011 1.4 Not Used 100 1.45 Not Used 101 1.5 Not Used 110 1.55 Not Used 111 1.6 FN8656 Rev.6.00 Jul 13, 2018 Page 63 of 72 ISL78229 OC_AVG_FAULT_LIMIT (D6h) Definition: Sets/reads the input average overcurrent fault threshold. The input average overcurrent fault is generated by a comparator comparing the IMON pin voltage with 2V threshold as default. This command sets the OC_AVG fault threshold with eight options ranging from 1V to 2V. The default is set at 07h meaning 2V for VIMON. Use Equation 33 to convert the OC_AVG fault thresholds in following table to the actual total boost input average current protection thresholds. This fault detection is active at the beginning of soft-start (t5 as shown in Figure 67 on page 30). When an OC_AVG fault occurs, the corresponding bit in the FAULT_STATUS register is set to 1 and the SALERT pin is pulled low. The OC_AVG fault protection is by default active and the fault response is either Hiccup or Latch-off determined by the corresponding bit of FAULT_RESPONSE register of which default value is determined by the HIC/LATCH pin. For related description, refer to “Average Overcurrent Fault (OC_AVG)” on page 38, Table 3 on page 41, and the related commands in “PMBus Command Summary” on page 43 to deactivate this fault and configure the fault response. Data Length in Bytes: 1 Data Format: Bit Field Type: R/W Protectable: Yes Default Value: 07h, which equals to 0000_0111b, meaning 2V threshold for the IMON pin voltage (VIMON) to detect OC_AVG fault. Units: V COMMAND OC_AVG_FAULT_LIMIT (D6h) Format Bit Field Bit Position 7 6 5 4 3 2 1 0 Access R/W R/W R/W R/W R/W R/W R/W R/W 1 1 1 Function Default Value See following table 0 0 0 0 0 BITS 7:3 (NOT USED) BITS 2:0 Not Used 000 1 Not Used 001 1.15 Not Used 010 1.25 Not Used 011 1.4 Not Used 100 1.55 Not Used 101 1.7 Not Used 110 1.85 Not Used 111 2 FN8656 Rev.6.00 Jul 13, 2018 OC_AVG THRESHOLD FOR VIMON (V) Page 64 of 72 ISL78229 Application Information Use Equation 36 to calculate L, where values of VIN, VOUT and ILpp are based on the considerations described in the following: External components and boost regulators can be defined several ways. This section shows one example of how to decide the parameters of the external components based on the typical application schematics as shown in Figure 4 on page 8. In the actual application, the parameters may need to be adjusted and additional components may be needed for the specific applications regarding noise, physical sizes, thermal, testing, and/or other requirements. Output Voltage Setting The output voltage (VOUT) of the regulator can be programmed by an external resistor divider connecting from VOUT to FB and FB to GND as shown in Figure 4 on page 8. Use Equation 2 on page 26 to calculate the desired VOUT, where VREF can be either VREF_DAC or VREF_TRK, whichever is lower. VREF_DAC default is 1.6V and can be programmed to a value between 0V to 2.04V using the PMBus command “VOUT_COMMAND (21h)” on page 48. In the actual application, the resistor value should be decided by considering the quiescent current requirement and loop response. Typically, between 4.7kΩ to 20kΩ is used for the RFB1. Switching Frequency Switching frequency is determined by requirements for transient response time, solution size, EMC/EMI, power dissipation, efficiency, ripple noise level, and input/output voltage range. Higher frequency may improve the transient response and help to reduce the solution size. However, this may increase the switching losses and EMC/EMI concerns. Thus, a balance of these parameters is needed when deciding the switching frequency. When the switching frequency fSW is decided, the frequency setting resistor (RFSYNC) can be determined by Equation 6 on page 29. Input Inductor Selection While the boost converter is operating in steady state Continuous Conduction Mode (CCM), the output voltage is determined by Equation 1 on page 25. With the required input and output voltage, duty cycle D can be calculated by Equation 34: V IN D = 1 – ---------------V OUT (EQ. 34) where D is the on-duty of the boost low-side power transistor. Under this CCM condition, the inductor peak-to-peak ripple current of each phase can be calculated as Equation 35: VIN I L(P-P) = D  T  ---------L (EQ. 35) From the previous equations, the inductor value is determined by Equation 36: FN8656 Rev.6.00 Jul 13, 2018 • The general rule for selecting the inductor is to have its ripple current IL(P-P) around 30% to 50% of maximum DC current. The individual maximum DC inductor current for the 2-phase boost converter can be calculated by Equation 37, where POUTmax is the maximum DC output power, EFF is the estimated efficiency: P OUTmax I Lmax = -------------------------------------------V INmin  EFF  2 (EQ. 37) Using Equation 36 with the two conditions listed above, a reasonable starting point for the minimum inductor value can be estimated from Equation 38, where K is typically selected as 30%. 2  EFF  2 V INmin  V INmin  L min =  1 – ---------------------------  --------------------------------------------------V OUTmax P OUTmax  K  f SW  (EQ. 38) Increasing the value of the inductor reduces the ripple current and therefore the ripple voltage. However, the large inductance value may reduce the converter’s response time to a load transient. Also, this reduces the ramp signal and may cause a noise sensitivity issue. The peak current at maximum load condition must be lower than the saturation current rating of the inductor with enough margin. In the actual design, the largest peak current may be observed at some transient conditions like the start-up or heavy load transient. Therefore, the inductor’s size needs to be determined with the consideration of these conditions. To avoid exceeding the inductor’s saturation rating, OC1 peak current limiting (refer to “Peak Current Cycle-by-Cycle Limiting (OC1)” on page 36) should be selected below the inductor’s saturation current rating. Output Capacitor To filter the inductor current ripples and to have sufficient transient response, output capacitors are required. A combination of electrolytic and ceramic capacitors is normally used. The ceramic capacitors filter the high frequency spikes of the main switching devices. In layout, these output ceramic capacitors must be placed as close as possible to the main switching devices to maintain the smallest switching loop. To maintain capacitance over the biased voltage and temperature range, high quality capacitors such as X7R or X5R are recommended. The electrolytic capacitors are normally used to handle the load transient and output ripples. The boost output ripples are mainly dominated by the load current and output capacitance volume. where T is the switching cycle 1/fSW and L is each phase inductor's inductance. V IN  V IN  L =  1 – ----------------  -------------------------------V I  OUT L(P-P)  f SW • One method is to select the minimum input voltage and the maximum output voltage under long term operation as the conditions to select the inductor. In this case, the inductor DC current is the largest. (EQ. 36) For the boost converter, the maximum output voltage ripple can be estimated using Equation 39, where IOUTmax is the load current at output, C is the total capacitance at output, and DMIN is the minimum duty cycle at VINmax and VOUTmin. Page 65 of 72 ISL78229 I OUTmax   1 – D MIN  V OUTripple = ---------------------------------------------------------C  2  f SW under limitation of maximum gate drive voltage, which is 5.2V (typical) for low-side MOSFET and 4.5V (typical) due to diode drop of boot diode for high-side MOSFET. (EQ. 39) For a 2-phase boost converter, the RMS current going through the output current can be calculated by Equation 39 for D > 0.5, where IL is per phase inductor DC current. For D < 0.5, time domain simulation is recommended to get the accurate calculation of the input capacitor RMS current. I CoutRMS = I L   1 – D    2D – 1   Bootstrap Capacitor The power required for high-side MOSFET drive is provided by the boot capacitor connected between BOOT and PH pins. The bootstrap capacitor can be chosen using Equation 41: Q gate C BOOT  -----------------------dV BOOT (EQ. 40) It is recommended to use multiple capacitors in parallel to handle this output RMS current. (EQ. 41) Input Capacitor Where Qgate is the total gate charge of the high-side MOSFET and dVBOOT is the maximum droop voltage across the bootstrap capacitor while turning on the high-side MOSFET. Depending upon the system input power rail conditions, the aluminum electrolytic type capacitors are normally used to provide a stable input voltage. The input capacitor should be able to handle the RMS current from the switching power devices. Refer to Equation 5 and Figure 62 on page 28 to estimate the RMS current the input capacitors need to handle. Though the maximum charging voltage across the bootstrap capacitor is PVCC minus the bootstrap diode drop (~4.5V), large excursions below GND by PH node requires at least 10V rating for this ceramic capacitor. To keep enough capacitance over the biased voltage and temperature range, a high quality capacitor such as X7R or X5R is recommended. Ceramic capacitors must be placed near the VIN and PGND pin of the IC. Multiple ceramic capacitors including 1µF and 0.1µF are recommended. Place these capacitors as close as possible to the IC. RESISTOR ON BOOTSTRAP CIRCUIT In the actual application, sometimes a large ringing noise at the PH node and the BOOT node occurs. This noise is caused by high dv/dt phase node switching and parasitic PH node capacitance due to PCB routing and the parasitic inductance. To reduce this noise, a resistor can be added between the BOOT pin and the bootstrap capacitor. A large resistor value reduces the ringing noise at PH node but limits the charging of the bootstrap capacitor during the low-side MOSFET on-time, especially when the controller is operating at very low duty cycle. Also, large resistance causes a voltage dip at BOOT each time the high-side driver turns on the high-side MOSFET. Make sure this voltage dip does not trigger the high-side BOOT to PH UVLO threshold 3V (typical), especially when a MOSFET with large Qg is used. Power MOSFET The external MOSFETs driven by the ISL78229 controller must be carefully selected to optimize the design of the synchronous boost regulator. The MOSFET's BVDSS rating must have enough voltage margin against the maximum boost output voltage plus the phase node voltage transient during switching. As the UG and LG gate drivers are 5V output, the MOSFET VGS need to be in this range. The MOSFET should have low Total Gate Charge (Qg), low ON-resistance (rDS(ON)) at VGS = 4.5V and small gate resistance (Rg >RCP, CCP1>>CCP2, and ROEA = infinite, the equation can be simplified as shown in Equation 46: s 1 + ---------1 + s  R CP  C CP1 1  z2 H e2  s  = g m  ---------------------------------------------------------------------------------- = -------  -------------------s  C CP1   1 + s  R CP  C CP2  s s 1 + --------- p2 (EQ. 46) To provide a quiet power rail to the internal analog circuitry, it is recommended to place an RC filter between PVCC and VCC. A 10Ω resistor between PVCC and VCC and at least 1µF ceramic capacitor from VCC to GND are recommended. Current Sense Circuit To set the current sense resistor, the voltage across the current sense resistor should be limited to within ±0.3V. In a typical application, it is recommended to set the voltage across the current sense resistor between 30mV to 100mV for the typical load current condition. Configuration to Support Single Phase Boost The IC can be configured to support single phase operation using either phase 1 or phase 2. The configurations needed to use phase 1 for single phase operation are listed below (use phase 2 for single phase operation by changing corresponding phase number to the other phase number): where: gm  p2 = --------------C CP1 1  z2 = -------------------------------R CP  C CP1 • BOOT2 = GND (UG2 disabled) 1  p3 = -------------------------------R CP  C CP2 • ISEN2P = ISEN2N = GND If Type-3 compensation is needed, the transfer function at the feedback resistor network is: s 1 + ---------R FB1  z1 H e1  S  = ------------------------------------  -------------------R FB1 + R FB2 s 1 + --------- p1 VCC Input Filter (EQ. 47) • PH2 = GND The extra notes are listed below with upper single phase configurations: • LG2 can be left floating. LG2 has PWM signals which is fine with no external MOSFET to drive. • IMON pin output current signal has only phase 1’s inductor current sensed signal. Equation 12, for calculating the IMON output current, is turned to into Equation 49. where: 1  z1 = --------------------------------------------C 1   R FB2 + R 1  I L1  R –6 SEN1 IMON = --------------------------------  0.125 + 17  10 R SET1 1  p1 = ----------------------------------------------------------------------------------------------------------------R FB2  R FB1 + R FB2  R 1 + R FB1  R 1 C 1  ----------------------------------------------------------------------------------------------------R FB2 + R FB1 (EQ. 49) The Constant Current Loop works on the same principle. The total transfer function with compensation network and gain stage is expressed: G open  s  = G vcvo  s   H e1  s   H e2  s  (EQ. 48) Use f = ω/2π to convert the pole and zero expressions to frequency domain, and from Equations 42, 47 and 48, select the compensator’s pole and zero locations. In general, as described earlier, a Type-2 compensation is enough. Typically the crossover frequency is set 1/5 to 1/3 of the ωRHZ frequency. For the compensator, as general rule, set ωp2/2π at very low end frequency; set ωz2/2π at 1/5 of the crossover frequency; set ωp3/2π at the ESR zero or the RHZ frequency ωRHZ/2π, whichever is lower. FN8656 Rev.6.00 Jul 13, 2018 Page 68 of 72 ISL78229 Layout Considerations The PCB layout is very important to ensure the desired performance for the DC/DC converter. 7. Place the 10µF decoupling ceramic capacitor at the PVCC pin and as close as possible to the IC. Put multiple vias close to the ground pad of this capacitor. 1. Place input ceramic capacitors as close as possible to the IC's VIN and PGND/SGND pins. 8. Place the 1µF decoupling ceramic capacitor at the VCC pin and as close as possible to the IC. Put multiple vias close to the ground pad of this capacitor. 2. Place the output ceramic capacitors as close as possible to the power MOSFET. Keep this loop (output ceramic capacitor and MOSFETs for each phase) as small as possible to reduce voltage spikes induced by the trace parasitic inductances when MOSFETs switching ON and OFF. 10. Keep the driver traces as short as possible and with relatively large width (25 mil to 40 mil is recommended), and avoid using vias or a minimal number of vias in the driver path to achieve the lowest impedance. 3. Place the output aluminum capacitors close to power MOSFETs too. 4. Keep the phase node copper area small but large enough to handle the load current. 5. Place the input aluminum and some ceramic capacitors close to the input inductors and power MOSFETs. 6. Place multiple vias under the thermal pad of the IC. Connect the thermal pad to the ground copper plane with as large an area as possible in multiple layers to effectively reduce the thermal impedance. Figure 77 shows the layout example for vias in the IC bottom pad. 9. Keep the bootstrap capacitor as close as possible to the IC. 11. Place the current sense setting resistors and the filter capacitor (shown as RSETxB, RBIASxB and CISENx in Figure 69 on page 32) as close as possible to the IC. Keep each pair of the traces close to each other to avoid undesired switching noise injections. 12. The current sensing traces must be laid out very carefully because they carry tiny signals with only tens of mV. For the current sensing traces close to the power sense resistor (RSENx), the layout pattern shown in Figure 78 is recommended. Assuming the RSENx is placed in the top layer (red), route one current sense connection from the middle of one RSENx pad in the top layer under the resistor (red trace). For the other current-sensing trace, from the middle of the other pad on RSENx in top layer, after a short distance, via down to the second layer and route this trace right under the top layer current sense trace. 13. Keep the current sensing traces far from the noisy traces like gate driving traces (LGx, UGx, and PHx), phase nodes in power stage, BOOTx signals, output switching pulse currents, driving bias traces, and input inductor ripple current signals, etc. FIGURE 77. RECOMMENDED LAYOUT PATTERN FOR VIAS IN THE IC BOTTOM PAD FIGURE 78. RECOMMENDED LAYOUT PATTERN FOR CURRENT SENSE TRACES REGULATOR FN8656 Rev.6.00 Jul 13, 2018 Page 69 of 72 ISL78229 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please visit our website to make sure you have the latest revision. DATE REVISION CHANGE Jul 13, 2018 FN8656.6 Updated the ordering information table by adding tape and reel column, adding T&R FGs to table, and updating Note 1. Added two lines to the “Absolute Maximum Ratings” on page 9. Changed “If the DE/PHDRP pin = GND” to “If the DE/PHDRP pin = VCC” in “Operation Initialization and Soft-Start” on page 30. Removed the About Intersil section and updated disclaimer. Sep 18, 2017 FN8656.5 Added Related Literature section Updated Equation 7 on page 31. Applied new header/footer. Feb 6, 2017 FN8656.4 - Added third sentence in the VIN pin description on page 5. - Figures 26 and 28 on page 19, changed "D" to "D_TRACK" in the title to avoid confusion. - Figure 51 on page 24, swapped VPORL_PVCC and VPORL_VCC data labels for the 2 curves. - Added “while the adaptive dead time control is still functioning at the same time” to the first sentence in “Programmable Adaptive Dead Time Control” on page 26. - Added “for three consecutive switching cycles” to the first sentence in “Peak Overcurrent Fault (OC2_PEAK)” on page 37. - Added the last paragraph in “Average Overcurrent Fault (OC_AVG)” on page 38. - Updated Figures 74, 75, and 76. - Updated Equation 42 on page 67, and expressions KDC, wpPS, Qp, and wn. - Updated Equation 43 on page 67. - Added section “Configuration to Support Single Phase Boost” on page 68. Feb 12, 2016 FN8656.3 Table 4 on page 41 updated D2h descriptions PMBus command summary Table 6 on page 43, simplified D2h descriptions. SET_FAULT_RESPONSE (D2h) on page 60 changes as follow: Changed 0000h to 03FFh, 00FFh to 0000h. Changed from “Not used” to “set by the HIC/LATCH pin” (2 places) Changed from “all the bits are set to 1 as default” to “each of bits[9:0] is set to 1 as default” Changed from “all the bits are set to 0 as default” to “each of bits[9:0] is set to 0 as default” Feb 4, 2016 FN8656.2 Changed in Figure 16 on page 18 label “IL1” to IL2” and in title “Phase 1” to “Phase 2”. Jan 4, 2016 FN8656.1 Updated 2nd and 3rd paragraph in section “External Over-Temperature Fault (OT_NTC_FAULT)” on page 39 for clarity and changed in 4th paragraph “450mV” to “300mV”. Changed in “IC_DEVICE_REV (AEh)”, “0B01h” and “010Ch” to “0C01h” and changed default value in table starting with the 6th number from “...011...” to “...100...” on page 43 and page 57. Changed Default Value for “FAULT_MASK FROM “0043h” to “0049h” on page 41 and page 59 Updated the table bit value: From: 0000-0000-0100-0011; To: 0000-0000-0100-1001 Updated D1h default value column in Table 4 on page 41. Updated expression Qp and Equation 44 on page 67 Removed text after Equation 44 on page 67 and before paragraph that begins with “Equation 42”. Nov 23, 2015 FN8656.0 Initial Release FN8656 Rev.6.00 Jul 13, 2018 Page 70 of 72 ISL78229 Package Outline Drawing For the most recent package outline drawing, see L40.6x6C. L40.6x6C 40 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (PUNCH QFN WITH WETTABLE FLANK) Rev 1, 1/14 2X A 0.10 M C A B 4.5 2X 5.75 N 5 0.60 DIA. 0.10 C A 6.00 4x 0.42 ± 0.18 1 2 3 PIN#1 ID R0.20 N 0.10 C B 0.45 1 2 3 4x 0.42 ± 0.18 5.75 4.5 6.00 CC (0.35) 0.40 ± 0.10 0.15 ± 0.10 (0.35) 0.10 C B 2X B 2X 0.10 C A TOP VIEW 0.10 M C A B 0.25 ± 0.05 0.10 M C A B 0.05 M C 0.50 BOTTOM VIEW 6 0.10 C 0.85 ± 0.05 0.05 C 0.01 ± 0.04 0.65 ± 0.05 4 0.25 ± 0.05 0.20 0.25 ± 0.05 0.15 ± 0.05 0.01 ± 0.04 0.01 ± 0.04 0.10 ± 0.05 SECTION “C-C” DETAIL “A” SCALE: NONE SCALE: NONE SEE DETAIL "A" NOTES: 12° MAX C SEATING PLANE SIDE VIEW 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance: Decimal ± 0.05 4. Dimension applies to the plated terminal and is measured 5. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be 6. Reference document: JEDEC MO220 between 0.15mm and 0.30mm from the terminal tip. 36x (0.50) either a mold or mark feature. (5.80) SQ (4.50) SQ 40x (0.25) 40x (0.60) TYPICAL RECOMMENDED LAND PATTERN FN8656 Rev.6.00 Jul 13, 2018 Page 71 of 72 Notice 1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for the incorporation or any other use of the circuits, software, and information in the design of your product or system. Renesas Electronics disclaims any and all liability for any losses and damages incurred by you or third parties arising from the use of these circuits, software, or information. 2. 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Renesas Electronics disclaims any and all liability for any damages or losses incurred by you or any third parties arising from the use of any Renesas Electronics product that is inconsistent with any Renesas Electronics data sheet, user’s manual or other Renesas Electronics document. 6. When using Renesas Electronics products, refer to the latest product information (data sheets, user’s manuals, application notes, “General Notes for Handling and Using Semiconductor Devices” in the reliability handbook, etc.), and ensure that usage conditions are within the ranges specified by Renesas Electronics with respect to maximum ratings, operating power supply voltage range, heat dissipation characteristics, installation, etc. Renesas Electronics disclaims any and all liability for any malfunctions, failure or accident arising out of the use of Renesas Electronics products outside of such specified ranges. 7. Although Renesas Electronics endeavors to improve the quality and reliability of Renesas Electronics products, semiconductor products have specific characteristics, such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Unless designated as a high reliability product or a product for harsh environments in a Renesas Electronics data sheet or other Renesas Electronics document, Renesas Electronics products are not subject to radiation resistance design. You are responsible for implementing safety measures to guard against the possibility of bodily injury, injury or damage caused by fire, and/or danger to the public in the event of a failure or malfunction of Renesas Electronics products, such as safety design for hardware and software, including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult and impractical, you are responsible for evaluating the safety of the final products or systems manufactured by you. 8. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. You are responsible for carefully and sufficiently investigating applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive, and using Renesas Electronics products in compliance with all these applicable laws and regulations. Renesas Electronics disclaims any and all liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. 9. Renesas Electronics products and technologies shall not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. You shall comply with any applicable export control laws and regulations promulgated and administered by the governments of any countries asserting jurisdiction over the parties or transactions. 10. It is the responsibility of the buyer or distributor of Renesas Electronics products, or any other party who distributes, disposes of, or otherwise sells or transfers the product to a third party, to notify such third party in advance of the contents and conditions set forth in this document. 11. This document shall not be reprinted, reproduced or duplicated in any form, in whole or in part, without prior written consent of Renesas Electronics. 12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products. (Note 1) “Renesas Electronics” as used in this document means Renesas Electronics Corporation and also includes its directly or indirectly controlled subsidiaries. (Note 2) “Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics. (Rev.4.0-1 November 2017) http://www.renesas.com SALES OFFICES Refer to "http://www.renesas.com/" for the latest and detailed information. Renesas Electronics America Inc. 1001 Murphy Ranch Road, Milpitas, CA 95035, U.S.A. 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