Datasheet
ISL78600
Multi-Cell Li-Ion Battery Manager
The ISL78600 Li-ion battery manager IC supervises
up to 12 series-connected cells. The part provides
accurate monitoring, cell balancing, and extensive
system diagnostics functions. Three cell balancing
modes are incorporated: Manual Balance mode,
Timed Balance mode, and Auto Balance mode. The
Auto Balance mode terminates balancing functions
when a charge transfer value specified by the host
microcontroller has been met.
The ISL78600 communicates to a host
microcontroller through an SPI interface and to other
ISL78600 devices using a robust, proprietary, 2-wire
daisy chain system.
Features
• Up to 12-cell voltage monitors with support for
Li-ion CoO2, Li-ion Mn2O4, and Li-ion FePO4
chemistries
• Board level cell voltage measurement accuracy
±1.5mV
• 13-bit cell voltage measurement
• Pack voltage measurement accuracy ±100mV
• 14-bit pack voltage and temperature measurements
• Cell voltage scan rate of 19.5µs per cell (234µs to
scan 12 cells)
The ISL78600 is offered in a 64 Ld TQFP package
and is specified for operation at a temperature range
of -40°C to +105°C.
• Internal and external temperature monitoring
Applications
• Integrated system diagnostics for all key internal
functions
• Hybrid Electric Vehicle (HEV), Plug-in Hybrid
Electric Vehicle (PHEV), and Electric Vehicle (EV)
battery packs
• Electric motorcycle battery packs
• Backup battery and energy storage systems
requiring high accuracy management and
monitoring
• Portable and semiportable equipment
• Up to four external temperature inputs
• Robust daisy chain communications system
• Hardwired and communications based fault
notification
• Integrated watchdog shuts down device if
communication is lost
• 2Mbps SPI
• AEC-Q100 qualified
Related Literature
For a full list of related documents, visit our website
• ISL78600 product page
FN7672 Rev.11.00
Jun.12.20
Page 1 of 139
ISL78600
TO OTHER DEVICES (OPTIONAL)
ISL78600
ISL78600
VG2 VG2
VG1 VG1
DHi2
DLo2
DHi2
DHi1
DLo2
DLo1
SCLK
DOUT
DIN
CS
DATA READY
HOST
MICRO
FAULT
EN
VG1
VG1
MONITOR BOARD (MASTER OR STANDALONE)
VG2
MONITOR BOARD (DAISY CHAIN - OPTIONAL)
Figure 1. Typical Application
FN7672 Rev.11.00
Jun.12.20
Page 2 of 139
ISL78600
Contents
1.
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1
1.2
1.3
1.4
2.
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6
7
8
8
Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1
2.2
2.3
2.4
2.5
2.6
2.7
3.
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10
11
11
11
19
20
21
Device Description and Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.1
3.2
3.3
4.
Cell Voltage Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Cell Balancing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
System Hardware Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
4.10
5.
Battery and Cell Balance Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Supplies and Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Communications Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Daisy Chain Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Typical Application Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating with Reduced Cell Counts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Board Layout Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Component Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Board Level Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
29
34
35
37
38
39
40
48
49
49
System Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
5.10
5.11
5.12
5.13
5.14
Device Response. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Address All. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read and Write Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Scan Voltages Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Scan Temperatures Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Scan Mixed Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Scan Wires Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Scan All Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Scan Continuous Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Scan Inhibit Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Measure Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Scan Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Temperature Monitoring Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Sleep Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Jun.12.20
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52
52
52
53
53
54
54
54
56
56
58
58
59
Page 3 of 139
ISL78600
5.15
5.16
5.17
5.18
5.19
5.20
5.21
5.22
5.23
5.24
6.
Wakeup Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reset Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Calc Register Checksum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Check Register Checksum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Balance Enable Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Balance Inhibit Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Cell Balancing Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Manual Balance Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timed Balance Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Auto Balance Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
60
60
61
61
61
61
61
63
64
65
Daisy Chain Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
6.1
6.2
6.3
7.
Identify Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
ACK (Acknowledge) Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
NAK (Not Acknowledge) Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
8.
SPI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Non-Daisy Chain Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Daisy Chain Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Communications Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Daisy Chain Commands/Responses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Communication Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Measurement Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Command Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Response Timing Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
73
74
76
77
81
84
84
87
88
System Timing Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
8.1
8.2
8.3
9.
Command Timing Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Measurement Timing Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Response Timing Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
System Diagnostics Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
9.1
9.2
9.3
9.4
9.5
9.6
9.7
9.8
9.9
9.10
Hardware Fault Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Out of Limit Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fault Signal Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Diagnostic Activity Settling Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Checksum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Communication Faults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Communications Failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Daisy Chain Communications Conflicts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Loss of Signal From Host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Alarm Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
100
100
100
102
102
103
103
104
105
106
10.
Fault Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
11.
Worked Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
11.1
11.2
11.3
11.4
Voltage Reference Check Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Cell Balancing – Manual Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Cell Balancing – Timed Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Cell Balancing – Auto Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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111
111
113
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ISL78600
12.
12.1
12.2
12.3
12.4
12.5
System Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Register Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Temperature Data, Secondary Voltage Reference Data, Scan Count . . . . . . . . . . . . . . . . . . . . . . . .
Fault Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference Coefficient Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Nonvolatile Memory (EEPROM) Checksum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
118
119
121
129
131
13.
Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
14.
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
15.
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
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ISL78600
1.1
Overview
Block Diagram
CONTROL LOGIC AND COMMUNICATIONS
1.
1. Overview
VBAT
VC12
CB12
VC11
CB11
VC10
VC8
CB8
VC7
CB7
VC6
CB6
VC5
CB5
VC4
CB4
BASE
VREG
V3P3
VDDEXT
V2P5
V2P5
VCC
VREF
MUX
CB9
REF
VC MUX
VC9
INPUT BUFFER/LEVEL SHIFT AND FAULT DETECTION
CB10
DAISY
CHAIN
AND
SPI
COMMS
DHI 2
DLO 2
SCLK/DHI 1
CS/DLO 1
DIN
DOUT
DATA READY
COMMS RATE 1
COMMS RATE 0
COMMS SELECT 2
COMMS SELECT 1
DGND
FAULT
EN
VC3
ADC
CB3
TEMPREG
VC2
CB2
CB1
VC0
IC TEMP
VC1
REFERENCE
TEMP MUX
ExT1
ExT2
ExT3
ExT4
VSS
Figure 2. Block Diagram
FN7672 Rev.11.00
Jun.12.20
Page 6 of 139
ISL78600
1.2
1. Overview
Ordering Information
Part Number
(Note 2, Note 3)
Part
Marking
Trim Voltage,
VNOM (V)
Temp. Range
(°C)
Tape and Reel
(Units) (Note 1)
Package
(RoHS
Compliant)
Pkg.
Dwg. #
ISL78600ANZ
ISL78600ANZ
3.3
-40 to +105
-
64 Ld TQFP
Q64.10x10D
ISL78600ANZ-T
ISL78600ANZ
3.3
-40 to +105
1k
64 Ld TQFP
Q64.10x10D
ISL78600EVKIT1Z
Evaluation Kit
Notes:
1. See TB347 for details about reel specifications.
2. These Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations).
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J
STD-020.
3. For Moisture Sensitivity Level (MSL), see the ISL78600 product information page. For more information about handling and processing
moisture sensitive devices, see TB363.
Table 1.
Product Family
Part Number
Maximum Initial Cell Voltage Monitor Error (Note 4)
ISL78600
2.0mV
ISL78610
10.0mV
Note:
4. Conditions: Temperature = -20°C to +60°C, VCELL = 2.6V to 4.0V, limits applied to a ±3 sigma distribution.
FN7672 Rev.11.00
Jun.12.20
Page 7 of 139
ISL78600
1.3
1. Overview
Pin Configuration
1.4
VC10
CB11
VC11
CB12
VC12
VBAT
VBAT
NC
DHi2
DLo2
NC
SCLK/DHi1
CS/DLo1
NC
DIN/NC
DOUT/NC
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
(64 Ld 10x10 TQFP)
Top View
VC4
12
37
DNC
CB4
13
36
V3P3
VC3
14
35
V2P5
CB3
15
34
VCC
VC2
16
33
REF
32
BASE
31
DNC
38
NC
39
11
VDDEXT
10
CB5
30
VC5
ExT4
COMMS SELECT 2
29
40
28
COMMS SELECT 1
9
ExT3
41
CB6
TEMPREG
VC6
27
COMMS RATE 1
26
42
8
NC
7
ExT2
CB7
25
COMMS RATE 0
24
DGND
43
NC
44
6
ExT1
5
VC7
23
CB8
NC
FAULT
22
DATA READY
45
21
46
4
VSS
3
VC8
VSS
CB9
20
EN
19
47
VC0
2
CB1
VC9
18
DNC
17
48
VC1
1
CB2
CB10
Pin Descriptions
Pin Name
Pin Number
Description
20, 18, 16, Battery cell voltage inputs. VCn connects to the positive terminal of CELLn and the negative terminal
VC0, VC1, VC2, VC3,
VC4, VC5, VC6, VC7, 14, 12, 10, 8, of CELLn+1. (VC12 connects only to the positive terminal of CELL12 and VC0 only connects with the
6, 4, 2, 64, negative terminal of CELL1.)
VC8, VC9, VC10,
62, 60
VC11, VC12
Cell Balancing FET control outputs. Each output controls an external FET, which provides a current
path around the cell for balancing.
CB1, CB2, CB3, CB4,
CB5, CB6, CB7, CB8,
CB9, CB10, CB11,
CB12
19, 17, 15,
13, 11, 9, 7,
5, 3, 1, 63,
61
VBAT
58, 59
Main IC supply pins. Connect to the most positive terminal in the battery string.
VSS
21, 22
Ground. These pins connect to the most negative terminal in the battery string.
ExT1, ExT2, ExT3,
ExT4
24, 26, 28,
30
External temperature monitor or general purpose inputs. The temperature inputs are intended for use
with external resistor networks using NTC type thermistor sense elements but can also be used as
general purpose analog inputs at the user’s discretion. 0V to 2.5V input range.
TEMPREG
29
Temperature monitor voltage regulator output. This switched 2.5V output supplies a reference voltage
to external NTC thermistor circuits to provide ratiometric ADC inputs for temperature measurement.
FN7672 Rev.11.00
Jun.12.20
Page 8 of 139
ISL78600
1. Overview
Pin Name
Pin Number
Description
VDDEXT
32
External V3P3 supply input/output. Connected to the V3P3 pin through a switch, this pin can be used
to power external circuits from the V3P3 supply. The switch is open when the ISL78600 is placed in
Sleep mode.
REF
33
2.5V voltage reference decoupling pin. Connect a 2.0µF to 2.5µF X7R capacitor to VSS. Do not
connect any additional external load to this pin.
VCC
34
Analog supply voltage input. Connect to V3P3 through a 33Ω resistor. Connect a 1µF capacitor to
ground.
V2P5
35
Internal 2.5V digital supply decoupling pin. Connect a 1µF capacitor to DGND.
V3P3
36
3.3V digital supply voltage input. Connect the emitter of the external NPN regulator transistor to this
pin. Connect a 1µF capacitor to DGND.
BASE
38
Regulator control pin. Connect the external NPN transistor’s base. Do not let this pin float.
DNC
37, 39, 48
COMMS SELECT 1
41
Communications Port 1 mode select pin. Connect to V3P3 through a 1kΩ resistor for daisy chain
communications on Port 1 or to DGND for SPI operation on Port 1.
COMMS SELECT 2
40
Communications Port 2 mode select pin. Connect to V3P3 through a 1kΩ resistor to enable Port 2 or
to DGND to disable this port.
COMMS RATE 0,
COMMS RATE 1
43, 42
Daisy chain communications data rate setting. Connect to DGND (‘0’) or to V3P3 (‘1’) through a 1kΩ
resistor to select between various communication data rates.
DGND
44
Digital ground.
FAULT
45
Logic fault output. Asserted low if a fault condition exists.
DATA READY
46
SPI data ready. Asserted low when the device is ready to transmit data to the host microcontroller.
EN
47
Enable input. Tie to V3P3 to enable the part, then the device is ready after a delay of tPUD (“Power-Up
Specifications” on page 13). Tie to DGND to disable (all IC functions are turned off).
DOUT/NC
49
Serial data output (SPI) or NC (daisy chain). 0V to 3.3V push-pull output.
DIN/NC
50
Serial data input (SPI) or NC (daisy chain). 0V to 3.3V input.
CS/DLo1
52
Chip-Select, active low 3.3V input (SPI) or daisy chain Port 1 Low connection.
SCLK/DHi1
53
Serial-clock input (SPI) or daisy chain Port 1 High connection.
DHi2
56
Daisy chain Port 2 High connection.
DLo2
55
Daisy chain Port 2 Low connection.
NC
23, 25, 27,
31, 51, 54,
57
FN7672 Rev.11.00
Jun.12.20
Do not connect. Leave pins floating.
No internal connection.
Page 9 of 139
ISL78600
2.
2.1
2. Specifications
Specifications
Absolute Maximum Ratings
Parameter
Minimum
Maximum
Unit
VBAT
-0.5
63
V
DHi1, DLo1, DHi2, DLo2,
-0.5
VBAT + 0.5
V
VCn (for n= 0 to 12)
-0.5
VBAT + 0.5
V
CBn (for n= 1 to 12)
-0.5
VBAT + 0.5
V
VC12
-0.5
63
V
VC11
-0.5
63
V
VC10
-0.5
63
V
VC9
-0.5
54
V
VC8
-0.5
45
V
VC7
-0.5
45
V
VC6
-0.5
36
V
VC5
-0.5
36
V
VC4
-0.5
27
V
VC3
-0.5
27
V
VC2
-0.5
18
V
VC1
-0.5
18
V
VC0
-0.5
9
V
V(VCn-1) - 0.5
V(VCn-1) + 9
V
V(VCn) - 9
V(VCn) + 0.5
V
BASE, DIN, SCLK, CS, DOUT, DATA READY, COMMS SELECT n,
TEMPREG, REF, V3P3, VCC, FAULT, COMMS RATE n, EN, VDDEXT
- 0.2
5.5
V
ExTn
- 0.2
4.1
V
V2P5
- 0.2
2.9
V
Voltage Relative to VSS, unless otherwise specified
CBn (for n= 1 to 9)
CBn (for n= 10 to 12)
Note: DOUT, DATA READY, and FAULT are digital outputs and should not be driven from external sources. V2P5, REF, TEMPREG and
BASE are analog outputs and should not be driven from external sources.
ESD Rating
Value
Unit
Human Body Model (Tested per AECQ100-002)
2
kV
Capacitive Discharge Model (Tested per AECQ100-011)
2
kV
Latch-Up (Tested per AEC-Q100-004; Class 2, Level A)
100
mA
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely
impact product reliability and result in failures not covered by warranty.
FN7672 Rev.11.00
Jun.12.20
Page 10 of 139
ISL78600
2.2
2. Specifications
Thermal Information
Thermal Resistance (Typical)
64 Ld TQFP Package (Notes 5, 6)
θJA (°C/W)
θJC (°C/W)
42
9
Notes:
5. JA is measured with the component mounted on a high-effective thermal conductivity test board in free air. See TB379.
6. For JC, the “case temp” location is taken at the package top center.
Parameter
Minimum
Maximum Continuous Package Power Dissipation
Storage Temperature
-55
Maximum Operating Junction Temperature
Pb-Free Reflow Profile
2.3
Maximum
Unit
400
mW
+125
°C
+125
°C
See TB493.
Recommended Operating Conditions
Parameter
Minimum
Maximum
Unit
-40
+105
°C
VBAT
6
60
V
VBAT (for Daisy Chain operation)
10
60
V
VCn - VC(n-1) (for n = 1 to 12)
-0.1
5.0
V
VC0
-0.1
+0.1
V
CBn - VC(n-1) (for n = 1 to 9)
-0.5
9.0
V
CBn - VC(n-1) (for n = 10 to 12)
-9.0
0.5
V
VC5, VC6
-0.5
36
V
DIN, SCLK, CS, COMMS SELECT 1, COMMS SELECT 2, V3P3, VCC, COMMS RATE 0,
COMMS RATE 1, EN
0
3.6
V
ExT1, ExT2, ExT3, ExT4 Input Voltage
0
2.5
V
Voltage Relative to VSS, Unless Otherwise Specified
TA, Ambient Temperature Range
2.4
Electrical Specifications
VBAT = 6 to 60V, TA = -20°C to +60°C, unless otherwise specified. Biasing setup as in Figure 45 on page 34 or equivalent.
Parameter
Symbol
Test Conditions
Min
(Note 7)
Typ
Max
(Note 7)
Unit
5
V
Measurement Specifications
Cell Voltage Input Measurement
Range
VCELL
Cell Monitor Voltage Resolution
VCELLRES
FN7672 Rev.11.00
Jun.12.20
VC(n) - VC(n-1), for design reference.
[VC(n) - VC(n-1)] LSB step size (13-bit signed
number), 5V full scale value
- 0.3
0.61
mV
Page 11 of 139
ISL78600
2. Specifications
VBAT = 6 to 60V, TA = -20°C to +60°C, unless otherwise specified. Biasing setup as in Figure 45 on page 34 or equivalent. (Continued)
Parameter
Symbol
ISL78600 Initial Cell Monitor Voltage
Error
(Note 9)
VNOM = Nominal calibration voltage
VCELL
Note: Cell measurement accuracy
figures assume a fixed 1kΩ resistor is
placed in series with each VCn pin (n
= 0 to 12).
Note: Cell accuracy figures assume a
fixed 1kΩ resistor is placed in series
with each VCn pin (n = 0 to 12)
Typ
Max
(Note 7)
Unit
-2.5
2.5
mV
VCELL = VNOM - 0.7V < VCELL < VNOM + 0.7V
-3.5
3.5
mV
-40°C to +85°C (Note 8)
-7.5
7.5
mV
-40°C to +105°C (Note 8)
-8.5
8.5
mV
-8.0
8.0
mV
-40°C to +85°C (Note 8)
-11.0
11.0
mV
-40°C to +105°C (Note 8)
-11.0
11.0
mV
-12.0
12.0
mV
-40°C to +85°C (Note 8)
-18.0
18.0
mV
-40°C to +105°C (Note 8)
-20.0
20.0
mV
-0.5
µA
-0.50
µA
VCELL = 0.5
IVCELL
Min
(Note 7)
VCELL = VNOM - 0.3V < VCELL < VNOM + 0.3V
VCELL = 4.95
See ““Performance Characteristics”
on page 20
Cell Input Current
Test Conditions
VC0 Input
VC0 ≥ 0.5 and VC0 ≤ 4.0V
-1.5
-1
VC0 > 4.0V
-1.75
-40°C to +105°C (Note 8)
-2.0
-1
-0.5
µA
VCn - VC(n-1) ≥ 0.5 and VCn - VC(n-1) ≤ 4.0V
-2.7
-2
-1.3
µA
VCn - VC(n-1) > 4.0V
-2.85
-1.00
µA
-40°C to +105°C (Note 8)
-3.0
-2
-1.0
µA
VCn - VC(n-1) ≥ 0.5 and VCn - VC(n-1) ≤ 4.0V
-0.6
0
0.6
µA
VCn - VC(n-1) > 4.0V
-0.7
0.7
µA
-40°C to +105°C (Note 8)
- 0.8
0
0.8
µA
0.5
2
2.7
µA
1.5
2
2.7
µA
VCn - VC(n-1) > 4.0V
1.50
2
2.85
µA
-40°C to +105°C (Note 8)
0.5
2
3.0
µA
VC12 - VC11 ≥ 0.5 and VC12 - C11 ≤ 4.0V
0.6
1
1.7
µA
VC12 - VC11 > 4.0V
0.60
1.75
µA
-40°C to +105°C (Note 8)
0.6
2.0
µA
VC1, VC2, VC3 Inputs
VC4 Input
VC5, VC6, VC7, VC8, VC9, VC10, VC11 inputs
VCn - VC(n-1) < 2.6V
VCn - VC(n-1) ≥ 2.6V and VCn - VC(n-1) ≤
4.0V
VC12 Input
VBAT Monitor Voltage Resolution
VBATRES
Initial VBAT monitor Voltage Error
(Note 9)
VBAT
External Temperature Monitoring
Regulator
FN7672 Rev.11.00
Jun.12.20
VTEMP
1
4.863
ADC resolution referred to input (VBAT) level.
14-bit unsigned number. Full scale
value = 79.67V.
mV
Measured at VBAT = 36V to 43.2V
-100
100
mV
Measured at VBAT = 31.2V to 48V
-125
125
mV
Measured at VBAT = 6V to 59.4V
-320
322
mV
Measured at VBAT = 6V to 59.4V
-40°C to +105°C (Note 8)
-490
490
mV
Voltage on TEMPREG output. (0 to 2mA load)
2.475
2.525
V
2.500
Page 12 of 139
ISL78600
2. Specifications
VBAT = 6 to 60V, TA = -20°C to +60°C, unless otherwise specified. Biasing setup as in Figure 45 on page 34 or equivalent. (Continued)
Parameter
External Temperature Output
Impedance
Symbol
Test Conditions
Min
(Note 7)
Typ
Max
(Note 7)
Unit
0.1
0.2
Ω
2344
mV
RTEMP
Output Impedance at TEMPREG pin. (Note 8)
0
External Temperature Input Range
VEXT
Effective ExTn input voltage range. For design
reference. This is the input voltage range that
does not trigger an open input condition.
0
External Temperature Input Pull-Up
REXTTEMP
External Temperature Input Offset
VEXTOFF
External Temperature Input INL
VEXTINL
External Temperature Input Gain
Error
VEXTG
Pull-up resistor to VTEMPREG applied to each
input during measurement
VINTMON
Internal Temperature Monitor
Resolution
TINTRES
MΩ
VBAT = 39.6V
-7.0
7.0
mV
VBAT = 39.6V, -40°C to +105°C (Note 8)
-10
10
mV
(Note 8)
Error at 2.5V input
-40°C to +105°C (Note 8)
Internal Temperature Monitor Error
10
±0.61
mV
-7.5
11
mV
-8
18.5
mV
±10
°C
Output resolution (LSB/°C), 14-bit number
31.9
LSB/°C
TINT25
Output count at +25°C
9180
Decimal
Power-Up Condition Threshold
VPOR
VBAT voltage (rising)
Power-Up Condition Hysteresis
VPORhys
Internal Temperature Monitor Output
Power-Up Specifications
4.8
5.1
5.6
460
V
mV
Initial Power-Up Delay
tPOR
Time after VPOR condition
VREF from 0V to 0.95 x VREF(nominal)
(EN tied to V3P3) Device can now
communicate
27.125
ms
Enable Pin Power-Up Delay
tPUD
Delay after EN = 1 to VREF from 0V to
0.95 x VREF(nominal)
(VBAT = 39.6V) - Device can now communicate
27.125
ms
FN7672 Rev.11.00
Jun.12.20
Page 13 of 139
ISL78600
2. Specifications
VBAT = 6 to 60V, TA = -20°C to +60°C, unless otherwise specified. Biasing setup as in Figure 45 on page 34 or equivalent. (Continued)
Parameter
Symbol
Test Conditions
Min
(Note 7)
Typ
Max
(Note 7)
Unit
Supply Current Specifications
VBAT Supply Current
IVBAT
Non-daisy chain configuration. Device enabled. No communications, ADC,
measurement, balancing, or open-wire detection activity.
6V
70
90
µA
39.6V
73
95
µA
60V
73
96
µA
105
µA
-40°C to +105°C (Note 8)
IVBATMASTER Daisy chain configuration – master device. Enabled. No communications, ADC,
measurement, balancing, or open-wire detection activity.
6V
400
550
660
µA
39.6V
500
650
900
µA
60V
550
710
1000
µA
1150
µA
-40°C to +105°C (Note 8)
Peak current when daisy chain transmitting
IVBATMID
18
Daisy chain configuration – Middle stack device. Enabled. No communications, ADC,
measurement, balancing, or open-wire detection activity.
6V
700
1020
1210
µA
39.6V
900
1210
1560
µA
60V
1000
1340
1700
µA
1850
µA
-40°C to +105°C (Note 8)
Peak current when daisy chain transmitting
IVBATTOP
18
6V
400
550
660
µA
39.6V
500
650
900
µA
60V
550
710
1000
µA
1150
µA
Peak current when daisy chain transmitting
IVBATSLEEP1 Sleep mode (EN = 1, daisy chain configuration)
(Note 8)
6V
18
mA
13
28
44
µA
39.6V
18
33
48
µA
60V
20
35
50
µA
120
µA
34.1
µA
109
µA
-40°C to +105°C
IVBATSLEEP2 Sleep mode (EN = 1, stand-alone, non-daisy
(Note 8)
chain)
-40°C to +105°C
13.2
19
13.5
Shutdown. device “off” (EN = 0) (Daisy chain and non-daisy chain configurations)
6V
6
13
28
µA
39.6V
7
15
29
µA
60V
7
16
30
µA
101
µA
-40°C to +105°C
FN7672 Rev.11.00
Jun.12.20
mA
Daisy chain configuration – top device. Enabled. No communications, ADC,
measurement, balancing, or open-wire detection activity.
-40°C to +105°C (Note 8)
IVBATSHDN
(Note 8)
mA
Page 14 of 139
ISL78600
2. Specifications
VBAT = 6 to 60V, TA = -20°C to +60°C, unless otherwise specified. Biasing setup as in Figure 45 on page 34 or equivalent. (Continued)
Parameter
VBAT Supply Current Tracking, Sleep
Mode
Symbol
Test Conditions
IVBATΔSLEEP EN = 1, daisy chain sleep mode configuration.
(Note 8)
VBAT current difference between any two
devices operating at the same temperature and
supply voltage.
-40°C to +105°C
VBAT Incremental Supply Current,
Balancing
IVBATBAL
All balancing circuits on. Incremental current:
Add to non-balancing VBAT current.
VBAT = 39.6V
-40°C to +105°C (Note 8)
V3P3 Regulator Voltage (Normal)
V3P3N
EN = 1, Load current range 0 to 5mA. VBAT =
39.6V
-40°C to +105°C (Note 8)
V3P3 Regulator Voltage (Sleep)
V3P3S
EN = 1, Load current range. No load. (SLEEP).
VBAT = 39.6V
V3P3 Regulator Control Current
IBASE
Current sourced from BASE output. VBAT = 6V
-40°C to +105°C (Note 8)
V3P3 Supply Current
IV3P3
Device enabled
No measurement activity, Normal mode
-40°C to +105°C (Note 8)
VREF Reference Voltage
VDDEXT Switch Resistance
VREF
RVDDEXT
IVCC
Unit
0
18
µA
0
56
µA
Typ
250
300
350
µA
200
300
400
µA
3.25
3.35
3.45
V
3.5
V
3.2
2.8
V
1
mA
1
mA
0.8
1
0.8
1.2
mA
1.3
mA
EN = 1, no load, normal mode
2.5
V
Switch “ON” resistance, VBAT = 39.6V
12
Ω
-40°C to +105°C (Note 8)
VCC Supply Current
Max
(Note 7)
Min
(Note 7)
Device enabled (EN = 1). Stand-alone or daisy
configuration. No ADC or daisy chain
communications active.
-40°C to +105°C (Note 8)
5
2.00
2.0
IVCCACTIVE1 Device enabled (EN = 1). Stand-alone or daisy
configuration. average current during 16ms scan
continuous operation. VBAT = 39.6V
IVCCSLEEP
Device enabled (EN = 1). Sleep mode.
VBAT = 39.6V
IVCCSHDN
Device disabled (EN = 0). Shutdown mode.
3.25
0
22
Ω
4.50
mA
5.0
mA
6.0
mA
0.5
µA
0.5
-40°C to +105°C (Note 8)
3.5
µA
9.0
µA
Over-Temperature Protection Specifications
Internal Temperature Limit Threshold
External Temperature Limit
Threshold
TINTSD
TXT
Balance stops and auto scan stops.
Temperature rising or falling.
150
°C
Corresponding to 0V (minimum) and VTEMPREG
(maximum)
External temperature input voltages higher than
15/16 VTEMPREG are registered as open input
faults.
0
16383
Decimal
Cell Over and Undervoltage Test Specifications
Undervoltage Threshold
VUV
Programmable. Corresponding to 0V (minimum)
and 5V (maximum)
0
8191
Decimal
Overvoltage Threshold
VOV
Programmable. Corresponding to 0V (minimum)
and 5V (maximum)
0
8191
Decimal
FN7672 Rev.11.00
Jun.12.20
Page 15 of 139
ISL78600
2. Specifications
VBAT = 6 to 60V, TA = -20°C to +60°C, unless otherwise specified. Biasing setup as in Figure 45 on page 34 or equivalent. (Continued)
Parameter
Symbol
Test Conditions
Min
(Note 7)
Typ
Max
(Note 7)
Unit
3.79
3.89
3.99
V
4.05
V
2.71
V
2.8
V
2.90
V
2.90
V
2.24
V
2.28
V
3.90
V
4.0
V
2.8
V
2.85
V
2.900
V
2.900
V
2.465
V
2.4
V
2.512
V
Voltage Reference/Oscillator Check Specifications
V3P3 Power-Good Window
V3PH
3.3V power-good window high threshold.
VBAT = 39.6V
-40°C to +105°C (Note 8)
V3PL
3.3V power-good window low threshold.
VBAT = 39.6V
-40°C to +105°C (Note 8)
V2P5 Power-Good Window
V2PH
2.5V power-good window high threshold.
VBAT = 39.6V
-40°C to +105°C (Note 8)
V2PL
(Note 8)
2.5V power-good window low threshold.
VBAT = 39.6V
-40°C to +105°C
VCC Power-Good Window
VVCCH
VCC power-good window high threshold.
VBAT = 39.6V
-40°C to +105°C (Note 8)
VVCCL
VCC power-good window low threshold.
VBAT = 39.6V
-40°C to +105°C (Note 8)
VREF Power-Good Window
VRPH
VREF power-good window high threshold.
VBAT = 39.6V
-40°C to +105°C (Note 8)
VRPL
VREF power-good window low threshold.
VBAT = 39.6V
-40°C to +105°C (Note 8)
3.70
2.54
2.64
2.5
2.65
2.70
2.53
1.85
2.03
1.76
3.60
3.74
3.6
2.6
2.7
2.55
2.525
2.700
2.525
2.150
2.300
2.0
VREF Secondary Reference Accuracy
Test
VRACC
VREF value calculated using stored coefficients.
VBAT = 39.6V
(“Voltage Reference Check Calculation” on
page 110)
Voltage Reference Check Timeout
tVREF
Time to check voltage reference value from
power-on, enable, or wakeup
20
ms
Oscillator Check Timeout
tOSC
Time to check main oscillator frequency from
power-on, enable, or wakeup
20
ms
Oscillator Check Filter Time
tOSCF
Minimum duration of fault required for detection
100
ms
2.488
2.500
Cell Open-Wire Detection (See “Scan Wires Command” on page 54 and “Open-Wire Test” on page 102.)
Open-Wire Current
IOW
ISCN bit = 0; VBAT = 39.6V
0.125
0.150
0.185
mA
ISCN bit = 1; VBAT = 39.6V
0.85
1.00
1.15
mA
Open-Wire Detection Time
tOW
Open-wire current source “on” time
4.6
ms
Open VC0 Detection Threshold
VVC0
CELL1 negative terminal (with respect to VSS)
VBAT = 39.6V (Note 8)
1.2
1.5
1.8
V
Open VC1 Detection Threshold
VVC1
CELL1 positive terminal (with respect to VSS)
VBAT = 39.6V (Note 8)
0.6
0.7
0.8
V
Primary Detection Threshold, VC2 to
VC12
VVC2_12P
V(VC(n - 1)) - V(VCn), n = 2 to 12
VBAT = 39.6V (Note 8)
--1.5
-1.2
-0.9
V
Secondary Detection Threshold, VC2
to VC12
VVC2_12S
Through ADC. VC2 to VC12 only
VBAT = 39.6V (Note 8)
-100
-39
10
mV
Open VBAT Fault Detection Threshold
VVBO
FN7672 Rev.11.00
Jun.12.20
VC12 - VBAT
200
mV
Page 16 of 139
ISL78600
2. Specifications
VBAT = 6 to 60V, TA = -20°C to +60°C, unless otherwise specified. Biasing setup as in Figure 45 on page 34 or equivalent. (Continued)
Parameter
Symbol
Open VSS Fault Detection Threshold
VVSSO
Test Conditions
Min
(Note 7)
VSS - VC0
Typ
Max
(Note 7)
250
Unit
mV
Cell Balance Output Specifications
Cell Balance Pin Output Impedance
RCBL
CBn output off impedance
between CB(n) to VC(n-1): cells 1 to 9 and
between CB(n) to VC(n): cells 10 to 12
2
4
5
MΩ
Cell Balance Output Current
ICBH1
CBn output on. (CB1-CB9); VBAT = 39.6V;
device sinking current
-28
-25
-21
μA
ICBH2
CBn output on. (CB10-CB12); VBAT = 39.6V;
device sourcing current
21
25
28
μA
Cell Balance Output Leakage in
Shutdown
ICBSD
EN = GND. VBAT = 39.6V
-500
10
700
nA
External Cell Balance FET Gate
Voltage
VGS
CBn Output on;
External 320kΩ between VCn and CBn
(n = 10 to 12) and between CBn and VCn-1
(n = 1 to 9)
7.04
8.00
8.96
V
ICB = 100µA
8.94
Internal Cell Balance Output Clamp
VCBCL
V
Logic Inputs: SCLK, CS, DIN
Low-Level Input Voltage
VIL
High-Level Input Voltage
VIH
Input Hysteresis
VHYS
Input Current
IIN
Input Capacitance (Note 8)
CIN
0.8
(Note 8)
0V < VIN < V3P3
V
1.75
V
100
mV
-1
+1
µA
10
pF
0.3*
V3P3
V
Logic Inputs: EN, COMMS SELECT1, COMMS SELECT2, COMMS RATE 0, COMMS RATE 1
Low-Level Input Voltage
VIL
High-Level Input Voltage
VIH
Input Hysteresis
VHYS
Input Current
IIN
Input Capacitance (Note 8)
CIN
(Note 8)
0V < VIN < V3P3
0.7*
V3P3
V
0.05*
V3P3
V
-1
+1
µA
10
pF
Logic Outputs: DOUT, Fault, Data Ready
Low-Level Output Voltage
High-Level Output Voltage
VOL1
At 3mA sink current
0
0.4
V
VOL2
At 6mA sink current
0
0.6
V
VOH1
At 3mA source current
V3P3
–0.4
V3P3
V
VOH2
At 6mA source current
V3P3
–0.6
V3P3
V
2
MHz
200
ns
SPI Interface Timing (See Figure 3 and Figure 4)
SCLK Clock Frequency
Pulse Width of Input Spikes
Suppressed
fSCLK
tIN1
50
Enable Lead Time
tLEAD
Chip select low to ready to receive clock data
200
ns
Clock High Time
tHIGH
(Note 8)
200
ns
Clock Low Time
tLOW
(Note 8)
200
ns
FN7672 Rev.11.00
Jun.12.20
Page 17 of 139
ISL78600
2. Specifications
VBAT = 6 to 60V, TA = -20°C to +60°C, unless otherwise specified. Biasing setup as in Figure 45 on page 34 or equivalent. (Continued)
Parameter
Enable Lag Time
Symbol
Min
(Note 7)
Typ
Max
(Note 7)
Unit
Last data read clock edge to chip select high
(Note 8)
250
ns
tCS:WAIT
Minimum high time for CS between bytes
200
ns
Slave Access Time
tA
Chip Select low to DOUT active. (Note 8)
200
ns
Data Valid Time
tV
Clock low to DOUT valid
350
ns
CHIP SELECT High Time
tLAG
Test Conditions
Data Output Hold Time (Note 8)
tHO
Data hold time after falling edge of SCLK
DOUT Disable Time
tDIS
DOUT disabled following rising edge of CS
(Note 8)
Data Setup Time
tSU
Data input valid prior to rising edge of SCLK
100
ns
Data Input Hold Time
tHI
Data input to remain valid following rising edge
of SCLK
80
ns
DATA READY Stop Delay Time
DATA READY High Time
SPI Communications Timeout
tDR:SP
tDR:WAIT
tSPI:TO
0
ns
240
ns
Chip select high to DATA READY high
750
ns
Time between bytes
1.0
µs
Time the CS remains high before SPI
communications time out - requiring the start of
a new command
100
µs
DOUT Rise Time
tR
Up to 50pF load
30
ns
DOUT Fall Time
tF
Up to 50pF load
30
ns
Daisy Chain Communications Interface: DHi1, DLo1, DHi2, DLo2
Daisy Chain Clock Frequency
Comms Rate (0, 1) = 11
450
500
550
kHz
Comms Rate (0, 1) = 10
225
250
275
kHz
Comms Rate (0, 1) = 01
112.5
125
137.5
kHz
Comms Rate (0, 1) = 00
56.25
62.5
68.75
kHz
Common-Mode Reference Voltage
VBAT/2
V
Notes:
7. Compliance to datasheet limits is assured by one or more methods: production test, characterization, and/or design.
8. These MIN and/or MAX values are based on characterization data and are not 100% tested.
9. Stresses may be induced in the ISL78600 during soldering or other high temperature events that affect measurement accuracy. Initial
accuracy does not include effects due to this. See Figure 6 on page 21 for cell reading accuracy obtained after soldering to Renesas
evaluation boards. When soldering the ISL78600 to a customized circuit board with a layout or construction significantly differing from the
Renesas evaluation board, design verification tests should be applied to determine drift due to soldering and over lifetime.
FN7672 Rev.11.00
Jun.12.20
Page 18 of 139
ISL78600
2.5
2. Specifications
Timing Diagrams
CS
(FROM μc)
tSPI:TO
tLEAD
tHIGH
tLOW
tCS:WAIT
tLAG
SCLK
(FROM µC)
tF
tV
tA
tDIS
tHO
DOUT
(TO µC)
tSU
tR
tHI
DIN
(FROM µC)
CLOCK DATA INTO
ISL78600
CLOCK DATA OUT OF
ISL78600
Figure 3. SPI Full Duplex (4-Wire) Interface Timing
tCS:WAIT
tSPI:TO
CS
(FROM µC)
tDR:WAIT
tDR:SP
DATA READY
(TO µC)
SCLK
(FROM µC)
tA
tDIS
DOUT
(TO µC)
CLOCK DATA OUT OF
ISL78600
DIN
(FROM µC)
SIGNALS ON DIN IGNORED
WHILE DATA READY IS LOW
CLOCK DATA INTO
ISL78600
Figure 4. SPI Half Duplex (3-Wire) Interface Timing
FN7672 Rev.11.00
Jun.12.20
Page 19 of 139
ISL78600
2.6
2. Specifications
Performance Characteristics
Table 2.
Board Level Cell Voltage Reading Error (Cell Chemistry Ranges)
Parameter
ISL78600 Cell Monitor
Voltage Error (Absolute)
Symbol
VCELLA
ISL78600 Initial VBAT
VBAT
Reading Error (Absolute)
Voltage Reference Long
Term Drift
Min
(Note 10)
Typ
Max
(Note 10)
Unit
VCELL = 3.25V at 25°C
(± 3 sigma)
(± 6 sigma)
-0.9
-2.8
1.01
1.01
2.9
4.8
mV
VCELL = 1.65V to 2.85V (±3 sigma)
-20°C to +60°C
-40°C to +85°C
-40°C to +105°C
-1.8
-2.8
-4.6
0.79
0.45
0.06
3.4
3.7
4.7
mV
VCELL = 1.65V to 2.85V (±6 sigma)
-20°C to +60°C
-40°C to +85°C
-40°C to +105°C
-4.4
-6.1
-9.1
0.79
0.45
0.06
5.9
7.0
9.2
mV
VCELL = 2.5V to 3.65V (±3 sigma)
-20°C to +60°C
-40°C to +85°C
-40°C to +105°C
-1.4
-1.4
-2.9
0.96
0.94
0.78
2.9
3.3
3.0
mV
VCELL = 2.5V to 3.65V (±6 sigma)
-20°C to +60°C
-40°C to +85°C
-40°C to +105°C
-2.8
-3.8
-5.8
0.96
0.94
0.78
4.3
5.6
5.9
mV
VCELL = 2.5V to 4.3V (±3 sigma)
-20°C to +60°C
-40°C to +85°C
-40°C to +105°C
-1.7
-1.8
-3.3
0.96
1.09
1.03
3.3
4.0
3.4
mV
VCELL = 2.5V to 4.3V (±6 sigma)
-20°C to +60°C
-40°C to +85°C
-40°C to +105°C
-4.2
-4.6
-6.7
0.96
1.09
1.03
5.8
6.8
6.8
mV
Temperature = -20°C to +60°C
VBAT = 30V to 48V
Limits applied to a ±3 sigma distribution
Limits applied to a ±5 sigma distribution
-51
-99
27
103
126
mV
Temperature = -20°C to +60°C
VBAT = 19.8V to 49V
Limits applied to a ±3 sigma distribution
Limits applied to a ±5 sigma distribution
-78
-159
36
153
195
mV
Temperature = -40°C to +105°C
VBAT = 30V to 48V
Limits applied to a ±3 sigma distribution
Limits applied to a ±5 sigma distribution
-71
-166
12
119
178
mV
Temperature = -40°C to +105°C
VBAT = 19.8V to 49V
Limits applied to a ±3 sigma distribution
Limits applied to a ±5 sigma distribution
-92
-210
18.5
156
229
mV
Test Conditions
-0.31
mV/
log(kHrs)
10. These distribution values are based on characterization of devices mounted on evaluation boards and are not 100% tested. Test
performed approximately 30 days post assembly, individually stored in static free bags at room temperature until testing.
FN7672 Rev.11.00
Jun.12.20
Page 20 of 139
ISL78600
2.7
2. Specifications
Typical Performance Curves
25
20
15
10
5
20
15
10
5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
-0.5
-1.0
-1.5
-2.0
-3.5
-2.5
0
0
-6.0
-5.5
-5.0
-4.5
-4.0
-3.5
-3.0
-2.5
-2.0
-1.5
-1.0
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
PERCENTAGE OF CELLS (%)
25
-3.0
PERCENTAGE OF CELLS (%)
30
CELL VOLTAGE READING ERROR (mV)
CELL VOLTAGE READING ERROR (mV)
Figure 6. Cell Voltage Accuracy Histogram
1.65V to 4.3V, and -40°C to +85°C
Figure 5. Cell Voltage Accuracy Histogram
1.65V to 4.3V, -20°C to +60°C
15
10
5
0
-8.5
-8.0
-7.5
-7.0
-6.5
-6.0
-5.5
-5.0
-4.5
-4.0
-3.5
-3.0
-2.5
-2.0
-1.5
-1.0
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
PERCENTAGE OF CELLS (%)
20
CELL VOLTAGE READING ERROR (mV)
35
PERCENTAGE OF READINGS (%)
PERCENTAGE OF READINGS (%)
Figure 7. Cell Voltage Accuracy Histogram
1.65V to 4.3V, and -40°C to +105°C
30
25
20
15
10
5
0
-60
-40
-20
0
20
40
60
80
20
15
10
5
0
100
VBAT VOLTAGE READING ERROR (mV)
Figure 8. VBAT Accuracy Histogram 30V to 48V;
-40°C to +85°C
FN7672 Rev.11.00
Jun.12.20
25
VBAT VOLTAGE READING ERROR (mV)
Figure 9. VBAT Accuracy Histogram 19.8V to 49V;
-40°C to +105°C
Page 21 of 139
ISL78600
2. Specifications
100
75
50
25
0
-25
-50
-75
-100
-40
19.8
25.8
30
34.2
39
43.8
48
49
-20
0
20
40
60
TEMPERATURE (°C)
80
100
120
SECOND REFERENCE ACCURACY
(mV)
VBAT VOLTAGE READING ERROR
(mV)
125
2
AVERAGES
19.8V to 49V
0
-2
-5 SIGMA
-4
-6
-8
-40
-20
0
20
40
60
80
100
120
Figure 11. Second Reference Error vs Temperature
VBAT = 19.8V to 49V
3.5
IC TEMP READING ERROR (°C)
3.5
3.0
2.5
2.0
110
90
100
IC TEMPERATURE (°C)
80
70
60
49V
40
48V
50
43.8V
30
39V
20
34.2V
0
0.5
10
30V
-10
25.8V
-20
19.8V
-30
1.0
Figure 12. Internal Temperature Reading Accuracy vs
Temperature
3.0
2.5
2.0
1.5
1.0
-35°C
25°C
105°C
0.5
0.0
120
1.5
-40
IC TEMP READING ERROR (°C)
+5 SIGMA
4
TEMPERATURE (°C)
Figure 10. VBAT Voltage Reading Error
-40°C to +105°C
0.0
6
15
20
25
-20°C
60°C
5°C
85°C
30
35
40
VBAT VOLTAGE (V)
45
50
55
Figure 13. Internal Temperature Reading Accuracy vs
Voltage
25.6
25.60
VCELL = 3.3V
BALANCE CURRENT (µA)
BALANCE CURRENT (µA)
25.4
25.55
25.50
25.45
25.2
25.0
24.8
24.6
24.4
25.40
0
10
20
30
40
50
PACK VOLTAGE (V)
Figure 14. Balance Current vs. Pack Voltage
FN7672 Rev.11.00
Jun.12.20
60
24.2
-40
-20
0
20
40
60
80
100
TEMPERATURE (°C)
Figure 15. Balance Current vs. Temperature
Page 22 of 139
ISL78600
2. Specifications
975
1000
VCELL = 3.3V
970
960
IOPWI (µA)
IOPWI (µA)
TEMPERATURE = +25°C
980
965
960
940
920
900
880
860
955
840
820
950
-40
-20
0
20
40
60
80
100
800
120
0
10
20
30
40
PACK VOLTAGE (V)
TEMPERATURE (°C)
Figure 16. Open-Wire Test Current vs. Temperature
(1mA Setting)
158.6
TEMPERATURE = +25°C
158.4
158
158.2
157
158.0
IOPWI (µA)
IOPWI (µA)
VCELL = 3.3V
159
156
155
157.8
157.6
154
157.4
153
157.2
-20
0
20
40
60
80
100
157.0
120
0
10
20
TEMPERATURE (°C)
30
40
50
60
PACK VOLTAGE (V)
Figure 18. Open-Wire Test Current vs. Temperature
(150µA Setting)
Figure 19. Open-Wire Test Current vs Pack Voltage
(150µA Setting)
4.05
4.045
VBAT = 39.6V
4.040
4.00
VBAT = 39.6V
4.035
3.95
FREQUENCY (MHz)
FREQUENCY (MHz)
60
Figure 17. Open-Wire Test Current vs Pack Voltage
(1mA Setting)
160
152
-40
50
3.90
3.85
3.80
3.75
3.70
-40
4.030
4.025
4.020
4.015
4.010
4.005
-20
0
20
40
60
80
100
120
TEMPERATURE (°C)
Figure 20. 4MHz Oscillator Frequency vs. Temperature
FN7672 Rev.11.00
Jun.12.20
4.000
2.5
2.7
2.9
3.1
3.3
VCC (V)
3.5
3.7
3.9
Figure 21. 4MHz Oscillator Frequency vs. VCC
Page 23 of 139
ISL78600
2. Specifications
31.35
31.6
VBAT = 39.6V
31.4
VBAT = 39.6V
31.30
FREQUENCY (kHz)
FREQUENCY (kHz)
31.2
31.0
30.8
30.6
30.4
31.25
31.20
31.15
31.10
30.2
31.05
30.0
29.8
-40
-20
0
20
40
60
80
100
120
31.00
2.5
2.7
2.9
3.1
3.7
3.9
Figure 23. 32kHz Oscillator Frequency vs. VCC
Figure 22. 32kHz Oscillator Frequency vs. Temperature
60
80
70
50
VBAT = 60V
IVBAT (µA)
30
VBAT = 39.6V
VBAT = 6V
20
VBAT = 60V
60
40
IVBAT (µA)
3.5
3.3
VCC (V)
TEMPERATURE (°C)
50
VBAT = 39.6V
40
VBAT = 6V
30
20
10
0
-40
10
-20
0
20
40
60
80
100
0
-40
120
-20
0
TEMPERATURE (°C)
Figure 24. VBAT Sleep Current vs. Temperature
(Standalone Mode) 6V, 39.6V, 60V
80
70
70
60
VBAT = 60V
IVBAT (µA)
IVBAT (µA)
60
50
VBAT = 39.6V
40
30
VBAT = 6V
50
10
10
20
40
60
80
100
120
TEMPERATURE ( °C )
Figure 26. VBAT Sleep Current vs. Temperature (Daisy
Chain Middle) 6V, 39.6V, 60V
FN7672 Rev.11.00
Jun.12.20
80
100
120
VBAT = 60V
VBAT = 39.6V
VBAT = 6V
30
20
0
60
40
20
-20
40
Figure 25. VBAT Sleep Current vs. Temperature (Daisy
Chain Master) 6V, 39.6V, 60V
80
0
-40
20
TEMPERATURE (°C)
0
-40
-20
0
20
40
60
80
100
120
TEMPERATURE ( °C )
Figure 27. VBAT Sleep Current vs. Temperature (Daisy
Chain Top) 6V, 39.6V, 60V
Page 24 of 139
ISL78600
2. Specifications
750
100
95
700
90
650
IVBAT (µA)
IVBAT (µA)
85
80
VBAT = 60V
75
70
VBAT = 39.6V
600
550
65
VBAT = 6V
60
VBAT = 6V
500
VBAT = 39.6V
55
50
-40
VBAT = 60V
-20
0
20
40
60
80
100
450
-40
120
-20
0
Figure 28. VBAT Supply Current vs. Temperature
(Standalone Mode) 6V, 39.6V, 60V
750
1350
700
1250
650
IVBAT (µA)
IVBAT (µA)
VBAT = 60V
VBAT = 39.6V
60
80
100
120
VBAT = 60V
VBAT = 39.6V
600
550
1050
950
850
-40
40
Figure 29. VBAT Supply Current vs. Temperature (Daisy
Chain Master) 6V, 39.6V, 60V
1450
1150
20
TEMPERATURE ( °C )
TEMPERATURE ( °C )
-20
0
20
40
60
80
VBAT = 6V
500
VBAT = 6V
100
450
-40
120
-20
0
TEMPERATURE (°C)
Figure 30. VBAT Supply Current vs. Temperature (Daisy
Chain Middle) 6V, 39.6V, 60V
20
40
60
TEMPERATURE (°C)
80
100
120
Figure 31. VBAT Supply Current vs. Temperature (Daisy
Chain Top) 6V, 39.6V, 60V
3.45
60
3.40
50
3.35
3.25
30
IVCC (mA)
IVBAT (µA)
40
VBAT = 39.6V
VBAT = 60V
20
3.20
3.15
3.10
3.05
VBAT = 6V
10
3.00
2.95
0
-40
-20
0
20
40
60
TEMPERATURE (°C)
80
100
120
Figure 32. VBAT Shutdown Current vs. Temperature
(EN = 0) 6V, 39.6V, 60V
FN7672 Rev.11.00
Jun.12.20
2.90
-60
-40
-20
0
20
40
60
80
100
120
TEMPERATURE (°C)
Figure 33. VCC Supply Current vs. Temperature
6V, 39.6V, 60V
Page 25 of 139
ISL78600
2. Specifications
1.06
2.5
2.0
CELL INPUT CURRENT (µA)
SUPPLY CURRENT (mA)
1.05
1.04
39.6V
1.03
60V
1.02
6V
1.01
1.00
0.99
-40
VCELL = 3.3V
VC5, VC6, VC7, VC8, VC9, VC10, VC11
1.5
1.0
VC12
0.5
0
VC4
-0.5
-1.0
VC0
-1.5
-2.0
-20
0
20
40
60
80
-2.5
-40
100
VC1, VC2, VC3
-20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 35. Cell Input Current vs. Temperature
Figure 34. V3P3 Supply Current vs. Temperature
6V, 39.6V, 60V
1.0
2.0 VC11
VC10
VC9
1.5 VC8
VC7
1.0 VC6
VC5
0.5
CELL MEASUREMENT ERROR (mV)
CELL INPUT CURRENT (µA)
2.5
VC12
VC4
0.0
-0.5
VC0
-1.0
-1.5
VC3
-2.0 VC2
VC1
-2.5
0
10
20
30
40
PACK VOLTAGE (V)
50
60
Figure 36. Cell Input Current vs. Pack Voltage (+25°C)
FN7672 Rev.11.00
Jun.12.20
0.8
0.6
0.4
0.2
-0.31*log(kHrs)
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
0.01
0.1
1.0
kHrs
10.0
100.0
Figure 37. Long Term Drift
Page 26 of 139
ISL78600
3.
3. Device Description and Operation
Device Description and Operation
The ISL78600 is a Li-ion battery manager IC that supervises up to 12 series-connected cells. Up to 14 ISL78600
devices can be connected in series to support systems with up to 168 cells. The ISL78600 provides accurate
monitoring, cell balance control, and diagnostic functions. The ISL78600 includes a voltage reference, 14-bit A/D
converter, and registers for control and data.
When multiple ISL78600 devices are connected to a series of cells, their power supply domains are normally nonoverlapping. The lower (VSS) supply of each ISL78600 nominally connects to the same potential as the upper
(VBAT) supply of the ISL78600 device below.
3.1
Cell Voltage Monitoring
Within each device, the cell voltage monitoring system has two basic elements: a level shift to eliminate the cell
common-mode voltage, and an analog-to-digital conversion of the cell voltage.
Each ISL78600 is calibrated at a specific cell input voltage value, VNOM. Cell voltage measurement error data is
given in “Measurement Specifications” on page 11 for various voltage and temperature ranges with voltage
ranges defined with respect to VNOM. Plots showing the typical error distribution over the full input range are
included in “Typical Performance Curves” on page 21.
To collect cell voltage and temperature measurements, the ISL78600 provides two multiple parameter
measurement “scanning” modes in addition to single parameter direct measurement capability. The scanning
modes provide pseudo-simultaneous measurement of all cell voltages in the stack.
The ISL78600 does not measure current. The system performs this separately using other measurement
systems.
The only filtering applied to the ADC measurements is that resulting from external protection circuits and the
limited bandwidth of the measurement path. No additional filtering is performed within the part. This arrangement
is typically needed to maintain timing integrity between the cell voltage and pack current measurements.
However, the ISL78600 does apply filtering to the fault detection systems.
3.2
Cell Balancing
Cell balancing is an important function in a battery pack consisting of a stack of multiple Li-ion cells. As the cells
charge and discharge, differences in each cell’s ability to take on and give up charge, typically leads to cells with
different states of charge. The problem with a stack of cells having different states of charge is that Li-ion cells
have a maximum voltage, above which it should not be charged, and a minimum voltage, below which it should
not be discharged. The extreme case, where one cell in the stack is at the maximum voltage and one cell is at the
minimum voltage, results in a nonfunctional battery stack, because the battery stack cannot be charged or
discharged.
The ISL78600 provides multiple cell balance modes: Manual Balance mode, Timed Balance mode, and Auto
Balance mode. These are described in more detail in “Alarm Response” on page 106.
The ISL78600 incorporates extensive fault diagnostics functions, which include cell overvoltage and
undervoltage, regulator and oscillator operation, open cell input detection, and communication faults. The current
status of most faults is accessible using the ISL78600 registers. Some communication faults are reported by
special responses to system commands and some as “unprompted” responses from the device detecting the fault
to the host microcontroller through the daisy chain.
3.3
Power Modes
To conserve power, the ISL78600 has three main power modes: Normal mode, Sleep mode, and “off” (Shutdown
mode).
FN7672 Rev.11.00
Jun.12.20
Page 27 of 139
ISL78600
3.3.1
3. Device Description and Operation
Sleep Mode
The device enters Sleep mode in response to a Sleep command or after a watchdog timeout (see “Watchdog
Function” on page 105.) Only the communications input circuits, low speed oscillator and internal registers are
active in Sleep mode, allowing the part to perform timed scan and balancing activity and to wake up in response
to communications.
3.3.2
Shutdown Mode (Hardware Reset)
The device is in Shutdown mode when the Enable pin is low. In this mode, the internal bias for most of the IC is
powered down except digital core, sleep mode regulators, and digital input buffers. When exiting, the device
powers up and does not reload the factory programmed configuration data from the EEPROM.
The host can perform a hardware reset by toggling the EN pin low, then high. This resets the hardware but does
not reload the registers. After waiting for a tUV settling time, see “Power-Up Specifications” on page 13 the host
must perform a new IDENTIFY sequence (see “Identify Command” on page 69). Also, since the hardware reset
does not recall the EEPROM values, it is recommended that a Reset command “Reset Command” on page 60 be
sent to each device to ensure that EEPROM values have been properly recalled. The following is the
recommended sequence following a hardware reset.
1. Switch EN on.
2. Wait the required delay (tUV “Power-Up Specifications” on page 13) after re-enabling the parts.
3. Identify devices
4. Send Reset command to each device starting from the top device.
(This operation recalls the EEPROM values and performs an EEPROM checksum calculation.)
5. Identify devices again (Identify is required after a software reset)
6. The host checks the EEPROM MISR Data Register and MISR Calculated Checksum register on all devices.
These two register values should match (see “Memory Checksum” on page 102).
7. Re-load all non-default setup parameters (like OV/UV limits) to all devices.
8. The host sends a Calc Register Checksum command to each device (see “Calc Register Checksum” on
page 61).
9. The host sends a Check Register checksum to verify that there is no error (see “Check Register Checksum”
on page 61). If there is a mismatch, the device sends a fault response back to the host (see “Memory
Checksum” on page 102).
3.3.3
Normal Mode
Normal mode consists of an active state and a standby state. In the standby state, all systems are powered and
the device is ready to perform an operation in response to commands from the host microcontroller. In the Active
state, the device is performing an operation, such as ADC conversion, open-wire detection, etc.
FN7672 Rev.11.00
Jun.12.20
Page 28 of 139
ISL78600
4.
4.1
4. System Hardware Connection
System Hardware Connection
Battery and Cell Balance Connection
The first consideration in designing a battery system around the ISL78600 is the connection of the cells to the IC.
The battery connection elements are split between the cell monitor connections (VCn) and the cell balance
connections (CBn).
4.1.1
Battery Connection
All inputs to the ISL78600 VCn pins are protected against battery voltage transients by external RC filters. The
basic input filter structure, with capacitors to the local ground, provides protection against transients and EMI for
the cell inputs. They carry the loop currents produced by EMI and should be placed as close to the battery
connector as possible. The ground terminals of the capacitors must be connected directly to a solid ground plane.
Do not use vias to connect these capacitors to the input signal path or to ground. Any vias should be placed in line
to the signal inputs so that the inductance of these forms a low pass filter with the grounded capacitors.
The resistors on the input filter provide a current limit function during hot plug events. The ISL78600 is calibrated
for use with 1kΩ series protection resistors at the VCn inputs. The VBAT connection uses a lower value input
resistor to accommodate the supply current of the ISL78600. As much as possible, the time constant produced by
the filtering applied to VBAT should be matched to that applied to the VCn monitoring inputs (see Figure 38).
LOCATE CLOSE
TO INPUT CONNECTOR
B14b
*EXAMPLE DIODE:
PTVS58VS1UTR
27
C1
820
B12
ISL78600
VBAT
58V*
VSS
180
VC12
22nF
820
B11
180
VC11
22nF
820
B10
180
VC10
22nF
820
B9
180
VC9
22nF
820
B3
180
22nF
820
B2
180
VC3
VC2
22nF
820
B1
180
VC1
22nF
820
B0
22nF
B0b
180
VC0
VSS
= “QUIET” GROUND
= “NOISY” GROUND
CELL BALANCE CIRCUITS NOT SHOWN IN THIS FIGURE
Figure 38. Typical Input Filter
FN7672 Rev.11.00
Jun.12.20
Page 29 of 139
ISL78600
4. System Hardware Connection
The filtered battery voltage connects to the internal cell voltage monitoring system. The monitoring system is
made up of three basic elements: a level shifter to eliminate the cell common-mode voltage, a multiplexer to
select a specific input, and an analog-to-digital conversion of the cell voltage.
Each ISL78600 is calibrated at a specific cell input voltage value, VNOM with an expected input series resistance
of 1kΩ. Cell voltage measurement error data is given in “Measurement Specifications” on page 11 for various
voltage and temperature ranges with voltage ranges defined with respect to VNOM. Plots showing the typical error
distribution over the full input range are included in “Typical Performance Curves” on page 21.
Another important consideration is the connection of cells in a stacked (non-overlapping) configuration. Mainly,
this involves how to connect the supply and ground pins at the junction of two devices. The diagram in Figure 39
shows the recommended minimum connection to the pack. It is preferred that there be four connection wires at
the intersection of two devices, but this does pose a cost constraint. To minimize the connections, the power and
monitor pins are connected separately, as shown in Figure 39. It is not recommended that all four wires connect
together with a single wire to the pack. There are two reasons for this. First, the power supply current for the
devices might affect the accuracy of the cell voltage readings. Second, if the single wire breaks, it is very difficult
for the system to tell specifically what happened through normal diagnostic methods.
An alternative circuit in Figure 40 shows the connection of one (or two) wires with additional Schottky diodes to
provide supply current paths to allow the device to detect a connection fault and to minimize the effects on cell
voltage measurements when there is an open connection to the battery.
100
820
ISL78600
ISL78600
VC2
22nF
100
22nF
100
22nF
VSS
820
VSS
100
VC12
22nF
VSS
100
VC11
VSS
Figure 39. Battery Connection Between Stacked Devices
(Option 1)
4.1.2
VSS2
ISL78600
VBAT
27
BOARD
CONNECTIONS
BOARD
CONNECTIONS
C1
VC0
22nF
ISL78600
VBAT
27
VSS2 180
820
VC0
VSS2
22nF
VC1
22nF
VSS2
820
VSS2 180
820
VC1
820
VC2
22nF
VSS2
820
180
820
C1
VSS
820
VSS
180
VC12
22nF
820
VSS
180
VC11
22nF
VSS
Figure 40. Battery Connection Between Stacked Devices
(Option 2)
Cell Balance Connection
The ISL78600 uses external MOSFETs for cell balancing. The gate drive for these is derived from on-chip current
sources on the ISL78600, which are 25µA nominally. The current sources are turned on and off as needed to
control the external MOSFET devices. The current sources are turned off when the device is in Shutdown mode
or Sleep mode. The ISL78600 uses a mix of N-channel and P-channel MOSFETs for the external balancing
function. The top three cell locations, Cells 10, 11, and 12 are configured to use P-channel MOSFETs while the
remaining cell locations, Cells 1 through 9 use N-channel MOSFETs. The mix of N-channel and P-channel devices
are used for the external FETs in order to remove the need for a charge pump, while providing a balance FET gate
voltage that is sufficient to drive the FET on, regardless of the cell voltages.
FN7672 Rev.11.00
Jun.12.20
Page 30 of 139
ISL78600
4. System Hardware Connection
Figures 41 and 42 show the circuit detail for the recommended balancing and cell voltage monitoring system. In
this configuration, the cell voltage is monitored after the cell balance resistor. This allows the system to monitor
the operation of the external balance circuits and is part of the fault detection system. However, this connection
prevents monitoring the cell voltage while cell balance is enabled for that cell.
Figure 41 shows the connection for VC12 to VC9. This connection for the upper 3 cells uses P-channel FETs,
while VC9 and below use N-channel FETs. Similarly, Figure 42 shows the connection for VC1 to VC3, using an Nchannel FETs, with the connections for VC3 through VC9 being similar. See Figure 52 on page 42 for a more
complete example.
R2
R5
VC12
22nF
C1
R1
Q1
C3
9V
100Ω
R3
R5
C1
R1
Q1
R3
R1
Q1
R5
R1
R4
R6
100Ω
R4
R6
100Ω
25µA
Q2
Q2
9V
100Ω
CB2
10kΩ
C1
25µA
R1
4MΩ
R3
VC9
22nF
C3
Q2
CB9
VC1
25µA
CB1
10kΩ
C1
R1
4MΩ
R2
4MΩ
22nF
R5
C3
25µA
9V
R5
9V
22nF
C2
R1
R3
25µA
C3
4MΩ
10kΩ
C1
VC2
22nF
C2
100Ω
22nF
R5
CB10
100Ω
C2
4MΩ
R3
VC10
C3
10kΩ
C2
10kΩ
C1
9V
22nF
C1
CB3
CB11
10kΩ
C2
Q2
4MΩ
C3
25µA
C3
VC11
22nF
VC3
22nF
C2
25µA
100Ω
100Ω
R5
R3
CB12
10kΩ
C2
4MΩ
9V
R5
VC0
22nF
VSS
VC8
ISL78600
ISL78600
Figure 41. Cell Monitor and Balance Circuit Arrangement Figure 42. Cell Monitor and Balance Circuit Arrangement
(VC8 to VC12)
(VC0 to VC3)
Table 3.
ISL78600 Input Filter Component Options
Q1 (P-channel)
with examples
Q2 (N-channel)
with examples
C1
C2
C3
R1
R2
R3
R4
R5
R6
30V A&O Semi AO3401
30V
A&O Semi AO3402
10nF
1nF
Not
populated
100k
820
720
1.54k
180
360
30V A&O Semi AO3401
30V
A&O Semi AO3402
10nF
1nF
100nF
100k
100
0
0
910
1900
60V Fairchild FDN5618
60V
Diodes DMN6140L-7
10nF
Not needed
Not
populated
330k
820
720
1.54k
180
360
60V Fairchild FDN5618
60V
Diodes DMN6140L-7
10nF
Not needed
100nF
330k
100
0
0
910
1900
Note: Q1 and Q2 should have low rDS(ON) specifications ( 1*tDAISY)
Figure 74. Command Timing to Avoid Daisy Buffer Underflow
7.4.2
Daisy Chain Receive Buffer
A 4-byte data buffer is provided between the Daisy Chain and SPI communications. This accommodates all single
transaction responses. Multiple byte responses, such as Identify, Read All Voltages, Read All Temperatures,
Read All Faults, and responses that may include a fault response from a device detecting an error, would overflow
this buffer. It is important therefore that the host microcontroller completes a read of the first byte of data before a
fifth byte arrives on the Master device’s daisy chain port and to clock data out from the SPI port faster than data is
clocked in through the Daisy port so as not to risk losing data.
For example, when performing the first step in an IDENTIFY operation (see “Identify Command” on page 69) the
daisy chain top device returns a 4-byte response plus 14 extra zeros (because it does not yet know how many
devices are in the stack.) If the Host does not read the first byte from the Master before the 32nd daisy clock, the
extra zeros overwrite the first byte of the response. In another example, a Read All Faults returns 22 bytes. It is
important for the Host to read data from the ISL78600 faster than 4 bytes every 31.5 Daisy clocks. (see Figure 75
on page 79).
DOUT
CS
RECEIVE IDENTIFY RESPONSE
SCK
≤ 31.5 tD
≤ 31.5 tD
DATA READY
Daisy Clocks
Master
Daisy Port
DHI2/DLO2
8* tD
8* tD
8* tD
8* tD
8* tD
8* tD
8* tD
8* tD
8* tD
8* tD
8* tD
8* tD
Extra Bytes during “Read All” responses, fault responses, and first Identify Response.
A fault response may precede command response, increasing number of returned bytes.
The first Identify Response has 14 extra clocks, because stack size is not yet known.
SPI must clock out 4 bytes before the Daisy can clock in 4 bytes to prevent buffer overflow
Figure 75. Example Worst Case Timing to Avoid Daisy Buffer Overflow
FN7672 Rev.11.00
Jun.12.20
Page 79 of 139
ISL78600
7.4.3
7. Communications
Communication Sequences
All daisy chain device responses are 4-byte sequences, except for the responses to the Read All command. All
responses start with the Device Address and use a 4-bit CRC. The response to the “Read All Commands” is to
send a normal 4-byte data response for the first data segment and continue sending the remaining data segments
in 3-byte sections composed of data address, data, and CRC. This creates an anomaly with the normal CRC
usage in that the first four bytes have a 4-bit CRC at the end (operating on 3.5 bytes of data) while the remaining
bytes have a CRC, which only operates on 2.5 bytes. The host microcontroller, having requested the data, must
be prepared for this.
Daisy chain devices require Device Address information to be added to the basic command set. Daisy chain
writes are 4-byte sequences. Daisy chain reads are three bytes. All commands, except register write operations,
are treated as reads. Daisy chain communications employ a 4-bit CRC (Cyclic Redundancy Check) using a
polynomial of the form 1 + X + X4. The first four bits of each daisy chain transmission contain the Device Address,
which can be any number from 0001 to 1110. All devices respond to the “Address All” (1111) and Identify (0000)
Device Addresses. The fifth bit is set to ‘1’ for write and ‘0’ for read. The rules for daisy chain installations are
shown in Table 30.
Table 30. ISL78600 Data Interpretation Rules for Daisy Chain Installations
Fifth Bit
(R/W)
Page
Data
Address
Interpretation
Device Address [3:0] (Nonzero)
0
011
001000
Measure command. Data address is followed by 6-bit element address.
0000
0
011
001001
Identify command. Data address is followed by device count data.
Device Address [3:0] (Nonzero)
0
Any
All other
Device Read command. Data address is followed by 6 zeros.
Device Address [3:0] (Nonzero)
1
Any
Any
First Four Bits in Sequence
7.4.4
Device Write command.
CRC Calculation
Daisy chain communications employ a 4-bit CRC using a polynomial of the form 1 + X + X4. The polynomial is
implemented as a 4-stage internal XOR standard linear feedback shift register as shown in Figure 76. The CRC
value is calculated using the base command data only. The CRC value is not included in the calculation.
The host microcontroller calculates the CRC when sending commands or writing data. The calculation is repeated
in the ISL78600 and checked for compliance. The ISL78600 calculates the CRC when responding with data
(device reads). The host microcontroller then repeats the calculation and checks for compliance.
DIN
+
+
FF0
FF1
FF2
FF3
Figure 76. 4-Bit CRC Calculation
FN7672 Rev.11.00
Jun.12.20
Page 80 of 139
ISL78600
7. Communications
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Figure 77. Example CRC Calculation Routine (Visual BASIC)
7.5
Daisy Chain Commands/Responses
When used in a daisy chain system each individual device dynamically assigns itself a unique address
(see “Identify Command” on page 69). In addition, all daisy chain devices respond to a common address allowing
them to be controlled simultaneously. For example, when using the Scan Voltages and Balance Enable
commands (see “Communication Timing” on page 84).
Examples of the various read and write command structures for daisy chain installations are shown in Figures 79
through 84. The MSB is transmitted first and the LSB is transmitted last.
FN7672 Rev.11.00
Jun.12.20
Page 81 of 139
ISL78600
7. Communications
CS
SCLK
DOUT
TRISTATE
COMMAND
DIN
0 0 0 1 1 0 1 0
1 0 0 1 0 1 0 0
R
DEVICE /W PAGE
ADDR
ADDR
1 1 0 0 0 0 0 0
1 1 0 0 0 0 0 0
DATA TO WRITE
DATA
ADDRESS
CRC
DEVICE
ADDRESS
(23:20)
R/W
Figure 78. SPI Half Duplex (Daisy Chain) Example: WRITE Device 1, Device Setup Register
1
0 0 1 1
1 1 1
MSB
DATA
ADDRESS
(15:10)
PAGE
(18:16)
0 0 1 0
BYTE 2
CRC
(3:0)
ZERO
(9:4)
1 0 0 0
0 0 0 0 1 1 1 0
BYTE 1
LSB
BYTE 0
DEVICE
ADDRESS
(23:20)
R/W
Figure 79. Daisy SLEEP Command
1 1 1 1
0 0 1
MSB
PAGE
(18:16)
DATA
ADDRESS
(15:10)
1 0 0 1
BYTE 2
ZERO
(9:4)
1 1 1 0
0 0 0 0
CRC
(3:0)
0 0 1 1
LSB
BYTE 0
BYTE 1
1
DEVICE
ADDRESS
(23:20)
1 0
MSB
0 1
R/W
Figure 80. Daisy WAKEUP Command
PAGE
(18:16)
DATA
ADDRESS
(15:10)
0
0 1 1 0
0 0 0 0
BYTE 2
1 0 0
ZERO
(9:4)
CRC
(3:0)
0 0 0 0 1
1 1 1
LSB
BYTE 0
BYTE 1
DEVICE
ADDRESS
(23:20)
1 0
MSB
0 1
R/W
Figure 81. Daisy SCAN VOLTAGES Command: Device 9,
PAGE
(18:16)
DATA
ADDRESS
(15:10)
0
0 0 1 0
0 0 1 1
BYTE 2
BYTE 1
1 0 0
ZERO
(9:4)
CRC
(3:0)
0 0 0 0 1
1 0 0
BYTE 0
LSB
Figure 82. Daisy READ Command: Device 9, Cell 7 Register
FN7672 Rev.11.00
Jun.12.20
Page 82 of 139
7. Communications
DEVICE
ADDRESS
(23:20)
0 1
MSB
0 0
R/W
ISL78600
PAGE
(18:16)
DATA
ADDRESS
(15:10)
0
0 1 1 0
0 1 0 0
BYTE 2
ELEMENT
ADDRESS
(9:4)
0 0 0
CRC
(3:0)
0 1 0 1 0
1 0 1
LSB
BYTE 0
BYTE 1
DEVICE
ADDRESS
(31:28)
0 1
1 1
MSB
R/W
Figure 83. Daisy MEASURE Command: Device 4, Cell 5 Voltage
PAGE
(26:24)
DATA
ADDRESS
(23:18)
1
0 1 0 0
1 0 0 1
BYTE 3
CRC
(3:0)
DATA
(17:4)
0 0 0 1
1 1 1
1 1
1 1 1
1 1 1 1 0 0
0
BYTE 0
LSB
BYTE 1
BYTE 2
Figure 84. Daisy WRITE Command: Device 7, External Temperature Limit Value = 14’h0FFF
DEVICE
ADDRESS
(31:28)
1
0 0 1
MSB
R/W
Response examples are shown in Figures 85 through 88.
PAGE
(26:24)
DATA
ADDRESS
(23:18)
0
0 0 1 0
0 0 1
BYTE 3
CRC
(3:0)
DATA
(17:4)
1 1 0 1
0 1 1 1
0
0 0 0 1 0 1 0 0 1
BYTE 1
BYTE 2
0 0
LSB
BYTE 0
DEVICE
ADDRESS
(31:28)
1
0 1 0
MSB
R/W
Figure 85. Daisy RESPONSE: Device 9, Cell 7 Voltage = 14’h170A (3.6V)
PAGE
(26:24)
DATA
ADDRESS
(23:18)
0
0 1 1 0
0 1 1
BYTE 3
CRC
(3:0)
ZEROS
(17:4)
0 0 0 0
0 0 0 0
0
0 0 0 0 0 0 0 0 1
BYTE 1
BYTE 2
0 0
LSB
BYTE 0
DEVICE
ADDRESS
(31:28)
R/W
Figure 86. Daisy RESPONSE: Device 10, ACK
0 0 0
0 0
MSB
0
BYTE 3
PAGE
(26:24)
DATA
ADDRESS
(23:18)
1 1 0 0
1 0 0 1
BYTE 2
DEVICE TYPE/
ADDRESS
(17:4)
0 0 0 0
0 0
0 0 1
BYTE 1
CRC
(3:0)
1 0 1
0 0 0 1 1 0
BYTE 0
LSB
Figure 87. Daisy RESPONSE: Device 4, IDENTIFY (Middle Stack Device)
FN7672 Rev.11.00
Jun.12.20
Page 83 of 139
ISL78600
7. Communications
R/W
DATA
CELL 11
DATA
CELL 12
CRC
CRC
ADDRESS 0BH
DATA
DATA
PAGE ADDRESS 0CH
(291:288)
(287:264)
(287:282)
(281:268)
(311:306)
(305:292)
(314:312
1 0 0 1 0 0 0 1 0 0 1 1 0 0 1 0 1 1 1 0 0 0 0 1 0 1 0 0 1 1 0 0 0 0 1 0 1 1 0 1 0 1 1 1 0 0 0 0 1 0 1 0 0 0 0 1
DEVICE
ADDRESS
(319:316)
MSB BYTE 39
BYTE 38
BYTE 37
BYTE 36
DATA
CELL 10
ADDRESS
DATA
CRC
0AH (263:258)
(257:244)
0 0 0 1 1 1 0 1 1 1 1 0 0 0 0 1 0 1 0 0 0 0 0 1
BYTE 32
BYTE 31
BYTE 35
DATA
ADDRESS
BYTE 34
PACK VOLTAGE
DATA
(17:4)
BYTE 33
CRC
(3:0)
0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 0 1 1 1 1 0 0 0 1
BYTE 30
BYTE 2
BYTE 1
BYTE 0
LSB
Figure 88. Daisy RESPONSE: Device 9, READ All Cell Voltage Data
7.6
Communication Timing
Collecting voltage and temperature data from daisy chained ISL78600 devices consists of three separate types of
operations: A command to initiate measurement, the Measurement itself, and a command and response to
retrieve data.
Commands are the same for all types of operations, but the timing is dependent on the number of devices in the
stack, the daisy chain clock rate, and the SPI clock rate.
Actual measurement operations occur within the device and start with the last bit of the command byte and end
with data being placed in a register. Measurement times are dependent on the ISL78600 internal clock. This clock
has the same variations (and is related to) as the daisy chain clock.
Responses have different timing calculations, based on the position of the addressed device in the daisy chain
stack and the daisy chain and SPI clock rates.
7.7
Measurement Timing Diagrams
All measurement timing is derived from the ISL78600’s internal oscillators. The figures shown in the following as
typical are those obtained with the oscillators operating at their nominal frequencies and with any synchronization
timing also at nominal value. Maximum figures are those obtained with the oscillators operating at their minimum
frequencies and with the maximum time for any synchronization timing.
Measurement timing begins with a Start Scan signal. This signal is generated internally by the ISL78600 at the
last clock falling edge of the Scan or Measure command. (This is the last falling edge of the SPI clock in the case
of a stand-alone or master device, or the last falling edge of the daisy chain clock, in the case of a daisy chain
device). Daisy chain middle or top devices impose additional synchronization delays. Communications sent on
the SPI port are passed on to the master device’s daisy chain port at the end of the first byte of data. Then, for
each device, there is an additional delay of one daisy chain clock cycle.
On receiving the Start Scan signal, the device initializes measurement circuits and proceeds to perform the
requested measurement(s). When the measurements are made, some devices perform additional operations,
such as checking for overvoltage conditions. The measurement command ends when registers are updated. At
this time the registers can be read using a separate command. A detailed timing breakdown is provided for each
measurement type as follows.
See Figure 89 for the measurement timing for a stand-alone device.
See Figure 90 for the measurement timing for daisy chain devices.
FN7672 Rev.11.00
Jun.12.20
Page 84 of 139
ISL78600
7. Communications
Table 34 on page 93 through Table 39 on page 95 give the typical and maximum timing for the critical elements of
the device internal measurement process. Each table shows the timing from the last edge of the Scan command
clock to the completion of the internal register update.
SCAN COMMAND
READ REGISTER COMMAND
DIN
SCK
DOUT
Note
INTERNAL SCAN
Note
Note
Note
MEASURE
INTERNAL OPERATION
UPDATE REGISTERS
See Table 34 through Table 39
Note: Ignore these output bytes
Figure 89. Scan/Measure Command Timing With Response (Stand-Alone)
SPI SCAN COMMAND
DIN
SCK
INTERNAL
OPERATION (MASTER)
SCAN/MEASURE
UPDATE REGISTERS
See Table 34 through Table 39
See Figure 91 on page 87, Table 31 and Table 32 on page 92
DAISY CHAIN SCAN COMMAND
UNIT 2
UNIT 6
4 DAISY CHAIN CLOCKS
INTERNAL OPERATION
(DAISY CHAIN UNIT 6)
SCAN/MEASURE
UPDATE REGISTERS
See Table 34 through Table 39
Figure 90. Scan/Measure Timing (6 Device Daisy Chain)
FN7672 Rev.11.00
Jun.12.20
Page 85 of 139
ISL78600
7. Communications
SPI SCAN COMMAND
DIN
SCK
INTERNAL
OPERATION (MASTER)
SCAN/MEASURE
UPDATE REGISTERS
See Table 34 through Table 39
See Figure 91 on page 87, Table 31 and Table 32 on page 92
DAISY CHAIN SCAN COMMAND
UNIT 2
UNIT 6
4 DAISY CHAIN CLOCKS
INTERNAL OPERATION
(DAISY CHAIN UNIT 6)
SCAN/MEASURE
UPDATE REGISTERS
See Table 34 through Table 39
Scan/Measure Timing (6 Device Daisy Chain)
FN7672 Rev.11.00
Jun.12.20
Page 86 of 139
ISL78600
7.8
7. Communications
Command Timing Diagram
SPI COMMAND
DIN
tCS:WAIT
CS
MASTER
SCK
tLEAD
tLAG
tSPI
tD
t1A
DAISY CLOCK
(P2 TRANSMIT)
8* tD
8* tD
8* tD
DEVICE 2
2 * tD
(P1 RECEIVE)
8* tD
8* tD
8* tD
8* tD
12 * tD
SCAN
2µs
2 * tD
4 * tD
DEVICE 6
12 * tD
8* tD
(Note 21) (Note 22)
(P1 RECEIVE)
(FROM DEVICE 5)
8* tD
8* tD
8* tD
8* tD 8 * tD
SCAN
2µs
2 * tD
DEVICE 14
8 * tD
(P1 RECEIVE)
(FROM DEVICE 13)
8* tD
8* tD
8* tD
8* tD
SCAN
2µs
2 * tD
t1B
COMMANDS:
• SCAN VOLTAGES
• SCAN TEMPERATURES
t1C
• SCAN MIXED
To Start of Scan (Master)
t 1A = t SPI 8 + t LEAD + t LAG 3 + 2 t CSWAIT
• SCAN WIRES
• SCAN ALL
To Start of Scan (Top/Middle)
• MEASURE
t 1B = t SPI 8 + t LEAD + t LAG + t D 28 + n – 2 + 2s
• READ
To End of Command
• WRITE
t 1C = t SPI 8 + t LEAD + t LAG + t D 34 + N – 2
• SCAN CONTINUOUS
• SCAN INHIBIT
where:
• SLEEP
tSPI = SPI clock period
tD = Daisy chain clock period
tCS:WAIT = CS High time
tLEAD = CS Low to first SPI Clock
tLAG = Last SPI Clock CS High
n = Stack position of target device
• NAK
• ACK
• BALANCE INHIBIT
• CALC CHECKSUM
• CHECK CHECKSUM
Notes:
21. Master adds extra byte of zeros as part of daisy protocol
22. Master adds N-2 clocks to allow communication to the end of the chain.
Figure 91. Command Timing
FN7672 Rev.11.00
Jun.12.20
Page 87 of 139
ISL78600
7.9
7. Communications
Response Timing Diagrams
Responses are different for Master, Middle, and Top devices. The response timings are shown in Figures 92, 92,
and 93. (Continued)
DOUT
MASTER
CS
SCK
tCS
DATA READY
2µs
DEVICE 6 DEVICE 2
(P2 RECEIVE)
(P1 TRANSMIT)
tDR:WAIT
8* tD
2µs
DEVICE 14
tLAG
tLEAD
tDR:SP
8* tD
8* tD
8* tD
8* tD
8* tD
8* tD
8* tD
8* tD
4 * tD
8* tD
(P1 TRANSMIT)
2*tD
8 * tD
8* tD
8* tD
8* tD
8* tD
12 * tD
4*tD
8 * tD
8* tD
(P1 TRANSMIT)
8* tD
8* tD
DAISY CHAIN ACK RESPONSE
2µs
t2
COMMAND
t2 = 8 t SPI + t DRSP + t DRWAIT + t CS + t LEAD + t LAG D – t DRSP + t D 50 + N – 2 + 4s
where:
tSPI = SPI clock period
tD = Daisy chain clock period
tCS = Host delay from DATA READY Low to the CS Low
tDRSP = CS High to DATA READY High
tDRWAIT = DATA READY High time
tLEAD = CS Low to first SPI Clock
tLAG = Last SPI Clock CS High
N = Stack position of TOP device
D = Number of data bytes
D = 4 for one register read (or ACK/NAK/Identify Response)
D = 40 for read all voltages
D = 22 for read all temperatures
D = 22 for read all faults
D = 43 for read all setup
Figure 92. Response Timing (Master Device)
FN7672 Rev.11.00
Jun.12.20
Page 88 of 139
ISL78600
7. Communications
tCS
DOUT
MASTER
CS
tLEAD
tDR:SP
DATA READY
2µs
DEVICE 6
DEVICE 2
(P2 RECEIVE)
(P1 TRANSMIT)
2µs
8* tD
8* tD
8* tD
8* tD
8* tD
8* tD
8* tD
8* tD
4* tD
(P1 TRANSMIT)
8* tD
8* tD
n
(P2 RECEIVE)
(FROM DEVICE 7)
8* tD
2*tD
DEVICE 14
tLAG
SCK
(P1 TRANSMIT)
8 * tD
N
8* tD
8* tD
8* tD
Note 24
8* tD
8* tD 4*tD
DAISY CHAIN READ DATA RESPONSE
2µs
8* tD
7*tD (= N - n - 1)
8* tD
8* tD
8* tD
8* tD
7* tD
DAISY CHAIN ACK RESPONSE Note 23
2µs
RESPONSE
COMMAND
t3
t4
t3 = t D 50 + N – n – 1 + 4s
t4 = t SPI 8 + t CS + t LEAD + t LAG + t DRSP + t D D 8 + n – 2 + 2s
where:
tD = Daisy Chain clock period
tSPI = SPI Clock Period
N = Stack position of TOP device
n = Stack position of middle stack device
tCS = Delay imposed by host from DATA READY to the CS Low.
D = Number of bytes in the Middle stack device response e.g. read all cell data = 40 bytes,
Register or ACK response = 4 bytes.
Notes:
23. Top device adds (N - n - 1) Daisy clocks to allow communications to the targeted middle stack device.
24. Middle stack device adds (n - 2) Daisy clocks to allow communications to the master device.
Figure 93. Response Timing (Middle Stack Device)
FN7672 Rev.11.00
Jun.12.20
Page 89 of 139
ISL78600
7. Communications
tCS
DOUT
CS
MASTER
tLEAD
tDR:SP
DATA READY
2µs
DEVICE 6 DEVICE 2
(P2 RECEIVE)
DEVICE 14
tLAG
SCK
(P1 TRANSMIT)
2µs
8* tD
8* tD
8* tD
8* tD
8* tD
8* tD
8* tD
8* tD
4 * tD
8* tD
(P1 TRANSMIT)
2*tD
8 * tD
COMMAND
2µs
8* tD
8* tD
8* tD
8* tD
12 * tD
4*tD
8 * tD
8* tD
(P1 TRANSMIT)
8* tD
8* tD
DAISY CHAIN DATA RESPONSE
T5
t5 = t SPI 8 + t LEAD + t LAG + t DRSP + t CS + t D D 8 + 10 + N – 2 + 4s
where:
tSPI = SPI clock period
tD = Daisy chain clock period
tCS = Host delay from DATA READY to the CS Low.
tDRSP = CS High to DATA READY High
tLEAD = CS Low to first SPI Clock
tLAG = Last SPI Clock CS High
N = stack position of TOP device
D = Number of bytes in response
Figure 94. Response Timing (Top Device)
FN7672 Rev.11.00
Jun.12.20
Page 90 of 139
ISL78600
8.
8.1
8. System Timing Tables
System Timing Tables
Command Timing Tables
The command timing Table 31 includes the time from the start of the command to the start of an internal operation
for each device in a stack. Table 32 shows the time required for the command to complete. For a stand-alone
device the two values are the same, because the internal operation starts at the end of the command. For a daisy
chain operation, the internal operation begins before the end of the command.
When calculating overall timing for a command, start with the time from start of the command to the start of the
internal operation for the Target device. Add to this the time for the internal operation, see “Measurement Timing
Tables” on page 93. Add to this the time it takes to read back the data. See “Response Timing Tables” on page 96.
Also needed is a wait time between sending each command (see Table 33 on page 92).
When using the Address All option, the command timing for the Top device in the stack determines when the
command ends, but use the Time to Start of Scan for each device to determine when that device begins its
internal operation. For example, in a stack of six devices, it takes 90.9µs for the command to complete, but
internal operations start at 13.8µs for the Master, 68.7µs for Device 2, 70.9µs for Device 3, etc.
In Tables 31 and 32, the calculation assumes a daisy chain (and internal) clock that is 10% slower than the
nominal and an SPI clock that is running at the nominal speed (because the SPI clock is normally crystal
controlled.) For the 500kHz daisy setting, timing assumes a 450kHz clock.
Table 31. Time to Start of Internal Operation
SPI Clock = 2MHz
Time to Start of Internal Operation for
Target Device
Daisy Clock = 500kHz
Daisy Clock = 250kHz
Units
1
17.5
17.5
µs
2
68.7
130.9
µs
3
70.9
135.4
µs
4
73.2
139.8
µs
5
75.4
144.3
µs
6
77.6
148.7
µs
7
79.8
153.2
µs
8
82.1
157.6
µs
9
84.3
162.1
µs
10
86.5
166.5
µs
11
88.7
170.9
µs
12
90.9
175.4
µs
13
93.2
179.8
µs
14
95.4
184.3
µs
FN7672 Rev.11.00
Jun.12.20
Page 91 of 139
ISL78600
8. System Timing Tables
Table 32. Time to End of Command
SPI Clock = 2MHz
Time to End of Command for Number of Devices
Daisy Clock = 500kHz
Daisy Clock = 250kHz
Units
1
17.5
17.5
µs
2
82.0
157.6
µs
3
84.2
162.0
µs
4
86.5
166.5
µs
5
88.7
170.9
µs
6
90.9
175.3
µs
7
93.1
179.8
µs
8
95.3
184.2
µs
9
97.6
188.7
µs
10
99.8
193.1
µs
11
102.0
197.6
µs
12
104.2
202.0
µs
13
106.5
206.5
µs
14
108.7
210.9
µs
8.1.1
Sequential Daisy Chain communications
When sending a sequence of commands to the master device, the host must allow time, after each response and
before sending the next command, for the daisy chain ports of all stack devices (other than the master) to switch
to receive mode. This wait time is equal to eight daisy chain clock cycles and is imposed from the time of the last
edge on the Master’s input daisy chain port to the last edge of the first byte of the subsequent command on the
SPI (see Figure 95). The minimum recommended wait time, between the host receiving a response and sending
the next command, is given in Equation 4. For definition of terms, see Figure 94. Also, see Table 33.
(EQ. 4)
t WAIT = t CLR – 2 8 t SPI + t LEAD + t LAG + t DRSP + t CS
Table 33. Minimum Recommended Communications Wait Time
Daisy Chain Data Rate (kHz)
Maximum Time for Daisy Chain Ports to Clear. See Figure 95.
ISL78600
DIN
500
250
125
62.5
UNITS
18
36
72
144
µs
NEXT SPI
COMMAND
SPI
COMMAND
SPI RESPONSE
DOUT
Equation 4
CS
SCK
DATAREADY
UNIT 2
Minimum Wait time
between commands.
See Table 33
UNIT n
Figure 95. Minimum Wait Time Between Commands (Daisy Chain Response - TOP Device)
FN7672 Rev.11.00
Jun.12.20
Page 92 of 139
ISL78600
8.2
8.2.1
8. System Timing Tables
Measurement Timing Tables
Scan Voltages
The Scan Voltages command initiates a sequence of measurements starting with a scan of each cell input from
Cell 12 to Cell 1, followed by a measurement of pack voltage. Additional measurements are then performed for
the internal temperature and to check the connection integrity test of the VSS and VBAT inputs. The process
completes with the application of calibration parameters and the loading of registers. Table 34 shows the times
after the start of scan that the cell voltage inputs are sampled. The voltages are held until the ADC completes its
conversion.
Table 34. Scan Voltages Function Timing - Daisy Chain Master or Stand-Alone Device
Elapsed Time (µs)
EVENT
TYP
MAX
Sample Cell 12
17
19
Sample Cell 11
38
42
Sample Cell 10
59
65
Sample Cell 9
81
89
Sample Cell 8
102
112
Sample Cell 7
123
135
Sample Cell 6
144
159
Sample Cell 5
166
182
Sample Cell 4
187
206
Sample Cell 3
208
229
Sample Cell 2
229
252
Sample Cell 1
251
276
Complete Cell Voltage Capture (ADC complete) Sample VBAT
304
334
Complete VBAT Voltage Capture
318
349
Measure Internal Temperature
423
465
Complete VSS Test
550
605
Complete VBAT Test
726
799
Load Registers
766
842
FN7672 Rev.11.00
Jun.12.20
Page 93 of 139
ISL78600
8.2.2
8. System Timing Tables
Scan Temperatures
The Scan Temperatures command turns on the TEMPREG output and, after a 2.5ms settling interval, samples
the ExT1 to ExT4 inputs. TEMPREG turns off on completion of the ExT4 measurement. The Reference Voltage,
IC Temperature, and Multiplexer loopback function are also measured. The sequence is completed with
respective registers being loaded.
Table 35. Scan Temperatures Function Timing – Daisy Chain Master or Stand-Alone Device
Elapsed Time (µs)
Event
Typical
Maximum
2
2
2518
2770
Sample ExT4
2564
2820
Sample Reference
2584
2842
Measure Internal Temperature
2689
2958
Load Registers
2689
2958
Turn On TEMPREG
Sample ExT1
~
8.2.3
Scan Mixed
The Scan Mixed command performs all the functions of the Scan Voltages command but interposes a
measurement of the ExT1 input between the Cell 7 and Cell 6 measurements.
Table 36. Scan Mixed Function Timing – Daisy Chain Master or Stand-Alone Device
Elapsed Time (μs)
Event
Typical
Maximum
Sample Cell 12
17
19
Sample Cell 11
38
42
Sample Cell 10
59
65
Sample Cell 9
80
88
Sample Cell 8
101
111
Sample Cell 7
122
134
Complete Cell Voltage Capture, Cells 12-7 and Sample Ext1
176
194
Complete Ext1 Capture
192
211
Sample Cell 6
207
228
Sample Cell 5
228
251
Sample Cell 4
249
274
Sample Cell 3
270
297
Sample Cell 2
291
321
Sample Cell 1
312
344
Complete Cell Voltage Capture Cells 6-1 ad Sample VBAT
367
404
Complete VBAT Voltage Capture
381
419
Load Registers
829
911
FN7672 Rev.11.00
Jun.12.20
Page 94 of 139
ISL78600
8.2.4
8. System Timing Tables
Scan Wires
The Scan Wires command initiates a sequence in which each input is loaded in turn with a test current for a
duration of 4.5ms (default). At the end of this time the input voltage is checked and the test current is turned off.
The result of each test is recorded and the Open-Wire Fault and Fault Status registers are updated (data latched)
at the conclusion of the tests.
Table 37. Scan Wires Function Timing – Daisy Chain Master or Stand-Alone Device
Elapsed Time (ms)
Event
Typical
Maximum
Turn On VC0 Current
0.03
0.05
Test VC0
4.5
5.0
Turn On VC1 Current
4.6
5.1
Test VC1
9.1
10.0
Turn On VC12 Current
54.9
60.3
Test VC12
59.4
65.3
Load Registers
59.4
65.3
~
8.2.5
Scan All
The Scan All command combines the Scan Voltages, Scan Wires, and Scan Temperatures commands into a
single scan function.
Table 38. Scan All Function Timing – Daisy Chain Master or Stand-Alone Device
Elapsed Time (ms)
Event
Typical
Maximum
0
0
Start Scan Wires
0.8
0.9
Start Scan Temperatures
60.1
66.2
Complete sequence
62.8
69.1
Start Scan Voltages
8.2.6
Measure Command
Single parameter measurements of the cell voltages, Pack Voltage, ExT1 to ExT4 inputs, IC temperature, and
Reference voltage are performed using the Measure command.
Table 39. Various Measure Function Timings – Daisy Chain Master or Stand-Alone Device
Elapsed Time (µs)
Event
Typical
Maximum
Measure Cell Voltage
178
196
Measure Pack Voltage
122
134
Measure ExT Input
2517
2768
Measure IC Temperature
106
116
Measure Reference Voltage
106
116
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8.3
8. System Timing Tables
Response Timing Tables
Response Timing depends on the number of devices in the Stack, the position of the device in the stack, and how
many bytes are read back. The following are the four types of responses:
• Single register read or ACK/NAK responses, where four bytes are returned by the Read Command
• Read All Voltage response, which returns 40 bytes
• Read all Temps or Read All Faults responses, which returns 22 bytes
• Read All Setup Registers response, which returns 43 bytes
In the following tables, the Master, Middle, and Top device response times for any number of daisy chain devices
are included with the command timing for that configuration. The right hand column shows the total time to
complete the read operation. This is calculated in Equation 5:
(EQ. 5)
N T COMMAND + N – 2 T MID + T TOP + T MASTER
where N = Number of devices in the stack.
In Tables 40 through 45, internal and daisy clocks are assumed to be slow by 10% and the SPI clock is assumed
to be at the stated speed.
For an example, consider a stack of six devices. To get the full scan time with a daisy clock of 500kHz and SPI
clock of 2MHz, it takes 77.6µs from the start of the Scan All command to the start of the internal scan of the Top
device (see Table 31), 842µs to complete an internal scan of all voltages (see Table 34 on page 93), 5.337ms to
read all cell voltages from all devices (see Table 42 on page 97), and 18µs delay before issuing another
command. In this case, all cell voltages in the host controller can be updated every 6.28ms.
8.3.1
4-Byte Response
Tables 40 and 41 show the calculated timing for read operations for 4 byte responses. This is the timing for an
ACK or NAK, as well as Read Register command.
8.3.2
40-Byte Response
Tables 42 and 43 on page 98 show the calculated timing for read operations for 40-byte responses. Specifically,
this is the timing for a Read All Voltages command.
Table 40. Read Timing (Max): 4-Byte Response, Daisy Clock = 500kHz, SPI Clock = 2MHz
Top Stack
Device
Command Time
to Start of Response
(Each Daisy Device) (µs)
2
80
138
3
82
141
4
85
5
6
Time to Complete Response (Daisy Chain) (µs)
Top Device
All Devices
Command + Response
All Devices (µs)
110
249
409
201
113
454
701
143
203
115
665
1003
87
145
206
117
879
1313
89
147
208
119
1098
1632
7
91
150
210
121
1322
1960
8
93
152
212
124
1549
2297
Master Device Middle Device
9
96
154
215
126
1782
2642
10
98
156
217
128
2019
2997
11
100
158
219
130
2260
3360
12
102
161
221
133
2505
3733
13
105
163
223
135
2756
4114
14
107
165
226
137
3010
4504
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8. System Timing Tables
Table 41. Read Timing (Max): 4-Byte Response, Daisy Clock = 250kHz, SPI Clock = 2MHz
Top
Stack
Device
Command Time
to Start of Response
(Each Daisy Device) (µs)
2
156
227
3
160
232
383
208
823
1303
4
165
236
388
213
1225
1883
5
169
241
392
217
1635
2479
6
173
245
397
221
2054
3094
7
178
250
401
226
2482
3726
8
182
254
406
230
2918
4377
9
187
258
410
235
3364
5044
10
191
263
415
239
3819
5730
Time to Complete Response (Daisy Chain) (µs)
Master Device Middle Device
Top Device
All Devices
Command + Response
All Devices (µs)
204
431
742
11
196
267
419
244
4282
6434
12
200
272
423
248
4754
7155
13
205
276
428
253
5236
7894
14
209
281
432
257
5726
8651
Table 42. Read Timing (Max): 40-Byte Response, Daisy Clock = 500kHz, SPI Clock = 2MHz
Top
Stack
Device
Command Time
to Start of Response
(Each Daisy Device) (µs)
2
80
642
3
82
645
4
85
5
6
Time to Complete Response (Daisy Chain) (µs)
Top Device
All Devices
Command + Response
All Devices (µs)
750
1393
1553
841
753
2238
2485
647
843
755
3089
3427
87
649
846
757
3943
4377
89
651
848
759
4802
5336
7
91
654
850
761
5666
6304
8
93
656
852
764
6533
7281
Master Device Middle Device
9
96
658
855
766
7406
8266
10
98
660
857
768
8283
9261
11
100
662
859
770
9164
10264
12
102
665
861
773
10049
11277
13
105
667
863
775
10940
12298
14
107
669
866
777
11834
13328
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8. System Timing Tables
Table 43. Read Timing (Max): 40-Byte Response, Daisy Clock = 250kHz, SPI Clock = 2MHz
Top
Stack
Device
Command Time
to Start of Response
(Each Daisy Device) (µs)
2
156
731
3
160
736
4
165
740
5
169
6
Time to Complete Response (Daisy Chain) (µs)
Top Device
All Devices
Command + Response All
Devices (µs)
1484
2215
2526
1663
1488
3887
4367
1668
1493
5569
6227
745
1672
1497
7259
8103
173
749
1677
1501
8958
9998
7
178
754
1681
1506
10666
11910
8
182
758
1686
1510
12382
13841
9
187
762
1690
1515
14108
15788
10
191
767
1695
1519
15843
17754
Master Device Middle Device
11
196
771
1699
1524
17586
19738
12
200
776
1703
1528
19338
21739
13
205
780
1708
1533
21100
23758
14
209
785
1712
1537
22870
25795
8.3.3
22-Byte Response
Table 44 and Table 45 show the calculated timing of read operations for 22-byte responses. This is the timing for
Read All Temperature or Read All Faults command.
Table 44. Read Timing (Max): 22-Byte Response, Daisy Clock = 500kHz, SPI Clock = 2MHz
Top
Stack
Device
Command Time
to Start of Response
(Each Daisy Device) (µs)
2
80
390
3
82
393
4
85
5
Time to Complete Response (Daisy Chain) (µs)
Top Device
All Devices
Command + Response
All Devices (µs)
430
821
981
521
433
1346
1593
395
523
435
1877
2215
87
397
526
437
2411
2845
6
89
399
528
439
2950
3484
7
91
402
530
441
3494
4132
8
93
404
532
444
4041
4789
9
96
406
535
446
4594
5454
10
98
408
537
448
5151
6129
11
100
410
539
450
5712
6812
12
102
413
541
453
6277
7505
13
105
415
543
455
6848
8206
14
107
417
546
457
7422
8916
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ISL78600
8. System Timing Tables
Table 45. Read Timing (Max): 22-Byte Response, Daisy Clock = 250kHz, SPI Clock = 2MHz
Top
Stack
Device
Command Time
to Start of Response
(Each Daisy Device) (µs)
2
156
479
3
160
484
4
165
488
5
169
6
Time to Complete Response (Daisy Chain) (µs)
Top Device
All Devices
Command + Response
All Devices (µs)
844
1323
1634
1023
848
2355
2835
1028
853
3397
4055
493
1032
857
4447
5291
173
497
1037
861
5506
6546
7
178
502
1041
866
6574
7818
8
182
506
1046
870
7650
9109
9
187
510
1050
875
8736
10416
10
191
515
1055
879
9831
11742
Master Device Middle Device
11
196
519
1059
884
10934
13086
12
200
524
1063
888
12046
14447
13
205
528
1068
893
13168
15826
14
209
533
1072
897
14298
17223
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ISL78600
9.
9. System Diagnostics Functions
System Diagnostics Functions
The system uses the following four types of faults to determine the overall health of the system.
• Automatic Fault detection within the IC.
• Fault detection that is automatic, but requires the host microcontroller to initiate an operation.
• Faults that are detected by the host microcontroller during normal communication. This includes lack of
response or responses that indicate a fault condition.
• Faults that are detected by the host microcontroller following a series of commands and responses that check
various internal and external circuits.
9.1
Hardware Fault Detection
The ISL78600 is always checking the internal V3P3, V2P5, and VREF power supplies using window comparators.
If any of these voltages exceed a programmed limit (either too high or too low), then a REG fault exists. This
immediately starts an alarm response. See “Alarm Response” on page 106.
The ISL78600 also checks the two oscillators continually. The high speed and low speed oscillators are compared
against limits and against each other. If there is a deviation greater than programmed, then an OSC fault exists.
This immediately starts an alarm response. See “Alarm Response” on page 106.
9.2
System Out of Limit Detection
Bits are set in the fault data registers for detection of:
• Overvoltage
• Undervoltage
• Open wires
• Over-temperature
• Open VBAT
• Open VSS
The overvoltage, undervoltage, over-temperature, and open-wire conditions have individual fault bits for each cell
input. These bits are OR’d and reflected to bits in the Fault Status register (one bit per data register). The Open
VBAT and Open VSS have one bit each in the Fault Status register.
These conditions are not detected unless the host initiates a scan operation. The cell overvoltage, cell
undervoltage, VBAT open, and VSS open faults are sampled at the same time at the end of a Scan Voltages
command. The cell undervoltage and cell overvoltage signals are also checked following a Measure cell voltage
command. These conditions are also checked during a scan continuous operation. If the host initiates a scan
continuous operation, then the status is checked automatically every scan cycle, without further host involvement.
For any other scan command, the host needs to periodically send the command to perform another check of the
system.
9.3
Fault Signal Filtering
Filtering is provided for the cell overvoltage, cell undervoltage, VBAT open, and VSS open tests. These fault
signals use a totalizing method in which an unbroken sequence of positive results is required to validate a fault
condition. The sequence length (number of sequential positive samples) is set by the [TOT2:0] bits in the Fault
Setup register (see Table 46 on page 101).
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9. System Diagnostics Functions
Table 46. Fault Setup Register
REGISTER BITS
0
Enable
Internal
Temperature
Totalizer
Count
SCN0
1
SCN1
2
SCN0
3
SCN1
WSCN
4
TOT0
5
TOT1
6
TOT2
7
TST0
8
TST1
9
TST2
10
TST3
11
TST4
12
Scan Interval
Time (ms)
0
0
0
0
None
0
Disable
0
0
0
1
0
Track Voltage
Scan
0
0
0
0
16
x
x
x
1
ExT1
1
Enable
0
0
1
2
1
Track Temp Scan
0
0
0
1
32
x
x
1
x
ExT2
0
1
0
4
0
0
1
0
64
x
1
x
x
ExT3
0
1
1
8
0
0
1
1
128
1
x
x
x
ExT4
1
0
0
16
0
1
0
0
256
1
0
1
32
0
1
0
1
512
1
1
0
64
0
1
1
0
1024
1
1
1
128
0
1
1
1
2048
1
0
0
0
4096
1
0
0
1
8192
1
0
1
0
16384
1
0
1
1
32768
1
1
0
0
65536
Scan Wires
If the host sends a Scan Continuous command, then the Scan Interval code and the totalizer count value set the
Fault Detection time (see Table 47).
Each cell input, VBAT, and VSS open circuits has separate filter functions. The filter is reset whenever a test
results in a negative result (no fault). All filters are reset when the Fault Status register bits are changed. When a
fault is detected, the bits must be rewritten.
Any out of limit condition generates an Alarm response. See “Alarm Response” on page 106.
Table 47. Fault Detection Time as a Function of Scan Interval and Number of Totalizer Samples
Fault Setup Register Bits (TOT2:TOT0)
000
001
010
011
100
101
110
111
Totalizer Count
1
2
4
8
16
32
64
128
Scan Interval Code
Scan Interval (ms)
0000
16
16
32
64
128
256
512
1024
2048
0001
32
32
64
128
256
512
1024
2048
4096
0010
64
64
128
256
512
1024
2048
4096
8192
0011
128
128
256
512
1024
2048
4096
8192
16384
0100
256
256
512
1024
2048
4096
8192
16384
32768
0101
512
512
1024
2048
4096
8192
16384
32768
65536
0110
1024
1024
2048
4096
8192
16384
32768
65536
131072
0111
2048
2048
4096
8192
16384
32768
65536
131072
262144
1000
4096
4096
8192
16384
32768
65536
131072
262144
524288
1001
8192
8192
16384
32768
65536
131072
262144
524288
1048576
1010
16384
16384
32768
65536
131072
262144
524288
1048576
2097152
1011
32768
32768
65536
131072
262144
524288
1048576
2097152
4194304
1100
65536
65536
131072
262144
524288
1048576
2097152
4194304
8388608
FN7672 Rev.11.00
Jun.12.20
Fault Detection Time (ms)
Page 101 of 139
ISL78600
9.4
9. System Diagnostics Functions
Diagnostic Activity Settling Time
The majority of diagnostic functions within the ISL78600 do not affect other system activity and there is no
requirement to wait before conducting further measurements. The exceptions to this are the open-wire test and
cell balancing functions.
9.4.1
Open-Wire Test
The open-wire test loads each VCn pin in turn with 150µA or 1mA current. This disturbs the cell voltage
measurement while the test is being applied such as, a 1mA test current applied with an input path resistance of
1kΩ reduces the pin voltage by 1V. The time required for the cell voltage to settle following the open-wire test is
dependent on the time constant of components used in the cell input circuit. The standard input circuit (Figure 52
on page 42) with the components given in Table 13 on page 48 provide settling to within 0.1mV in approximately
2.8ms. This time should be added at the end of each open-wire scan to allow the cell voltages to settle.
9.4.2
Cell Balancing
The standard applications circuit (Figure 52 on page 42) configures the balancing circuits so that the cell input
measurement reads close to zero volts when balancing is activated. There are time constants associated with the
turn-on and turn-off characteristics of the cell balancing system that must be allowed for when conducting cell
voltage measurements.
The turn-on time of the balancing circuit is primarily a function of the 25µA drive current of the cell balancing
output and the gate charge characteristic of the MOSFET and needs to be determined for a particular setup. Turnon settling times to within 2mV of final “on” value are typically less than 5ms.
The turn-off time is a function of the MOSFET gate charge and the VGS connected resistor and capacitor values
(for example R27 and C27 in Figure 52 on page 42) and is generally longer than the turn-on time. As with the turnon case, the turn-off time needs to be determined for the particular components used. Turn-off settling times in the
range 10ms to 15ms are typical for settling to within 0.1mV of final value.
9.5
Memory Checksum
Two checksum operations are available to the host microcontroller for checking memory integrity, one for the
EEPROM and one for the Page 2 registers.
Two registers are provided to verify the contents of EEPROM memory. One (Page 4, address 6’h3F) contains the
correct checksum value, which is calculated during factory testing. The other (Page 5, address 6’h00) contains
the checksum value calculated each time the nonvolatile memory is loaded to shadow registers, either after a
power cycle or after a software reset (receiving a Reset command). An inequality between these two numbers
indicates corruption of the shadow register contents (and possible corruption of EEPROM data). The external
microcontroller needs to compare the two registers, because it is not automatic. Resetting the device (using the
Reset command) reloads the shadow registers. A persistent difference between these two checksum register
values indicates EEPROM corruption.
All Page 2 registers (device configuration registers) are subject to a checksum calculation. A Calculate Register
Checksum command calculates the Page 2 checksum and saves the value internally (it is not accessible). The
Calculate Register Checksum command can be run any time, but should be sent whenever a Page 2 register is
changed.
A Check Register Checksum command recalculates the Page 2 checksum and compares it to the internal value.
The occurrence of a Page 2 checksum error sets the PAR bit in the Fault Status register and causes a Fault
response accordingly. The normal response to a PAR error is for the host microcontroller to rewrite the Page 2
register contents. A PAR fault also causes the device to cease any scanning or cell balancing activity.
See items 42 through 49 in Table 51 on page 107.
FN7672 Rev.11.00
Jun.12.20
Page 102 of 139
ISL78600
9.6
9. System Diagnostics Functions
Communication Faults
There is no specific flag to indicate a communications fault. A fault is indicated by receiving an abnormal
communications response or by an absence of all communications.
Non-daisy chain device commands and responses use CRC (Cyclical Redundancy Check) error detection. Standalone systems do not use the CRC. If a CRC is not recognized by a target device, a command includes an
Address All when it is not allowed, or if there are too few bits in the sequence there is a NAK response. The host
can tell where this fault occurred by reading the Device address.
If there is no response, then there is a communications failure.
9.7
Communications Failure
All commands except the Scan Voltages, Scan Temperatures, Scan Mixed, Scan Wires, Scan All, Measure, and
Reset have a response from either the stack Top device or the target device. Correct receipt of a command is
indicated by the correct response. The Wakeup command is a special case. If any Daisy Chain Middle device is in
Sleep mode, while another device above it in the stack is not in Sleep mode, there is no response. Otherwise the
Wakeup command responds with ACK. (For a summary of Command responses, see Table 15 on page 52).
Each device in the stack waits for a response from the stack device above. A device that does not receive a
response within a timeout period reports a Communications Failure. The timeout value in each device is stack
position dependent, with a device farther from the top waiting longer for the response. The device that detects the
fault transmits the Communications Failure response, which includes its Device Address.
Table 48 shows the minimum time the host should wait for a response before sending a new command to the
Master device.
Table 48. Maximum Time to Communications Failure Response
Daisy Chain Data Rate (kHz) Note 25
Communications Failure Wait Time For
500
250
125
62.5
Unit
2 Devices in the stack
330
660
1320
2640
µs
3 Devices in the stack
510
1010
2010
4010
µs
4 Devices in the stack
700
1390
2780
5550
µs
5 Devices in the stack
950
1900
3790
7570
µs
6 Devices in the stack
1250
2490
4980
9950
µs
7 Devices in the stack
1610
3220
6430
12850
µs
8 Devices in the stack
2070
4140
8280
16550
µs
9 Devices in the stack
2620
5240
10480
20950
µs
10 Devices in the stack
3280
6560
13120
26230
µs
11 Devices in the stack
4070
8140
16280
32560
µs
12 Devices in the stack
5170
10340
20680
41360
µs
13 Devices in the stack
6270
12540
25080
50160
µs
14 Devices in the stack
7810
15620
31240
62480
µs
25. The times are the longest expected wait times for communications to time-out. Typical wait times are approximately 10% shorter than the
times in the table. The times are measured from the falling edge of the eighth clock in the first byte of the command received by the Master
to the first falling edge of the DataReady signal.
As an example, assume that the system has a stack of ten devices. Since a break in the daisy chain can happen
anywhere, and since the wait times are different for each device, it is likely best for the system programmer to
build in a delay time equal to the response from the device farthest from the top. In this case, the host would wait
at least 3.28ms for a response before issuing a command to try to clear the fault or declaring a daisy chain
no-response fault.
FN7672 Rev.11.00
Jun.12.20
Page 103 of 139
ISL78600
9. System Diagnostics Functions
If the target device receives a Communications Failure response from the device above, then the target device
relays the Communications Failure followed by the requested data (in the case of a read) or simply relays the
Communications Failure only (in the case of a Write, Balance command, etc).
A Communications Failure response can be caused by one of three circumstances:
• The communications system has been compromised, such as a component failure or broken wire,
• One or more devices in the stack are in Sleep mode. A device would go to Sleep mode if it doesn't receive valid
communications before its watchdog timer expires. There are three ways this might occur in a system. Different
devices might have been programmed with different WDT timeout values. Each device has its own oscillator, so
the timeout is a little different for each device. Finally, if the system communicates with some, but not all
devices, such as if the host repeatedly reads the status of the top device in a stack of four devices, then the top
device and the master receive valid communications, but the middle two devices do not. So the middle devices
time out.
• A daisy chain input port is in the wrong idle state.
This latter condition is unlikely but could arise in response to external influence, such as a large transient event.
The daisy chain ports are forced to the correct idle condition at the end of each communication. An external event
would have the potential to “flip” the input such that the port settles in the inverse state.
A flipped input condition recovers during the normal course of communications. If a flipped input is suspected,
having received notification of a communications fault condition for example, the user can send a sequence of all
1s (that is, a command of FF FF FF FF) to clear the fault. Wait for the resulting NAK response and then send an
ACK to the device that reported the fault. The “all 1” sequence allows a device to correct a flipped condition
through the normal end of the communication process. If the microcontroller communication code requires that
the command CRC be valid, the command FB FF FF FF also works to return to the idle state.
If a command results in a Communications Failure response, the next steps for the host microcontroller are:
1. Send a Sleep command (this makes sure that the Master is asleep prior to sending the Wakeup command,
because if the Master is awake when it receives the Wakeup command, it does not send the Wakeup
command on to the other stack devices),
2. Wait for all stack devices to go to sleep,
3. Send a Wakeup command,
4. Wait for the Wakeup command to propagate through the stack,
5. If successful, then the host microcontroller receives an ACK indicating that all devices are awake.
6. If there is no response, it could be an indication that more than one device was asleep (separated by devices
that are awake.) If this is the case, repeat steps 1 through 5, until there is an ACK response.
7. If this loop is executed more times that there are devices in the stack, then there is likely a more significant
break in communications.
9.8
Daisy Chain Communications Conflicts
Conflicts in the daisy chain system can occur if both a stack device and the host microcontroller are transmitting at
the same time, or if more than one stack device transmits at the same time. Conflicts caused by a stack device
transmitting at the same time as the host microcontroller are recognized by the absence of the required response
(such as, an ACK response to a write command), or by the scan counter not being incremented in the case of
Scan and Measure commands.
Conflicts which arise from more than one device transmitting simultaneously can occur if two devices detect faults
at the same time. This can occur when the stack is operating normally (such as, if two devices register an
undervoltage fault in response to a Scan Voltages command sent to all devices). It is recommended that the host
microcontroller checks the Fault Status register contents of all devices whenever a Fault response is received
from one device.
FN7672 Rev.11.00
Jun.12.20
Page 104 of 139
ISL78600
9.9
9. System Diagnostics Functions
Loss of Signal From Host
A watchdog timer is provided as part of the daisy chain communications fault detection system. The watchdog
has no effect in non-daisy chain systems.
Each device must receive a valid communications sequence before its watchdog timeout period is exceeded. A
valid communications sequence is one that requires an action or response from the device. Address All
commands, such as the Scan and Balance commands provide a simple way to reset the watchdog timers on all
devices with a single communication. Single device communications (such as ACK) must be sent individually to
each device to reset the watchdog timer in that device. A read of the Fault Status register of each device is also a
good way to reset the watchdog timer on each device. This functionality guards against situations where a
runaway host microcontroller might continually send data.
Failure to receive valid communications within the required time causes the WDGF bit to be set in the Fault Status
register and the device to be placed in Sleep mode, with all measurement and balancing functions disabled. Daisy
chain devices assert the FAULT output in response to a watchdog fault and maintain this asserted state while in
Sleep mode. Notice that no watchdog fault response is automatically sent on the daisy chain interface.
9.9.1
Watchdog Function
The watchdog timeout is settable in two ranges using the lower 7 bits of the Watchdog/Balance time register (see
Table 49). The low range (7’b0000001 to 7’b0111111) provides timeout settings in 1 second increments from 1
second to 63 seconds. The high range (7’b1000000 to 7’b1111111) provides timeout settings in 2 minute intervals
from 2 minutes to 128 minutes (see Table 49 for details).
Table 49. Watchdog/Balance Time Register
Register Bits
6
5
4
3
2
1
0
WDG6
WDG5
WDG4
WDG3
WDG2
WDG1
WDG0
Watchdog Timeout
0
0
0
0
0
0
0
Disabled
0
0
0
0
0
0
1
1s
0
0
0
0
0
1
0
2s
-
0
1
1
1
1
1
0
62s
0
1
1
1
1
1
1
63s
1
0
0
0
0
0
0
2 min
1
0
0
0
0
0
1
4 min
-
1
1
1
1
1
1
0
126 min
1
1
1
1
1
1
1
128 min
A zero setting (7’b0000000) disables the watchdog function. A watchdog password function is provided to guard
against accidental disabling of the watchdog function. The upper 6 bits of the Device Setup register must be set to
6’h3A (111010) to allow the watchdog to be set to zero. The watchdog is disabled by first writing the password to
the Device Setup register (see “Setup Registers” on page 124) and then writing zero to the lower bits of the
Watchdog/Balance time register. The password function does not prevent changing the watchdog timeout setting
to a different nonzero value.
The watchdog continues to function when the ISL78600 is in Sleep mode. Parts in Sleep mode assert the FAULT
output when the watchdog timer expires.
FN7672 Rev.11.00
Jun.12.20
Page 105 of 139
ISL78600
9.9.2
9. System Diagnostics Functions
Watchdog Password
Before writing a zero to the watchdog timer, which turns off the timer, it is necessary to write a password to the
[WP5:0] bits. The password value is 6’h3A.
9.10
Alarm Response
If any of the fault bits are set, the FAULT logic output is asserted low in response to the fault condition. The output
then remains low until the bits of the Fault Status register are reset. Individual bits in the fault data registers must
first be cleared before the associated bits in the Fault Status register can be cleared.
If the device is in a daisy chain, the Fault logic also sends an “unprompted” response down the daisy chain to the
Master, which notifies the Host microcontroller that a problem exists.
The daisy chain fault response is immediate, so long as there is no communications activity on the device ports,
and comprises the normal Fault Status register read response. As such, it includes the contents of the Status
Register and includes the device address that is reporting the fault.
The Fault response is only sent for the first fault occurrence. Subsequent faults do not activate the Fault response
until after the Fault Status register has been cleared. If multiple devices report a fault, the response shows the
results from the lowest stack device.
If a fault occurs while the device ports are active, then the device waits until communications activity ceases
before sending the Fault response. The host microcontroller has the option to wait for this response before
sending the next message. Alternately the host microcontroller may send the next message immediately (after
allowing the daisy chain ports to clear (see “Sequential Daisy Chain communications” on page 92). Any conflicts
resulting from additional transmissions from the stack are recognized by the lack of response from the stack.
Table 50 provides the maximum time from DATA READY going low for the last byte of the normal response to
DATA READY going low for the first byte of the Fault response in the case where a Fault response is held up by
active communications.
Table 50. Maximum Time Between Data Ready Signals and Delayed Fault Response
Daisy Chain Data Rate (kHz)
Maximum Time between DATA READY Assertions during delayed Fault
Response
500
250
125
62.5
Unit
68
136
272
544
µs
Further read communications to the device return the Fault response followed by the requested data. Write
communications return only the fault response. Action commands return nothing. The host microcontroller resets
the register bits corresponding to the fault by writing 14’h0000 to the Fault Status register, having first cleared the
bits in the fault data register(s) if these are set. The device then responds ACK as with a normal write response
because the fault status bits are now cleared. This also prevents further Fault responses unless the fault
reappears, in which case the Fault response is repeated.
Additionally, the fault status of each part can be obtained at any time by reading the Fault Status register.
The FAULT logic output is asserted in Sleep mode, if a fault has been detected and has not been cleared.
FN7672 Rev.11.00
Jun.12.20
Page 106 of 139
ISL78600
10. Fault Diagnostics
10. Fault Diagnostics
Table 51 shows a summary of commands and responses for the various fault diagnostics functions.
Table 51. Summary of Fault Diagnostic Commands and Responses
Item
Diagnostic
Function
Action Required
1
Static Fault
Detection
Functions
Check fault status (or
look for normal fault
response)
2
Oscillator Check Check for device in
Function
Sleep mode if stack
returns a
Communications
Failure response.
3
Cell Overvoltage Set cell overvoltage
limit
Register Read/write
Read Fault Status
Register
Comments
The main internal functions of the ISL78600 are monitored
continuously. Bits are set in the Fault Status register in response
to faults being detected in these functions.
Oscillator faults are detected as part of the Static Fault detection
functions. The response to an oscillator fault detection is to set
the OSC bit in the Fault Status register and then to enter Sleep
mode. A sleeping device does not respond to normal
communications, producing a Communications Failure
notification from the next device down the stack. The normal
recovery procedure is send repeated Sleep and Wakeup
commands ensure all devices are awake.
Write Overvoltage Limit Full scale value 14'h1FFF = 5V
Register
4
Set fault filter sample
value
Write TOT bits in Fault
Setup Register
Default is 3'b011 (eight samples) - (see Table 46 on page 101)
5
Identify which inputs
have cells connected
Write Cell Setup
Register
A '0' bit value indicates cell is connected. A '1' bit value indicates
no cell connected to this input. The overvoltage test is not applied
to unconnected cells.
6
Scan cell voltages
Send Scan Voltages
Command
A cell overvoltage condition is flagged after a number of
sequential overvoltage conditions are recorded for a single cell.
The number is programmed above in item 4.
7
Check fault status
Read Fault Status
Register
The device sends the Fault Status register contents automatically
if a fault is detected, if the register value is zero before the fault is
detected.
8
Check overvoltage
fault register
Read Overvoltage
Fault Register
Only required if the Fault Status register returns a fault condition.
9
Reset fault bits
Reset bits in the Overvoltage Fault register followed and bits in
the Fault Status register.
10
Reset fault filter
Change the value of the [TOT2:0] bits in the Fault Setup register
and then change back to the required value. This resets the filter.
The filter is also reset if a false overvoltage test is encountered.
11
Cell
Undervoltage
Set cell undervoltage
limit
Write Undervoltage
Limit Register
Full scale value 14'h1FFF = 5V
12
Set fault filter sample
value
Write TOT Bits in Fault
Setup Register
Default is 3'b011 (eight samples)
13
Identify which inputs
have cells connected
Write Cell Setup
Register
A '0' bit value indicates cell is connected. A '1' bit value indicates
no cell connected to this input. The undervoltage test is not
applied to unconnected cells.
14
Scan cell voltages
Send Scan Voltages
Command
A cell undervoltage condition is flagged after a number of
sequential undervoltage conditions are recorded for a single cell.
The number is programmed above in item 12.
15
Check fault status
Read Fault Status
Register
The device sends the Fault Status register contents automatically
if a fault is detected, if the register value is zero before the fault is
detected.
16
Check undervoltage
fault register
Read Undervoltage
Fault Register
Only required if the Fault Status register returns a fault condition.
17
Reset fault bits
FN7672 Rev.11.00
Jun.12.20
Reset bits in the Undervoltage Fault register followed by bits in
the Fault Status register.
Page 107 of 139
ISL78600
10. Fault Diagnostics
Table 51. Summary of Fault Diagnostic Commands and Responses (Continued)
Item
Diagnostic
Function
18
19
Action Required
Register Read/write
Reset fault filter
Change the value of the [TOT2:0] bits in the Fault Setup register
and then change back to the required value. This resets the filter.
The filter is also reset if a false undervoltage test is encountered.
Set fault filter sample
value
Write TOT bits in Fault
Setup Register
Default is 3'b011 (eight samples)
20
Scan cell voltages
Send Scan Voltages
Command
A open condition on VBAT or VSS is flagged after a number of
sequential open conditions are recorded for a single cell. The
number is programmed above in item 19.
21
Check fault status
Read Fault Status
Register
The device sends the Fault Status register contents automatically
if a fault is detected, if the register value is zero before the fault is
detected.
22
Reset fault bits
Reset bits in the Fault Status register.
23
Reset fault filter
Change the value of the [TOT2:0] bits in the Fault Setup register
and then change back to the required value. This resets the filter.
The filter is also reset if a false open test is encountered.
24
VBAT or VSS
Connection Test
Comments
Set scan current
value
Write Device Setup
Sets scan current to 1mA (recommended) by setting ISCN = 1.
Register: ISCN = 1 or 0 Or, set the scan current to 150µA by setting ISCN = 0.
25
Identify which inputs
have cells connected
Write Cell Setup
Register
A '0' bit value indicates cell is connected. A '1' bit value indicates
no cell connected to this input. Cell inputs VC2 to VC12: the
open-wire detection system is disabled for cell inputs with a '1'
setting in the Cell Setup register. Cell inputs VC0 and VC1 are
not affected by the Cell Setup register.
26
Activate scan wires
function
Send Scan Wires
Command
Wait for Scan Wires to complete.
27
Check fault status
Read Fault Status
Register
The device sends the Fault Status register contents automatically
if a fault is detected, if the register value is zero before the fault is
detected.
28
Check open-wire fault Read Open-Wire Fault
register
Register
Only required if the Fault Status register returns a fault condition.
29
Reset fault bits
Reset bits in the open-wire fault register followed by bits in the
Fault Status register.
30
Open Wire Test
Set external
temperature limit
Write External
Temperature Limit
Register
Full scale value 14'h3FFF = 2.5V
31
Identify which inputs
are required to be
tested
Write Fault Setup
Register Bits TST1 to
TST4
A '1' bit value indicates input is tested. A '0' bit value indicates
input is not tested.
32
Scan temperature
inputs
Send Scan
Temperatures
Command
An over-temperature condition is flagged immediately if the input
voltage is below the limit value.
33
Check fault status
Read Fault Status
Register
The device sends the Fault Status register contents automatically
if a fault is detected, if the register value is zero before the fault is
detected.
34
Check overtemperature fault
register
Read OverTemperature Fault
Register
Only required if the Fault Status register returns a fault condition.
35
Reset fault bits
36
OverTemperature
Indication
Reference
Check Function
37
FN7672 Rev.11.00
Jun.12.20
Reset bits in the Over-temperature Fault register followed by bits
in the Fault Status register.
Read reference
coefficient A
Read Reference
Coefficient A Register
Read reference
coefficient B
Read Reference
Coefficient B Register
Page 108 of 139
ISL78600
10. Fault Diagnostics
Table 51. Summary of Fault Diagnostic Commands and Responses (Continued)
Item
Diagnostic
Function
Action Required
Register Read/write
38
Read reference
coefficient C
Read Reference
Coefficient C Register
39
Scan temperature
inputs
Send Scan
Temperatures
Command
40
Read reference
voltage value
Read Reference
Voltage Register
41
Calculate voltage
reference value
42
See Voltage Reference Check Calculation in the Worked
Examples section of this data sheet (see ““Voltage Reference
Check Calculation” on page 110).
Calculate register
checksum value
Send Calculate
Register Checksum
Command
This causes the ISL78600 to calculate a checksum based on the
current contents of the page 2 registers. This action must be
performed each time a change is made to the register contents.
The checksum value is stored for later comparison.
43
Check register
checksum value
Send Check Register
Checksum Command
The checksum value is recalculated and compared to the value
stored by the previous Calc Register Checksum command. The
PAR bit in the Fault Status register is set if these two numbers
are not the same.
44
Check fault status
Read Fault Status
Register
The device sends the Fault Status register contents automatically
if a fault is detected, if the register value is zero before the fault is
detected.
45
Rewrite registers
Load all page 2
Registers With Their
Correct Values.
This is only required if a PAR fault is registered. It is
recommended that the host reads back the register contents to
verify values prior to sending a Calculate Register Checksum
command.
46
Reset fault bits
47
Register
Checksum
Comments
EEPROM MISR
Checksum
Reset bits in the Fault Status register.
Read checksum value Read the EEPROM
stored in EEPROM
MISR Register
48
Read checksum value Read the MISR
calculated by
Checksum Register
ISL78600
The checksum value is calculated each time the EEPROM
contents are loaded to registers, either following the initial
application of power or the device receiving a Reset command.
49
Compare checksum
values
Correct function is indicated by the two values being equal.
Memory corruption is indicated by an unequal comparison. In this
event the host should send a Reset command and repeat the
check process.
FN7672 Rev.11.00
Jun.12.20
Page 109 of 139
ISL78600
11. Worked Examples
11. Worked Examples
The following worked examples are provided to assist with the setup and calculations associated with various
functions.
11.1
Voltage Reference Check Calculation
Table 52. Example Register Data
R/W
Page
Address
Parameter
Value (Hex)
Decimal
0
001
010000
IC Temperature
14’h2425
9253
0
001
010101
Reference Voltage
14’h20A7
8359
0
010
111000
Coefficient C
14’h00A4
164
0
010
111001
Coefficient B
14’h3FCD
-51
0
010
111010
Coefficient A
9’h006
6
Coefficients A, B, and C are two’s complement numbers.
Coefficients B and C have a range +8191 to -8192.
Coefficient A has a range +255 to -256.
Coefficient B in the example is a negative number (Hex value > 1FFF). The value for Coefficient B is
14’h3FCD - 14h3FFF- 1 or (1633310 - 1638310 - 1) = -51.
Coefficient A occupies the upper nine bits of register 6’b111010 (6'h3A). One way to extract the coefficient data
from this register is to divide the complete register value by 32 and rounding the result down to the nearest
integer. With 9'h006 in the upper nine bits, and assuming the lower five bits are 0, the complete register value is
14'h0C0 = 192 decimal. Divide this by 32 to obtain 6.
Coefficients A, B, and C are used with the IC temperature reading to calibrate the Reference Voltage reading. The
calibration is applied by subtracting, from the Reference Voltage reading, an adjustment of the form:
(EQ. 6)
2
B
A
Adjustment = ----------------------------- dT + ------------- dT + C
8192
256 8192
An example calculation using the data of Table 52 is given in Equation 7.
(EQ. 7)
9253 – 9180
dT = -------------------------------- = 36.5
2
where 9180 is the Internal Temperature Monitor reading at +25°C (see the “Electrical Specifications” table, TINT25
on page 13).
(EQ. 8)
2
51
6
Adjustment = ----------------------------- 36.5 – ------------- 36.5 + 164 = 163.8
8192
256 8192
(EQ. 9)
Corrected V REF = 8359 – 163.8 = 8195.2
(EQ. 10)
8195.2
V REF value = ------------------ 5 = 2.5010
16384
FN7672 Rev.11.00
Jun.12.20
Page 110 of 139
ISL78600
11.2
11. Worked Examples
Cell Balancing – Manual Mode
See “Manual Balance Mode” on page 63.
11.2.1
Example: Activate balancing on cells 1, 5, 7 and 11
1. Write Balance Setup register: Set Manual Balance mode, Balance Status pointer, and turn off balance.
BMD = 01 (Manual Balance mode)
BWT = XXX
BSP = 0000 (Balance status pointer location 0)
BEN = 0 (Balancing disabled)
Table 53. Write Balance Setup Register (Manual Balance)
Device Address
R/W
Page
Address
Data
CRC
AAAA
1
010
010011
XX XX00 000X XX01
CCCC
X = Do not care
AAAA = Device Address in Daisy Chain. Not needed in Stand-Alone
CCCC = CRC value in Daisy Chain. Not needed in Stand-Alone
2. Write Balance Status register: Set BAL[0], BAL[4], BAL[6], BAL[10]
BAL12:1 = 0100 0101 0001
Table 54. Write Balance Status Register (Manual Balance)
Device Address
R/W
Page
Address
Data
CRC
AAAA
1
010
010100
XX 0100 0101 0001
CCCC
X = Do not care
AAAA = Device Address in Daisy Chain. Not needed in Stand-Alone
CCCC = CRC value in Daisy Chain. Not needed in Stand-Alone
3. Enable balancing using Balance Enable command
Table 55. Send “Balance Enable” Command
Device Address
R/W
Page
Address
Data
CRC
AAAA
0
011
010000
00 0000
CCCC
AAAA = Device Address in Daisy Chain. Not needed in Stand-Alone
CCCC = CRC value in Daisy Chain. Not needed in Stand-Alone
or enable balancing by setting BEN directly in the Balance Setup register:
BEN = 1
Table 56. Write Balance Setup Register
Device Address
R/W
Page
Address
Data
CRC
AAAA
1
010
010011
XX XX1X XXXX XXXX
CCCC
X = Do not care
AAAA = Device Address in Daisy Chain. Not needed in Stand-Alone
CCCC = CRC value in Daisy Chain. Not needed in Stand-Alone
The balance FETs attached to Cells 1, 5, 7, and 11 turn on.
Turn balancing off by resetting BEN or by sending the Balance Inhibit command (Page 3, address 6’h11).
11.3
Cell Balancing – Timed Mode
See “Timed Balance Mode” on page 64.
FN7672 Rev.11.00
Jun.12.20
Page 111 of 139
ISL78600
11.3.1
11. Worked Examples
Example: Activate Balancing on Cells 2 and 8 for 1 Minute
1. Write Balance Setup register: Set Timed Balance mode, Balance Status pointer, and turn off balance.
BMD = 10 (Timed Balance mode)
BWT = XXX
BSP = 0000 (Balance status pointer location 0)
BEN = 0 (BALANCING disabled)
Table 57. Write Balance Setup Register (Timed Balance)
Device Address
R/W
Page
Address
Data
CRC
AAAA
1
010
010011
XX XX00 000X XX10
CCCC
X = Do not care
AAAA = Device Address in Daisy Chain. Not needed in Stand-Alone
CCCC = CRC value in Daisy Chain. Not needed in Stand-Alone
2. Write Balance Status register: Set BAL[1] and BAL[7]
BAL12:1 = 0000 1000 0010
Table 58. Write Balance Status Register (Timed Balance)
Device Address
R/W
Page
Address
Data
CRC
AAAA
1
010
010100
XX 0000 1000 0010
CCCC
X = Do not care
AAAA = Device Address in Daisy Chain. Not needed in Stand-Alone
CCCC = CRC value in Daisy Chain. Not needed in Stand-Alone
3. Write balance timeout setting to the Watchdog/Balance Time register (Page 2, address 6’h15, Bits [13:7])
BTM6:1 = 0000011 (1 minute)
Table 59. Write Watchdog/Balance Time Register (Timed Balance)
Device Address
R/W
Page
Address
Data
CRC
AAAA
1
010
010101
00 0001 1XXX XXXX
CCCC
X = The lower bits are the watchdog timeout value and should be set to a time longer than the balance time. (111 1111) is suggested.
AAAA = Device Address in Daisy Chain. Not needed in Stand-Alone
CCCC = CRC value in Daisy Chain. Not needed in Stand-Alone
4. Enable balancing using Balance Enable command
Table 60. Send “Balance Enable” Command (Timed Balance)
Device Address
R/W
Page
Address
Data
CRC
AAAA
0
011
010000
00 0000
CCCC
AAAA = Device Address in Daisy Chain. Not needed in Stand-Alone
CCCC = CRC value in Daisy Chain. Not needed in Stand-Alone
or enable balancing by setting BEN directly in the Balance Setup register:
BEN = 1
Table 61. Write Balance Setup Register (Timed Balance)
Device Address
R/W
Page
Address
Data
CRC
AAAA
1
010
010011
XX XX1X XXXX XXXX
CCCC
X = Do not care.
AAAA = Device Address in Daisy Chain. Not needed in Stand-Alone
CCCC = CRC value in Daisy Chain. Not needed in Stand-Alone
FN7672 Rev.11.00
Jun.12.20
Page 112 of 139
ISL78600
11. Worked Examples
The balance FETs attached to Cells 2 and 8 turn on. The FETs turn off after 1 minute. Balancing can be stopped
by resetting BEN or by sending the Balance Inhibit command.
11.4
Cell Balancing – Auto Mode
See “Auto Balance Mode” on page 65.
11.4.1
Balance Value Calculation Example
This example is based on a cell State of Charge (SOC) of 9360 coulombs, a target SOC of 8890 coulombs, a
balancing leg impedance of 31Ω (30Ω resistor plus 1Ω FET on resistance) and a sampling time interval of 5
minutes (300 seconds).
The Balance Value is calculated using Equation 11.
8191
31
B = ------------- 9360 – 8890 ---------- = 79562 = 28h00136CA
5
300
(EQ. 11)
The value 8191/5 is the scaling factor of the cell voltage measurement.
The value of 28’h00136CA is loaded to the required Cell Balance Register and the value 7’b0001111 (5 minutes)
is loaded to the Balance Time bits in the Watchdog/Balance time register.
In this example, the total coulomb difference to be balanced is: 470 coulomb (9360 - 8890). At 3.3V/31Ω * 300s =
31.9 coulomb per cycle it takes about 15 cycles for the balancing to terminate.
11.4.2
Auto Balance Mode Cell Balancing Example
The following describes a simple setup to demonstrate the Auto Balance mode cell balancing function of the
ISL78600. Note that this balancing setup is not related to the balance value calculation in Equation 11.
Auto balance cells using the following criteria:
• Balance time = 20 seconds
• Balance wait time (dead time between balancing cycles) = 8 seconds
• Balancing disabled during cell measurements.
• Balance Values: See Table 62
Table 62. Cell Balance Values (HEX) for Each Cell
Cell 1
Cell 2
28’h406A 28’h3E4D
Cell 3
28’h0
Cell 4
Cell 5
Cell 6
28’h292F 28’h3E00
28’h0
Cell 7
Cell 8
28’h2903 28’h3D06
Cell 9
Cell 10
Cell 11
Cell 12
28’h0
28’h151E
28’h502
28’h6D6
Balance Status Register: Set up balance see Table 63:
Cells 1, 4, 7, and 10 on 1st cycle.
Cells 3, 6, 9, and 12 on 2nd cycle.
Cells 2, 5, 8, and 11 on 3rd cycle
Table 63. Balance Status Register Setup (Auto Balance)
Cell
BPS [3:0]
1
2
3
0000
4
5
6
7
8
9
10
11
12
Reserved for Manual Balance mode and Timed Balance mode
0001
1
0
0
1
0
0
1
0
0
1
0
0
0010
0
0
1
0
0
1
0
0
1
0
0
1
0011
0
1
0
0
1
0
0
1
0
0
1
0
0100
0
0
0
0
0
0
0
0
0
0
0
0
FN7672 Rev.11.00
Jun.12.20
Page 113 of 139
ISL78600
11. Worked Examples
Table 63. Balance Status Register Setup (Auto Balance) (Continued)
Cell
BPS [3:0]
1
2
3
4
5
6
0101 - 1111
7
8
9
10
11
12
Not needed
1. Write Balance Value registers
Table 64. Setup Balance Value Registers (For Cell1) - Value 28’h406A (Auto Balance)
Register Bit
Address
6’20
13
Bit
Bit
11
10
9
8
7
6
5
4
3
2
1
0
B0113 B0112 B1011 B0110 B0109 B0108 B0107 B0106 B0105 B0104 B0103 B0102 B0101 B0100
Value
6’21
12
0
0
0
0
0
0
0
1
1
0
1
0
1
0
B0127 B0126 B0125 B0124 B0123 B0122 B0121 B0120 B0119 B0118 B0117 B0116 B0115 B0114
Value
0
0
0
0
0
0
0
0
0
0
0
0
0
1
Table 65. Write Balance Value Register (Auto Balance)
Write Value Register Command
For Cell
Number
Device Address
R/W
Page
Address
Data (Hex)
CRC
1
AAAA
1
010
100000
14’h006A
CCCC
AAAA
1
010
100001
14’h0001
CCCC
AAAA
1
010
100010
14’h3E4D
CCCC
AAAA
1
010
100011
14’h0000
CCCC
AAAA
1
010
100100
14’h0000
CCCC
AAAA
1
010
100101
14’h0000
CCCC
AAAA
1
010
100110
14’h292F
CCCC
AAAA
1
010
100111
14’h0000
CCCC
AAAA
1
010
101000
14’h3E00
CCCC
AAAA
1
010
101001
14’h0000
CCCC
AAAA
1
010
101010
14’h0000
CCCC
AAAA
1
010
101011
14’h0000
CCCC
AAAA
1
010
101100
14’h2903
CCCC
AAAA
1
010
101101
14’h0000
CCCC
AAAA
1
010
101110
14’h3D06
CCCC
AAAA
1
010
101111
14’h0000
CCCC
AAAA
1
010
110000
14’h0000
CCCC
AAAA
1
010
110001
14’h0000
CCCC
AAAA
1
010
110010
14’h151E
CCCC
AAAA
1
010
110011
14’h0000
CCCC
AAAA
1
010
110100
14’h0502
CCCC
AAAA
1
010
110101
14’h0000
CCCC
AAAA
1
010
110110
14’h06D6
CCCC
AAAA
1
010
110111
14’h0000
CCCC
2
3
4
5
6
7
8
9
10
11
12
AAAA = Device Address in Daisy Chain. Not needed in Stand-Alone
CCCC = CRC value in Daisy Chain. Not needed in Stand-Alone
FN7672 Rev.11.00
Jun.12.20
Page 114 of 139
ISL78600
11. Worked Examples
2. Write BDDS bit in Device Setup register (turn balancing functions off during measurement)
BDDS = 1
Table 66. Write Device Setup Register (Auto Balance)
Device Address
R/W
Page
Address
Data
CRC
AAAA
1
010
011001
XX XXXX 1XXX XXXX
CCCC
X = Do not care.
AAAA = Device Address in Daisy Chain. Not needed in Stand-Alone
CCCC = CRC value in Daisy Chain. Not needed in Stand-Alone
3. Write balance timeout setting to the Watchdog/Balance Time register: Balance timeout code = 0000001
(20 seconds)
BTM6:0 = 000 0001
Table 67. Write Balance Timeout Register (Auto Balance)
Device Address
R/W
Page
Address
Data
CRC
AAAA
1
010
010101
00 0000 1XXX XXXX
CCCC
X = The lower bits are the watchdog timeout value and should be set to a time longer than the balance time. (111 1111) is suggested.
AAAA = Device Address in Daisy Chain. Not needed in Stand-Alone
CCCC = CRC value in Daisy Chain. Not needed in Stand-Alone
4. Setup Balance Status register (from Table 63 on page 113)
This operation is a repetitive process that consists of writing to the Balance Setup Register to set a pointer to a
location in the Balance Status Register, then writing the Balance Status Register. Since the Balance Status
Register needs to write four locations, this operation is repeated four times.
The following bits are set as part of the procedure. They can be set on the last step or re-written each time. In this
example, the bits are re-written in each step.
BMD = 11 (Auto Balance mode)
BWT = 100 (8 seconds)
BEN = 0 (Balancing disabled
This operation starts by setting the Balance Status Pointer to 1.
BSP = 0001 (Balance status pointer = 1)
a. Write Balance Setup register: Set Auto Balance mode, set 8 second Balance wait time, and set balance off:
Table 68. Write Balance Setup Register (Auto Balance - Pointer = 1)
Device Address
R/W
Page
Address
Data
CRC
AAAA
1
010
010011
XX XX00 0011 0011
CCCC
X = Do not care.
AAAA = Device Address in Daisy Chain. Not needed in Stand-Alone
CCCC = CRC value in Daisy Chain. Not needed in Stand-Alone
b. Write Balance Status register: Set Bits 1, 4, 7, and 10
BAL12:1 = 0010 0100 1001
Table 69. Write Balance Status Register (Auto Balance - Pointer = 1)
Device Address
R/W
Page
Address
Data
CRC
AAAA
1
010
010100
XX 0010 0100 1001
CCCC
X = Do not care.
AAAA = Device Address in Daisy Chain. Not needed in Stand-Alone
CCCC = CRC value in Daisy Chain. Not needed in Stand-Alone
FN7672 Rev.11.00
Jun.12.20
Page 115 of 139
ISL78600
11. Worked Examples
c. Write Balance Setup register: Set Balance Status Pointer = 2
BSP = 0010 (Balance status pointer = 2)
Table 70. Write Balance Setup Register (Auto Balance - Pointer = 2)
Device Address
R/W
Page
Address
Data
CRC
AAAA
1
010
010011
XX XX00 0101 0011
CCCC
X = Do not care.
AAAA = Device Address in Daisy Chain. Not needed in Stand-Alone
CCCC = CRC value in Daisy Chain. Not needed in Stand-Alone
d. Write Balance Status register: Set Bits 3, 6, 9, and 12
BAL12:1 = 1001 0010 0100
Table 71. Write Balance Status Register (Auto Balance - Pointer = 2)
Device Address
R/W
Page
Address
Data
CRC
AAAA
1
010
010100
XX 1001 0010 0100
CCCC
X = Do not care.
AAAA = Device Address in Daisy Chain. Not needed in Stand-Alone
CCCC = CRC value in Daisy Chain. Not needed in Stand-Alone
e. Write Balance Setup register: Set Balance Status Pointer = 3
BSP = 0011 (Balance status pointer = 3)
Table 72. Write Balance Setup Register (Auto Balance - Pointer = 3)
Device Address
R/W
Page
Address
Data
CRC
AAAA
1
010
010011
XX XX00 0111 0011
CCCC
X = Do not care.
AAAA = Device Address in Daisy Chain. Not needed in Stand-Alone
CCCC = CRC value in Daisy Chain. Not needed in Stand-Alone
f. Write Balance Status register: Set Bits 2, 5, 8, and 11
BAL12:1 = 0100 1001 0010
Table 73. Write Balance Status Register (Auto Balance - Pointer = 3)
Device Address
R/W
Page
Address
Data
CRC
AAAA
1
010
010100
XX 0100 1001 0010
CCCC
X = Do not care.
AAAA = Device Address in Daisy Chain. Not needed in Stand-Alone
CCCC = CRC value in Daisy Chain. Not needed in Stand-Alone
g. Write Balance Setup register: Set Balance Status Pointer = 4
BSP = 0100 (Balance status pointer = 4)
Table 74. Write Balance Setup Register (Auto Balance - Pointer = 4)
Device Address
R/W
Page
Address
Data
CRC
AAAA
1
010
010011
XX XX00 1001 0011
CCCC
X = Do not care.
AAAA = Device Address in Daisy Chain. Not needed in Stand-Alone
CCCC = CRC value in Daisy Chain. Not needed in Stand-Alone
FN7672 Rev.11.00
Jun.12.20
Page 116 of 139
ISL78600
11. Worked Examples
h. Write Balance Status register: Set bits to all zero to set the end point for the instances.
BAL12:1 = 0000 0000 0000
Table 75. Write Balance Status Register (Auto Balance - Pointer = 4)
Device Address
R/W
Page
Address
Data
CRC
AAAA
1
010
010100
XX 0000 0000 0000
CCCC
X = Do not care.
AAAA = Device Address in Daisy Chain. Not needed in Stand-Alone
CCCC = CRC value in Daisy Chain. Not needed in Stand-Alone
5. Enable balancing using Balance Enable command
Table 76. Send “Balance Enable” Command (Auto Balance)
DEVICE ADDRESS
R/W
PAGE
ADDRESS
DATA
CRC
AAAA
0
011
010000
00 0000
CCCC
AAAA = Device Address in Daisy Chain. Not needed in Stand-Alone
CCCC = CRC value in Daisy Chain. Not needed in Stand-Alone
or enable balancing by setting BEN directly in the Balance Setup register:
BEN = 1
Table 77. Write Balance Setup Register (Auto Balance)
DEVICE ADDRESS
R/W
PAGE
ADDRESS
DATA
CRC
AAAA
1
010
010011
XX XX1X XXXX XXXX
CCCC
X = Do not care.
AAAA = Device Address in Daisy Chain. Not needed in Stand-Alone
CCCC = CRC value in Daisy Chain. Not needed in Stand-Alone
The balance FETs cycle through each instance of the Balance Status register in a loop, interposing the balance
wait time between each instance. The measured voltage of each cell being balanced is subtracted from the
balance value for that cell at the end of each Balance Status instance. The process continues until the Balance
Value register for each cell contains zero.
FN7672 Rev.11.00
Jun.12.20
Page 117 of 139
ISL78600
12. System Registers
12. System Registers
System registers contain 14-bits each. All register locations are memory mapped using a 9-bit address. The
MSBs of the address form a 3-bit page address. Page 1 (3’b001) registers are the measurement result registers
for cell voltages and temperatures. Page 3 (3’b011) is used for commands. Pages 1 and 3 are not subject to the
checksum calculations. Page addresses 4 and 5 (3’b100 and 3b’101), with the exception of the EEPROM
checksum registers, are reserved for internal functions.
All Page 2 registers (device configuration registers) and EEPROM checksum registers are subject to a checksum
calculation. The checksum is calculated in response to the CRC command using a Multiple Input Shift Register
(MISR) error detection technique. The checksum is tested in response to a Check Register Checksum command.
The occurrence of a checksum error sets the PAR bit in the Fault Status register and causes a Fault response
accordingly. The normal response to a PAR error is for the host microcontroller to rewrite the Page 2 register
contents. A PAR fault also causes the device to cease any scanning or cell balancing activity.
A description of each register is included in Register Descriptions and includes a depiction of the register with bit
names and initialization values at power up or when the device receives a Reset command. Bits which reflect the
state of external pins are notated “Pin” in the initialization space. Bits which reflect the state of nonvolatile memory
bits (EEPROM) are notated “NV” in the initialization space. Initialization values are shown below each bit name.
Reserved bits (indicated by gray areas) should be ignored when reading and should be set to “0” when writing to
them.
12.1
Register Descriptions
Register locations identified as “N/A” are not available and reserved for future use.
12.1.1
Cell Voltage Data
Base Address
(Page)
3’b001
Access
Read
Only
FN7672 Rev.11.00
Jun.12.20
Address
Range
Description
6’h00 - 6’h0C Measured cell voltage and pack voltage values
and 6’h0F
Address 001111 accesses all cell and Pack Voltage data with one read operation. See Figure 88
on page 84.
Cell values are output as 13-bit signed integers with the 14th bit (MSB) denoting the sign, (for
example, positive full scale is 14’h1FFF, 8191 decimal, negative full scale is 14’h2000, 8192
decimal). VBAT is a 14-bit unsigned integer.
Page 118 of 139
ISL78600
12. System Registers
Access
Page
Address
Register
Address
Read Only
3’b001
6’h00
VBAT Voltage
6’h01
Cell 1 Voltage
6’h02
Cell 2 Voltage
6’h03
Cell 3 Voltage
6’h04
Cell 4 Voltage
6’h05
Cell 5 Voltage
6’h06
Cell 6 Voltage
6’h07
Cell 7 Voltage
6’h08
Cell 8 Voltage
6’h09
Cell 9 Voltage
6’h0A
Cell 10 Voltage
Description
6’h0B
Cell 11 Voltage
6’h0C
Cell 12 Voltage
6’h0F
Read all
cell voltages
HEXvalue
– 16384 2 2.5
10
VCx = ---------------------------------------------------------------------------------------
ifHEXvalue 10 8191
8192
HEXvalue
2 2.5
10
VCx = ----------------------------------------------------------
ifHEXvalue 10 8191
8192
HEXvalue 10 15.9350784 2.5
V BAT = ------------------------------------------------------------------------------------------------------------------------8192
HEXvalue10 = Hex to Decimal conversion of the register contents.
12.2
Temperature Data, Secondary Voltage Reference Data, Scan Count
Base
Address
(Page)
3’b001
Access
Address
Range
Description
6’h10 - 6’h16 Measured temperature, Secondary reference, Scan Count
See
individual and 6’h1F Address 011111 accesses all these data in a continuous read (see Figure 88 on page 84.)
register
Temperature and reference values are output as 14-bit unsigned integers, (such as, full scale is
14’h3FFF (16383 decimal)).
Access
Page
Address
Register
Address
Read Only
3’b001
6’h10
Description
Internal temperature reading.
HEXvalue
– 9180
10
T INTERNAL C = ------------------------------------------------------ + 25
31.9
HEXvalue10 = Hex to Decimal conversion of the register
contents.
FN7672 Rev.11.00
Jun.12.20
6’h11
External temperature Input 1
reading.
6’h12
External temperature Input 2
reading.
6’h13
External temperature Input 3
reading.
HEXvalue
2.5
10
V TEMP = -----------------------------------------------16384
T EXTERNAL C = V TEMP R DIVIDER
RDIVIDER depends on the external resistor divider circuit that
includes an NTC thermistor (see Figure 50 on page 39 for an
example external circuit.)
6’h14
External temperature Input 4
reading.
6’h15
Reference voltage (raw ADC) value. Use to calculate corrected reference value using reference
coefficient data. See Page 2 data, address 6’h38 – 6’h3A.
Page 119 of 139
ISL78600
Access
Read/
Write
12. System Registers
Page
Address
Register
Address
3’h001
6’h16
Description (Continued)
Scan Count
Current scan instruction count. Count is incremented each time a scan command is received and wraps
to zero when overflowed. Register can be compared to previous value to confirm scan command
receipt.
Bit Designations:
13
12
11
10
9
8
7
6
5
4
N/A
0
Read Only
3’h001
FN7672 Rev.11.00
Jun.12.20
6’h1F
0
0
0
0
0
0
0
0
0
3
2
1
0
SCN
3
SCN
2
SCN
1
SCN
0
0
0
0
0
Read all: Temperature Data, Secondary Voltage Reference Data, Scan Count (locations 6’h10 - 6’h16)
Page 120 of 139
ISL78600
12.3
Fault Registers
Base
Address
(Page)
3’h010
Access
Read/
Write
12. System Registers
Access
Read/
Write
Address
Range
Description
6’h00 - 6’h05 Fault registers
and 6’h0F
Fault setup and status information. Address 6’h0F accesses all fault data in a continuous read
(daisy chain configuration only). See Figure 88 on page 84.
Page
Address
Register
Address
3’h010
6’h00
Description
Overvoltage Fault
Overvoltage fault on cells 12 to 1 correspond with bits OF12 to OF1, respectively.
Default values are all zero.
Bits are set to 1 when faults are detected.
The contents of this register can be reset through a register write (14’h0000).
13
12
N/A
0
Read/
Write
3’h010
6’h01
0
6’h02
0
0
0
8
7
6
5
4
3
2
1
0
OF9
OF8
OF7
OF6
OF5
OF4
OF3
OF2
OF1
0
0
0
0
0
0
0
0
0
12
0
11
10
9
8
7
6
5
4
3
2
1
0
UF12
UF11
UF10
UF9
UF8
UF7
UF6
UF5
UF4
UF3
UF2
UF1
0
0
0
0
0
0
0
0
0
0
0
0
Open-Wire Fault
Open Wire fault on Pins VC12 to VC0 correspond with bits OC12 to OC0, respectively.
Default values are all zero.
Bits are set to 1 when faults are detected.
The contents of this register can be reset through a register write (14’h0000).
13
N/A
0
FN7672 Rev.11.00
Jun.12.20
9
Undervoltage Fault
Undervoltage fault on cells 12 to 1 correspond with bits UF12 to UF1, respectively.
Default values are all zero.
Bits are set to 1 when faults are detected.
The contents of this register can be reset through a register write (14’h0000).
N/A
3’h010
10
OF12 OF11 OF10
0
13
Read/
Write
11
12
11
10
OC12 OC11 OC10
0
0
0
9
8
7
6
5
4
3
2
1
0
OC9
OC8
OC7
OC6
OC5
OC4
OC3
OC2
OC1
OC0
0
0
0
0
0
0
0
0
0
0
Page 121 of 139
ISL78600
Fault Setup
These bits control various Fault configurations.
Default values are shown below, as are descriptions of each bit.
0
0
0
0
0
1
0
1
1
4
0
3
0
2
0
1
0
0
SCN0
5
SCN1
6
SCN2
7
SCN3
8
WSCN
9
TOT0
10
0
SCN0,
SCN1,
SCN2,
SCN3
Scan interval code. Decoded to provide the scan interval setup for the auto scan function.
Initialized to 0000 (16ms scan interval). See Table 16 on page 55.
WSCN
Scan Wires timing control (See Table 16 on page 55.) This bit only affects timing in Scan
Continuous mode.
When this bit is 0 (default), Scan Wires is performed at the same rate as Scan Voltages,
except when the SCN3:0 bits select a scan interval of 512 ms or less. In this case Scan
Wires is performed every 512 ms.
When this bit is 1, Scan Wires is performed at the same rate as Scan Temperatures.
TOT0,
TOT1,
TOT2
Fault Totalizer code bits. Decoded to provide the required fault totalization. An unbroken
sequence of positive fault results equal to the totalize amount is needed to verify a fault
condition. Initialized to 011 (8 sample totalizing.) See Table 47 on page 101.
This register must be rewritten following an error detection resulting from totalizer overflow.
TST0
Controls temperature testing of internal IC temperature. Set bit to 1 to enable internal
temperature test. Set to 0 to disable (not recommended). Initialized to 1 (on).
TST1 to
TST4
FN7672 Rev.11.00
Jun.12.20
11
TOT1
N/A
12
TOT2
13
TST0
6’h03
TST1
3’h010
Description (Continued)
TST2
Register
Address
TST3
Read/
Write
Page
Address
TST4
Access
12. System Registers
Controls temperature testing on the external temperature inputs 1 to 4, respectively. Set bit
to 1 to enable the corresponding temperature test. Set to 0 to disable. Allows external
inputs to be used for general voltage monitoring without imposing a limit value.
TST1 to TST4 are initialized to 0 (off).
Page 122 of 139
ISL78600
Fault Status
The FAULT logic output is an OR function of the bits in this register: the output is asserted low if any bits in
the Fault Status register are set.
0
0
OSC
WDGF
FN7672 Rev.11.00
Jun.12.20
0
0
0
0
7
0
6
0
5
0
4
0
3
0
2
1
0
0
N/A
OSC
8
WDGF
9
OT
10
OV
11
UV
12
REG
MUX
13
OW
6’h04
OVBAT
3’h010
Description (Continued)
OVSS
Register
Address
PAR
Read/
Write
Page
Address
REF
Access
12. System Registers
0
0
Oscillator fault bit. Bit is set in response to a fault on either the 4MHz or 32kHz oscillators.
Note that communications functions can be disrupted by a fault in the 4MHz oscillator.
Watchdog timeout fault. Bit is set in response to a watchdog timeout.
OT
Over-temperature fault. ‘OR’ of over-temperature fault bits: TFLT0 to TFLT4. This bit is
latched. The bits in the over-temperature fault register must first be reset before this bit can
be reset. Reset by writing 14’h0000 to this register.
OV
Overvoltage fault. ‘OR’ of overvoltage fault bits: OF1 to OF12. This bit is latched. The bits in
the Overvoltage Fault register must be reset before this bit can be reset. Reset by writing
14’h0000 to this register.
UV
Undervoltage fault. ‘OR’ of undervoltage fault bits: UF1 to UF12. This bit is latched. The bits
in the Undervoltage Fault register must be reset before this bit can be reset. Reset by
writing 14’h0000 to this register.
OW
Open-wire fault. ‘OR’ of open-wire fault bits: OC0 to OC12. This bit is latched. The bits in
the open-wire fault register must be reset before this bit can be reset. Reset by writing
14’h0000 to this register.
OVBAT
Open-wire fault on VBAT connection. Bit set to 1 when a fault is detected. Can be reset
through a register write (14’h0000).
OVSS
Open wire fault on VSS connection. Bit set to 1 when a fault is detected. Can be reset
through a register write (14’h0000).
PAR
Register checksum (Parity) error. This bit is set in response to a register checksum error.
The checksum is calculated and stored in response to a Calc Register Checksum
command and acts on the contents of all Page 2 registers. The Check Register Checksum
command, see Table 12.4.3 on page 130, is used to repeat the calculation and compare the
results to the stored value. The PAR bit is then set if the two results are not equal. This bit is
not set in response to a nonvolatile EEPROM memory checksum error.
REF
Voltage reference fault. This bit is set if the voltage reference value is outside its
“power-good” range.
REG
Voltage regulator fault. This bit is set if a voltage regulator value (V3P3, VCC or V2P5) is
outside its “power-good” range.
MUX
Temperature multiplexer error. This bit is set if the VCC loopback check returns a fault. The
VCC loopback check is performed at the end of each temperature scan.
Page 123 of 139
ISL78600
Access
Read/
Write
12. System Registers
Page
Address
Register
Address
3’h010
6’h05
Description (Continued)
Cell Setup
Default values are shown below, as are descriptions of each bit.
13
12
FFSN FFSP
0
0
C1 to C12
11
10
9
8
7
6
5
4
3
2
1
0
C12
C11
C10
C9
C8
C7
C6
C5
C4
C3
C2
C1
0
0
0
0
0
0
0
0
0
0
0
0
Enable/disable cell overvoltage, undervoltage and open-wire detection on Cell 1 to 12,
respectively. Set to 1 to disable OV/UV and open wire tests. Note: Cell voltage readings for
disabled cells are not valid, so should be discarded.
FFSP
Force ADC input to Full Scale Positive. All cell scan readings forced to 14'h1FFF. All
temperature scan readings forced to 14'h3FFF.
FFSN
Force ADC input to Full Scale Negative. All cell scan readings forced to 14'h2000. All
temperature scan readings forced to 14'h0000.
Note: The ADC input functions normally if both FFSN and FFSP are set to '1' but this setting is not
supported.
Over-temperature Fault
Over-temperature fault on Cells 12 to 1 correspond with bits OF12 to OF1, respectively.
Default values are all zero.
Bits are set to 1 when fault are detected.
The contents of this register can be reset through a register write (14’h0000).
11
10
9
8
7
6
5
0
0
0
0
N/A
0
Read
Only
12.3.1
Base
Address
(Page)
3’h010
6’h0F
0
0
0
0
3
0
2
0
1
0
0
0
TFLT0
Internal over-temperature fault. Bit set to 1 when a fault is detected. Can be reset through a
register write (14’h0000).
TFLT1 TFLT4
External over-temperature inputs 1 to 4 (respectively.) Bit set to 1 when a fault is detected.
Can be reset through a register write (14’h0000).
Read all Fault and Cell Setup data from locations: 6’h00 - 6’h06. See Figure 88 on page 84.
Setup Registers
Access
3’b010
Address
Range
Description
6’h10 - 6’h1D Device Setup registers
and 6’h1F
All device setup data.
Page
Access Address
Read/
Write
0
4
TFLT0
12
TFLT1
13
TFLT2
6’h06
TFLT3
3’h010
TFLT4
Read/
Write
Register
Address
3’b010
6’h10
Description
Overvoltage Limit
Overvoltage Limit Value
Overvoltage limit is compared to the measured values for Cells 1 to 12 to test for an Overvoltage condition
at any of the cells.
Bit 0 is the LSB, Bit 12 is the MSB. Bit 13 is not used and must be set to 0.
13
N/A
0
FN7672 Rev.11.00
Jun.12.20
12
11
10
OV12 OV11 OV10
1
1
1
9
8
7
6
5
4
3
2
1
0
OV9
OV8
OV7
OV6
OV5
OV4
OV3
OV2
OV1
OV0
1
1
1
1
1
1
1
1
1
1
Page 124 of 139
ISL78600
Undervoltage Limit
Undervoltage Limit Value
Undervoltage limit is compared to the measured values for Cells 1 to 12 to test for an undervoltage
condition at any of the cells.
Bit 0 is the LSB, Bit 12 is the MSB. Bit 13 is not used and must be set to 0.
13
N/A
0
5
4
3
2
1
0
UV9
UV8
UV7
UV6
UV5
UV4
UV3
UV2
UV1
UV0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
5
4
0
3
2
1
0
ETL0
6
ETL1
7
ETL2
8
ETL3
9
ETL4
10
ETL5
11
ETL6
12
0
0
0
0
0
4
3
2
1
0
0
0
BMD0,
BMD1
BEN
0
7
0
0
6
0
5
0
0
0
0
0
BMD0
0
N/A
8
BMD1
0
9
BWT0
10
BWT2
11
BSP0
12
BWT1
Balance Setup
Default values are shown below, as are descriptions of each bit.
13
FN7672 Rev.11.00
Jun.12.20
6
BSP1
6’h13
0
7
ETL7
ETL13
0
3’b010
0
8
External Temperature Limit
Over-temperature Limit Value
Over-temperature limit is compared to the measured values for external temperatures 1 to 4 to test for an
over-temperature condition at any input. The temperature limit assumes NTC temperature measurement
devices (i.e., an over-temperature condition is indicated by a temperature reading below the limit value).
Bit 0 is the LSB, Bit 13 is the MSB.
13
Read/
Write
UV12 UV11 UV10
9
BSP2
6’h12
10
ETL8
3’b010
11
BSP3
Read/
Write
12
ETL9
6’h11
ETL10
3’b010
Description (Continued)
ETL11
Read/
Write
Register
Address
ETL12
Page
Access Address
12. System Registers
0
Balance mode. These bits set balance mode.
BMD1
BMD0
Mode
0
0
OFF
0
1
Manual
1
0
Timed
1
1
Auto
BWT0,
BWT1,
BWT2
Balance wait time. Register contents are decoded to provide the required wait time
between device balancing. This is to assist with thermal management and is used
with the Auto Balance mode. See Table 21 on page 63.
BSP0,
BSP1,
BSP2,
BSP3
Balance Status register pointer. Points to one of the 13 incidents of the Balance
Status register. Balance Status register 0 is used for Manual Balance mode and
Timed Balance mode. Balance status registers 1 to 12 are used for Auto Balance
mode. Reads and writes to the Balance Status register are accomplished by first
configuring the Balance Status register pointer (such as, to read (write) Balance
Status register 5, load 0101 to the Balance Status register pointer, then read (write)
to the Balance Status register). See Table 21 on page 63.
BEN
Balance enable. Set to ‘1’ to enable balancing. ‘0’ inhibits balancing. Setting or
clearing this bit does not affect any other register contents. Balance Enable and
Balance Inhibit commands are provided to allow control of this function without
requiring a register write. These commands have the same effect as setting this bit
directly. This bit is cleared automatically when balancing is complete and the EOB
bit is set (see “Device Setup” on page 127).
Page 125 of 139
ISL78600
Balance Status
The Balance Status register is a multiple incidence register controlled by the BSP0-4 bits in the Balance
setup register. See Table 21 on page 63.
Bit 0 is the LSB, Bit 11 is the MSB.
0
0
0
BAL1 to BAL12
0
0
0
0
0
0
0
1
0
0
BAL1
2
BAL2
3
BAL3
4
BAL4
5
BAL5
6
BAL6
7
0
Cell 1 to Cell 12 balance control, respectively. A bit set to 1 enables balance control
(turns FET on) of the corresponding cell. Writing this bit enables balance output for
the current incidence of the Balance Status register for the cells corresponding to
the particular bits, depending on the condition of BEN in the Balance Setup
register. Read this bit to determine the current status of each cell’s balance control.
Watchdog/Balance Time
Defaults are shown below:
0
0
0
0
0
0
0
1
5
1
4
1
3
1
2
1
1
1
0
WDG0
6
WDG1
7
WDG2
8
WDG3
9
WDG4
10
WDG5
11
WDG6
12
BTM5
BTM6
13
FN7672 Rev.11.00
Jun.12.20
0
8
BTM0
6’h15
0
9
BTM1
3’b010
BTM4
Read/
Write
10
BAL7
BAL12
N/A
11
BAL8
12
BAL8
13
BAL10
6’h14
BTM2
3’b010
Description (Continued)
BAL11
Read/
Write
Register
Address
BTM3
Page
Access Address
12. System Registers
1
WDG0 to WDG6
Watchdog timeout setting. Decoded to provide the time out value for the watchdog
function. See “Watchdog Function” on page 105 for details. The watchdog can only
be disabled (set to 7’h00) if the watchdog password is set. The watchdog setting
can be changed to a nonzero value without writing to the watchdog password.
Initialized to 7’h7F (128 minutes).
BTM0 to BTM6
Balance timeout setting. Decoded to provide the time out value for Timed Balance
mode and Auto Balance mode. Initialized to 7’00 (Disabled). See Table 23 on
page 65.
Page 126 of 139
ISL78600
Page
Access Address
12. System Registers
Register
Address
Description (Continued)
6’h16
6’h17
User Register
28 bits of register space arranged as 2 x 14 bits available for user data. These registers have no effect on
the operation of the ISL78600. These registers are included in the register checksum function.
Read
Only
3’b010
6’h18
Comms Setup
0
0
0
0
0
0
0
ADDR0
1
ADDR1
2
ADDR2
3
ADDR3
4
SIZE0
5
SIZE1
SIZE2
CSEL1
SIZE3
0
6
0
0
Device stack size (top stack device address). Corresponds to the number of
devices in the stack. The stack size is determined automatically by the stack
devices in response to an “Identify” command. The resulting number is stored in
SIZE0-3 and is used internally for communications paring and sequencing. The
stack size can be read by the user but not written to.
CSEL1,
CSEL2
Communications setup bits. These bits reflect the state of the COMMS SELECT 1,
2 pins and determine the operating mode of the communications ports. See
Table 7 on page 35.
CRAT0,
CRAT1
Communications rate bits. These bits reflect the state of the COMMS RATE 0,1
pins and determine the bit rate of the daisy chain communications system. Table 8
on page 36.
Device Setup
0
PIN37, PIN39
0
0
0
0
0
0
0
0
1
2
1
0
Pin
0
PIN39
3
PIN37
4
N/A
5
EOB
6
SCAN
7
ISCN
8
N/A
9
BDDS
10
WP0
11
WP1
12
WP2
13
0
FN7672 Rev.11.00
Jun.12.20
7
SIZE0-SIZE3
WP3
6’h19
8
Device Address. The Device Address (device position in the stack) is determined
automatically by the device in response to an “Identify” command. The resulting
address is stored in ADDR0-3 and is used internally for communications paring
and sequencing. The Device Address can be read by the user but not written to.
WP4
3’b010
9
ADDR0-ADDR3
WP5
Read/
Write
0
10
COMMS SEL 1
pin
N/A
11
CSEL2
12
COMMS SEL 2
pin
13
COMMS RATE 0 CRAT0
pin
3’b010
COMMS RATE 1 CRAT1
pin
Read/
Write
Pin
These bits indicate the signal level on pin 37 and pin 39 of the device.
EOB
End Of Balance. This bit is set by the device when balancing is complete. This
function is used in the Timed Balance mode and Auto Balance mode. The BEN bit
is cleared as a result of this bit being set. Initialized to 1.
SCAN
Scan Continuous mode. This bit is set in response to a Scan Continuous command
and cleared by a Scan Inhibit command.
ISCN
Set wire scan current source/sink values. Set to 0 for 150µA. Set to 1 for 1mA.
BDDS
Balance condition during measurement. Controls the balance condition in Scan
Continuous mode and Auto Balance mode. Set to 1 to have balancing functions
turned off 10ms prior to and during cell voltage measurement. Set to 0 for normal
operation (balancing functions not affected by measurement).
WP5:0
Watchdog disable password. These bits must be set to 6’h3A (111010) before the
watchdog can be disabled. Disable watchdog by writing 7’h00 to the watchdog bits.
Page 127 of 139
ISL78600
12. System Registers
Internal Temperature Limit
Bit 0 is the LSB, Bit 13 is the MSB.
1
1
0
ITL1 to ITL12
1
0
0
1
0
0
3
0
0
2
0
1
1
0
ITL0
4
ITL1
5
ITL2
6
ITL3
7
ITL4
8
ITL5
9
ITL6
10
ITL7
11
ITL8
12
ITL12
13
ITL9
6’h1A
ITL10
3’b010
Description (Continued)
ITL13
Read
Only
Value
set in
EEPRO
M
Register
Address
ITL11
Page
Access Address
0
IC over-temperature limit value. Over-temperature limit is compared to the
measured values for internal IC temperature to test for an over-temperature
condition. The internal temperature limit value is stored in nonvolatile memory
during test and loaded to these register bits at power up. The register contents can
be read by the user but not written to.
Read
Only
3’b010
6’h1B
6’h1C
Serial Number
The 28b serial number programmed in nonvolatile memory during factory test is mirrored to these 2 x 14
bit registers. The serial number can be read at any time but can not be written.
Read
Only
Value
set in
EEPRO
M
3’b010
6’h1D
Trim Voltages
13
12
11
10
9
8
TV5
TV4
TV3
TV2
TV1
TV0
N/A
1
0
0
0
0
1
Ignore the contents of these bits
TV5:0
Read
Only
12.3.2
Base
Address
(Page)
3’b010
Access
Read/
Write
3’h010
6’h1F
7
6
5
4
3
2
1
0
Trim voltage (VNOM). The nominal cell voltage is programmed to nonvolatile
memory during test and loaded to the Trim Voltage register at power up. The
VNOM value is a 6-bit representation of the 0V to 5V cell voltage input range with
5010 (6’h32) representing 5V. By default the trim value is 6’h21, which translates to
33 decimal, or 3.3V. The parts are additionally marked with the trim voltage by the
addition of a two digit code to the part number such as, 3.3V is denoted by the
code 33.
Read all Setup data from locations: 6’h10 - 6’h1D. See Figure 88 on page 84.
Cell Balance Registers
Access
Read/
Write
Address
Range
6’h20 - 6’h37
Description
Cell balance registers
These registers are loaded with data related to change in SOC desired for each cell. This data is
then used during Auto Balance mode. The data value is decremented with each successive ADC
sample until a zero value is reached. The register space is arranged as 2 x 14-bit per cell for 24 x
14-bit total. The registers are cleared at device power up or by a Reset command. See “Auto
Balance Mode” on page 65.
Page
Address
Register
Address
3’b010
6’h20
Cell 1 balance value Bits 0 to 13.
6’h21
Cell 1 balance value Bits 14 to 27.
Description
~
FN7672 Rev.11.00
Jun.12.20
6’h36
Cell 12 balance value Bits 0 to 13.
6’h37
Cell 12 balance value Bits 14 to 27.
Page 128 of 139
ISL78600
12.4
12. System Registers
Reference Coefficient Registers
12.4.1
Reference Coefficient C
Reference calibration coefficient C LSB. Use with coefficients A and B and the measured
reference value to obtain the compensated reference measurement. This result can be compared
to limits given in parameter “VRACC” in the “Voltage Reference/Oscillator Check Specifications” on
page 16 to check that the reference is within limits. The register contents can be read by the user
but not written to.
NV
NV
NV
NV
NV
NV
NV
0
RCC0
1
RCC1
2
RCC2
3
RCC3
4
RCC4
5
RCC5
RCC6
RCC8
RCC9
RCC7
NV
6
NV
NV
NV
NV
NV
NV
NV
NV
NV
4
NV
3
NV
2
NV
1
NV
0
RCB0
5
RCB1
6
RCB2
7
RCB3
8
RCB4
9
RCB5
10
RCB6
11
RCB7
12
NV
Reference Coefficient A
Reference calibration coefficient A LSB. Use with coefficients B and C and the measured
reference value to obtain the compensated reference measurement. This result can be compared
to limits given in parameter “VRACC” in the “Voltage Reference/Oscillator Check Specifications” on
page 16 to check that the reference is within limits. The register contents can be read by the user
but not written to.
NV
NV
11
NV
10
NV
9
NV
8
NV
7
NV
6
NV
5
RCA0
12
RCA1
RCA8
13
FN7672 Rev.11.00
Jun.12.20
7
RCA2
6’h3A
NV
RCB8
RCB13
NV
3’b010
NV
8
Reference Coefficient B
Reference calibration coefficient B LSB. Use with coefficients A and C and the measured
reference value to obtain the compensated reference measurement. This result can be compared
to limits given in parameter “VRACC” in the “Voltage Reference/Oscillator Check Specifications” on
page 16 to check that the reference is within limits. The register contents can be read by the user
but not written to.
13
Read Only
NV
9
RCA3
6’h39
NV
10
RCB9
3’b010
NV
11
RCA4
Read Only
12
RCC10
RCC13
13
RCB10
6’h38
RCA5
3’b010
Description
RCC11
Register
Address
RCB11
Page
Address
Reference Coefficients
Bit 13 is the MSB, Bit 0 is the LSB
RCA6
Read Only
Value set in
EEPROM
6’h38 - 6’h3A
Description
RCC12
Access
Read
Only
Address
Range
RCB12
3’b010
Access
RCA7
Base
Address
(Page)
NV
4
3
2
1
0
N/A
Ignore the content of these bits
Page 129 of 139
ISL78600
Description
6’h3B
Cells Balance Enabled (Valid for non-daisy chain configuration only)
This register reports the current condition of the cell balance outputs.
Bit 0 is the LSB, Bit 11 is the MSB.
12
0
CBEN12
N/A
11
0
0
10
0
9
0
8
0
7
0
6
5
0
0
4
0
3
0
2
0
1
0
CBEN1
13
CBEN2
6’h3B
CBEN3
3’b010
CBEN4
Read Only
Description
CBEN5
Register
Address
CBEN6
Page
Address
CBEN7
Access
Cells In Balance
CBEN8
Read
Only
Address
Range
CBEN8
3’b010
Access
CBEN10
Base
Address
(Page)
Cells In Balance Register
CBEN11
12.4.2
12. System Registers
0
0
CBEN1 to CBEN12 Indicates the current balancing status of Cell 1 to Cell 12 (respectively). “1”
indicates balancing is enabled for this cell. “0” indicates that balancing is turned
off.
12.4.3
Base
Address
(Page)
Device Commands
Access
Address
Range
3’b011
Read
Only
Page
Address
Register
Address
3’b011
6’h01
Scan Voltages. Device responds by scanning VBAT and all 12 cell voltages and storing the results in local
memory.
6’h02
Scan Temperatures. Device responds by scanning external temperature inputs, internal temperature, and the
secondary voltage reference, and storing the results in local memory.
6’h03
Scan Mixed. Device responds by scanning VBAT, cell and ExT1 voltages and storing the results in local memory.
The ExT1 measurement is performed in the middle of the cell voltage scans to minimize measurement latency
between the cell voltages and the voltage on ExT1.
6’h04
Scan Wires. Device responds by scanning for pin connection faults and stores the results in local memory.
6’h05
Scan All. Device responds by performing the functions of the Scan Voltages, Scan Temperatures, and Scan
Wires commands in sequence. Results are stored in local memory.
6’h06
Scan Continuous. Places the device in Scan Continuous mode by setting the Device Setup register SCAN bit.
6’h07
Scan Inhibit. Stops Scan Continuous mode by clearing the Device Setup register SCAN bit.
6’h08
Measure. Device responds by measuring a targeted single parameter (cell voltage/VBAT/external or internal
temperatures or secondary voltage reference).
6’h09
Identify. Special mode function used to determine device stack position and address. Devices record their own
Device Address and the total number of devices in the stack. See “Identify Command” on page 69 for details.
6’h0A
Sleep. Places the part in Sleep mode (wakeup through daisy comms). See “Communication Timing” on page 84.
FN7672 Rev.11.00
Jun.12.20
6’h01 - 6’h14
Description
Device commands.
Actions and communications administration. Not physical registers but memory mapped device
commands. Commands from host and device responses are all configured as reads (BASE
ADDR MSB = 0).
Write operations breaks the communication rules and produce NAK from the target device.
Description
Page 130 of 139
ISL78600
Page
Address
12.5
12. System Registers
Register
Address
Description
6’h0B
NAK. Device response if communications is not recognized. The device responds NAK down the daisy chain to
the host microcontroller. The host microcontroller typically retransmits on receiving a NAK.
6’h0C
ACK. Used by host microcontroller to verify communications without changing anything. Devices respond with
ACK.
6’h0E
Communications Failure. Used in daisy chain implementations to communicate Communications Failure. If a
communication is not acknowledged by a stack device, the last stack device that did receive the communication
responds with Communications Failure. This is part of the communications integrity checking. Devices
downstream of a communications fault are alerted to the fault condition by the watchdog function.
6’h0F
Wakeup. Used in daisy chain implementations to wake up a sleeping stack of devices. The Wakeup command is
sent to the Bottom stack device (Master device) through SPI. The Master device then wakes up the rest of the
stack by transmitting a low frequency clock. The Top stack device responds ACK when it is awake. See “Wakeup
Command” on page 60.
6’h10
Balance Enable. Enables cell balancing by setting BEN. Can be used to enable cell balancing on all devices
simultaneously using the “Address All” address 1111.
6’h11
Balance Inhibit. Disables cell balancing by clearing BEN. Can be used to disable cell balancing on all devices
simultaneously using the “Address All” address 1111.
6’h12
Reset. Resets all digital registers to its power-up state (i.e., reloads the factory programmed configuration data
from non-volatile memory. Stops all scan and balancing activity. Daisy chain devices must be reset in sequence
starting with the Top stack device and proceeding down the stack to the Bottom (Master) device. The Reset
command must be followed by an Identify command (daisy chain configuration) before volatile registers can be rewritten.
6’h13
Calculate register checksum. Calculates the checksum value for the current Page 2 register contents (registers
with base address 0010). See “System Hardware Connection” on page 29.
6’h14
Check register checksum. Verifies the register contents are correct for the current checksum. An incorrect result
sets the PAR bit in the Fault status register which starts a standard fault response. See “System Hardware
Connection” on page 29.
Nonvolatile Memory (EEPROM) Checksum
A checksum is provided to verify the contents of EEPROM memory. Two registers are provided. The MISR
register (below) contains the correct checksum value, which is calculated during factory testing. The MISR
Shadow register contains the checksum value that is calculated each time the nonvolatile memory is loaded to
shadow registers, either after a power cycle or after a device receives a Reset command. See “Fault Diagnostics”
on page 107.
Base
Address
(Page)
Access
Address
Range
Description
100
Read
Only
6’h3F
Nonvolatile memory Multiple Input Shift Register (MISR) register. This checksum value for the
nonvolatile memory contents. It is programmed during factory testing.
101
Read
Only
6’h00
MISR shadow register checksum value. This value is calculated when shadow registers are
loaded from nonvolatile memory either after a power cycle or a software reset.
FN7672 Rev.11.00
Jun.12.20
Page 131 of 139
ISL78600
13. Register Map
13. Register Map
R/W + Page
Read
0001
0001
0001
0001
0001
0001
0001
0001
0001
0001
0001
0001
0001
Write
Bit 7
Address
000000
000001
000010
000011
000100
000101
000110
000111
001000
001001
001010
001011
001100
Register Name
VBAT Voltage
Cell 1 Voltage
Cell 2 Voltage
Cell 3 Voltage
Cell 4 Voltage
Cell 5 Voltage
Cell 6 Voltage
Cell 7 Voltage
Cell 8 Voltage
Cell 9 Voltage
Cell 10 Voltage
Cell 11 Voltage
Cell 12 Voltage
0001
001111
All Cell Voltage Data
0001
010000
IC Temperature
0001
0001
0001
0001
010001
010010
010011
010100
FN7672 Rev.11.00
Jun.12.20
Bit 6
VB7
C1V7
C2V7
C3V7
C4V7
C5V7
C6V7
C7V7
C8V7
C9V7
C10V7
C11V7
C12V7
VB6
C1V6
C2V6
C3V6
C4V6
C5V6
C6V6
C7V6
C8V6
C9V6
C10V6
C11V6
C12V6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
VB5
VB4
VB3
VB2
VB1
VB0
VB13
VB12
VB11
VB10
VB9
VB8
C1V5
C1V4
C1V3
C1V2
C1V1
C1V0
C1V13
C1V12
C1V11
C1V10
C1V9
C1V8
C2V5
C2V4
C2V3
C2V2
C2V1
C2V0
C2V13
C2V12
C2V11
C2V10
C2V9
C2V8
C3V5
C3V4
C3V3
C3V2
C3V1
C3V0
C3V13
C3V12
C3V11
C3V10
C3V9
C3V8
C4V5
C4V4
C4V3
C4V2
C4V1
C4V0
C4V13
C4V12
C4V11
C4V10
C4V9
C4V8
C5V5
C5V4
C5V3
C5V2
C5V1
C5V0
C5V13
C5V12
C5V11
C5V10
C5V9
C5V8
C6V5
C6V4
C6V3
C6V2
C6V1
C6V0
C6V13
C6V12
C6V11
C6V10
C6V9
C6V8
C7V5
C7V4
C7V3
C7V2
C7V1
C7V0
C7V13
C7V12
C7V11
C7V10
C7V9
C7V8
C8V5
C8V4
C8V3
C8V2
C8V1
C8V0
C8V13
C8V12
C8V11
C8V10
C8V9
C8V8
C9V5
C9V4
C9V3
C9V2
C9V1
C9V0
C9V13
C9V12
C9V11
C9V10
C9V9
C9V8
C10V5
C10V4
C10V3
C10V2
C10V1
C10V0
C10V13
C10V12
C10V11
C10V10
C10V9
C10V8
C11V5
C11V4
C11V3
C11V2
C11V1
C11V0
C11V13
C11V12
C11V11
C11V10
C11V9
C11V8
C12V5
C12V4
C12V3
C12V2
C12V1
C12V0
C12V13
C12V12
C12V11
C12V10
C12V9
C12V8
Daisy chain configuration only. This command returns all Page 1 data from address
6’h00 through 6’h0C in a single data stream. See ““Response Timing Tables” on
page 96 and “System Out of Limit Detection” on page 94. See example in
Figure 88 on page 84.
ICT7
External Temperature 1
Input Voltage (ExT1 pin)
ET1V7
External Temperature 2
Input Voltage (ExT2 pin)
ET2V7
External Temperature 3
Input Voltage (ExT3 pin)
ET3V7
External Temperature 4
Input Voltage (ExT4 pin)
ET4V7
ICT6
ET1V6
ET2V6
ET3V6
ET4V6
ICT5
ICT4
ICT3
ICT2
ICT1
ICT0
ICT13
ICT12
ICT11
ICT10
ICT9
ICT8
ET1V5
ET1V4
ET1V3
ET1V2
ET1V1
ET1V0
ET1V13
ET1V12
ET1V11
ET1V10
ET1V9
ET1V8
ET2V5
ET2V4
ET2V3
ET2V2
ET2V1
ET2V0
ET2V13
ET2V12
ET2V11
ET2V10
ET2V9
ET2V8
ET3V5
ET3V4
ET3V3
ET3V2
ET3V1
ET3V0
ET3V13
ET3V12
ET3V11
ET3V10
ET3V9
ET3V8
ET4V5
ET4V4
ET4V3
ET4V2
ET4V1
ET4V0
ET4V13
ET4V12
ET4V11
ET4V10
ET4V9
ET4V8
Page 132 of 139
ISL78600
13. Register Map
R/W + Page
Read
Write
0001
Bit 7
Address
010101
Register Name
Secondary Reference
Voltage
0001
010110
Scan Count
0001
011111
All Temperature Data
000000
Overvoltage Fault
0010
0010
0010
0010
0010
0010
0010
1010
1010
1010
1010
1010
1010
1010
0010
0010
0010
0010
0010
0010
0010
0010
0010
1010
1010
1010
1010
1010
1010
1010
1010
000001
000010
000011
000100
000101
Undervoltage Fault
Open-Wire Fault
Fault Setup
Fault Status
Cell Setup
000110
Over-Temperature Fault
001111
All Fault Data
010000
Overvoltage Limit
010001
010010
010011
010100
010101
010110
010111
FN7672 Rev.11.00
Jun.12.20
Bit 6
Undervoltage Limit
External Temp Limit
Balance Setup
RV7
OF8
UF8
OC7
TOT2
OW
C8
Bit 3
Bit 2
Bit 1
Bit 0
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
RV5
RV4
RV3
RV2
RV1
RV0
RV13
RV12
RV11
RV10
RV9
RV8
SCN3
SCN2
SCN1
SCN0
OF7
UF7
OC6
TOT1
UV
C7
OF6
OF4
OF3
OF2
OF1
OF12
OF11
OF10
OF9
UF4
UF3
UF2
UF1
UF12
UF11
UF10
UF9
OC4
OC3
OC2
OC1
OC0
OC12
OC11
OC10
OC9
OC8
WSCN
SCN3
SCN2
SCN1
SCN0
TTST4
TTST3
TTST2
TTST1
TTST0
OV
OT
WDGF
OSC
0
0
MUX
REG
REF
PAR
OVSS
OVBAT
C6
C5
C4
C3
C2
C1
FFSN
FFSP
C12
C11
C10
C9
TFLT4
TFLT3
TFLT2
TFLT1
TFLT0
UF6
OC5
TOT0
OF5
UF5
Daisy chain configuration only. This command returns all Page 2 data from address
6’h00 through 6’h06 in a single data stream. See ““Response Timing Tables” on
page 96 and “System Out of Limit Detection” on page 94. See example in
Figure 88 on page 84.
OV7
UV7
ETL7
BSP2
BAL8
Watchdog/Balance Time
BTM0
User Register
Bit 4
Daisy chain configuration only. This command returns all Page 1 data from address
6’h10 through 6’h16 in a single data stream. See ““Response Timing Tables” on
page 96 and “System Out of Limit Detection” on page 94. See example in
Figure 88 on page 84.
Balance Status
(Cells to Balance)
User Register
RV6
Bit 5
UR7
UR21
OV6
UV6
ETL6
BSP1
BAL7
WDG6
UR6
UR20
OV5
OV4
OV3
OV2
OV1
OV0
OV13
OV12
OV11
OV10
OV9
OV8
UV5
UV4
UV3
UV2
UV1
UV0
UV13
UV12
UV11
UV10
UV9
UV8
ETL5
ETL4
ETL3
ETL2
ETL1
ETL0
ETL13
ETL12
ETL11
ETL10
ETL9
ETL8
BSP0
BWT2
BWT1
BWT0
BMD1
BMD0
BEN
BSP3
BAL6
BAL5
BAL4
BAL3
BAL2
BAL1
BAL12
BAL11
BAL10
BAL9
WDG5
WDG4
WDG3
WDG2
WDG1
WDG0
BTM6
BTM5
BTM4
BTM3
BTM2
BTM1
UR5
UR4
UR3
UR2
UR1
UR0
UR13
UR12
UR11
UR10
UR9
UR8
UR19
UR18
UR17
UR16
UR15
UR14
UR27
UR26
UR25
UR24
UR23
UR22
Page 133 of 139
ISL78600
13. Register Map
R/W + Page
Read
Write
0010
0010
Bit 7
Address
011000
1010
0010
011001
011010
0010
011011
011100
0010
0010
011101
Bit 6
Register Name
Comms Setup
Device Setup
Internal Temp Limit
Serial Number 0
Serial Number 1
SIZE3
BDDS
ITL7
SN7
SN21
SIZE2
0
ITL6
SN6
SN20
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
SIZE1
SIZE0
ADDR3
ADDR2
ADDR1
ADDR0
CRAT1
CRAT0
CSEL2
CSEL1
ISCN
SCAN
EOB
0
Pin 37
Pin 39
WP5
WP4
WP3
WP2
WP1
WP0
ITL5
ITL4
ITL3
ITL2
ITL1
ITL0
ITL13
ITL12
ITL11
ITL10
ITL9
ITL8
SN5
SN4
SN3
SN2
SN1
SN0
SN13
SN12
SN11
SN10
SN9
SN8
SN19
SN18
SN17
SN16
SN15
SN14
SN27
SN26
SN25
SN24
SN23
SN22
TV3
TV2
TV1
TV0
Trim Voltage
N/A
TV5
0010
0010
0010
0010
0010
1010
1010
1010
1010
011111
All Setup Data
100000
Cell 1 Balance Value 0
100001
100010
100011
~
0010
0010
0010
0010
0010
1010
110111
111000
111001
111010
111011
Cell 1 Balance Value 1
Cell 2 Balance Value 0
Cell 2 Balance Value 1
Daisy chain configuration only. This command returns all Page 2 data from address
6’h10 through 6’h1D in a single data stream. See ““Response Timing Tables” on
page 96 and “System Out of Limit Detection” on page 94. See example in
Figure 88 on page 84.
B0107
B0121
B0207
B0221
B0106
B0120
B0206
B0220
B0105
B0104
B0103
B0102
B0101
B0100
B0113
B0112
B1011
B0110
B0109
B0108
B0119
B0118
B0117
B0116
B0115
B0114
B0127
B0126
B0125
B0124
B0123
B0122
B0205
B0204
B0203
B0202
B0201
B0200
B0213
B0212
B1011
B0210
B0209
B0208
B0219
B0218
B0217
B0216
B0215
B0214
B0227
B0226
B0225
B0224
B0223
B0222
~
Cell 12 Balance Value 1
Reference Coefficient C
Reference Coefficient B
Reference Coefficient A
Cell Balance Enabled
Valid in Stand-Alone Only.
Register read responds
NAK otherwise.)
0011
000001
Scan Voltages
0011
000010
Scan Temperatures
0011
000011
Scan Mixed
0011
000100
Scan Wires
0011
000101
Scan All
0011
000110
Scan Continuous
FN7672 Rev.11.00
Jun.12.20
TV4
~
B1221
RCC7
RCB7
RCA2
CBEN8
B1220
RCC6
RCB6
RCA1
CBEN7
B1219
B1218
B1217
B1216
B1215
B1214
B1227
B1226
B1225
B1224
B1223
B1222
RCC5
RCC4
RCC3
RCC2
RCC1
RCC0
RCC13
RCC12
RCC11
RCC10
RCC9
RCC8
RCB5
RCB4
RCB3
RCB2
RCB1
RCB0
RCB13
RCB12
RCB11
RCB10
RCB9
RCB8
RCA0
N/A
RCA8
RCA7
RCA6
RCA5
RCA4
RCA3
CBEN6
CBEN5
CBEN4
CBEN3
BAL2
CBEN1
CBEN12 CBEN11 CBEN10
CBEN9
Page 134 of 139
ISL78600
13. Register Map
R/W + Page
Read
Write
Bit 7
Address
Register Name
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
0011
000111
Scan Inhibit
0011
001000
Measure
0011
001001
Identify
0011
001010
Sleep
0011
001011
NAK
0011
001100
ACK
0011
001110
Communications Failure
0011
001111
Wakeup
0011
010000
Balance Enable
0011
010001
Balance Inhibit
0011
010010
Reset
0011
010011
Calc Register Checksum
0011
010100
Check Register
Checksum
0100
111111
EEPROM MISR Data
Register
14-bit MISR EEPROM checksum value. Programmed during test.
0101
000000
MISR Calculated
Checksum
14-bit shadow register MISR checksum value. Calculated when shadow registers
are loaded from nonvolatile memory
FN7672 Rev.11.00
Jun.12.20
Page 135 of 139
ISL78600
14. Revision History
14. Revision History
Revision
Date
Change
11.00
Jun.12.20
Applied new formatting throughout.
Updated minimum and maximum ISL78600 Initial Cell Monitor Voltage Error specification values.
Updated Performance Characteristics and Typical Performance Curves sections.
Updated Communications Failure table Table 48 on page 103 and description.
Clarified use of the term reset to be Software Reset and Hardware reset and updated the response
to both actions.
Changed description of Identify, adding additional diagrams and text.
Changed default values for WSCN, TST0 and TST1 in Register table. Changed the description of
the WSCN bit.
Updated Table 15 on page 52 and associated text to match device operation.
Made minor changes to text in multiple locations to clarify device operation.
Removed the capacitor from VDDEXT to Ground in Figure 45 on page 34.
Moved 10k (R1) resistor in Figure 50 on page 39 and changed Table 12 on page 39 to match.
Updated Long Term Drift chart, Figure 37 on page 26.
Updated Figure 95 on page 92 to show more detail and changed text associated with figure.
Corrected t1A equation in Figure 91 on page 87 (missing parentheses).
Changed t2 equation in Figure 92 on page 88
Corrected definition of tCS in Figure 93 on page 89 and Figure 94 on page 90.
Correction to Figure 89 on page 85.
Corrected DIN/DOUT references on various figures to always refer to ISL78600 signals.
Updated timing values in Table 40 on page 96 through Table 45 on page 99.
Table 15 on page 52. Added Note 15 and corrected other note references in table.
Section , “Cell Setup,” on page 124: Added the following text to C1 to C12, “Note: Cell voltage
readings for disabled cells are not valid, so should be discarded.”
Added Daisy Chain Transmit Buffer section.
Added Note to Section 5.10, “Scan Inhibit Command,” on page 56.
10.00
Apr.12.18
Updated the Ordering Information table (removed Note 4).
Changed the following Abs Max values from 4.1V to 5.5V (BASE, DIN, SCLK, CS, DOUT, DATA
READY, COMMS SELECT n, TEMPREG, REF, V3P3, VCC, FAULT, COMMS RATE n, EN,
VDDEXT).
Updated Figure 41 and Figure 42 on page 31, Figure 43 and Figure 44 on page 32, Figure 51 on
page 41, Figure 55 on page 45, and Figure 56 on page 46 to reflect new recommended input filter
circuits.
Added Table 3 on page 31 and Table 4 on page 33 and updated Table 13 on page 48.
Added a paragraph in the Daisy Chain Circuits section page 37 that discusses board capacitance
effect on capacitor selection and changed Table 10 on page 38 and Table 11 on page 38 to match.
Re-arranged the specifications for VCELL to group like voltage ranges.
Re-arranged the specifications for VCELL/VBAT board level accuracy Table (page 20).
Added Board Level accuracy table for various cell chemistry voltages (page 21)
Updated Figure 45 and added Table 6 (No actual changes to content).
Updated Figure 48 and Table 10 (No actual changes to content).
Updated Figure 49 and Table 11 (No actual changes to content).
Updated Figure 50 and Table 12 (No actual changes to content).
Removed About Intersil section and updated the disclaimer.
9.00
May.23.17
Added Section “Daisy Chain Receive Buffer” on page 74.
Added Figure 75 on page 79 and text to clarify Buffer over-flow.
In Figures 70 to 72 and Figure 77, removed a 30us time reference between CS and first SPI clock.
8.00
Feb.10.17
Clarified that “Cells in Balance” register is available only during Stand-Alone operation (page 68,
page 130, and page 134).
Clarified that Scan Continuous functions during Manual, Timed, and Auto Balance modes (page 54
and page 68).
Clarified that the “BDDS” bit function in Timed and Auto Balance modes (page 68).
Clarified the calculation of internal and external temperature values (page 118).
Updated POD Q64.10x10D from rev 2 to rev 3. Changes:
Added land pattern back in (as in rev 1), but removed the exposed pad.
FN7672 Rev.11.00
Jun.12.20
Page 136 of 139
ISL78600
14. Revision History
Revision
Date
Change
7.00
Apr.12.16
Added AEC-Q100 to Features on page 1.
Updated Ordering Information table on page 7 by adding Tape and Reel option in note and
removing evaluation board FG until release.
Added Table 1 on page 7.
Added table “Performance Characteristics” on page 20.
Pages 17-22: Updated Performance Curves.
“Absolute Maximum Ratings” on page 10 Updated ESD Ratings testing information from JESD to
AEC-Q100 and changed CDM from 500V to 2kV.
Changed Thermal Information Tja from “49” to “42” and updated pb-free reflow profile to standard
Pages 7-13: Changed selected electrical specifications as follows:
Page 7: Changed Abs Max specs for the BASE pin changes from 4.1V to 5.5V.
Page 8: Changed IVBAT and IVBATSHDN Typical and Max Current specifications.
Page 8: Updated IVBATSHDN Minimum Current specifications.
Page 10: Deleted VBAT for 31.2V to 59.4V and changed Min and Max for two other voltage ranges.
Page 13: Deleted tDR:ST parameter (not valid in system timing.)
Page 13: Changed tDR:SP and tDR:WAIT to typical values (timing is dependent on system
variations.)
Removed Note 8 which read “Scan and Measurement start times...” from Electrical Spec Table due
to not being referenced.
Page 15: Removed tDR:ST from Figure 4.
Updated graphics (Figures 51 through 57) to Intersil standards.
Page 63: Changed the equation for calculating Pack voltage.
Changed the heading from "Communication Timing Tables" to “System Timing Tables” on page 91.
6.00
Jan.20.15
Changed ground references in Application Diagram on Page 1.
Figure 4B, page 16: Deleted the word “Maximum” from the caption.
Page 7 - Capacitive Discharge Model: Changed 750V to 500V. Removed Machine Model
specification.
“Recommended Operating Conditions” on page 11, changed Recommended Operating Conditions
for ExT1, ExT2, ExT3, ExT4 from 3.6V to 2.5V and removed outputs FAULT, BASE, DOUT, DATA
READY, TEMPREG and VREF.
Added to “BASE” Pin Description on page 8, “Do not let this pin float.”
Some changes to Electrical Specifications, pages 9-13.
On page 11, “V2P5 Power Good Window”, Changed V2PH Min from 2.55 to 2.62 and Max from 2.9
to 2.766V. For the -40°C to 105°C line, change V2PH Min from 2.55 to 2.616 and Max from 2.9 to
2.77.
Table 17 on page 57, Changed “Cell0 Voltage” to “VBAT Voltage”.
“CRC Calculation” on page 80: Added example software CRC calculation code.
Added note: “A Reset command should be issued following a “hard reset” in which the EN pin is
toggled.” to “Reset Command” on page 60.
“Fault Diagnostics” on page 107 changed to add the comment, “When a fault is detected, the
[TOT2:0] bits should be re-written.”
Table on page 109, Read checksum value calculated by ISL78600changed “cycling the EN pin or
the host issuing a Reset command.” to “cycling the EN pin followed by a host initiated Reset
command, or simply the host issuing a Reset command.”
Section, “Register Descriptions,” on page 113: Changed “VC0 Voltage” to “VBAT Voltage” and
added voltage calculation equations.
Changed Section, “System Hardware Connection,” on page 27. Changed “when the EN pin is low”
to “when the EN pin is toggled and the device receives a Reset Command”.
“Fault Setup” on page 122 description for TOT bits: Added the comment, “This register must be rewritten following an error detection resulting from Totalizer overflow.”
Added Note to Figure 72 indicating max CS to SCK timing on SPI Read
Added to Description in Section, “Power Supplies and Reference,” on page 31, “The external pass
transistor is required. Do not allow this pin to float.”
Moved Note 10: “Biasing setup as in Figure 45 on page 34 or equivalent” to Electrical Table
heading.
Changed all pin name references to all caps.
5.00
Feb.26.14
Changed Note on page 137 From: Initial accuracy does not include drift due to solder or heat
effect.
To: Stresses may be induced in the ISL78600 during soldering or other high temperature events
that affect measurement accuracy. Initial accuracy does not include effects due to this. See Figure
6 for cell reading accuracy obtained after soldering to Intersil evaluation boards. When soldering
the ISL78600 to a customized circuit board with a layout or construction significantly differing from
the Intersil evaluation board, design verification tests should be applied to determine drift due to
soldering and over life time.
FN7672 Rev.11.00
Jun.12.20
Page 137 of 139
ISL78600
14. Revision History
Revision
Date
4.00
Oct.25.13
Updated bullet in Features AEC - Q100 Qualified to Qualified for Automotive applications.
Updated in Disclaimer Intersil products to Intersil Automotive Qualified Products and ISO9000 to
TS16949.
Page 18 - removed “Note: Boards baked at +105°C for 12 hours to accelerate recovery from
soldering” from Figure 4B.
3.00
Sep.26.13
Open Wire Current ISCN bit = 0 on page 16 changed MAX from 0.175 to 0.185
Updated Electrical Spec Table by adding/modifying Note, TJA Spec, and VCELL, VRACC,
IVCELL, ICBSD Specs.
Added Typical Performance Curve: Maximum Cell Reading Error from 114 Evaluations Boards At
3.3V, +25°C. Histogram
Updated Definitions for Shutdown Mode in “Alarm Response” on page 106 and “Reset Command”
on page 60.
Page 35: Table 10, Updated recommendation for C1
Replaced “Measurement and Communication Timing” Section (pages 51 to 58 of previous
document) with new sections “Communication Timing” on page 84 and “System Timing Tables” on
page 91 with new figures and tables to offer more clarity and flexibility in communication and
measurement timing calculations.
2.00
Nov.30.12
Removed “BASE” from “Recommended Operating Conditions” on page 11.
Page 60, Updated Tables 42 and 43.
“Setup Registers” on page 124, changed “Enable/disable cell overvoltage and undervoltage
detection on cell 1 to 12, respectively. Set to 1 to disable OV/UV test” to “Enable/disable cell
overvoltage, undervoltage and open wire detection on cell 1 to 12, respectively. Set to 1 to disable
OV/UV and open wire tests”.
Page 32- page 38: Modified and simplified typical application circuits to reflect single RC filters for
cell inputs and Ext Temp inputs, as well as the BOM list.
Figure 47 on page 36: Modified connections for cell balancing pins with 10 cells
Page 80 - page 81: Removed information regarding “ISL78600 Supplied through an external
regulated 3.3V Supply”.
Page 81: Removed comments: regarding an optional zener diode.
Table 10 on page 38: modified C2 values
Figure 50 on page 39: Simplified and removed RC filters for Ext Temp inputs 1-4, as well as the
BOM list in Table 54.
1.00
Sep.27.12
Initial Release.
FN7672 Rev.11.00
Jun.12.20
Change
Page 138 of 139
ISL78600
15. Package Outline Drawing
15. Package Outline Drawing
For the most recent package outline drawing, see Q64.10x10D.
Q64.10x10D
64 LEAD THIN PLASTIC QUAD FLATPACK PACKAGE
Rev 3, 11/16
4 5
12.00
10.00
D 3
3
A
12.00
10.00 4 5
B
0.50
3
4X
0.20 C A-B D
TOP VIEW
11/13°
4X
0.20 H A-B D
BOTTOM VIEW
1.20 MAX
0.05
/ / 0.10 C
SIDE VIEW
0° MIN.
0.08
C
SEE DETAIL "A"
2
H
1.00 ±0.05
7
0.08 M C A-B D
WITH LEAD FINISH
0.22 ±0.05
0.05/0.15
0.08
R. MIN.
0.20 MIN.
0.09/0.20
0.60 ±0.15
0.09/0.16
0.20 ±0.03
0-7° 0.25 GAUGE
PLANE
DETAIL "A"
SCALE: NONE
BASE METAL
(1.00)
NOTES:
(10.00)
(0.28) TYP
1. All dimensioning and tolerancing conform to ANSI Y14.5-1982.
2. Datum plane H located at mold parting line and coincident
with lead, where lead exits plastic body at bottom of parting line.
3. Datums A-B and D to be determined at centerline between
leads where leads exit plastic body at datum plane H.
4. Dimensions do not include mold protrusion. Allowable mold
protrusion is 0.254mm.
10.00
5. These dimensions to be determined at datum plane H.
6. Package top dimensions are smaller than bottom dimensions
and top of package does not overhang bottom of package.
(1.50) TYP
7. Does not include dambar protrusion. Allowable dambar
protrusion shall be 0.08mm total at maximum material
condition. Dambar cannot be located on the lower radius
or the foot.
8. Controlling dimension: millimeter.
9. This outline conforms to JEDEC publication 95 registration
MS-026, variation ACD.
10. Dimensions in ( ) are for reference only.
TYPICAL RECOMMENDED LAND PATTERN
FN7672 Rev.11.00
Jun.12.20
Page 139 of 139
Notice
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