DATASHEET
ISL80101A
FN7712
Rev 6.00
Aug 21, 2020
High Performance 1A Linear Regulator with Programmable Current Limiting
The ISL80101A is a low dropout voltage, single output LDO
with programmable current limiting. This LDO operates from
input voltages of 2.2V to 6V, and is capable of providing output
voltages of 0.8V to 5V. Other custom voltage options are
available upon request.
A submicron BiCMOS process is utilized for this product family
to deliver the best-in-class analog performance and overall
value. The programmable current limiting improves system
reliability of end applications. An external capacitor on the
soft-start pin provides an adjustable soft-starting ramp. The
ENABLE feature allows the part to be placed into a low
quiescent current shutdown mode.
This CMOS LDO will consume significantly lower quiescent
current as a function of load compared to bipolar LDOs, which
translates into higher efficiency and packages with smaller
footprints. Quiescent current is modestly compromised to
achieve a very fast load transient response.
Table 1 shows the differences between the ISL80101A and
others in its family:
PROGRAMMABLE
ILIMIT
ILIMIT
(DEFAULT)
ADJ OR FIXED
VOUT
ISL80101-ADJ
No
1.75A
ADJ
ISL80101A
Yes
1.62A
ADJ
ISL80121-5
Yes
0.75A
5.0V
10µF
CIN
10
9
RSET
8
10k
R1
VIN
VOUT
VIN
VOUT
ADJ
ISET
10µF
COUT
7
6
0.01µF
CSS
ENABLE
PG
100k
0.464k
R2
ISL80101A
4
• 100µVRMS output noise
• Power-good output
• Programmable soft-start
• Over-temperature protection
• Small 10 Ld DFN package
Applications
• Telecommunications and networking
• Medical equipment
• Instrumentation systems
• Gaming
• Routers and switchers
• ISL80101A device page
2
3
• Very fast transient response
For a full list of related documents, visit our website:
3.3V
2.61k
R3
• High accuracy current limit programmable up to 1.75A
Related Literature
1
100pF
CPB
• Very low 212mV dropout voltage at VIN = 4.5V
1.5
CURRENT LIMIT (A)
5.0V ± 5%
• ±2% VADJ accuracy guaranteed over line, load and
TJ = -40°C to +125°C
• USB devices
TABLE 1. KEY DIFFERENCES BETWEEN FAMILY OF PARTS
PART NUMBER
Features
VIN = 4.5V
1.2
0.9
VIN = 5.5V
0.6
VIN = 5.0V
0.3
SS
GND
5
0.0
10
2.9x2xV – 1
IN
I LIMIT ~ 1.62 – --------------------------------------R SET k
100
RSET (kΩ)
1000
FIGURE 1. TYPICAL APPLICATION
FN7712 Rev 6.00
Aug 21, 2020
Page 1 of 13
ISL80101A
Block Diagram
SS
THERMAL
SHUTDOWN
VIN
+
CURRENT
LIMITER
VOUT
ISET
PG
VOLTAGE
REFERENCE
POWERGOOD
ADJ
ENABLE
GND
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
VOUT
VOLTAGE
TEMP. RANGE
(°C)
Tape and Reel
(Units) (Note 1)
PACKAGE
(RoHS COMPLIANT)
PKG
DWG. #
ISL80101AIRAJZ
DZAC
ADJ
-40 to +125
-
10 Ld 3x3 DFN
L10.3x3
ISL80101AIRAJZ-T
DZAC
ADJ
-40 to +125
6k
10 Ld 3x3 DFN
L10.3x3
ISL80101AEVAL2Z
Evaluation Board
NOTES:
1. See TB347 for details about reel specifications.
2. These Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate
plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), see ISL80101A device page. For more information on MSL see TB363.
FN7712 Rev 6.00
Aug 21, 2020
Page 2 of 13
ISL80101A
Pin Configuration
ISL80101A
(10 LD 3x3 DFN)
TOP VIEW
VOUT 1
10 VIN
VOUT 2
9 VIN
ADJ 3
EPAD
PG 4
GND 5
8 ISET
7 ENABLE
6 SS
Pin Descriptions
PIN NUMBER
PIN NAME
DESCRIPTION
1, 2
VOUT
Output voltage. A minimum 10µF X5R/X7R output capacitor (for VOUT from 1.5V to 5V) is required for stability. See
“External Capacitor Requirements” on page 8 for more details.
3
ADJ
LDO output feedback input. To adjust the output voltage, connect this pin to a resistive voltage divider from VOUT
to GND.
4
PG
VOUT in regulation signal. Logic low indicates VOUT is not in regulation, and must be grounded if not used.
5
GND
6
SS
7
ENABLE
8
ISET
Current limit setting. Current limit is 1.62A when this pin is left floating. This default value can be increased by tying
RSET to GND, or decreased by tying RSET to VIN. See “Programmable Current Limit” on page 8 for more details.
9, 10
VIN
Input supply. A minimum of 10µF X5R/X7R input capacitor is required for stability. See “External Capacitor
Requirements” on page 8 for more details.
-
EPAD
FN7712 Rev 6.00
Aug 21, 2020
Ground
External capacitor adjusts inrush current.
VIN-independent chip enable. TTL and CMOS compatible.
EPAD at ground potential. Soldering it directly to GND plane is required for thermal considerations. See “Power
Dissipation and Thermals” on page 9 for more details.
Page 3 of 13
ISL80101A
Absolute Maximum Ratings
Thermal Information
(Note 6)
VIN Relative to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V
VOUT Relative to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V
PG, ENABLE, ADJ, SS, ISET
Relative to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V
ESD Rating
Human Body Model (Tested per JEDEC) . . . . . . . . . . . . . . . . . . . . . .2.5kV
Machine Model (Tested per JEDEC) . . . . . . . . . . . . . . . . . . . . . . . . . . 250V
Latch-Up (Tested per JEDEC) . . . . . . . . . . . . . . . . . . . . . ±100mA at +125°C
Thermal Resistance (Typical)
JA (°C/W) JC (°C/W)
10 Ld 3x3 DFN Package (Notes 4, 5) . . . .
48
7
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . .+150°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
Recommended Operating Conditions
Junction Temperature Range (TJ) . . . . . . . . . . . . . . . . . . .-40°C to +125°C
VIN Relative to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.2V to 6V
VOUT Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 800mV to 5V
PG, ENABLE, ADJ, SS, ISET Relative to GND . . . . . . . . . . . . . . . . . . 0V to 6V
PG Sink Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions can adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. JA is measured in free air with the component mounted on a high-effective thermal conductivity test board with “direct attach” features. See TB379.
5. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
6. Absolute maximum voltage rating is defined as the voltage applied for a lifetime average duty cycle above 6V of 1%.
Electrical Specifications
Unless otherwise noted, all parameters are established over the following specified conditions:
2.2V < VIN < 6V, VOUT = 0.5V, TJ = +25°C, ILOAD = 0A. Applications must follow thermal guidelines of the package to determine worst case junction
temperature. See “Functional Description” on page 8 and TB379. Boldface limits apply across the operating temperature range, -40°C to +125°C. Pulse
load techniques used by ATE to ensure TJ = TA defines established limits.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 7)
TYP
MAX
(Note 7)
UNIT
DC CHARACTERISTICS
DC ADJ Pin Voltage Accuracy
VADJ
VOUT + 0.4V < VIN < 6V, VOUT = 2.5V;
0A < ILOAD < 1A
490
500
510
mV
DC Input Line Regulation
(VOUT low line VOUT high line)/
VOUT low line
VOUT + 0.4V < VIN < 6V, VOUT = 2.5V
-1
0.2
1
%
DC Output Load Regulation
(VOUT no load - VOUT + 0.4V < VIN < 6V, VOUT = 2.5V;
VOUT high load)/ 0A < ILOAD < 1A
VOUT no load
-1
1
%
0.01
1
µA
ILOAD = 0A, VOUT + 0.4V < VIN < 6V, VOUT = 2.5V
3
5
mA
ILOAD = 1A, VOUT + 0.4V < VIN < 6V, VOUT = 2.5V
5
7
mA
ENABLE = 0.2V, VIN = 6V
0.2
12
µA
ILOAD = 1A, VIN = 4.5V, VADJ = 0V
90
212
mV
VADJ = 0.5V
Feedback Input Current
Ground Pin Current
Ground Pin Current in Shutdown
Dropout Voltage (Note 8)
Output Current Limit
IQ
ISHDN
VDO
ILIMIT
4.5V < VIN < 6V, ISET is floating
VIN = 5V, RSET = 25.5kΩ
1.62
0.540
0.640
A
0.740
A
Thermal Shutdown Temperature
TSD
160
°C
Thermal Shutdown Hysteresis
TSDn
30
°C
FN7712 Rev 6.00
Aug 21, 2020
Page 4 of 13
ISL80101A
Electrical Specifications
Unless otherwise noted, all parameters are established over the following specified conditions:
2.2V < VIN < 6V, VOUT = 0.5V, TJ = +25°C, ILOAD = 0A. Applications must follow thermal guidelines of the package to determine worst case junction
temperature. See “Functional Description” on page 8 and TB379. Boldface limits apply across the operating temperature range, -40°C to +125°C. Pulse
load techniques used by ATE to ensure TJ = TA defines established limits. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 7)
MAX
(Note 7)
TYP
UNIT
AC CHARACTERISTICS
Input Supply Ripple Rejection
PSRR
Output Noise Voltage
f = 1kHz, ILOAD = 1A, VIN = 5.0V, VOUT = 3.3V
48
dB
f = 120Hz, ILOAD = 1A, VIN = 5.0V, VOUT = 3.3V
48
dB
ILOAD = 10mA, BW = 300Hz < f < 300kHz, VIN = 3.7,
VOUT = 3.3V
100
µVRMS
VIN = 2.2V, VOUT = 1.8V, ILOAD = 1A, BW = 100Hz <
f < 100kHz
53
µVRMS
ENABLE PIN CHARACTERISTICS
Turn-On Threshold
VEN(HIGH)
0.5
0.8
1.0
V
Hysteresis
VEN(HYS)
10
80
200
mV
ENABLE Pin Turn-On Delay
tEN
ENABLE Pin Leakage Current
COUT = 10µF, ILOAD = 1A
80
µs
VIN = 6V, ENABLE = 3V
1
µA
SOFT-START CHARACTERISTICS
Reset Pull-Down Current
IPD
Soft-Start Charge Current
ICHG
VIN = 3.5V, EN = 0V, SS = 1V
0.5
1
1.3
mA
-3.3
-2
-0.8
µA
75
84
92
% VOUT
PG PIN CHARACTERISTICS
VOUT PG Flag Threshold
VOUT PG Flag Hysteresis
4
PG Flag Low Voltage
ISINK = 500µA
PG Flag Leakage Current
VIN = 6V, PG = 6V
%
47
100
mV
0.05
1
µA
NOTES:
7. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
8. Dropout is defined by the difference in supply VIN and VOUT when the output is below its nominal regulation.
FN7712 Rev 6.00
Aug 21, 2020
Page 5 of 13
ISL80101A
Typical Operating Performance
Unless otherwise noted: VIN = 5V, VOUT = 3.3V, CIN = COUT = 10µF,
TJ = +25°C, IL = 0A.
150
0.505
+125°C
120
0.504
0.503
+25°C
DROPOUT (mV)
0.502
VADJ (V)
90
60
0.501
0.500
0.499
0.498
0.497
30
0.496
-40°C
0
0
0.2
0.4
0.6
0.8
0.495
-40
1.0
-20
0
20
60
80
100
120
FIGURE 3. VADJ vs TEMPERATURE
FIGURE 2. DROPOUT vs LOAD
1.8
4.0
3.6
+25°C
1.2
3.2
2.8
0.6
2.4
VOUT (%)
OUTPUT VOLTAGE (V)
40
TEMPERATURE (°C)
LOAD CURRENT (A)
-40°C
2.0
1.6
+125°C
+25°C
0
-0.6
1.2
0.8
-40°C
+125°C
-1.2
0.4
0
0
2
1
3
4
5
6
-1.8
0
0.25
SUPPLY VOLTAGE (V)
FIGURE 4. OUTPUT VOLTAGE vs SUPPLY VOLTAGE
0.50
0.75
OUTPUT CURRENT (A)
1.00
FIGURE 5. OUTPUT VOLTAGE vs OUTPUT CURRENT
3.5
5
GROUND CURRENT (mA)
GROUND CURRENT (mA)
3.0
2.5
2.0
1.5
+25°C
+125°C
-40°C
1.0
0.5
0
0
0.2
0.4
0.6
0.8
LOAD CURRENT (A)
FIGURE 6. GROUND CURRENT vs LOAD CURRENT
FN7712 Rev 6.00
Aug 21, 2020
1.0
4
3
2
1
0
2
3
4
5
6
INPUT VOLTAGE (V)
FIGURE 7. GROUND CURRENT vs SUPPLY VOLTAGE
Page 6 of 13
ISL80101A
Typical Operating Performance
Unless otherwise noted: VIN = 5V, VOUT = 3.3V, CIN = COUT = 10µF,
TJ = +25°C, IL = 0A. (Continued)
1.8
1.6
1.4
CURRENT LIMIT (A)
ENABLE (5V/DIV)
SS (1V/DIV)
VOUT (2V/DIV)
1.2
1.0
RSET = OPEN
0.8
0.6
0.4
0.2
PG (2V/DIV)
RSET = 25.5kΩ
0
-40
10
TIME (5ms/DIV)
FIGURE 8. ENABLE START-UP
60
TEMPERATURE (°C)
110
FIGURE 9. CURRENT LIMIT vs TEMPERATURE
90
80
100mA
70
0mA
VOUT AT 50mV/DIV
PSRR (dB)
60
50
40
30
20
IOUT = 1A
10
IOUT = 10mA
1000mA
0
100
1k
TIME (20µs/DIV)
500mA
10k
FREQUENCY (Hz)
100k
1M
FIGURE 11. PSRR vs FREQUENCY
FIGURE 10. LOAD TRANSIENT RESPONSE
NOISE (µV/√Hz)
10
1
0.1
VIN = 2.2V
VOUT = 1.8V
COUT = 10µF
IOUT = 1A
0.01
10
100
1k
FREQUENCY (Hz)
10k
100k
FIGURE 12. OUTPUT NOISE SPECTRAL DENSITY
FN7712 Rev 6.00
Aug 21, 2020
Page 7 of 13
ISL80101A
Functional Description
Input Voltage Requirements
ISL80101A is capable of delivering output voltages from 0.8V to
5.0V. Due to the nature of an LDO, VIN must be some margin
higher than VOUT plus dropout at the maximum rated current of
the application if active filtering (PSRR) is expected from VIN to
VOUT. The generous dropout specification of this family of LDOs
allows applications to design for a level of efficiency that can
accommodate profiles smaller than the TO220/263.
Programmable Current Limit
The ISL80101A protects against overcurrent due to short-circuit
and overload conditions applied to the output. When this
happens, the LDO performs as a constant current source. If the
short circuit or overload condition is removed, the output returns
to normal voltage regulation operation.
The current limit is set at 1.62A by default when the ISET pin is
left floating.
This limit can be increased by tying a resistor RSET from the ISET
pin to ground. The current limit is determined by RSET as shown
in Equation 1. Do not short this pin to ground. Increasing the
current limit past 1.75A may cause damage to the part and is
highly discouraged.
2.9
I LIMIT 1.62 + ---------------------------R SET k
(EQ. 1)
The current limit can be decreased from the 1.62A default by
tying RSET from the ISET pin to VIN. The current limit is then
determined by both RSET and VIN following Equation 2.
2.9 2 V IN – 1
I LIMIT 1.62 – -----------------------------------------R SET k
(EQ. 2)
Figure 13 shows the relationship between RSET and the current
limit when RSET is tied from the ISET pin to VIN for various VIN
values.
CURRENT LIMIT (A)
1.5
1.2
VIN = 5.5V
0.6
VIN = 5.0V
0.3
0.0
10
100
RSET (kΩ)
Power-Good Operation
PG is a logic output that indicates the status of VOUT, current limit
tripping, and VIN. The PG flag is an open-drain NMOS that can
sink up to 10mA during a fault condition. The PG pin requires an
external pull-up resistor typically connected to the VOUT pin. The
PG pin should not be pulled up to a voltage source greater than
VIN. PG goes low when the output voltage drops below 84% of
the nominal output voltage, the current limit faults, or the input
voltage is too low. PG functions during shutdown, but not during
thermal shutdown. For applications not using this feature,
connect this pin to ground.
Soft-Start Operation
The soft-start circuit controls the rate at which the output voltage
rises up to regulation at power-up or LDO enable. This start-up
ramp time can be set by adding an external capacitor from the
SS pin to ground. An internal 2µA current source charges up this
CSS and the feedback reference voltage is clamped to the
voltage across it. The start-up time is set by Equation 3.
C SS x0.5
T start = ---------------------------2A
(EQ. 3)
Equation 4 determines the CSS required for a specific start-up inrush
current, where VOUT is the output voltage, COUT is the total
capacitance on the output and IINRUSH is the desired inrush current.
V OUT xC OUT x2A
C SS = -------------------------------------------------------I INRUSH x0.5V
(EQ. 4)
The external capacitor is always discharged to ground at the
beginning of start-up or enabling.
Output Voltage Selection
An external resistor divider is used to scale the output voltage
relative to the internal reference voltage. This voltage is then fed
back to the error amplifier. The output voltage can be
programmed to any level between 0.8V and 5V. An external
resistor divider, R2 and R3, is used to set the output voltage as
shown in Equations 5 and 6. See Table 2 for recommended
values of R2 and R3.
VIN = 4.5V
0.9
not be left floating, and should be tied to VIN if not used. A 1kΩ to
10kΩ pull-up resistor is required for applications that use open
collector or open-drain outputs to control the ENABLE pin. The
ENABLE pin may be connected directly to VIN for applications
with outputs that are always on.
R
V OUT = 0.5V ------3- + 1
R2
(EQ. 5)
V OUT
R 3 = R 2 --------------- – 1
0.5V
(EQ. 6)
1000
FIGURE 13. CURRENT LIMIT vs RSET AT DIFFERENT VIN
Enable Operation
External Capacitor Requirements
External capacitors are required for proper operation. Careful
attention must be paid to the layout guidelines and selection of
capacitor type and value to ensure optimal performance.
The ENABLE turn-on threshold is typically 800mV with 80mV of
hysteresis. An internal pull-up or pull-down resistor to change
these values is available upon request. As a result, this pin must
FN7712 Rev 6.00
Aug 21, 2020
Page 8 of 13
ISL80101A
OUTPUT CAPACITOR
INPUT CAPACITOR
The ISL80101A applies state-of-the-art internal compensation to
keep the selection of the output capacitor simple for the
customer. Stable operation over full temperature, VIN range,
VOUT range and load extremes are guaranteed for all capacitor
types and values assuming a minimum of 10µF X5R/X7R is used
for local bypass on VOUT. This output capacitor must be
connected to the VOUT and GND pins of the LDO with PCB traces
no longer than 0.5cm.
For proper operation, a minimum capacitance of 10µF X5R/X7R
is required at the input. This ceramic input capacitor must be
connected to the VIN and GND pins of the LDO with PCB traces no
longer than 0.5cm.
There is a growing trend to use very-low ESR multilayer ceramic
capacitors (MLCC) because they can support fast load transients
and also bypass very high frequency noise from other sources.
However, the effective capacitance of MLCCs drops with applied
voltage, age and temperature. X7R and X5R dielectric ceramic
capacitors are strongly recommended as they typically maintain
a capacitance range within ±20% of nominal voltage over full
operating ratings of temperature and voltage.
Additional capacitors of any value in ceramic, POSCAP,
alum/tantalum electrolytic types may be placed in parallel to
improve PSRR at higher frequencies and/or load transient AC
output voltage tolerances.
Phase Boost Capacitor
A small phase boost capacitor, CPB, can be placed across the top
resistor, R3, in the feedback resistor divider network in order to
place a zero at:
1
F z = ---------------------------------2xR 3 xC PB
(EQ. 7)
Power Dissipation and Thermals
The junction temperature must not exceed the range specified in
the “Recommended Operating Conditions” on page 4. The power
dissipation can be calculated by using Equation 8:
P D = V IN – V OUT I OUT + V IN I GND
The maximum allowable junction temperature, TJ(MAX) and the
maximum expected ambient temperature, TA(MAX) determine
the maximum allowable power dissipation, as shown in
Equation 9:
P D MAX = T J MAX – T A JA
Table 2 shows the recommended CPB, R3 and R2 for different
output voltage and ceramic COUT.
TABLE 2. RECOMMENDED CPB FOR DIFFERENT VOUT AND COUT
VOUT
(V)
R3
(kΩ)
R2
(kΩ)
COUT
(µF)
CPB
(pF)
5.0
2.61
0.287
10
100
3.3
2.61
0.464
10
100
2.5
2.61
0.649
10
82
1.8
2.61
1.0
10
82
1.5
2.61
1.3
10
68
1.5
2.61
1.3
22
150
1.2
2.61
1.87
22
120
1.2
2.61
1.87
47
270
1.0
2.61
2.61
47
220
0.8
2.61
4.32
47
220
FN7712 Rev 6.00
Aug 21, 2020
(EQ. 9)
JA is the junction-to-ambient thermal resistance.
For safe operation, ensure that the power dissipation PD,
calculated from Equation 8, is less than the maximum allowable
power dissipation PD(MAX).
The DFN package uses the copper area on the PCB as a heatsink. The EPAD of this package must be soldered to the copper
plane (GND plane). Figure 14 shows a curve for the JA of the
DFN package for different copper area sizes.
46
This zero increases the crossover frequency of the LDO and
provides additional phase resulting in faster load transient
response.
44
JA (°C/W)
It is also important to note that the LDO stability and load
transient are affected by the type of output capacitor used. For
optimal result, empirical tuning is suggested for each specific
application.
(EQ. 8)
42
40
38
36
34
2
4
6
8
10
12
14
16
18
20
22
24
EPAD-MOUNT COPPER LAND AREA ON PCB, mm2
FIGURE 14. 3mmx3mm 10 LD DFN ON 4-LAYER PCB WITH THERMAL
VIAS JA vs EPAD-MOUNT COPPER LAND AREA ON PCB
Thermal Fault Protection
The power level and the thermal impedance of the package
(+48°C/W for DFN) determine when the junction temperature
exceeds the thermal shutdown temperature. In the event that the
die temperature exceeds around +160°C, the output of the LDO
will shut down until the die temperature cools down to about
+130°C.
Page 9 of 13
ISL80101A
General PowerPAD Design Considerations
Figure 15 shows the recommended use of vias on the thermal
pad to remove heat from the IC. This typical array populates the
thermal pad footprint with vias spaced three times the radius
distance from the center of each via. Small via size is advisable,
but not to the extent that solder reflow becomes difficult.
All vias should be connected to the pad potential, with low
thermal resistance for efficient heat transfer. Complete
connection of the plated-through hole to each plane is important.
It is not recommended to use “thermal relief” patterns to connect
the vias.
FN7712 Rev 6.00
Aug 21, 2020
FIGURE 15. PCB VIA PATTERN
Page 10 of 13
ISL80101A
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted.
Please go to web to make sure you have the latest revision.
DATE
August 21, 2020
REVISION
CHANGE
FN7712.6 Page 1, Updated Table 1 - removed ISL80101.
Added Related Literature
Page 2, Ordering Information table - added ISL80101AIRAJZ-T and updated Note 1
Removed About Intersil section
Updated Disclaimer
November 17, 2016 FN7712.5 On page 4, Removed Note 7 “Electromigration specification defined as lifetime average junction temperature of
+110°C where max rated DC current = lifetime average current.”
August 11, 2015
FN7712.4 Figure 1 on page 1 - updated equation.
Removed Sense Voltage Version from “Block Diagram” on page 2
Changed PAD to EPAD in Pin Configuration on page 3
“Pin Descriptions” on page 3 - VOUT pin - added after the word capacitor: “(for VOUT from 1.5V to 5V)”.
Changed “SENSE” to “ADJ” under “Absolute Maximum Ratings” and “Recommended Operating Conditions” on page 4
Changed in “Absolute Maximum Ratings” on page 4 - Latch-up temp from: +85°C to +125°C
Electrical Spec Table changes beginning on page 4:
Electrical Spec table conditions changed from: VIN = VOUT + 0.4V, VOUT = 3.3V, CIN = COUT = 10µF, TJ = +25°C,
ILOAD = 0A, to: 2.2V < VIN < 6V, VOUT = 0.5V, TJ = +25°C, ILOAD = 0A
DC ADJ Pin Voltage Accuracy - changed test conditions from: VOUT + 0.4V < VIN < 6V; 0A < ILOAD < 1A
to: VOUT + 0.4V < VIN < 6V, VOUT = 2.5V; 0A < ILOAD < 1A
DC Input Line Regulation - changed test conditions from: VOUT + 0.4V < VIN < 6.0V, VOUT = 5.0V to: VOUT + 0.4V < VIN
< 6V, VOUT = 2.5V. Added “-1” MIN
DC Output Load Regulation – Test Conditions added: VOUT + 0.4V < VIN < 6V, VOUT = 2.5V Added “1” MAX
Ground Pin Current – changed Test Conditions from: ILOAD = 0A, 2.2V < VIN
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