ISL80112EVAL1Z

DATASHEET ISL80111, ISL80112, ISL80113 FN7841 Rev.4.01 Jun 12, 2020 Ultra Low Dropout 1A, 2A, 3A Low Input Voltage NMOS LDOs The ISL80111, ISL80112, and ISL80113 are ultra low dropout LDOs providing the optimum balance between performance, size and power consumption in size constrained designs for data communication, computing, storage and medical applications. These LDOs are specified for 1A, 2A, and 3A of output current and are optimized for low voltage conversions. Operating with a VIN of 0.7V to 3.6V and with a legacy 2.9V to 5.5V on the BIAS, the VOUT is adjustable from 0.5V to 3.3V. With a VIN PSRR greater than 40dB at 100kHz makes these LDOs an ideal choice in noise sensitive applications. The guaranteed ±1.6% VOUT accuracy overall conditions lend these parts to supplying an accurate voltage to the latest low voltage digital ICs. An enable input allows the part to be placed into a low quiescent current shutdown mode. A submicron CMOS process is utilized for this product family to deliver best-in-class analog performance and overall value for applications in need of input voltage conversions typically below 2.5V. It also has the superior load transient regulation unique to a NMOS power stage. These LDOs consume significantly lower quiescent current as a function of load compared to bipolar LDOs. Features • Ultra low dropout: 75mV at 3A, (typical) • Excellent VIN PSRR: 70dB at 1kHz (typical) • ±1.6% assured VOUT accuracy for -40ºC < TJ < +125ºC • Very fast load transient response • Extensive protection and reporting features • VIN range: 0.7V to 3.6V, VOUT range: 0.5V to 3.3V • Small 10 Ld 3x3 DFN package Applications • Noise-sensitive instrumentation and medical systems • Data acquisition and data communication systems • Storage, telecommunications and server equipment • Low voltage DSP, FPGA and ASIC core power supplies • Post-regulation of switched mode power supplies Related Literature For a full list of related documents, visit our website: ISL80111, ISL80112, ISL80113 1.2V ±5% VIN VOUT 1 VOUT 2 9 CIN 10µF 3.3V ±10% VBIAS CBIAS 1µF VIN 10 VIN 4 VBIAS PG 7 ENABLE GND 5 OPEN-DRAIN COMPATIBLE EN 1.0V VOUT COUT 10µF 6 PGOOD R3 1.0kΩ ADJ 3 R4 1.0kΩ DROPOUT VOLTAGE, BIAS = 5V (mV) • ISL80111, ISL80112, and ISL80113 device pages 100 IOUT = 1A 60 IOUT = 0A IOUT = 2A 40 BIAS = 5V VIN = 3.3V VOUT = 2.5V COUT = 10µF 100 1k IOUT = 3A 10k FREQUENCY (Hz) 100k FIGURE 3. VIN PSRR vs LOAD CURRENT (ISL80113) FN7841 Rev.4.01 Jun 12, 2020 1M VADJ +25°C NORMALIZED PSRR (dB) 3A 80 70 2A 60 50 40 1A 30 20 10 0 -40 25 85 TEMPERATURE (°C) 125 1.015 80 0 90 FIGURE 2. DROPOUT VOLTAGE OVER-TEMP AND IOUT FIGURE 1. TYPICAL APPLICATION SCHEMATIC 20 100 1.010 1.005 1.000 0.995 0.990 0.985 -40 0 25 85 TEMPERATURE (°C) 125 FIGURE 4. VADJ vs TEMPERATURE Page 1 of 16 ISL80111, ISL80112, ISL80113 Block Diagram VIN VBIAS CURRENT LIMIT BIAS UVLO VIN UVLO VIN M3 DRIVER EN R7 IL IL/10,000 VOUT THERMAL SHUTDOWN EN EN ADJ - EN + ENABLE M1 POWER NMOS PG M7 500mV - + - M2 + 425mV + GND FIGURE 5. BLOCK DIAGRAM Pin Configuration ISL80111, ISL80112, ISL80113 (10 LD 3X3 DFN) TOP VIEW VOUT 1 10 VIN VOUT 2 9 VIN ADJ 3 VBIAS 4 GND 5 FN7841 Rev.4.01 Jun 12, 2020 EPAD (GND) 8 NC 7 ENABLE 6 PG PIN NUMBER PIN NAME 1, 2 VOUT 3 ADJ 4 VBIAS 5 GND 6 PG VOUT in regulation signal. Logic low defines when VOUT is not in regulation. Range 0V to BIAS 7 ENABLE VIN independent chip enable. TTL and CMOS compatible. Range 0V to VBIAS. VEN must always be less than or equal to the voltage applied to VBIAS. When this pin is not used, it must be tied to VBIAS. 8 NC No Connect 9, 10 VIN Input supply pins. Range 0.7V to 3.6V - EPAD DESCRIPTION Output voltage pin. Range 0.5V to 3.3V ADJ pin for externally setting VOUT. Bias voltage pin for internal control circuits. Range 2.9V to 5.5V Ground pin EPAD at ground potential. It is recommended to solder the EPAD to the ground plane. Page 2 of 16 ISL80111, ISL80112, ISL80113 Ordering Information PART NUMBER (Notes 2, 3) PART MARKING VOUT (V) TEMP RANGE (°C) TAPE AND REEL (Units) (Note 1) PACKAGE (RoHS COMPLIANT) PKG DWG. # ISL80111IRAJZ 1ADJ ADJ -40 to +125 - 10 Ld 3x3 DFN L10.3x3 ISL80111IRAJZ-T 1ADJ ADJ -40 to +125 6k 10 Ld 3x3 DFN L10.3x3 ISL80111IRAJZ-T7A 1ADJ ADJ -40 to +125 250 10 Ld 3x3 DFN L10.3x3 ISL80112IRAJZ 2ADJ ADJ -40 to +125 - 10 Ld 3x3 DFN L10.3x3 ISL80112IRAJZ-T 2ADJ ADJ -40 to +125 6k 10 Ld 3x3 DFN L10.3x3 ISL80112IRAJZ-T7A 2ADJ ADJ -40 to +125 250 10 Ld 3x3 DFN L10.3x3 ISL80113IRAJZ 3ADJ ADJ -40 to +125 - 10 Ld 3x3 DFN L10.3x3 ISL80113IRAJZ-T 3ADJ ADJ -40 to +125 6k 10 Ld 3x3 DFN L10.3x3 ISL80113IRAJZ-T7A 3ADJ ADJ -40 to +125 250 10 Ld 3x3 DFN L10.3x3 ISL80111EVAL1Z ISL80111 Evaluation Board ISL80112EVAL1Z ISL80112 Evaluation Board ISL80113EVAL1Z ISL80113 Evaluation Board NOTES: 1. See TB347 for details about reel specifications. 2. These Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J-STD-020. 3. For Moisture Sensitivity Level (MSL), see the ISL80111, ISL80112, and ISL80113 device pages for. For more information about MSL, see TB363. TABLE 1. KEY DIFFERENCE BETWEEN FAMILY OF PARTS PART NUMBER IOUT MAXIMUM ISL80111 1A ISL80112 2A ISL80113 3A FN7841 Rev.4.01 Jun 12, 2020 Page 3 of 16 ISL80111, ISL80112, ISL80113 Absolute Maximum Ratings Thermal Information (Note 4) VIN Relative to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +6V VOUT Relative to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +4V PG, ENABLE, ADJ, Relative to GND (Note 5) . . . . . . . . . . . . . . . . -0.3 to +6V VBIAS Relative to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6V PG Rated Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA ESD Rating Human Body Model (Tested per JESD22-A114E). . . . . . . . . . . . . . 4000V Machine Model (Tested per JESD22-115-A) . . . . . . . . . . . . . . . . . . . 300V Charged Device Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2000V Latch-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mA Thermal Resistance (Typical) JA (°C/W) JC (°C/W) 10 Ld 3x3 DFN Package (Notes 6, 7) . . . . 48 4 θJB at Pin 3 (Note 8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.7°C/W θJB at Pin 5 (Note 8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8.9°C/W Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493 Recommended Operating Conditions (Notes 4) Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C VIN Relative to GND (ISL80113). . . . . . . . . . . . . . . . . VOUT + 0.30V to 3.6V VIN Relative to GND (ISL80112). . . . . . . . . . . . . . . . . VOUT + 0.25V to 3.6V VIN Relative to GND (ISL80111). . . . . . . . . . . . . . . . . VOUT + 0.20V to 3.6V Nominal VOUT Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500mV to 3.3V PG, ENABLE, ADJ, SS Relative to GND . . . . . . . . . . . . . . . . . . . . .0V to 5.5V VBIAS Relative to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0V to 5.5V CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions can adversely impact product reliability and result in failures not covered by warranty. NOTES: 4. Absolute maximum ratings define limits of safe operation. Extended operation at these conditions may compromise reliability. Exceeding these limits will result in damage. Recommended operating conditions define limits where specifications are guaranteed. 5. Absolute maximum voltage rating is defined as the voltage applied for a lifetime average duty cycle above 6V of 1%. 6. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with direct attach features. See TB379. 7. For JC, the case temperature location is the center of the exposed metal pad on the package underside. 8. For θJB, the board temperature is taken on the board near the edge of the package, on a copper trace at either lead #3 or lead #5, as applicable. See TB379. Electrical Specifications Unless otherwise specified, VIN = 3V, VBIAS = 5.5V, VOUT = 0.5V, TJ = +25°C, IL = 0mA. Applications must follow thermal guidelines of the package to determine worst-case junction temperature. See the “Power Dissipation” on page 13 and TB379. Boldface limits apply across junction temperature (TJ) range, -40°C to +125°C. Pulse load techniques used by ATE to ensure TJ = TA where datasheet limits are defined. PARAMETER SYMBOL TEST CONDITIONS MIN (Note 9) TYP MAX (Note 9) UNIT 2.3 2.9 V 1.55 2.1 2.8 V DC CHARACTERISTICS VBIAS UVLO VBIAS UVLO Hysteresis DC ADJ Pin Voltage Accuracy UVLO_BIAS_r VBIAS Rising UVLO_BIAS_f VBIAS Falling UVLOB_HYS VADJ 0.2 0.7V  VIN  3.6V, ILOAD  0A, 2.9V  VBIAS  5.5V, VOUT = VADJ V 494 502 510 mV DC Input Line Regulation (VOUT low line-VOUT high 2.9V  VIN  3.6V, VOUT = 2.5V line)/VOUT low line -0.18 0.02 0.18 % DC Bias Line Regulation (VOUT low line-VOUT high 4.5V