ISL8024AIRTAJZ-T

DATASHEET ISL8023, ISL8024 FN7812 Rev 3.00 March 24, 2014 Compact Synchronous Buck Regulator Features The ISL8023, ISL8024 are highly efficient, monolithic, synchronous step-down DC/DC converters that can deliver 3A (ISL8023) or 4A (ISL8024) of continuous output current from a 2.7V to 5.5V input supply. The devices use current mode control architecture to deliver very low duty cycle operation at high frequency with fast transient response and excellent loop stability. • 2.7V to 5.5V input voltage range • Very low on-resistance FET’s - P-Channel 45mΩ and N-Channel 19mΩ typical values • High efficiency synchronous buck regulator with up to 95% efficiency The ISL8023 and ISL8024 integrate a very low On-resistance P-Channel (45mΩ) high side FET and N-Channel (19mΩ) low side FET to maximize efficiency and minimize external component count. The 100% duty-cycle operation allows less than 200mV dropout voltage at 4A output current. The operation frequency of the pulse-width modulator (PWM) is adjustable from 500kHz to 4MHz. The default switching frequency of 1MHz is set by connecting the FS pin high, which allows for the use of small external components. • 0.8% reference accuracy over-temperature/load/line • Complete BOM with as few as 3 external parts • Start-up with pre-biased output • Internal soft-start - 1ms or adjustable • Soft-stop output discharge during disabled • Adjustable frequency from 500kHz to 4MHz - default at 1MHz (8023/24), 2MHz (8023A/24A) The ISL8023, ISL8024 can be configured for discontinuous or forced continuous operation at light load. Forced continuous operation reduces noise and RF interference while discontinuous mode provides higher efficiency by reducing switching losses at light loads. • External synchronization up to 4MHz • Over-temperature, Overcurrent, Overvoltage and negative overcurrent protection • Tiny 3x3 QFN package Fault protection is provided by internal hiccup mode current limiting during short circuit and overcurrent conditions. Other protection, such as overvoltage and over-temperature are also integrated into the device. A power-good output voltage monitor indicates when the output is in regulation. Applications • DC/DC POL modules • μC/µP, FPGA and DSP power The ISL8023, ISL8024 offer a 1ms Power-Good (PG) timer at power-up. When in shutdown, ISL8023, ISL8024 discharges the output capacitor through an internal soft-stop switch. Other features include internal fixed or adjustable soft-start and internal/external compensation. • Plug-in DC/DC modules for routers and switchers The ISL8023 and ISL8024 are offered in a space saving 16 Ld 3x3 Pb-free QFN package with an exposed pad for improved thermal performance and 1mm maximum height. The complete converter occupies less than 0.22 in2 area. Related Literature • Portable instruments • Test and measurement systems • Li-ion battery powered devices • See AN1759, “3A/4A Low Quiescent Current High Efficiency Synchronous Buck Regulator” Various fixed output voltages are available upon request. See the “Ordering Information” on page 4 for more details. 100 EFFICIENCY (%) 90 3.3VOUT PFM 80 70 3.3VOUT PWM 60 50 40 0.0 0.5 1.0 1.5 2.0 2.5 IOUT (A) 3.0 3.5 4.0 FIGURE 1. EFFICIENCY T = +25°C, VIN = 5V FN7812 Rev 3.00 March 24, 2014 Page 1 of 20 ISL8023, ISL8024 NOTE: Full solution in size board. The full schematic and Gerber files are available for down load from Intersil.com. FN7812 Rev 3.00 March 24, 2014 Page 2 of 20 ISL8023, ISL8024 Pin Configuration 16 15 14 PHASE PHASE PHASE VIN ISL8023, ISL8024 (16 LD TQFN) TOP VIEW 13 11 PGND PG 3 10 SGND SYNC 4 9 FB 5 6 7 8 COMP VDD 2 SS PGND FS 12 EN VIN 1 Pin Descriptions PIN NUMBER SYMBOL 1, 16 VIN DESCRIPTION 2 VDD 3 PG Power-good is an open-drain output. Use 10kΩ to 100kΩ pull-up resistor connecting between VIN and PG. At power-up or EN HI, PG rising edge is delayed by 1ms upon output reached within regulation. 4 SYNC Mode Selection pin. Connect to logic high or input voltage VIN for PWM mode. Connect to logic low or ground for PFM mode. Connect to an external function generator for synchronization with the positive edge trigger. There is an internal 1MΩ pull-down resistor to prevent an undefined logic state in case of SYNIN pin float. 5 EN Regulator enable pin. Enable the output when driven to high. Shutdown the chip and discharge output capacitor when driven to low. There is an internal 1MΩ pull-down resistor to prevent an undefined logic state in case of EN pin float. 6 FS This pin sets the oscillator switching frequency, using a resistor, RFS, from the FS pin to GND. The frequency of operation may be programmed between 500kHz to 4MHz. The default frequency is 1MHz and configured for internal compensation if FS is connected to VIN. 7 SS SS is used to adjust the soft-start time. Set to SGND for internal 1ms rise time. Connect a capacitor from SS to SGND to adjust the soft-start time. Do not use more than 33nF per IC. 8, 9 COMP, FB The feedback network of the regulator, VFB, is the negative input to the transconductance error amplifier. COMP is the output of the amplifier if FS resistor is used. Otherwise COMP is disconnected thru a MOSFET for internal compensation. Recommend connecting COMP to SGND in internal compensation mode. The output voltage is set by an external resistor divider connected to VFB. With a properly selected divider, the output voltage can be set to any voltage between the power rail (reduced by converter losses) and the 0.6V reference. There is an internal compensation to meet a typical application. Additional external network across COMP and SGND might be required to improve the loop compensation of the amplifier operation. In addition, the regulator power-good and undervoltage protection circuitry use VFB to monitor the regulator output voltage. 10 SGND Signal ground. Input supply voltage. Connect two 22µF ceramic capacitors to power ground. Input supply voltage for the logic. Connect VIN PIN. 11, 12 PGND Power ground. 13, 14, 15 PHASE Switching node connection. Connect to one terminal of the inductor. Exposed Pad - FN7812 Rev 3.00 March 24, 2014 The exposed pad must be connected to the SGND pin for proper electrical performance. Place as much vias as possible under the pad connecting to SGND plane for optimal thermal performance. Page 3 of 20 ISL8023, ISL8024 Ordering Information PART NUMBER (Notes 1, 2, 3) PART MARKING OUTPUT VOLTAGE (V) TEMP. RANGE (°C) PACKAGE (Pb-Free) PKG. DWG. # ISL8023IRTAJZ 023A Adjustable -40 to +85 16 Ld 3x3 TQFN L16.3x3D ISL8024IRTAJZ 024A Adjustable -40 to +85 16 Ld 3x3 TQFN L16.3x3D ISL8023AIRTAJZ 23AA Adjustable -40 to +85 16 Ld 3x3 TQFN L16.3x3D ISL8024AIRTAJZ 24AA Adjustable -40 to +85 16 Ld 3x3 TQFN L16.3x3D ISL8023EVAL3Z Evaluation Board ISL8024EVAL3Z Evaluation Board ISL8023AEVAL3Z Evaluation Board ISL8024AEVAL3Z Evaluation Board NOTES: 1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL8023, ISL8024. For more information on MSL, please see tech brief TB363. Typical Application Diagram INPUT 2.7V TO 5.5V VIN PHASE VDD C1 22µF C2 2 x 22µF EN R1 100k R2 200k PGND PG ISL8023, ISL8024 C3* 4.7pF R3 100k SGND SYNC OUTPUT 1.8V/4A L 1µH VFB COMP VIN FS SS SGND * C3 is optional. Recommend to put a placeholder for it. Check loop analysis first before use. FIGURE 2. TYPICAL APPLICATION DIAGRAM TABLE 1. COMPONENT SELECTION TABLE VOUT 0.8V 1.2V 1.5V 1.8V 2.5V 3.3V 3.6 C1 22µF 22µF 22µF 22µF 22µF 22µF 22µF C2 4X22µF 2 x 22µF 2 x 22µF 2 x 22µF 2 x 22µF 2 x 22µF 2 x 22µF C3 4.7pF 4.7pF 4.7pF 4.7pF 4.7pF 4.7pF 4.7pF L1 0.47~1µH 0.47~1µH 0.47~1µH 0.68~1.5µH 0.68~1.5µH 1~2.2µH 1~2.2µH R2 33k 100k 150k 200k 316k 450k 500k R3 100k 100k 100k 100k 100k 100k 100k FN7812 Rev 3.00 March 24, 2014 Page 4 of 20 ISL8023, ISL8024 COMP SS SHUTDOWN SYNC 55pF Soft SOFT START SHUTDOWN 100kΩ VDD + BANDGAP VREF + EN FS + COMP - EAMP - VIN OSCILLATOR PWM/PFM LOGIC CONTROLLER PROTECTION HS DRIVER 3pF + P PHASE LS DRIVER N PGND VFB Slope SLOPE COMP 6k 0.6V + OV 0.85*VREF PG + CSA - - + UV + OCP - + SKIP - ISET THRESHOLD 1ms DELAY NEG CURRENT SENSING SGND ZERO-CROSS SENSING 0.5V SCP + 100Ω SHUTDOWN FIGURE 3. FUNCTIONAL BLOCK DIAGRAM FN7812 Rev 3.00 March 24, 2014 Page 5 of 20 ISL8023, ISL8024 Absolute Maximum Ratings (Reference to GND) Thermal Information VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.5V (DC) or 7V (20ms) EN, FS, PG, SYNC, VFB . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VIN + 0.3V PHASE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -3V (100ns)/(DC) to 6.5V (DC) COMP, SS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.7V Thermal Resistance JA (°C/W) JC (°C/W) 16 LD TQFN Package (Notes 4, 5) . . . . . . . 45 6.5 Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-55°C to +125°C Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Recommended Operating Conditions VIN Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V Load Current Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0A to 4A Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 4. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 5. JC, “case temperature” location is at the center of the exposed metal pad on the package underside. Electrical Specifications Unless otherwise noted, all parameter limits are established over the recommended operating conditions and the typical specification are measured at the following conditions: TA = -40°C to +85°C, VIN = 3.6V, EN = VIN, unless otherwise noted. Typical values are at TA = +25°C. Boldface limits apply over the operating temperature range, -40°C to +85°C PARAMETER SYMBOL TEST CONDITIONS MIN (Note 6) TYP MAX (Note 6) UNITS 2.5 2.7 V INPUT SUPPLY VIN Undervoltage Lockout Threshold VUVLO Rising, no load Falling, no load Quiescent Supply Current Shutdown Supply Current IVIN ISD 2.2 2.4 V SYNC = GND, no load at the output 50 µA SYNC = GND, no load at the output and no switches switching 50 60 µA SYNC = VIN, FS = 1MHz, no load at the output 8 15 mA SYNC = GND, VIN = 5.5V, EN = low 5 7 µA 0.600 0.605 V OUTPUT REGULATION Reference Voltage - ISL8023IRZ, ISL8024IRZ VREF VFB Bias Current - ISL8023IRZ, ISL8024IRZ IVFB 0.595 VFB = 0.75V 0.01 µA Line Regulation VIN = VO + 0.5V to 5.5V (minimal 2.7V) 0.2 %/V Soft-Start Ramp Time Cycle SS = SGND 1 ms Soft-Start Charging Current ISS VSS = 0.1V 1.2 1.6 2.0 µA OVERCURRENT PROTECTION Current Limit Blanking Time tOCON 17 Clock pulses Overcurrent and Auto Restart Period tOCOFF 8 SS cycle Positive Peak Current Limit IPLIMIT Peak Skip Limit ISKIP Zero Cross Threshold Negative Current Limit FN7812 Rev 3.00 March 24, 2014 4A application 5.2 6.5 7.8 A 3A application 3.9 4.8 5.9 A 4A application (test at 3.6V) 0.9 1.2 1.5 A 3A application (test at 3.6V) 0.65 0.9 1.15 A 200 mA -1.8 A -200 INLIMIT -3.0 -2.4 Page 6 of 20 ISL8023, ISL8024 Electrical Specifications Unless otherwise noted, all parameter limits are established over the recommended operating conditions and the typical specification are measured at the following conditions: TA = -40°C to +85°C, VIN = 3.6V, EN = VIN, unless otherwise noted. Typical values are at TA = +25°C. Boldface limits apply over the operating temperature range, -40°C to +85°C (Continued) PARAMETER SYMBOL TEST CONDITIONS MIN (Note 6) TYP MAX (Note 6) UNITS COMPENSATION Error Amplifier Trans-Conductance Trans-Resistance FS = VIN 80 µA/V FS with Resistor 150 µA/V RT 0.15 0.2 0.25 Ω VIN = 5V, IO = 200mA 35 45 55 mΩ VIN = 2.7V, IO = 200mA 50 70 90 mΩ VIN = 5V, IO = 200mA 12 19 25 mΩ VIN = 2.7V, IO = 200mA 20 28 37 mΩ PHASE P-Channel MOSFET ON-Resistance N-Channel MOSFET ON-Resistance PHASE Maximum Duty Cycle  100 PHASE Minimum On-Time SYNC = High 140 ns 1200 kHz OSCILLATOR Nominal Switching Frequency Fsw FS = VIN 800 1000 FS with RS = 402kΩ 490 kHz FS with RS = 42.2kΩ 4200 kHz SYNC Logic Low to High Transition Range 0.70 SYNC Hysteresis 0.75 0.80 0.15 3.6 V 5 µA 0.3 V 1 2 ms PG Pin Leakage Current 0.01 0.1 µA OVP PG Rising Threshold 0.80 SYNC Logic Input Leakage Current VIN = 3.6V V PG Output Low Voltage Delay Time (Rising Edge) UVP PG Rising Threshold 0.5 80 85 V 90 % UVP PG Hysteresis 5 % PGOOD Delay Time (Falling Edge) 15 µs EN Logic Input Low Logic Input High 0.4 0.9 V V EN Logic Input Leakage Current 0.1 1 µA Thermal Shutdown 150 °C Thermal Shutdown Hysteresis 25 °C NOTE: 6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. FN7812 Rev 3.00 March 24, 2014 Page 7 of 20 ISL8023, ISL8024 Typical Operating Performance Unless otherwise noted, operating conditions are: TA = +25°C, VVIN = 5V, EN = VIN, 100 100 90 90 1.2VOUT 80 1.5VOUT 1.8VOUT EFFICIENCY (%) EFFICIENCY (%) SYNC = VIN, L = 1.0µH, C1 = 22µF, C2 = 2 x 22µF, IOUT = 0A to 4A. 2.5VOUT 70 60 50 0.5 1.0 1.5 2.0 IOUT (A) 2.5 3.0 3.5 1.8VOUT 2.5VOUT 70 60 40 0.0 4.0 FIGURE 4. EFFICIENCY vs LOAD (1MHz 3.3 VIN PWM) 0.5 1.0 1.5 2.0 IOUT (A) 2.5 3.0 3.5 4.0 FIGURE 5. EFFICIENCY vs LOAD (1MHz 3.3 VIN PFM) 100 100 90 90 1.2VOUT 80 1.5VOUT 1.8VOUT 2.5VOUT EFFICIENCY (%) EFFICIENCY (%) 1.5VOUT 50 40 0.0 3.3VOUT 70 60 50 80 1.2VOUT 1.5VOUT 1.8VOUT 2.5VOUT 3.3VOUT 70 60 50 40 0.0 0.5 1.0 1.5 2.0 IOUT (A) 2.5 3.0 3.5 40 0.0 4.0 FIGURE 6. EFFICIENCY vs LOAD (1MHz 5VIN PWM) 1.08 1.244 0.90 1.238 0.72 1.232 3.3VIN PWM MODE 0.54 5VIN PWM MODE 0.36 1.226 1.220 0.18 0 0.0 0.5 1.0 1.5 2.0 IOUT (A) 2.5 3.0 3.5 4.0 FIGURE 7. EFFICIENCY vs LOAD (1MHz 5VIN PFM) vOUT (V) POWER DISSIPATION (W) 1.2VOUT 80 3.3VIN PFM MODE 5VIN PFM MODE 1.214 0.5 1.0 1.5 2.0 IOUT (A) 2.5 3.0 3.5 4.0 FIGURE 8. POWER DISSIPATION vs LOAD (1MHz, VOUT = 1.8V) FN7812 Rev 3.00 March 24, 2014 3.3VIN PWM MODE 1.208 0.0 0.5 1.0 1.5 2.0 IOUT (A) 5VIN PWM MODE 2.5 3.0 3.5 FIGURE 9. VOUT REGULATION vs LOAD (1MHz, VOUT = 1.2V) Page 8 of 20 4.0 ISL8023, ISL8024 Typical Operating Performance Unless otherwise noted, operating conditions are: TA = +25°C, VVIN = 5V, EN = VIN, SYNC = VIN, L = 1.0µH, C1 = 22µF, C2 = 2 x 22µF, IOUT = 0A to 4A. (Continued) 1.529 1.830 1.524 1.824 1.519 1.818 3.3VIN PFM MODE 3.3VIN PFM MODE 1.514 VOUT (V) VOUT (V) 5VIN PFM MODE 5VIN PFM MODE 1.812 1.806 1.509 3.3VIN PWM MODE 3.3VIN PWM MODE 1.800 1.504 5VIN PWM MODE 1.499 0.0 0.5 1.0 1.5 2.0 IOUT (A) 2.5 3.0 3.5 1.794 0.0 4.0 1.0 1.5 2.0 IOUT (A) 2.5 3.0 3.5 4.0 3.354 2.540 2.532 3.345 3.3VIN PFM MODE 3.336 2.524 5VIN PFM MODE VOUT (V) VOUT (V) 0.5 FIGURE 11. VOUT REGULATION vs LOAD (1MHz, VOUT = 1.8V) FIGURE 10. VOUT REGULATION vs LOAD (1MHz, VOUT = 1.5V) 2.516 2.508 5VIN PFM MODE 3.327 3.318 3.3VIN PWM MODE 3.309 2.500 5VIN PWM MODE 2.492 0.0 0.5 1.0 1.5 2.0 IOUT (A) 2.5 3.0 3.5 3.300 0.0 4.0 FIGURE 12. VOUT REGULATION vs LOAD (1MHz, VOUT = 2.5V) 1.836 1.810 1.828 0A LOAD VOUT (V) 2A LOAD 1.790 1.785 2.0 3.0 3.5 4.0 VIN (V) 4.5 1.5 2.0 IOUT (A) 2.5 3.0 3.5 4.0 0A LOAD 1.812 2A LOAD 1.796 5.0 5.5 6.0 FIGURE 14. OUTPUT VOLTAGE REGULATION vs VIN (PWM VOUT = 1.8 ) FN7812 Rev 3.00 March 24, 2014 1.0 1.804 4A LOAD 2.5 0.5 1.820 1.800 1.795 5VIN PWM MODE FIGURE 13. VOUT REGULATION vs LOAD (1MHz, VOUT = 3.3V) 1.815 1.805 VOUT (V) 5VIN PWM MODE 1.788 2.0 4A LOAD 2.5 3.0 3.5 4.0 VIN (V) 4.5 5.0 5.5 6.0 FIGURE 15. OUTPUT VOLTAGE REGULATION vs VIN (PFM VOUT = 1.8V) Page 9 of 20 ISL8023, ISL8024 Typical Operating Performance Unless otherwise noted, operating conditions are: TA = +25°C, VVIN = 5V, EN = VIN, SYNC = VIN, L = 1.0µH, C1 = 22µF, C2 = 2 x 22µF, IOUT = 0A to 4A. (Continued) PHASE 2V/DIV VOUT RIPPLE 20mV/DIV PHASE 2V/DIV VOUT RIPPLE 20mV/DIV IL 1A/DIV IL 1A/DIV FIGURE 16. STEADY STATE OPERATION AT NO LOAD (PWM) PHASE 2V/DIV FIGURE 17. STEADY STATE OPERATION AT NO LOAD (PFM) VOUT RIPPLE 50mV/DIV IL 2A/DIV IL 2A/DIV VOUT RIPPLE 20mV/DIV FIGURE 18. STEADY STATE OPERATION WITH FULL LOAD VOUT RIPPLE 50mV/DIV FIGURE 19. LOAD TRANSIENT (PWM) EN 2V/DIV VOUT 1V/DIV IL 2A/DIV IL 1A/DIV PG 5V/DIV FIGURE 20. LOAD TRANSIENT (PFM) FN7812 Rev 3.00 March 24, 2014 FIGURE 21. SOFT-START WITH NO LOAD (PWM) Page 10 of 20 ISL8023, ISL8024 Typical Operating Performance Unless otherwise noted, operating conditions are: TA = +25°C, VVIN = 5V, EN = VIN, SYNC = VIN, L = 1.0µH, C1 = 22µF, C2 = 2 x 22µF, IOUT = 0A to 4A. (Continued) EN 2V/DIV EN 2V/DIV VOUT 1V/DIV VOUT 1V/DIV IL 1A/DIV IL 1A/DIV PG 2V/DIV PG 5V/DIV FIGURE 22. SOFT-START AT NO LOAD (PFM) EN 2V/DIV FIGURE 23. SOFT-START WITH PRE-BIASED 1V EN 2V/DIV VOUT 1V/DIV VOUT 1V/DIV IL 1A/DIV IL 2A/DIV PG 5V/DIV PG 5V/DIV FIGURE 24. SOFT-START AT FULL LOAD PHASE 5V/DIV VOUT RIPPLE 20mV/DIV PHASE 5V/DIV VOUT RIPPLE 20mV/DIV IL 0.5A/DIV IL 2A/DIV SYNC 5V/DIV SYNC 5V/DIV FIGURE 26. STEADY STATE OPERATION AT NO LOAD WITH FREQUENCY = 2MHz FN7812 Rev 3.00 March 24, 2014 FIGURE 25. SOFT-DISCHARGE SHUTDOWN FIGURE 27. STEADY STATE OPERATION AT FULL LOAD WITH FREQUENCY = 2MHz Page 11 of 20 ISL8023, ISL8024 Typical Operating Performance Unless otherwise noted, operating conditions are: TA = +25°C, VVIN = 5V, EN = VIN, SYNC = VIN, L = 1.0µH, C1 = 22µF, C2 = 2 x 22µF, IOUT = 0A to 4A. (Continued) PHASE 5V/DIV PHASE 5V/DIV VOUT RIPPLE 20mV/DIV VOUT RIPPLE 20mV/DIV IL 1A/DIV IL 0.2A/DIV SYNC 5V/DIV FIGURE 28. STEADY STATE OPERATION AT NO LOAD WITH FREQUENCY = 4MHz SYNC 5V/DIV FIGURE 29. STEADY STATE OPERATION AT FULL LOAD (PWM) WITH FREQUENCY = 4MHz PHASE 5V/DIV PHASE 5V/DIV IL 2A/DIV VOUT 1V/DIV VOUT 1V/DIV IL 2A/DIV SYNC 5V/DIV SYNC 5V/DIV FIGURE 30. OUTPUT SHORT CIRCUIT FIGURE 31. OUTPUT SHORT CIRCUIT RECOVERY Typical Operating Performance for A Part Unless otherwise noted, operating conditions are: TA = +25°C, VVIN = 5V, EN = VIN, SYNC = VIN, L = 1.0µH, C1 = 22µF, C2 = 2 x 22µF, IOUT = 0A to 4A. PHASE 2V/DIV VOUT RIPPLE 20mV/DIV PHASE 2V/DIV VOUT RIPPLE 20mV/DIV IL 0.5A/DIV IL 1A/DIV FIGURE 32. STEADY STATE OPERATION AT NO LOAD (PWM) FN7812 Rev 3.00 March 24, 2014 FIGURE 33. STEADY STATE OPERATION AT NO LOAD (PFM) Page 12 of 20 ISL8023, ISL8024 Typical Operating Performance for A Part Unless otherwise noted, operating conditions are: TA = +25°C, VVIN = 5V, EN = VIN, SYNC = VIN, L = 1.0µH, C1 = 22µF, C2 = 2 x 22µF, IOUT = 0A to 4A. (Continued) EN 2V/DIV PHASE 2V/DIV VOUT 1V/DIV IL 2A/DIV IL 1A/DIV VOUT RIPPLE 20mV/DIV PG 5V/DIV FIGURE 34. STEADY STATE OPERATION WITH FULL LOAD FIGURE 35. SOFT-START WITH NO LOAD (PWM) EN 2V/DIV EN 2V/DIV VOUT 1V/DIV VOUT 1V/DIV IL 1A/DIV IL 1A/DIV PG 5V/DIV FIGURE 36. SOFT-START AT NO LOAD (PFM) PG 5V/DIV FIGURE 37. SOFT-START AT FULL LOAD EN 2V/DIV VOUT 1V/DIV IL 1A/DIV PG 5V/DIV FIGURE 38. SOFT-DISCHARGE SHUTDOWN FN7812 Rev 3.00 March 24, 2014 Page 13 of 20 ISL8023, ISL8024 Theory of Operation The ISL8023, ISL8024 is a step-down switching regulator optimized for battery-powered handheld applications. The regulator operates at 1MHz fixed default switching frequency, when FS is connected to VIN, under heavy load conditions to allow smaller external inductors and capacitors to be used for minimal printed-circuit board (PCB) area. By connecting a resistor from FS to SGND, the operational frequency adjustable range is 500kHz to 4MHz. At light load, the regulator reduces the switching frequency, unless forced to the fixed frequency, to minimize the switching loss and to maximize the battery life. The quiescent current when the output is not loaded is typically only 50µA. The supply current is typically only 5µA when the regulator is shutdown. PWM Control Scheme Pulling the SYNC pin HI (>0.8V) forces the converter into PWM mode, regardless of output current. The ISL8023, ISL8024 employs the current-mode pulse-width modulation (PWM) control scheme for fast transient response and pulse-by-pulse current limiting. Figure 3 on page 5 shows the Functional Block Diagram. The current loop consists of the oscillator, the PWM comparator, current sensing circuit and the slope compensation for the current loop stability. The slope compensation is 440mV/Ts, which changes with frequency. The gain for the current sensing circuit is typically 200mV/A. The control reference for the current loops comes from the error amplifier's (EAMP) output. The PWM operation is initialized by the clock from the oscillator. The P-Channel MOSFET is turned on at the beginning of a PWM cycle and the current in the MOSFET starts to ramp up. When the sum of the current amplifier CSA and the slope compensation reaches the control reference of the current loop, the PWM comparator COMP sends a signal to the PWM logic to turn off the P-FET and turn on the N-Channel MOSFET. The N-FET stays on until the end of the PWM cycle. Figure 39 shows the typical operating waveforms during the PWM operation. The dotted lines illustrate the sum of the slope compensation ramp and the current-sense amplifier’s CSA output. The output voltage is regulated by controlling the VEAMP voltage to the current loop. The bandgap circuit outputs a 0.6V reference voltage to the voltage loop. The feedback signal comes from the VFB pin. The soft-start block only affects the operation during the start-up and will be discussed separately. The error amplifier is a transconductance amplifier that converts the voltage error signal to a current output. The voltage loop is internally compensated with the 55pF and 100kΩ RC network. The maximum EAMP voltage output is precisely clamped to 1.6V. FN7812 Rev 3.00 March 24, 2014 VEAMP VCSA DUTY CYCLE IL VOUT FIGURE 39. PWM OPERATION WAVEFORMS SKIP Mode Pulling the SYNC pin LO (