ISL85009EVAL1Z

User Guide 112 ISL85009EVAL1Z Evaluation Board User Guide Description Key Features The ISL85009 is a 3.8V to 18V input, 9A synchronous buck regulator for applications with input voltage from multi-cell batteries or regulated 5V and 12V power rails. The device also provides an integrated bootstrap diode for the high-side gate driver to reduce the external parts count. The ISL85009EVAL1Z platform allows quick evaluation of the high-performance features of the ISL85009 buck regulator. • Switch selectable EN (enabled/disabled) • Frequency synchronization option • Jumper selectable mode (DEM/Forced CCM) • Jumper selectable OCP mode (Hiccup/Latch-Off) • Jumper selectable frequency (600kHz/300kHz) • Connectors and test points for easy probing Specifications • Compact design Related Literature This board has been configured and optimized for the following operating conditions: • For a full list of related documents, visit our website - ISL85009 product page • Input voltage range from 4.5V to 18V • 1.8V nominal output voltage • Up to 9A output current capability Ordering Information • Default internally set to 600kHz switching frequency PART NUMBER • Default internally set to 3ms soft-start DESCRIPTION ISL85009EVAL1Z • Operating temperature range: -40°C to +85°C Evaluation board for ISL85009 DISABLE ENABLE R1 R2 R3 C1 15 14 13 12 11 10 VIN EN DNC DNC COMP FB PVIN PVIN 9 L1 4.5V TO 18V CIN PHASE VOUT 8 1.8V/9A C OUT GND GND C4 7 GND SYNC MODE FREQ PG VDD BOOT 1 2 3 4 5 6 600kHz 300kHz HICCUP FCCM DEM LATCH-OFF C3 FIGURE 1. BLOCK DIAGRAM February 15, 2017 UG112.0 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2017. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. User Guide 112 Connector and Test Point Descriptions The ISL85009EVAL1Z evaluation board includes I/O connectors and test points as shown in Table 1. TABLE 1. CONNECTORS AND TEST POINTS REFERENCE DESIGNATOR DESCRIPTION 2. Connect an electronic load to J2 (VOUT) for the positive connection and J4 (GND) for the negative connection. 3. Measure the output voltage (test points VOUT and GND) with the voltmeter. 4. Place scope probes on VOUT test point (J7) and other test points of interest. 5. Toggle selection switch SW5 to ON position. 6. Set the load current to be 0.1A and turn on the power supply. The output voltage should be in regulation with a nominal 1.8V output. J1 Input voltage positive connection J2 Output voltage positive connection J3 Input voltage return connection J4 Output voltage return connection J6 Two-position socket connector for PHASE to GND test 8. Slowly sweep VIN from 4.5V to 18V. The output voltage should remain in regulation with a nominal 1.8V output. J7 Two-position socket connector for VOUT to GND test 9. Decrease the input voltage to 0V to shut down the regulator. PVIN PVIN positive test point GND GND test point VIN VIN positive test point VOUT Output voltage positive test point SYNC External synchronization clock connection EN VDD PG Enable test point Internal LDO output test point Power-good output Selection Switch and Jumper Descriptions • Switch SW5 (Enable) The switch enables and disables the ISL85009: - When the switch is in the ON position, ISL85009 enabled. - When the switch is in the OFF position, ISL85009 disabled. • Jumper J9 The jumper provides selection of different operating modes detailed as following: - When the jumper is in the FCCM position, the ISL85009 operates in Forced CCM. - When the jumper is in the DEM position, the ISL85009 operates in Diode Emulation mode and enables automatic transition from CCM to DCM at light-load conditions. • Jumper J10 sets the switching frequency at either 600kHz or 300kHz. • Jumper J11 sets the OCP scheme in either Hiccup mode or Latch-Off mode. Quick Setup Guide Refer to the following instructions to configure and power-up the board for proper operation. 1. Set the power supply voltage to 12V and turn off the power supply. Connect the positive output of the power supply to J1 (PVIN) and the negative output to J3 (GND). Submit Document Feedback 2 7. Slowly increase the load up to 9A while monitoring the output voltage, which should remain in regulation with a nominal 1.8V output. Frequency Synchronization The ISL85009 can be synchronized to an external clock with frequency ranges from 100kHz to 1MHz by applying the external clock to test point SYNC on the ISL85009EVAL1Z evaluation board. The external clock should meet the specifications of pulse width and voltage level described in the ISL85009 datasheet. Evaluating Other Output Voltages The ISL85009EVAL1Z has a nominal 1.8V output voltage. The output voltage is programmable by an external resistor divider formed by R1 and R2 as shown in Figure 1 on page 1. R1 is usually chosen first, then the value for R2 can be calculated based on R1 and the desired output voltage using Equation 1. R 1  0.6V R 2 = ---------------------------------V OUT – 0.6V (EQ. 1) PCB Layout Considerations The PCB layout is critical for proper operation of the ISL85009. The following guidelines should be followed to achieve good performance. 1. Use a multilayer PCB structure to achieve optimized performance. A four-layer PCB is recommended for this design. 2. Use a combination of bulk capacitors and smaller ceramic capacitors with lower ESL for the input capacitors, and place them as close to the IC as possible. 3. Place the VDD decoupling capacitor close to the IC between VDD and GND. A 1µF ceramic capacitor is typically used. 4. Place a bootstrap capacitor close to the IC between the BOOT and PHASE pins. A 0.1µF ceramic capacitor is typically used. 5. Connect the feedback resistor divider between the output capacitor positive terminal and AGND pin of the IC, and place the resistors close to the FB pin of the IC. 6. Connect the GND of the IC to the ground planes underneath using multiple thermal vias to improve thermal performance. UG112.0 February 15, 2017 User Guide 112 ISL85009EVAL1Z Evaluation Board FIGURE 2. TOP VIEW ISL85009EVAL1Z Schematic Disable (1 6: & '13 S 5 & '13 5 N '13 5  5 N  &203 (1 9,1   8 5  '13  *1' 5 1& & Q)  9,1 & )% 5   5 N & X Internal Compensation 6:63'7 1& Enable 39,1 -   39,1 ,6/ 9287 - /  & & X) X) X+ X)   & Q - 6