DATASHEET
ISL85403
FN8631
Rev.4.00
Sep 28, 2020
2.5A Regulator with Integrated High-side MOSFET for Synchronous Buck or
Boost Buck Converter
The ISL85403 is a 40V, 2.5A synchronous buck or boost buck
controller with an integrated high-side MOSFET and low-side
driver. In Buck mode, the ISL85403 supports a wide input
range of 3V to 40V. In Boost-Buck mode, the input range can
be extended down to 2.5V and output regulation can be
maintained when VIN drops below VOUT, enabling sensitive
electronics to remain on in low input voltage conditions.
Features
The ISL85403 has a flexible selection of Forced PWM mode
and PFM mode. In PFM mode, the quiescent input current is as
low as 180µA (AUXVCC connected to VOUT). The load boundary
between PFM and PWM can be programmed to cover wide
applications.
• 300µA IC quiescent current (PFM, no load); 180µA input
quiescent current (PFM, no load, VOUT tied to AUXVCC)
The low-side driver can either be used to drive an external
low-side MOSFET for a synchronous buck or left unused for a
standard non-synchronous buck. The low-side driver can also
be used to drive a boost converter as a preregulator followed
by a buck controlled by the same IC, which greatly expands the
operating input voltage range down to 2.5V or lower (See
Figure 5).
ISL85403 offers robust current protection. It uses peak current
mode control with cycle-by-cycle current limiting. It is
implemented with frequency foldback under current limit
condition; also, the hiccup overcurrent mode ensures reliable
operations under harsh short conditions.
The ISL85403 has comprehensive protections against various
faults including overvoltage and over-temperature protections.
Related Literature
• Buck mode: input voltage range 3V to 40V (See “Input
Voltage” for more details)
• Boost mode expands operating input voltage lower than
2.5V (See “Input Voltage” for more details)
• Selectable Forced PWM mode or PFM mode
• Less than 5µA (MAX) shutdown input current (IC disabled)
• Operational topologies
- Synchronous buck
- Non-synchronous buck
- Two-stage boost buck
- Non-inverting single inductor buck boost
• Programmable frequency from 200kHz to 2.2MHz and
frequency synchronization capability
• ±1% tight voltage regulation accuracy
• Reliable overcurrent protection
- Temperature compensated current sense
- Cycle-by-cycle current limiting with frequency foldback
- Hiccup mode for worst case short condition
• 20 Ld 4x4 QFN package
• Pb-free (RoHS compliant)
Applications
For a full list of related documents, visit our website:
• General purpose
• ISL85403 device page
• 24V bus power
• Battery power
• Point-of-load
• Embedded processor and I/O supplies
100
95
VIN
SYNC
AUXVCC
VCC
VIN
BOOT
ISL85403
ISL85403
PHASE
ILIMIT
LGATE
SS
PGND
EXT_BOOST
FS
SGND
FB
COMP
6V VIN
90
V OUT
EFFICIENCY (%)
PGOOD
EN
MODE
85
12V VIN
80
36V VIN
75
24V VIN
70
65
60
55
50
0.1m
1m
10m
100m
1.0
LOAD CURRENT (A)
FIGURE 1. TYPICAL APPLICATION
FN8631 Rev.4.00
Sep 28, 2020
FIGURE 2. EFFICIENCY, SYNCHRONOUS BUCK, PFM MODE,
VOUT 5V, TA = +25°C
Page 1 of 24
2.5
ISL85403
Table of Contents
Typical Application Schematics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Functional Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Soft-Start. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PWM Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PFM Mode Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Synchronous and Non-Synchronous Buck . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AUXVCC Switchover . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-Stage Boost Buck Converter Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Oscillator and Synchronization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PGOOD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14
14
14
14
14
14
15
15
15
15
16
17
18
Fault Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overcurrent Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overvoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18
18
18
18
Component Selections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Capacitors - Buck . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Capacitors - Buck . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Inductor - Buck . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Low-Side Power MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Voltage Feedback Resistor Divider. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Boost Inductor (2-Stage Boost Buck) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Boost Output Capacitor (2-Stage Boost Buck) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18
18
19
19
19
19
19
19
Loop Compensation Design - Buck . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PWM Comparator Gain Fm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current Sampling Transfer Function He(S). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Stage Transfer Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20
20
20
20
Loop Compensation Design for 2-Stage Boost Buck and Single-Stage Buck Boost. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Layout Suggestions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
FN8631 Rev.4.00
Sep 28, 2020
Page 2 of 24
ISL85403
Typical Application Schematics
I
PGOOD
EN
MODE
SYNC
AUXVCC
PGOOD
EN
MODE
VIN
VIN
SYNC
AUXVCC
BOOT
VCC
ISL85403
V OUT
PHASE
VCC
ILIMIT
VIN
VIN
BOOT
ISL85403
V OUT
PHASE
ILIMIT
LGATE
SS
LGATE
SS
PGND
PGND
EXT_BOOST
FS
SGND
EXT_BOOST
FS
SGND
FB
COMP
(a) SYNCHRONOUS BUCK
FB
COMP
(b) NON-SYNCHRONOUS BUCK
FIGURE 3. TYPICAL APPLICATION SCHEMATIC I
PGOOD
EN
MODE
SYNC
AUXVCC
VCC
PGOOD
EN
MODE
VIN
VIN
SYNC
AUXVCC
BOOT
ISL85403
VCC
V OUT
PHASE
BOOT
ISL85403
V OUT
PHASE
ILIMIT
ILIMIT
LGATE
SS
VIN
VIN
LGATE
SS
PGND
PGND
EXT_BOOST
FS
SGND
EXT_BOOST
FS
SGND
FB
COMP
(a) SYNCHRONOUS BUCK
FB
COMP
(b) NON-SYNCHRONOUS BUCK
FIGURE 4. TYPICAL APPLICATION SCHEMATIC II - VCC SWITCHOVER TO VOUT
Battery
+
+
R1
R2
PGOOD
EN
MODE
EXT_BOOST
PGOOD
EN
R3
LGATE
AUXVCC
SYNC
VCC
1M
VCC
ILIMIT
ISL85403
SS
BOOT
PHASE
V OUT
SGND
VIN
ISL85403
BOOT
FB
(a) 2-STAGE BOOST BUCK
V OUT
PHASE
PGND
LGATE
PGND
COMP
VIN
SS
FS
FS
AUXVCC
SYNC
R4
VIN
ILIMIT
EXT_BOOST
VCC
130k
SGND
COMP
FB
(b) NON-INVERTING SINGLE INDUCTOR BUCK BOOST
FIGURE 5. TYPICAL APPLICATION SCHEMATIC III - BOOST BUCK CONVERTER
FN8631 Rev.4.00
Sep 28, 2020
Page 3 of 24
AUXVCC
VCC
PGOOD
ISL85403
FN8631 Rev.4.00
Sep 28, 2020
Block Diagram
VIN (x2)
VIN
CURRENT
MONITOR
AUXILARY LDO
BIAS LDO
ILIMIT
POWER-ON
RESET
SGND
VCC
BOOT
OCP, OVP, OTP
PFM LOGIC
BOOST MODE CONTROL
EN
EXT_BOOST
MODE
PFM/FPWM
PHASE (x2)
GATE DRIVE
VOLTAGE
MONITOR
SYNC
FS
SLOPE
COMPENSATION
LGATE
OSCILLATOR
+
SOFT-START
LOGIC
VCC
BOOT REFRESH
0.8V
REFERENCE
5 µA
COMPARATOR
EA
SS
+
FB
COMP
FIGURE 6. BLOCK DIAGRAM
PGND
Page 4 of 24
ISL85403
Ordering Information
PART NUMBER
(Notes 2, 3)
PART
MARKING
TEMP.
RANGE (°C)
Tape and Reel
(Units) (Note 1)
PACKAGE
(RoHS Compliant)
PKG. DWG. #
ISL85403FRZ
85 403FRZ
-40 to +105
-
20 Ld 4x4 QFN
L20.4x4C
ISL85403FRZ-T
85 403FRZ
-40 to +105
6k
20 Ld 4x4 QFN
L20.4x4C
ISL85403FRZ-T7A
85 403FRZ
-40 to +105
250
20 Ld 4x4 QFN
L20.4x4C
ISL85403FRZ-TK
85 403FRZ
-40 to +105
1k
20 Ld 4x4 QFN
L20.4x4C
ISL85403DEMO1Z
Compact size demo board for SYNC buck
ISL85403EVAL1Z
Evaluation Board
ISL85403EVAL2Z
Evaluation Board for non-inverting buck-boost configuration
NOTES:
1. See TB347 for details about reel specifications.
2. These Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate
plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), see the ISL85403 device page. For more information about MSL see TB363.
Pin Configuration
AUXVCC
VCC
SGND
VIN
VIN
20 LD QFN
TOP VIEW
20
19
18
17
16
1
15
BOOT
FS
2
14
PGND
SS
3
EN
PAD
Thermal
Pad
21
5
11
EXT_BOOST
6
7
8
9
10
PHASE
COMP
PHASE
SYNC
PGOOD
FB
12
MODE
LGATE
4
ILIMIT
13
Functional Pin Descriptions
PIN NAME
PIN #
DESCRIPTION
EN
1
Enable the IC by leaving the EN pin floating or pulling it HIGH. Disable the IC by pulling this pin LOW.
Range: 0V to 5.5V.
FS
2
Force the IC to have a 500kHz switching frequency by connecting the FS pin to VCC or GND, or by leaving the FS pin open. Program
the oscillator switching frequency by adjusting the resistor from this pin to GND.
SS
3
Connect a capacitor from this pin to ground. The capacitor, along with an internal 5µA current source, sets the converter's soft-start
interval. Also, this pin can be used to track a ramp on this pin.
FB
4
The inverting input of the voltage feedback error amplifier. With a properly selected resistor divider connected from VOUT to FB, the
output voltage can be set to any voltage between the power rail (reduced by maximum duty cycle and voltage drop) and the 0.8V
reference. Connect an R-C network across COMP and FB for loop compensation. The FB pin is also monitored for overvoltage events.
COMP
5
Output of the voltage feedback error amplifier.
FN8631 Rev.4.00
Sep 28, 2020
Page 5 of 24
ISL85403
Functional Pin Descriptions
(Continued)
PIN NAME
PIN #
DESCRIPTION
ILIMIT
6
Programmable current limit pin. With this pin connected to the VCC pin, or to GND, or left open, the current limiting threshold is set
to default of 3.6A; the current limiting threshold can be programmed with a resistor from this pin to GND.
MODE
7
Mode selection pin. Pull this pin to GND for Forced PWM mode; leave it floating or connected to VCC to enable PFM mode when the
peak inductor current is below the default threshold of 700mA. The current boundary threshold between PFM and PWM can also
be programmed with a resistor at this pin to ground. See “PFM Mode Operation” for more details.
PGOOD
8
An open-drain output and pull-up pin with a resistor to VCC for proper function. PGOOD is pulled low when the output is out of
regulation (OV or UV) or the EN pin is pulled low. PGOOD rising has a fixed 128 cycle delay.
PHASE
9, 10 The PHASE pins are the PHASE nodes that should be connected to the output inductor. These pins are connected to the source of
the high-side N-channel MOSFET.
EXT_BOOST
11
Set Boost mode and monitors the battery voltage that is the input of the boost converter. After VCC POR, the controller detects the
voltage on this pin; if the voltage on this pin is below 200mV, the controller is set in synchronous/non-synchronous Buck mode and
latches in this state unless VCC is below POR falling threshold; if the voltage on this pin after VCC POR is above 200mV, the
controller is set in Boost mode and latches in this state. In Boost mode, the low-side driver outputs PWM with the same duty cycle
as the upper-side driver to drive the boost switch.
In Boost mode, this pin is used to monitor input voltage through a resistor divider. By setting the resistor divider, the high threshold
and hysteresis can be programmed. When voltage on this pin is above 0.8V, the PWM output (LGATE) for the boost converter is
disabled. When voltage on this pin is below 0.8V minus the hysteresis, the boost PWM is enabled.
In Boost mode operation, PFM is disabled when boost PWM is enabled. Check the “2-Stage Boost Buck Converter Operation” for
more details.
SYNC
12
This pin can be used to synchronize two or more ISL85403 controllers. Multiple ISL85403s can be synchronized with their SYNC
pins connected together. 180° phase shift is automatically generated between the master and slave ICs.
The internal oscillator can also lock to an external frequency source applied on this pin with a square pulse waveform (with
frequency 10% higher than the IC’s local frequency, and pulse width higher than 150ns). Range: 0V to 5.5V.
Leave this pin floating if not used.
LGATE
13
In synchronous Buck mode, this pin is used to drive the lower side MOSFET to improve efficiency. Add a 5.1k or smaller value resistor
to connect LGATE to ground to avoid falsely turning on LGATE caused by coupling noise.
When a diode is used as the bottom side power device in non-synchronous Buck mode, connect this pin to VCC through a resistor
(less than 5k) before IC start-up to disable the low-side driver (LGATE).
In Boost mode, this pin can drive the boost power MOSFET. The boost control PWM is the same with the buck control PWM.
PGND
14
The ground connection of the power flow, including the driver. Connect this pin to a large ground plane.
BOOT
15
Provides bias voltage to the high-side MOSFET driver. A bootstrap circuit creates a voltage suitable to drive the internal N-channel
MOSFET. The boot charge circuitries are integrated inside of the IC. No external boot diode is needed. A 1µF ceramic capacitor is
recommended between BOOT and PHASE pin.
VIN
16, 17 Connected to the drain of the integrated high-side MOSFET as well as the source for the internal linear regulator that provides the
bias of the IC. Connect the input rail to these VIN pins. Range: 3V to 40V.
With the part switching, the operating input voltage applied to the VIN pins must be under 40V. This recommendation allows for
short voltage ringing spikes (within a couple of ns time range) due to switching while not exceeding the “Absolute Maximum
Ratings”.
SGND
18
Provides the return path for the control and monitor portions of the IC. Connect it to a quiet ground plane.
VCC
19
Output of the internal linear regulator that supplies the bias for the IC including the driver. A minimum 4.7µF decoupling ceramic
capacitor is recommended between VCC to ground.
AUXVCC
20
Input of the auxiliary internal linear regulator, which can be supplied by the regulator output after power-up. With such configuration,
the power dissipation inside of the IC is reduced. The input range for this LDO is 4.5V to 20V.
In Boost mode operation, this pin works as a boost output overvoltage detection pin. It detects the boost output through a resistor
divider. When voltage on this pin is above 0.8V, the boost PWM is disabled; when voltage on this pin is below 0.8V minus the
hysteresis, the boost PWM is enabled.
Range: 0V to 20V.
PAD
-
Bottom thermal pad. It is not connected to any electrical potential of the IC. In layout it must be connected to a PCB ground copper
plane with an area as large as possible to effectively reduce the thermal impedance.
FN8631 Rev.4.00
Sep 28, 2020
Page 6 of 24
ISL85403
Absolute Maximum Ratings
Thermal Information
VIN, PHASE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +44V
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +6.0V
AUXVCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +22V
Absolute Boot Voltage, VBOOT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +50.0V
Upper Driver Supply Voltage, VBOOT - VPHASE. . . . . . . . . . . . . . . . . . . +6.0V
All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to VCC + 0.3V
ESD Rating
Human Body Model (Tested per JESD22-A114F) . . . . . . . . . . . . . . .2.5kV
Machine Model (Tested per JESD22-A115C) . . . . . . . . . . . . . . . . . . 250V
Charged Device Model (Tested per JESD22-C101E) . . . . . . . . . . . . . 1kV
Latch-Up Rating (Tested per JESD78B; Class II, Level A). . . . . . . . . 100mA
Thermal Resistance
JA (°C/W) JC (°C/W)
QFN 4x4 Package (Notes 4, 5). . . . . . . . . . . . . . .
40
3.5
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . . . . +150°C
Maximum Storage Temperature Range. . . . . . . . . . . . . . . . . -65°C to +150°C
Pb-Free reflow profile. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
Recommended Operating Conditions
Supply Voltage on VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3V to 40V
AUXVCC, Buck Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5V to +20V
AUXVCC, Boost-Buck Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to +20V
Ambient Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +105°C
Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions can adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. JA is measured in free air with the component mounted on a high-effective thermal conductivity test board with “direct attach” features. See TB379.
5. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
See Figure 6 and the “Typical Application Schematics” on page 3. Operating conditions unless otherwise
noted: VIN = 12V, or VCC = 4.5V ±10%, TA = -40°C to +105°C. Typicals are at TA = +25°C. Boldface limits apply across the operating temperature range,
-40°C to +105°C.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6) UNIT
VIN PIN SUPPLY
VIN Pin Voltage Range
Operating Supply Current
Shutdown Supply Current
IQ
IIN_SD
VIN pin
3.05
40
V
VIN pin connected to VCC
3.05
5.5
V
MODE = VCC/FLOATING (PFM), no load at the
output
300
µA
MODE = GND (forced PWM), VIN = 12V,
IC operating, not including driving current
1.3
mA
EN connected to GND, VIN = 12V
2.8
4.5
µA
4.5
4.8
V
0.3
0.52
V
0.25
0.42
V
INTERNAL MAIN LINEAR REGULATOR
MAIN LDO VCC Voltage
MAIN LDO Dropout Voltage
VCC
VIN > 5V
4.2
VDROPOUT_MAIN VIN = 4.2V, IVCC = 35mA
VIN = 3V, IVCC = 25mA
VCC Current Limit of MAIN LDO
60
mA
INTERNAL AUXILIARY LINEAR REGULATOR
AUXVCC Input Voltage Range
AUX LDO VCC Voltage
LDO Dropout Voltage
VAUXVCC
VCC
4.5
VAUXVCC > 5V
4.2
VDROPOUT_AUX VAUXVCC = 4.2V, IVCC = 35mA
VAUXVCC = 3V, IVCC = 25mA
Current Limit of AUX LDO
20
V
4.5
4.8
V
0.3
0.52
V
0.25
0.42
V
60
mA
AUX LDO Switchover Rising Threshold
VAUXVCC_RISE
AUXVCC voltage rise; switch to auxiliary LDO
2.97
3.1
3.2
V
AUX LDO Switchover Falling Threshold Voltage
VAUXVCC_FALL
AUXVCC voltage fall; switch back to main BIAS
LDO
2.73
2.87
2.97
V
AUX LDO Switchover Hysteresis
VAUXVCC_HYS
AUXVCC switchover hysteresis
FN8631 Rev.4.00
Sep 28, 2020
0.2
Page 7 of 24
V
ISL85403
Electrical Specifications
See Figure 6 and the “Typical Application Schematics” on page 3. Operating conditions unless otherwise
noted: VIN = 12V, or VCC = 4.5V ±10%, TA = -40°C to +105°C. Typicals are at TA = +25°C. Boldface limits apply across the operating temperature range,
-40°C to +105°C. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 6)
TYP
2.82
2.9
3.05
V
2.8
V
MAX
(Note 6) UNIT
POWER-ON RESET
Rising VCC POR Threshold
VPORH_RISE
Falling VCC POR Threshold
VPORL_FALL
2.6
VCC POR Hysteresis
VPORL_HYS
0.3
V
ENABLE
Enable On Voltage
VENH
Enable Off voltage
VENL
EN Pull-Up Current
IEN_PULLUP
1.7
V
1
V
VEN = 1.2V, VIN = 24V
1.5
µA
VEN = 1.2V, VIN = 12V
1.2
µA
VEN = 1.2V, VIN = 5V
0.9
µA
OSCILLATOR
PWM Frequency
FOSC
RT = 665kΩ
160
200
240
kHz
RT = 51.1kΩ
1870
2200
2530
kHz
FS pin connected to VCC or floating or GND
450
500
550
kHz
MIN ON-Time
tMIN_ON
130
225
ns
MIN OFF-Time
tMIN_OFF
210
330
ns
Input High Threshold
VIH
2
V
Input Low Threshold
VIL
0.5
V
Input Minimum Pulse Width
25
ns
Input Impedance
100
kΩ
Input Minimum Frequency Divided by Free
Running Frequency
1.1
Input Maximum Frequency Divided by Free
Running Frequency
1.6
SYNCHRONIZATION
Output Pulse Width
CSYNC = 100pF
RLOAD = 1kΩ
100
ns
Output Pulse High
VOH
VCC-0.25
V
Output Pulse Low
VOL
GND
V
VREF
0.8
V
REFERENCE VOLTAGE
Reference Voltage
System Accuracy
-1.0
FB Pin Source Current
+1.0
%
5
nA
Soft-Start
Soft-Start Current
ISS
3
5
7
µA
ERROR AMPLIFIER
Unity Gain-Bandwidth
CLOAD = 50pF
10
MHz
DC Gain
CLOAD = 50pF
88
dB
Maximum Output Voltage
3.6
V
Minimum Output Voltage
0.5
V
5
V/µs
Slew Rate
FN8631 Rev.4.00
Sep 28, 2020
SR
CLOAD = 50pF
Page 8 of 24
ISL85403
Electrical Specifications
See Figure 6 and the “Typical Application Schematics” on page 3. Operating conditions unless otherwise
noted: VIN = 12V, or VCC = 4.5V ±10%, TA = -40°C to +105°C. Typicals are at TA = +25°C. Boldface limits apply across the operating temperature range,
-40°C to +105°C. (Continued)
MIN
(Note 6)
TYP
MAX
(Note 6) UNIT
MODE = VCC or floating
700
mA
Limits apply for +25°C only
127
LGate Source Resistance
100mA source current
3.5
Ω
LGATE Sink Resistance
100mA sink current
2.8
Ω
PARAMETER
SYMBOL
TEST CONDITIONS
PFM MODE CONTROL
Default PFM Current Threshold
INTERNAL HIGH-SIDE MOSFET
Upper MOSFET rDS(ON)
rDS(ON)_UP
140
mΩ
LOW-SIDE MOSFET GATE DRIVER
BOOST CONVERTER CONTROL
EXT_BOOST Boost_Off Threshold Voltage
EXT_BOOST Hysteresis Sink Current
IEXT_BOOST_HYS
AUXVCC Boost Turn-Off Threshold Voltage
AUXVCC Hysteresis Sink Current
IAUXVCC_HYS
0.74
0.8
0.86
V
2.1
3.2
4.2
µA
0.74
0.8
0.86
V
2.1
3.2
4.2
µA
104
110
116
%
POWER-GOOD MONITOR
Overvoltage Rising Trip Point
VFB/VREF
Percentage of reference point
Overvoltage Rising Hysteresis
VFB/VOVTRIP
Percentage below OV trip point
Undervoltage Falling Trip Point
VFB/VREF
Percentage of reference point
VFB/VUVTRIP
Percentage above UV trip point
Undervoltage Falling Hysteresis
PGOOD Rising Delay
3
84
tPGOOD_R_DELAY
PGOOD Leakage Current
PGOOD HIGH, VPGOOD = 4.5V
90
%
96
%
3
%
128
cycles
10
nA
0.10
V
VPGOOD
PGOOD LOW, IPGOOD = 0.2mA
Default Cycle-by-Cycle Current Limit Threshold
IOC_1
ILIMIT = GND or VCC or floating
Hiccup Current Limit Threshold
IOC_2
Hiccup, IOC_2/IOC_1
115
%
OV 120% Trip Point
Active in and after soft-start.
Percentage of reference point
LG = UG = LOW
120
%
OV 120% Release Point
Active in and after soft-start.
Percentage of reference point
102.5
%
OV 110% Trip Point
Active after soft-start done.
Percentage of reference point
LG = UG = LOW
110
%
OV 110% Release Point
Active after soft-start done.
Percentage of reference point
102.5
%
Over-Temperature Trip Point
160
°C
Over-Temperature Recovery Threshold
140
°C
PGOOD Low Voltage
OVERCURRENT PROTECTION
3
3.6
4.2
A
OVERVOLTAGE PROTECTION
OVER-TEMPERATURE PROTECTION
NOTE:
6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
FN8631 Rev.4.00
Sep 28, 2020
Page 9 of 24
ISL85403
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
0.0
100
95
6V VIN
90
24V VIN
12V VIN
36V VIN
6V VIN
12V VIN
85
EFFICIENCY (%)
EFFICIENCY (%)
Typical Performance Curves
80
36V VIN
75
24V VIN
70
65
60
55
0.5
1.0
1.5
50
0.1m
2.5
2.0
1m
10m
100m
1.0
FIGURE 7. EFFICIENCY, SYNCHRONOUS BUCK, FORCED PWM
MODE, 500kHz, VOUT 5V, TA = +25°C
FIGURE 8. EFFICIENCY, SYNCHRONOUS BUCK, PFM MODE,
VOUT 5V, TA = +25°C
5.200
5.200
5.150
5.150
5.100
IO = 0A
5.050
VOUT (V)
VOUT (V)
5.100
5.000
4.950
4.900
IO = 1A
4.850
4.800
5
10
15
12V VIN
4.950
36V VIN
6V VIN
4.850
30
35
40
4.800
0
0.5
1.0
1.5
LOAD CURRENT (A)
2.0
2.5
FIGURE 10. LOAD REGULATION, VOUT 5V, TA = +25°C
100
95
90
12V VIN
85
24V VIN
EFFICIENCY (%)
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
0.0
24V VIN
5.000
4.900
IO = 2A
20
25
INPUT VOLTAGE (V)
5.050
FIGURE 9. LINE REGULATION, VOUT 5V, TA = +25°C
EFFICIENCY (%)
2.5
LOAD CURRENT (A)
LOAD CURRENT (A)
36V VIN
6V VIN
6V VIN
12V VIN
80
36V VIN
75
24V VIN
70
65
60
55
50
45
0.5
1.0
1.5
2.0
LOAD CURRENT (A)
FIGURE 11. EFFICIENCY, SYNCHRONOUS BUCK, FORCED PWM
MODE, 500kHz, VOUT 3.3V, TA = +25°C
FN8631 Rev.4.00
Sep 28, 2020
2.5
40
0.1m
1m
10m
100m
LOAD CURRENT (A)
1.0
FIGURE 12. EFFICIENCY, SYNCHRONOUS BUCK, PFM MODE,
VOUT 3.3V, TA = +25°C
Page 10 of 24
2.5
ISL85403
Typical Performance Curves (Continued)
200
180
VIN = 12V
INPUT CURRENT (µA)
160
VOUT 2V/DIV
140
120
VIN = 24V
100
80
PHASE 20V/DIV
60
40
20
0
-50
-25
0
25
50
75
100
125
AMBIENT TEMPERATURE (°C)
FIGURE 13. INPUT QUIESCENT CURRENT UNDER NO LOAD,
PFM MODE, VOUT = 5V
2ms/DIV
FIGURE 14. SYNCHRONOUS BUCK MODE, VIN 36V, IO 2A,
ENABLE ON
VOUT 2V/DIV
VOUT 2V/DIV
PHASE 20V/DIV
PHASE 20V/DIV
2ms/DIV
FIGURE 15. SYNCHRONOUS BUCK MODE, VIN 36V, IO 2A,
ENABLE OFF
2ms/DIV
FIGURE 16. VIN 36V, PREBIASED START-UP
VOUT 100mV/DIV (5V OFFSET)
VOUT 20mV/DIV (5V OFFSET)
IOUT 1A/DIV
PHASE 20V/DIV
PHASE 20V/DIV
5µs/DIV
FIGURE 17. SYNCHRONOUS BUCK WITH FORCE PWM MODE,
VIN 36V, IO 2A
FN8631 Rev.4.00
Sep 28, 2020
1ms/DIV
FIGURE 18. VIN 24V, 0 TO 2A STEP LOAD, FORCE PWM MODE
Page 11 of 24
ISL85403
Typical Performance Curves (Continued)
VOUT 200mV/DIV (5V OFFSET)
VOUT 70mV/DIV (5V OFFSET)
VOUT 1V/DIV
LGATE 5V/DIV
LGATE 5V/DIV
IOUT 1A/DIV
PHASE 20V/DIV
PHASE 20V/DIV
100µs/DIV
1ms/DIV
FIGURE 19. VIN 24V, 80mA LOAD, PFM MODE
FIGURE 20. VIN 24V, 0 TO 2A STEP LOAD, PFM MODE
VOUT 10mV/DIV (5V OFFSET)
VOUT 10mV/DIV (5V OFFSET)
PHASE 5V/DIV
PHASE 10V/DIV
20µs/DIV
5µs/DIV
FIGURE 21. NON-SYNCHRONOUS BUCK, FORCE PWM MODE,
VIN 12V, NO LOAD
VOUT BUCK 100mV/DIV (5V OFFSET)
FIGURE 22. NON-SYNCHRONOUS BUCK, FORCE PWM MODE,
VIN 12V, 2A
VOUT BUCK 100mV/DIV (5V OFFSET)
VIN_BOOST_INPUT 5V/DIV
VIN_BOOST_INPUT 5V/DIV
PHASE_BOOST 10V/DIV
PHASE_BUCK 10V/DIV
PHASE_BOOST 10V/DIV
PHASE_BUCK 10V/DIV
20ms/DIV
FIGURE 23. BOOST BUCK MODE, BOOST INPUT STEP FROM 36V TO
3V, VOUT BUCK = 5V, IOUT_BUCK = 1A
FN8631 Rev.4.00
Sep 28, 2020
10ms/DIV
FIGURE 24. BOOST BUCK MODE, BOOST INPUT STEP FROM
3V TO 36V, VOUT BUCK = 5V, IOUT_BUCK = 1A
Page 12 of 24
ISL85403
Typical Performance Curves (Continued)
95
VOUT 5V/DIV
90
15V VIN
30V VIN
85
EFFICIENCY (%)
IL_BOOST 2A/DIV
PHASE_BOOST 20V/DIV
80
5V VIN
75
65
9V VIN
60
PHASE_BUCK 20V/DIV
6V VIN
70
55
50
0.0 0.2
0.4 0.6
0.8 1.0 1.2
10ms/DIV
1.4 1.6
1.8 2.0
2.2 2.4
LOAD CURRENT (A)
FIGURE 26. EFFICIENCY, BOOST BUCK, 500kHz, VOUT 12V,
TA = +25°C
FIGURE 25. BOOST BUCK MODE, VO = 9V, IO = 1.8A, BOOST INPUT
DROPS FROM 16V TO 9V DC
180
170
160
150
140
130
120
130
110
120
90
100
80
70
60
50
40
30
20
0
10
-10
-20
-50
100
-30
110
-40
UPPER MOSFET rDS(ON) (mΩ)
190
DIE TEMPERATURE (°C)
FIGURE 27. UPPER MOSFET rDS(ON) (mΩ) OVER-TEMPERATURE
FN8631 Rev.4.00
Sep 28, 2020
Page 13 of 24
ISL85403
Functional Description
PFM Mode Operation
Initially the ISL85403 continually monitors the voltage at the EN
pin. When the voltage on the EN pin exceeds its rising ON
threshold, the internal LDO starts up to build up VCC. Soft-starts
initiates after Power-on Reset (POR) circuits detect that VCC
voltage has exceeded the POR threshold.
Soft-Start
The soft-start (SS) ramp is built up in the external capacitor on
the SS pin, which is charged by an internal 5µA current source.
The SS ramp starts from 0V to a voltage above 0.8V. When SS
reaches 0.8V, the bandgap reference takes over and the IC
begins steady state operation. The soft-start time refers to the
duration that the SS pin ramps from 0V to 0.8V while the output
voltage ramps up with the same rate from 0V to the target
regulated voltage. The required capacitance at the SS pin can be
calculated from Equation 1.
C SS F = 6.5 t SS S
(EQ. 1)
The SS plays a vital role in Hiccup mode. The IC applies
cycle-by-cycle peak current limiting at over load conditions. When
a harsh condition occurs and the current in the upper side
MOSFET reaches the second overcurrent threshold, the SS pin is
pulled to ground and a dummy soft-start cycle is initiated. During
the dummy SS cycle, the current to charge soft-start capacitor is
reduced to 1/5 of its normal value. Thus, a dummy SS cycle
takes five times as long as the regular SS cycle. During the
dummy SS period, the control loop is disabled and there is no
PWM output. At the end of this cycle, it starts the normal SS.
Hiccup mode persists until the second overcurrent threshold is
no longer reached.
The ISL85403 is capable of starting up with prebiased output.
PWM Control
Pull the MODE pin to GND directly or with a resistor no greater
than 10kΩ to set the IC in Forced PWM mode. The ISL85403
employs the Peak Current mode PWM control for fast transient
response and cycle-by-cycle current limiting. See Figure 6 on
page 4.
The PWM operation is initialized by the clock from the oscillator.
The upper MOSFET is turned on by the clock at the beginning of a
PWM cycle and the current in the MOSFET starts to ramp up.
When the sum of the current sense signal and the slope
compensation signal reaches the error amplifier output voltage
level, the PWM comparator is triggered to shut down the PWM
logic to turn off the high-side MOSFET. The high-side MOSFET
stays off until the next clock signal comes for the next cycle.
The output voltage is sensed by a resistor divider from VOUT to
the FB pin. The difference between the FB voltage and the 0.8V
reference is amplified and compensated to generate the error
voltage signal at the COMP pin. Then the COMP pin signal is
compared with the current ramp signal to shut down the PWM.
FN8631 Rev.4.00
Sep 28, 2020
Pull the MODE pin HIGH (>2.5V) or leave the MODE pin floating to
set the IC to have PFM (Pulse Frequency Modulation) operation in
light load. In PFM mode, the switching frequency is dramatically
reduced to minimize the switching loss. The ISL85403 enters
PFM mode when the MOSFET peak current is lower than the
PWM/PFM boundary current threshold. The default threshold is
700mA when there is no programming resistor at the MODE pin.
The current threshold for the PWM/PFM boundary can be
programmed by connecting a resistor between the MODE pin and
ground. The MODE pin resistor value can be calculated using
Equation 2.
118500
R MODE = --------------------------------------I PFM + 0.2
(EQ. 2)
where IPFM is the required PWM/PFM boundary current
threshold and RMODE is the programming resistor. The usable
resistor value range to program the PFM current threshold is
150kΩ to 200kΩ. Do not use RMODE values outside this range.
For applications with output voltages higher than 5V and rated
load currents below 1A, Renesas recommends non-synchronous
operation by using a diode for the low-side device instead of a
MOSFET. If the rated load current is higher than 1A, synchronous
operation with a low-side MOSFET can be used but Forced PWM
mode must be enabled by connecting the MODE pin to GND.
200
190
RMODE (kΩ)
Initialization
180
170
160
150
0.3
0.4
0.5
IPFM (A)
0.6
0.7
FIGURE 28. RMODE vs IPFM
Synchronous and Non-Synchronous Buck
The ISL85403 supports both Synchronous and Non-Synchronous
buck operations.
In Synchronous buck configuration, add a 5.1k or smaller value
resistor from the LGATE to ground to avoid false turn-on of the
LGATE caused by coupling noise.
For a non-synchronous buck operation when a power diode is
used as the low-side power device, the LGATE driver can be
disabled with the LGATE connected to VCC (before IC start-up).
For non-synchronous buck operation, the phase node shows
oscillations after the high-side device turns off (as shown in
Figure 21 on page 12 - blue trace). This is normal due to the
oscillations among the parasitic capacitors at phase node and
output inductor. An RC snubber (200Ω and 2.2nF as typical) at
the phase node can reduce ringing.
Page 14 of 24
ISL85403
AUXVCC Switchover
Output Voltage
The ISL85403 has an auxiliary LDO integrated as shown in the
Figure 6. It is used to replace the internal MAIN LDO function
after the IC start-up. Figure 4 shows its basic application setup
with output voltage connected to AUXVCC. After IC soft-start is
done and the output voltage is built up to steady state, and when
the AUXVCC pin voltage is over the AUX LDO Switchover Rising
Threshold, the MAIN LDO is shut off and the AUXILIARY LDO is
activated to bias VCC. Because the AUXVCC pin voltage is lower
than the input voltage VIN, the internal LDO dropout voltage and
the consequent power loss are reduced. This feature brings
substantial efficiency improvements in light load range,
especially at high input voltage applications. Because both Vin
LDO and AUX LDO are regulated at 4.5V, it is better to use the
AUX LDO with input voltage at AUXVCC pin in the range between
4.5V to 20V.
The output voltage can be programmed down to 0.8V by a
resistor divider from VOUT to FB. For a buck converter, the
maximum achievable voltage is (VIN*DMAX - VDROP), where
VDROP is the voltage drop in the power path including mainly the
MOSFET rDS(ON) and inductor DCR. The maximum duty cycle
DMAX is (1 - fSW * tMIN(OFF)).
When the voltage at AUXVCC falls below the AUX LDO Switchover
Falling Threshold, the AUXILIARY LDO is shut off and the MAIN LDO
is reactivated to bias VCC. At the OV/UV fault events, the IC also
switches back over from AUXILIARY LDO to MAIN LDO.
The AUXVCC switchover function is offered in buck configuration.
It is not offered in boost configuration when the AUXVCC pin is
used to monitor the boost output voltage for OVP.
Input Voltage
With the part switching, the operating ISL85403 input voltage
must be under 40V. This recommendation allows for short
voltage ringing spikes (within a couple of ns time range) due to
the part switching while not exceeding the 44V, as stated in the
“Absolute Maximum Ratings” on page 7.
The lowest IC operating input voltage (VIN pin) depends on the
VCC voltage and the Rising and Falling VCC POR Threshold in
Electrical Specifications table on page 8. At IC start-up when VCC
is just over the rising POR threshold, there is no switching before
soft-start. Therefore, the IC minimum start-up voltage on the VIN
pin is 3.05V (MAX of Rising VCC POR). When the soft-start is
initiated, the regulator is switching and the dropout voltage
across the internal LDO increases due to driving current. Thus,
the IC VIN pin shutdown voltage is related to driving current and
VCC POR falling threshold. The internal upper side MOSFET has a
typical 10nC gate drive. For a typical example of synchronous
buck with 4nC lower MOSFET gate drive and 500kHz switching
frequency, the driving current is 7mA total, causing a 70mV drop
across internal LDO under 3V VIN. Then the IC shutdown voltage
on the VIN pin is 2.87V (2.8V + 0.07V). In practical design, extra
room should be taken into account with concern to voltage
spikes at VIN.
In boost buck configuration, the input voltage range can be
expanded further down to 2.5V or lower depending on the boost
stage voltage drop upon maximum duty cycle. Because the boost
output voltage is connected to the VIN pin as the buck inputs,
after the IC starts up, the IC keeps operating and switching as
long as the boost output voltage can keep the VCC voltage higher
than the falling threshold. See “2-Stage Boost Buck Converter
Operation” on page 16 for more details.
FN8631 Rev.4.00
Sep 28, 2020
For applications with output voltages higher than 5V and rated
load currents below 1A, Renesas recommends use
non-synchronous operation by using a diode for the low-side
device instead of a MOSFET. If the rated load current is higher
than 1A, synchronous operation with a low-side MOSFET can be
used but Forced PWM mode must be enabled by connecting the
MODE pin to GND.
Output Current
With the high-side MOSFET integrated, the maximum output
current the ISL85403 can support is decided by the package and
many operating conditions including input voltage, output
voltage, duty cycle, switching frequency and temperature the die
temperature should not exceed +125°C with the power loss
dissipated inside of the IC.
Note that more temperature rise is expected at higher ambient
temperature due to more conduction loss caused by rDS(ON)
increase.
The die temperature is equal to the sum of the ambient
temperature and the temperature rise resulting from the power
dissipated by the IC package with a certain junction to ambient
thermal impedance JA. The power dissipated in the IC is related
to the MOSFET switching loss, conduction loss, and the internal
LDO loss. Besides the load, these losses are also related to input
voltage, output voltage, duty cycle, switching frequency, and
temperature. With the exposed pad at the bottom, the heat of
the IC mainly goes through the bottom pad and JA is greatly
reduced. The JA is highly related to layout and air flow
conditions. In layout, multiple vias (≥9) are strongly
recommended in the IC bottom pad. The bottom pad with its vias
should be placed in the ground copper plane with an area as
large as possible across multiple layers. The JA can be reduced
further with air flow. See Figures 12 and 13 for the thermal
performance with 100 CFM air flow.
For applications with high output current and bad operating
conditions (such as compact board size or high ambient
temperature), synchronous buck is highly recommended
because the external low-side MOSFET generates less heat than
the external low-side power diode. This helps to reduce PCB
temperature rise around the ISL85403 and reduce junction
temperature rise.
Page 15 of 24
ISL85403
2-Stage Boost Buck Converter Operation
The Figure 5 on page 3, shows the boost function circuits.
Schematic (a) shows a boost working as a pre-stage to provide
input to the following Buck stage. This is for applications when
the input voltage could drop to a very low voltage in some
constants (for example, in some battery powered systems),
causing the output voltage to drop out of regulation. The boost
converter can be enabled to boost the input voltage up to keep
the output voltage in regulation. When system input voltage
recovers back to normal, the boost stage is disabled while only
the buck stage is switching.
The EXT_BOOST pin is used to set Boost mode and monitor the
boost input voltage. At IC start-up before soft-start, the controller
is latched in Boost mode when the voltage is at or above 200mV;
it latches in synchronous Buck mode if the voltage on the
EXT_BOOST pin is below 200mV. In Boost mode, the low-side
driver output PWM has the same PWM signal as the buck
regulator.
In Boost mode, the EXT_BOOST pin is used to monitor boost input
voltage to turn on and turn off the boost PWM. The AUXVCC pin is
used to monitor the boost output voltage to turn on and turn off
the boost PWM.
Referring to Figure 29, a resistor divider from the boost input
voltage to the EXT_BOOST pin is used to detect the boost input
voltage. When the voltage on the EXT_BOOST pin is below 0.8V,
the boost PWM is enabled with a fixed 500µs soft-start and the
boost duty cycle increases linearly from tMIN(ON)*Fs to ~50%. A
3µA sinking current is enabled at the EXT_BOOST pin for
hysteresis purposes. When the voltage on the EXT_BOOST pin
recovers to be above 0.8V, boost PWM is disabled immediately.
Use Equation 3 to calculate the upper resistor RUP (R1 in
Figure 29) for a required hysteresis VHYS at the boost input
voltage.
V HYS
R UP M = --------------------3 A
(EQ. 3)
Use Equation 4 to calculate the lower resistor RLOW (R2 in
Figure 29) according to a required boost enable threshold.
R UP 0.8
R LOW = --------------------------------------VFTH – 0.8
(EQ. 4)
where VFTH is the required falling threshold on boost input
voltage to turn on the boost, 3µA is the hysteresis current, and
0.8V is the reference voltage to be compared with.
Note that the boost start-up threshold has to be selected in a way
that the buck is operating correctly and kept in close loop
regulation before boost start-up. Otherwise, a large inrush
current at boost start-up can occur at boost input due to the buck
open loop saturation. Set the boost start-up input voltage
threshold high enough to cover the boost inductor and diode DC
voltage drop, and the buck’s maximum duty cycle and voltage
conduction drop. This ensures the buck does not reach maximum
duty cycle before boost start-up.
Similarly, a resistor divider from the boost output voltage to the
AUXVCC pin is used to detect the boost output voltage. When the
voltage on the AUXVCC pin is below 0.8V, the boost PWM is
enabled with a fixed 500µs soft-start and a 3µA sinking current
is enabled at AUXVCC pin for hysteresis purposes. When the
voltage on the AUXVCC pin recovers to be above 0.8V, the boost
PWM is disabled immediately. Use Equation 3 to calculate the
upper resistor RUP (R3 in Figure 29) according to a required
hysteresis VHY at boost output voltage. Use Equation 4 to
calculate the lower resistor RLOW (R4 in Figure 29) according to a
required boost enable threshold at boost output.
Assuming VBAT is the boost input voltage, VOUT_BST is the boost
output voltage and VOUT is the buck output voltage, the steady
state DC transfer function are:
1
V OUTBST = ------------------ V BAT
1–D
(EQ. 5)
D
V OUT = D V OUTBST = ------------------ V BAT
1–D
(EQ. 6)
BATTERY
VOUT_BST
+
R1
+
EXT_BOOST
0.8V
R2
I_HYS = 3µA
LOGIC
R3
R4
LGATE
AUXVCC
0.8V
PWM
LGATE
DRIVE
I_HYS = 3µA
FIGURE 29. BOOST CONVERTER CONTROL
FN8631 Rev.4.00
Sep 28, 2020
Page 16 of 24
ISL85403
V OUTBST = V BAT + V OUT
(EQ. 7)
After the IC starts up, the boost buck converters can keep
working when the battery voltage drops extremely low because
the IC’s bias (VCC) LDO is powered by the boost output. For
example, if a 3.3V output application battery drops to 2V and the
VIN pin voltage is powered by the 5.2V boost output voltage
(Equation 7), the VIN pin (buck input) still sees 5.2V to keep the
IC working.
Note that in the previously mentioned case, the boost input
current could be high because the input voltage is very low
(VIN*IIN = VOUT*IOUT/Efficiency). For the design to achieve the
low input operation with full load, the inductor and MOSFET have
to be selected with enough current ratings to handle the high
current appearing at boost input. The boost inductor current is
the same with the boost input current, which can be estimated as
Equation 8, where POUT is the output power, VBAT is the boost input
voltage, and EFF is the estimated efficiency of the whole boost and
buck stages.
P OUT
IL IN = ------------------------------------------V BAT EFF
(EQ. 8)
Based on the same concerns of boost input current, the start-up
sequence must follow the rule that the IC is enabled after the
boost input voltage rise above a certain level. The shutdown
sequence must follow the rule that the IC is disabled first before
the boost input power source is turned off. In Boost mode
applications where there is no external control signal to
enable/disable the IC, an external input UVLO circuit must be
implemented for the start-up and shutdown sequence.
Non-Inverting Single Inductor Buck Boost
Converter Operation
In Figure 5 on page 3, schematic (b) shows a non-inverting single
inductor buck boost configuration. The recommended setting is
to use 1MΩ and 130kΩ resistor dividers (as shown in TYP
Schematic III b) connecting from VCC to both the EXT_BOOST and
AUXVCC pins (the EXT_BOOST and AUXVCC pins are directly
connected). In this way, the EXT_BOOST pin voltage is a fixed
voltage of 0.52V that is higher than the Boost mode detection
threshold of 0.2V to set the IC in Boost mode and lower than the
boost switching threshold of 800mV to have boost being
constantly switching (during and after soft-start).
Similar to 2-stage boost Buck mode, LGATE switches ON the
same phase that the upper FETs switch ON, meaning both upper
and lower side FETs are ON and OFF at the same time with the
same duty cycle. When both FETs are ON, input voltage charges
the inductor current ramping up for duration of DT; when both
FETs are OFF, the inductor current is free wheeling through the
two power diodes to output and output voltage discharge the
inductor current ramping down for (1-D)T (in CCM mode). The
steady state DC transfer function is:
D
V OUT = ------------------ V IN
1–D
FN8631 Rev.4.00
Sep 28, 2020
(EQ. 9)
where VIN is the input voltage, VOUT is the buck boost output
voltage, and D is duty cycle.
Use Equation 10 to calculate the inductor DC current as below:
1
IL DC = ------------------ I OUT
1–D
(EQ. 10)
where ILDC is the inductor DC current and IOUT is the output DC
current.
Equation 10 shows the inductor current is charging output only
during (1-D)T, which means inductor current has larger DC
current than output load current. Thus, for this IC with high-side
FET integrated, the non-inverting buck boost configuration has
less load current capability compared with buck and 2-stage
boost buck configurations. Its load current capability depends
mainly on the duty cycle and inductor current.
Inductor ripple current can be calculated using Equation 11:
V OUT 1 – D T
IL RIPPLE = ----------------------------------------------------L
(EQ. 11)
The inductor peak current is:
1
IL PEAK = IL DC + ---- IL RIPPLE
2
(EQ. 12)
In power stage DC calculations, use Equation 9 to calculate D,
then use Equation 10 to calculate ILDC. D and ILDC are useful for
estimating the high-side FET’s power losses and checking if the
part can meet the load current requirements.
Oscillator and Synchronization
The oscillator has a default frequency of 500kHz with the FS pin
connected to VCC or ground, or floating. The frequency can be
programmed to any frequency between 200kHz and 2.2MHz with
a resistor from the FS pin to GND.
145000 – 16 f SW kHz
R FS k = ------------------------------------------------------------------------------------------f SW [kHz]
(EQ. 13)
1200
1000
800
RFS (kΩ)
From Equations 5 and 6, Equation 7 can be derived to estimate
the steady state boost output voltage asa function of VBAT and
VOUT:
600
400
200
0
0
500
1000
1500
fSW (kHz)
2000
2500
FIGURE 30. RFS vs FREQUENCY
The SYNC pin is bidirectional and it outputs the IC’s default or
programmed local clock signal when it is free running. The IC
locks to an external clock injected to the SYNC pin (external clock
frequency is recommended to be 10% higher than the free
running frequency). The delay from the rising edge of the external
clock signal to the PHASE rising edge is half of the free running
switching period pulse 220ns, (0.5tSW+220ns). The maximum
Page 17 of 24
ISL85403
external clock frequency is recommended to be 1.6 times of the
free running frequency.
is attempted again. The IOC2 offers a robust and reliable
protection against the worst case conditions.
When the part enters PFM pulse skipping mode, the
synchronization function is shut off and no clock signal is output
in SYNC pin.
The frequency foldback is implemented on the ISL85403. When
overcurrent limiting, the switching frequency is reduced to be
proportional to the output voltage to keep the inductor current
under the limit threshold during an overload condition. The low
frequency limit under frequency foldback operation is 40kHz.
With the SYNC pins connected together, multiple ISL85403s can
be synchronized. The slave ICs automatically have 180° phase
shift with respect to the master IC.
The PGOOD pin is the output of an open-drain transistor (See
Figure 6 on page 4). An external resistor is required to be pulled
up to VCC for proper PGOOD function. At start-up, PGOOD is
turned HIGH (internal PGOOD open-drain transistor is turned off)
with 128 cycles delay after soft-start is finished (soft-start ramp
reaches 1.02V) and the FB voltage is within the OV/UV window
(90%REF < FB < 110%REF).
At normal operation, PGOOD is pulled low with one cycle
(minimum) and six cycles (maximum) delay if any of the OV
(110%) or UV (90%) comparators are tripped. PGOOD is released
HIGH with 128 cycles delay after FB recovers to be within the
OV/UV window (90%REF < FB < 110%REF). When EN is pulled
low or VCC is below POR, PGOOD is pulled low with no delay.
If the PGOOD pin is pulled up by the external bias supply instead
of VCC by itself, when the part is disabled, the internal PGOOD
open-drain transistor is off, the external bias supply can charge
PGOOD pin HIGH. This is known as false PGOOD reporting. At
start-up when VCC rises from 0V, PGOOD is pulled low when VCC
reaches 1V. After EN is pulled low and VCC is falling, the PGOOD
internal open-drain transistor opens with high impedance when
VCC falls below 1V. The time between when EN is pulled low and
PGOOD OPEN depends on the VCC falling time to 1V.
Overcurrent Protection
The overcurrent function protects against any overload condition
and output short at worst case by monitoring the current flowing
through the upper MOSFET.
There are two current limiting thresholds: IOC1 and IOC2. IOC1
limits the high-side MOSFET peak current cycle-by-cycle. The
current limit threshold is set at 3.6A (default) with the ILIMIT pin
connected to GND or VCC, or left open. The current limit threshold
can also be programmed by a resistor, RLIM, at the ILIMIT pin to
ground. Use Equation 14 to calculate the resistor.
(EQ. 14)
Note that IOC1 is higher with lower RLIM. The resistor value range
to program the OC1 peak current threshold is 40kΩ to 330kΩ.
RLIM values out of this range are not recommended.
The second current protection threshold, IOC2, is 15% higher
than IOC1. Instantly after the high-side MOSFET current reaches
IOC2, the PWM is shut off after a two-cycle delay and the IC
enters Hiccup mode. In Hiccup mode, the PWM is disabled for a
dummy soft-start cycle that is equal to five regular soft-start
periods. After this dummy soft-start cycle, the true soft-start cycle
FN8631 Rev.4.00
Sep 28, 2020
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0
IOC1 (A)
FIGURE 31. RLIM vs IOC1
Overvoltage Protection
If the voltage detected on the FB pin is over 110% or 120% of
reference, the high-side and low-side drivers shut down
immediately and stay off until the FB voltage drops to 0.8V.
When the FB voltage drops to 0.8V, the drivers are released ON.
110% OVP is off during soft-start and active after soft-start is
complete. 120% OVP is active during and after soft-start.
Thermal Protection
The ISL85403 PWM is disabled if the junction temperature
reaches +160°C. There is +20°C hysteresis for OTP. The part
restarts after the junction temperature drops below +140°C.
Fault Protection
300000
R LIM = -----------------------------------------------------I OC A + 0.018
RLIM (kΩ)
PGOOD
320
300
280
260
240
220
200
180
160
140
120
100
80
60
40
Component Selections
The ISL85403 iSim model can be used to simulate for both the
time domain behaviors and small signal loop stability analysis.
Output Capacitors - Buck
An output capacitor is required to filter the inductor current.
Output ripple voltage and transient response are two critical
factors when considering output capacitance choice. The current
mode control loop allows for the usage of low ESR ceramic
capacitors and thus smaller board layout. Electrolytic and
polymer capacitors can also be used.
Additional consideration applies to ceramic capacitors. While
they offer excellent overall performance and reliability, the actual
in-circuit capacitance must be considered. Ceramic capacitors
are rated using large peak-to-peak voltage swings with no DC
bias. In DC/DC converter applications, these conditions do not
reflect reality. As a result, the actual capacitance may be
considerably lower than the advertised value. Consult the
manufacturer’s datasheet to determine the actual in-application
capacitance. Most manufacturers publish capacitance vs DC bias
Page 18 of 24
ISL85403
so this effect can be easily accommodated. The effects of AC
voltage are not frequently published, but an assumption of ~20%
further reduction generally suffices. The result of these
considerations can easily result in an effective capacitance 50%
lower than the rated value. Nonetheless, ceramic capacitors are
a very good choice in many applications due to their reliability
and extremely low ESR.
In buck topology, the following equations allow calculation of the
required capacitance to meet a required ripple voltage level.
Additional capacitance may be used.
For the ceramic capacitors (low ESR):
I
V OUTripple = ------------------------------------------8 f SW C OUT
(EQ. 15)
where I is the inductor’s peak-to-peak ripple current, fSW is the
switching frequency, and COUT is the output capacitor.
If using electrolytic capacitors then:
V OUTripple = I*ESR
(EQ. 16)
Regarding transient response needs, a good starting point is to
determine the allowable overshoot in VOUT if the load is suddenly
removed. In this case, energy stored in the inductor is transferred
to COUT, causing its voltage to rise. After calculating capacitance
required for both ripple and transient needs, choose the larger of
the calculated values. Equation 17 determines the required
output capacitor value to achieve a wanted overshoot relative to
the regulated voltage.
I OUT 2 L
C OUT = ----------------------------------------------------------------------------------------------V OUT 2 V OUTMAX V OUT 2 – 1
(EQ. 17)
where VOUTMAX/VOUT is the relative maximum overshoot
allowed during the removal of the load.
Input Capacitors - Buck
Depending on the system input power rail conditions, the
aluminum electrolytic type capacitor is normally needed to
provide the stable input voltage. Thus, restrict the switching
frequency pulse current in a small area over the input traces for
better EMC performance. The input capacitor should be able to
handle the RMS current from the switching power devices.
Ceramic capacitors must be used at the VIN pin of the IC and
multiple capacitors including 1µF and 0.1µF are recommended.
Place these capacitors as close as possible to the IC.
Output Inductor - Buck
The inductor value determines the converter’s ripple current.
Choosing an inductor current requires a somewhat arbitrary
choice of ripple current, I. A reasonable starting point is 30% to
40% of total load current. The inductor value is calculated using
Equation 18:
V IN – V OUT V OUT
L = -------------------------------- ---------------V IN
f SW I
The inductor current rating should not saturate in overcurrent
conditions.
Low-Side Power MOSFET
In a synchronous buck application, a power N MOSFET is needed
as the synchronous low-side MOSFET and a good one should
have low Qgd, low rDS(ON), and small Rg (Rg_typ < 1.5Ω
recommended). The Vgth_min is recommended to be 1.2V or
higher. A good example is SQS462EN.
Add a 5.1k or smaller value resistor to connect LGATE to ground
to avoid false turn-on of the LGATE caused by coupling noise.
Output Voltage Feedback Resistor Divider
The output voltage can be programmed down to 0.8V by a
resistor divider from VOUT to FB according to Equation 19.
R UP
V OUT = 0.8 1 + ----------------
R LOW
(EQ. 19)
In an application requiring low input quiescent current, use large
resistors for the divider. Generally, a resistor value of 10k to 300k
can be used for the upper resistor.
Boost Inductor (2-Stage Boost Buck)
Besides the need to sustain the current ripple to be within a
certain range (30% to 50%), the boost inductor current at its
soft-start is a more important perspective to be considered in
selection of the boost inductor. Each time the boost starts up,
there is a fixed 500µs soft-start time when the duty cycle
increases linearly from tMIN(ON)*fSW to ~50%. Before and after
boost start-up, the boost output voltage jumps from VIN_BOOST to
voltage (VIN_BOOST + VOUT_BUCK). The design target in boost
soft-start is to ensure the boost input current is sustained to a
minimum but is able to charge the boost output voltage to have a
voltage step equaling to VOUT_BUCK. A large inductor prevents
the inductor current from increasing and is not high enough to be
able to charge the output capacitor to the final steady state value
(VIN_BOOST + VOUT_BUCK) within 500µs. A 6.8µH inductor is a
good starting point for its selection in design. Check the boost
inductor current at start-up with an oscilloscope to ensure it is
under an acceptable range. It is suggested to run the iSim model
(use the ISL85403 iSim model) to assist in the proper inductor
value.
Boost Output Capacitor (2-Stage Boost Buck)
Based on the same theory in boost start-up, a large capacitor at
boost output causes high inrush current at boost PWM start-up.
22µF is a good choice for applications with a buck output voltage
less than 10V. Also some minimum amount of capacitance has
to be used in boost output to keep the system stable. Renesas
recommends running the iSim model to assist in designing the
proper capacitor value.
(EQ. 18)
Increasing the value of inductance reduces the ripple current and
therefore the ripple voltage. However, the larger inductance value
may reduce the converter’s response time to a load transient.
FN8631 Rev.4.00
Sep 28, 2020
Page 19 of 24
ISL85403
Loop Compensation Design Buck
Power Stage Transfer Functions
Transfer function F1(S) from control to output voltage is:
The ISL85403 uses constant frequency peak current mode
control architecture to achieve fast loop transient response. An
accurate current sensing pilot device in parallel with the upper
MOSFET is used for peak current control signal and overcurrent
protection. The inductor is not considered a state variable
because its peak current is constant and the system becomes a
single order system. It is much easier to design the compensator
to stabilize the loop compared with voltage mode control. Peak
current mode control has an inherent input voltage feed-forward
function to achieve good line regulation. Figure 32 shows the
small signal model of a buck regulator.
+
^
i in
^
Vin
ILd^
1:D
^
iL
LP
Vin d^
+
GAIN (VLOOP (S(fi))
RT
(EQ. 23)
where:,
C
1
1
esr = --------------- ,Q p R o ------o- , o = ------------------Rc Co
LP
LP Co
Transfer function F2(S) from control to inductor current is given
by Equation 24:
S
1 + -----ˆI
z
V in
o
F 2 S = ---- = ------------------------- --------------------------------------R o + R LP 2
dˆ
S
S
------- + --------------- + 1
2 Q
o p
o
^
vo
RLP
S1 + ---------- esr
vˆ o
F 1 S = ------ = V in --------------------------------------2
dˆ
S
S
------- + --------------- + 1
2 Q
o p
o
Rc
(EQ. 24)
1
where z = -------------Ro Co .
Ro
Co
Current loop gain Ti(S) is expressed as Equation 25:
Ti(S)
d^
(EQ. 25)
(S)
Fm
+
T i S = R t F m F 2 S H e S
The voltage loop gain with open current loop is expressed in
Equation 26:
Tv (S)
He(S)
v^comp
T v S = KF m F 1 S A v S
-Av(S)
FIGURE 32. SMALL SIGNAL MODEL OF BUCK REGULATOR
PWM Comparator Gain Fm
The PWM comparator gain, Fm, for peak current mode control is
given by Equation 20:
1
dˆ
F m = ----------------- = ------------------------------- S e + S n T s
vˆ comp
(EQ. 20)
where Se is the slew rate of the slope compensation and Sn is
given by Equation 21:
V in – V o
S n = R t --------------------L
(EQ. 21)
P
where Rt is the gain of the current amplifier.
Current Sampling Transfer Function He(S)
The Voltage loop gain with current loop closed is given by
Equation 27:
Tv S
L v S = ----------------------1 + Ti S
2
where Qn and n are given by
(EQ. 27)
If Ti(S)>>1, then Equation 27 can be simplified as Equation 28:
S
1 + ----------- esr A v S
R o + R LP
1
L v S = ------------------------- ---------------------- ---------------- , p --------------S He S
Rt
Ro Co
1 + ------p
(EQ. 28)
Equation 28 shows that the system is a single order system.
Therefore, a simple type II compensator can be easily used to
stabilize the system. A type III compensator is needed to expand
the bandwidth for current mode control in some cases.
A compensator with two zeros and one pole is recommended for
this part, as shown in Figure 33.
In a current loop, the current signal is sampled every switching
cycle. It has the following transfer function in Equation 22:
S
S
H e S = ------- + --------------- + 1
2 Q
n n
n
(EQ. 26)
R2
C1
R3
C3
(EQ. 22)
VO
VCOMP
2
Q n = – --- n = f SW
R1
VREF
RBIAS
FIGURE 33. TYPE III COMPENSATOR
FN8631 Rev.4.00
Sep 28, 2020
Page 20 of 24
ISL85403
Its transfer function is expressed as Equation 29:
S
S
1 + ------------ 1 + -------------
cz1
cz2
vˆ comp
1
- = ------------------- --------------------------------------------------------A v S = ---------------SR 1 C
S
vˆ O
1 + --------1
(EQ. 29)
Example: VIN = 12V, Vo = 5V, Io = 2A, fSW = 500kHz,
Co = 60µF/3mΩ, L = 10µH, Rt = 0.20V/A, fc = 50kHz,
R1 = 105k, RBIAS = 20kΩ.
where:
Select the crossover frequency to be 35kHz. Because the
output capacitors are all ceramic, use Equations 33 and 34
to derive R3 to be 20k and C3 to be 470pF.
1
1
1
cz1 = --------------- , cz2 = ---------------------------------- cp = --------------R2 C1
R3 C3
R 1 + R 3 C 3
Then use Equations 35 and 36 to calculate C1 to be 180pF
and R2 to be 12.7k. Select 150pF for C1 and 15k for R2.
cp
There is approximately 30pF parasitic capacitance between
COMP to FB pins that contributes to a high frequency pole. Any
extra external capacitor is not recommended between COMP and
FB.
Compensator design goal:
1
1
- f
Loop bandwidth fc: --4- to ----10 SW
Gain margin: >10dB
Figure 34 shows the simulated Bode plot of the loop. It has
26kHz loop bandwidth with 70° phase margin and -28 dB gain
margin.
Phase margin: 45°
The compensator design procedure is as follows:
1. Position CZ2 and CP to derive R3 and C3.
Put the compensator zero CZ2 at (1 to 3)/(RoCo)
(EQ. 30)
3
cz2 = --------------Ro Co
Put the compensator pole CP at ESR zero or 0.35 to 0.5
times of switching frequency, whichever is lower. In an
all-ceramic-cap design, the ESR zero is normally higher than
half of the switching frequency. R3 and C3 can be derived as
follows:
1
Case A: ESR zero ---------------------- less than (0.35 to 0.5)fSW
Note in applications where the PFM mode is required especially
when type III compensation network is used, the value of the
capacitor between the COMP pin and the FB pin (not the
capacitor in series with the resistor between COMP and FB)
should be minimal to reduce the noise coupling for proper PFM
operation. No external capacitor between COMP and FB is
recommended for PFM applications.
In PFM mode operations, an RC filter from FB to ground (R in
series with C, connecting from FB to ground) can help reduce the
noise effects injected to FB pin. The recommended values for the
filter are 499Ω to 1k for the R and 470pF for the C.
2R c C o
R o C o – 3R c C o
C 3 = --------------------------------------3R 1
(EQ. 31)
3R c R 1
R 3 = ----------------------R o – 3R c
(EQ. 32)
1
Case B: ESR zero ---------------------- larger than (0.35 to 0.5)fSW
2R c C o
0.33R o C o f SW – 0.46
C 3 = ------------------------------------------------------f SW R
(EQ. 33)
R1
R 3 = ----------------------------------------0.73R o C o f s – 1
(EQ. 34)
1
2. Derive R2 and C1.
The loop gain Lv(S) at crossover frequency of fc has unity
gain. Therefore, C1 is determined by Equation 35.
R 1 + R 3 C 3
C 1 = --------------------------------2f c R t R 1 C
(EQ. 35)
o
The compensator zero CZ1 can boost the phase margin and
bandwidth. To put CZ1 at two times of crossover frequency
fc is a good starting point. It can be adjusted according to the
specific design. R1 can be derived from Equation 36.
1
R 2 = -------------------4f c C 1
FN8631 Rev.4.00
Sep 28, 2020
(EQ. 36)
Page 21 of 24
ISL85403
Loop Compensation Design for
2-Stage Boost Buck and
Single-Stage Buck Boost
For 2-stage boost buck and single-stage non-inverting buck boost
configurations, it is highly recommended to use the iSim model
to evaluate the loop bandwidth and phase margin.
Layout Suggestions
1. Place the input ceramic capacitors as close as possible to the
IC VIN pin and power ground connecting to the power MOSFET
or diode. Keep this loop (input ceramic capacitor, IC VIN pin
and MOSFET/diode) as small as possible to achieve the
fewest voltage spikes induced by the trace parasitic
inductance.
2. Place the input aluminum capacitors as close as possible to
the IC VIN pin.
80
60
3. Keep the phase node copper area small but large enough to
handle the load current.
40
4. Place the output ceramic and aluminum capacitors close to
the power stage components as well.
20
dB
5. Place vias (≥9) in the bottom pad of the IC. Place the bottom
pad in the ground copper plane with an area as large as
possible in multiple layers to effectively reduce the thermal
impedance.
0
-20
6. Place the 4.7µF ceramic decoupling capacitor at the VCC pin
(the closest place to the IC). Put multiple vias (≥3) close to the
ground pad of this capacitor.
-40
-60
100
1•103
1•104
1•105
1•106
7. Keep the bootstrap capacitor close to the IC.
8. Keep the LGATE drive trace as short as possible and try to
avoid using vias in the LGATE drive path to achieve the lowest
impedance.
FREQUENCY (Hz)
180
160
9. Place the positive voltage sense trace close to the place that
is strictly regulated.
140
10. Place all the peripheral control components close to the IC.
DEGREE (°)
120
100
80
60
40
20
0
100
1•103
1•104
1•105
1•106
FIGURE 35. PCB VIA PATTERN
FREQUENCY (Hz)
FIGURE 34. SIMULATED LOOP BODE PLOT
FN8631 Rev.4.00
Sep 28, 2020
Page 22 of 24
ISL85403
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have
the latest revision.
DATE
REVISION
Sep 28, 2020
4.00
Updated the AUXVCC pin description by changing 3V to 4.5V.
Updated the AUXVCC Input Voltage Range minimum specification from 3V to 4.5V.
Updated Recommended Operating Condition for AUXVCC.
Updated AUXVCC Switchover section.
Aug 8, 2019
3.00
Updated first sentence in PWM Control section on page 14.
Updated second paragraph in PFM Mode Operation section on page 14.
Mar 11, 2019
2.00
Updated Releated literature section.
Updated order of datasheet.
Updated ordering information table by updating Note 1, adding tape and reel versions and column.
Updated PFM Mode Operation section by adding last paragraph.
Updated Output Voltage section by adding last paragraph.
Removed About Intersil section.
Updated Disclaimer.
March 13, 2015
1.00
Changed the max input Voltage (Vin) from 36V to 40V on the following pages:
On page 1: In the description and features sections
On page 6: VIN pin description
On page 7: Recommended operating conditions for VIN
On page 15: Application description for the “Input Voltage” section
On page 1, added “Related Literature” section.
On page 5, added ISL85403EVAL2Z to the Ordering Information table.
Replaced Figures 9 and 10.
Removed Figures 10 and 11 and the references on page 15.
March 12, 2014
0.00
Initial Release
FN8631 Rev.4.00
Sep 28, 2020
CHANGE
Page 23 of 24
ISL85403
Package Outline Drawing
For the most recent package outline drawing, see L20.4x4C.
L20.4x4C
20 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 0, 11/06
4X
4.00
2.0
16X 0.50
A
B
16
6
PIN #1 INDEX AREA
20
6
PIN 1
INDEX AREA
1
4.00
15
2 .70 ± 0 . 15
11
(4X)
5
0.15
6
10
0.10 M C A B
4 20X 0.25 +0.05 / -0.07
20X 0.4 ± 0.10
TOP VIEW
BOTTOM VIEW
SEE DETAIL "X"
0.10 C
0 . 90 ± 0 . 1
C
BASE PLANE
( 3. 8 TYP )
(
2. 70 )
SEATING PLANE
0.08 C
( 20X 0 . 5 )
SIDE VIEW
( 20X 0 . 25 )
C
0 . 2 REF
5
( 20X 0 . 6)
0 . 00 MIN.
0 . 05 MAX.
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
FN8631 Rev.4.00
Sep 28, 2020
Page 24 of 24
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(Rev.1.0 Mar 2020)
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