DATASHEET
ISL854102
FN8870
Rev.1.00
Mar 15, 2019
Wide VIN 1.2A Synchronous Buck Regulator
The ISL854102 is a 1.2A synchronous buck regulator with an
input range of 3V to 40V. It provides an easy-to-use, high
efficiency, low BOM count solution for a variety of applications.
Features
The ISL854102 integrates both high-side and low-side NMOS
FETs and features a PFM mode for improved efficiency at light
loads. This feature can be disabled if a forced PWM mode is
needed. The ISL854102 switches at a default frequency of
500kHz; however, it can also be programmed using an
external resistor from 300kHz to 2MHz. The ISL854102 has
the ability to use internal or external compensation. By
integrating both NMOS devices and providing internal
configuration options, minimal external components are
required, which reduces the BOM count and design complexity.
• Synchronous operation for high efficiency
With a wide VIN range and reduced BOM, the ISL854102
provides an easy to implement design solution for a variety of
applications while giving superior performance. The
ISL854102 provides a very robust design for high-voltage
industrial applications and an efficient solution for battery
powered applications.
• Minimal external components required
• Wide input voltage range: 3V to 40V
• No compensation required
• Integrated high-side and low-side NMOS devices
• Selectable PFM or forced PWM mode at light loads
• Internal fixed frequency (500kHz) or adjustable switching
frequency (300kHz to 2MHz)
• Continuous output current up to 1.2A
• Internal or external soft-start
• Power-good and enable functions available
Applications
• Industrial control
• Medical devices
The ISL854102 is available in a small Pb-free 4mmx3mm DFN
plastic package with a full-range industrial temperature of
-40°C to +125°C.
• Portable instrumentation
• Distributed power supplies
• Cloud infrastructure
Related Literature
For a full list of related documents, visit our website:
• ISL854102 device page
100
95
90
2
CBOOT
100nF
VOUT
COUT
10µF
SYNC
COMP
3 BOOT
FB
4 VIN
CVIN
10µF
5 PHASE
L1
22µH
6
PGND
85
FS 12
GND
11
R2
10
9
R3
CFB
EFFICIENCY (%)
1 SS
80
75
70
65
VIN=12V
PG
60
VIN=15V
EN
55
VIN=24V
VCC
CVCC
1µF
50
INTERNAL DEFAULT PARAMETER SELECTION
0
0.1
0.2 0.3 0.4 0.5 0.6 0.7
0.8
0.9
1
1.1
1.2
OUTPUT LOAD (A)
FIGURE 1. TYPICAL APPLICATION
FN8870 Rev.1.00
Mar 15, 2019
FIGURE 2. EFFICIENCY vs LOAD, PFM, VOUT = 5V, L1 = 22µH
Page 1 of 21
ISL854102
Table of Contents
Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Typical Application Schematics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Efficiency Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Soft-Start. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-Good . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PWM Control Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Light Load Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Voltage Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13
13
13
13
13
14
14
Protection Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overcurrent Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Negative Current Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Over-Temperature Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Boot Undervoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14
15
15
15
15
Application Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Simplifying the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Minimum On/Off-Time Limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Synchronization Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Inductor Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Buck Regulator Output Capacitor Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Loop Compensation Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15
15
15
15
16
16
16
16
Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
FN8870 Rev.1.00
Mar 15, 2019
Page 2 of 21
ISL854102
Pin Configuration
12 LD 4x3 DFN
TOP VIEW
12 FS
SS 1
11 COMP
SYNC 2
10 FB
BOOT 3
VIN 4
GND
9
VCC
PHASE 5
8
PG
PGND 6
7
EN
Pin Descriptions
PIN NUMBER
SYMBOL
PIN DESCRIPTION
1
SS
Controls the soft-start ramp time of the output. A single capacitor from the SS pin to ground determines the
output ramp rate. See “Soft-Start” on page 13 for soft-start details. If the SS pin is tied to VCC, an internal
soft-start of 2ms is used.
2
SYNC
Synchronization and light load operational mode selection input. Connect to logic high or VCC for PWM
mode. Connect to logic low or ground for PFM mode. Logic ground enables the IC to automatically choose
PFM or PWM operation. Connect to an external clock source for synchronization with positive edge trigger.
The sync source must be higher than the programmed IC frequency. An internal 5MΩ pull-down resistor
prevents an undefined logic state if SYNC is left floating.
3
BOOT
Floating bootstrap supply pin for the power MOSFET gate driver. The bootstrap capacitor provides the
necessary charge to turn on the internal N-Channel MOSFET. Connect an external 100nF capacitor from this
pin to PHASE.
4
VIN
5
PHASE
Switch node output. It connects the switching FETs with the external output inductor.
6
PGND
Power ground connection. Connect directly to the system GND plane.
7
EN
Regulator enable input. The regulator and bias LDO are held off when the pin is pulled to ground. When the
voltage on this pin rises above 1V, the chip is enabled. Connect this pin to VIN for automatic start-up. Do not
connect the EN pin to VCC because the LDO is controlled by EN voltage.
8
PG
Open-drain, power-good output that is pulled to ground when the output voltage is below regulation limits or
during the soft-start interval. There is an internal 5MΩ internal pull-up resistor.
9
VCC
Output of the internal 5V linear bias regulator. Decouple to PGND with a 1µF ceramic capacitor at the pin.
10
FB
Feedback pin for the regulator. FB is the inverting input to the voltage loop error amplifier. COMP is the
output of the error amplifier. The output voltage is set by an external resistor divider connected to FB. In
addition, the PWM regulator’s power-good and UVLO circuits use FB to monitor the regulator output voltage.
11
COMP
COMP is the output of the error amplifier. When it is tied to VCC, internal compensation is used. When only
an RC network is connected from COMP to GND, external compensation is used. See “Loop Compensation
Design” on page 16 for more details.
12
FS
Frequency selection pin. Tie to VCC for 500kHz switching frequency. Connect a resistor to GND for adjustable
frequency from 300kHz to 2MHz.
EPAD
GND
Signal ground connections. Connect to the application board GND plane with at least five vias. All voltage
levels are measured with respect to this pin. The EPAD MUST NOT float.
FN8870 Rev.1.00
Mar 15, 2019
The input supply for the power stage of the regulator and the source for the internal linear bias regulator.
Place a minimum of 4.7µF ceramic capacitance from VIN to GND and close to the IC for decoupling.
Page 3 of 21
ISL854102
Typical Application Schematics
1
2
3
CBOOT
100nF
4
CVIN
10µF
VOUT
5
L1
22µH
COUT
10µF
6
SS
FS
COMP
SYNC
12
11
R2
CFB
10
BOOT
FB
GND
9
VIN
R3
VCC
PHASE
CVCC
1µF
PG
PGND
EN
FIGURE 3. INTERNAL DEFAULT PARAMETER SELECTION
1
CSS
SS
FS
2
COMP
SYNC
3
CBOOT
100nF
4
CVIN
10µF
5
VOUT
COUT
10µF
L1
22µH
6
12
RFS
11
R2
CFB
10
BOOT
FB
GND
9
VIN
R3
VCC
PHASE
CVCC
1µF
PG
PGND
RCOMP
EN
CCOMP
FIGURE 4. USER PROGRAMMABLE PARAMETER SELECTION
TABLE 1. EXTERNAL COMPONENT SELECTION
VOUT (V)
L1 (µH)
COUT (µF)
R2 (kΩ)
R3 (kΩ)
CFB (pF)
RFS (kΩ)
RCOMP (kΩ)
CCOMP (pF)
12
22
2 x 22
90.9
4.75
22
115
150
470
5
22
47 + 22
90.9
12.4
27
DNP (Note 1)
100
470
3.3
22
47 + 22
90.9
20
27
DNP (Note 1)
100
470
2.5
22
47 + 22
90.9
28.7
27
DNP (Note 1)
100
470
1.8
12
47 + 22
90.9
45.5
27
DNP (Note 1)
70
470
NOTE:
1. Connect FS to VCC.
FN8870 Rev.1.00
Mar 15, 2019
Page 4 of 21
ISL854102
Functional Block Diagram
SS
EN
POWERGOOD
LOGIC
FB
EN/SOFTSTART
FB
5M
VCC
BIAS
LDO
500mV/A
CURRENT SENSE
OSCILLATOR
5M
SYNC
PWM/PFM
SELECT LOGIC
PFM
CURRENT
SET
BOOT
FAULT
LOGIC
600mV VREF
FS
VIN
PG
GATE
DRIVE AND
PWM DEADTIME
PWM
s Q
FB
R Q
ZERO CURRENT
DETECTION
PHASE
PGND
450mV/T SLOPE
COMPENSATION
(PWM ONLY)
150k
INTERNAL
54pF COMPENSATION
INTERNAL = 50µA/V
EXTERNAL = 230µA/V
PACKAGE
PADDLE
GND
COMP
FIGURE 5. FUNCTIONAL BLOCK DIAGRAM
Ordering Information
PART NUMBER
(Notes 3, 4)
PART
MARKING
TEMP. RANGE
(°C)
TAPE AND REEL
(Units) (Note 2)
PACKAGE
(RoHS Compliant)
PKG.
DWG. #
ISL854102FRZ
4102
-40 to +125
-
12 Ld DFN
L12.4x3
ISL854102FRZ-T
4102
-40 to +125
6k
12 Ld DFN
L12.4x3
ISL854102FRZ-T7A
4102
-40 to +125
250
12 Ld DFN
L12.4x3
ISL854102EVAL1Z
Buck regulator evaluation board
ISL854102DEMO1Z
Buck regulator demonstration board (compact version)
ISL854102DEMO2Z
Dual output Isolated buck converter
ISL854102DEMO3Z
Dual output Isolated buck-boost converter
NOTES:
2. See TB347 for details about reel specifications.
3. These Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate
plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
4. For Moisture Sensitivity Level (MSL), see the ISL854102 device page. For more information about MSL, see TB363.
FN8870 Rev.1.00
Mar 15, 2019
Page 5 of 21
ISL854102
TABLE 2. KEY DIFFERENCES BETWEEN FAMILY OF PARTS
INPUT VOLTAGE
(V)
OUTPUT
CURRENT
ISL85412
3.5 to 40
150mA
Internal Only
Internal 700kHz
No
Internal
ISL85413
3.5 to 40
300mA
Internal Only
Internal 700kHz
No
Internal
ISL85415
3 to 36
500mA
Internal/External
Internal 500kHz/external 300kHz to 2MHz
Yes
Internal/External
ISL85418
3 to 40
800mA
Internal/External
Internal 500kHz/external 300kHz to 2MHz
Yes
Internal/External
ISL85410
3 to 40
1A
Internal/External
Internal 500kHz/external 300kHz to 2MHz
Yes
Internal/External
ISL854102
3 to 40
1.2A
Internal/External
Internal 500kHz/external 300kHz to 2MHz
Yes
Internal/External
PART NUMBER
FN8870 Rev.1.00
Mar 15, 2019
COMPENSATION
SWITCHING FREQUENCY
EXT SYNC
SOFT-START
Page 6 of 21
ISL854102
Absolute Maximum Ratings
Thermal Information
VIN to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +43V
PHASE to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VIN + 0.3V (DC)
PHASE to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2V to +44V (20ns)
EN to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +43V
BOOT to PHASE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +5.5V
COMP, FS, PG, SYNC, SS, VCC to GND . . . . . . . . . . . . . . . . . . -0.3V to +5.9V
FB to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +2.95V
ESD Rating
Human Body Model (Tested per JESD22-A114) . . . . . . . . . . . . . . . . . 2kV
Charged Device Model (Tested per JESD22-C101E). . . . . . . . . . . . .1.5kV
Latch-Up (Tested per JESD-78A; Class 2, Level A) . . . . . . . . . . . . 100mA
Thermal Resistance
JA (°C/W) JC (°C/W)
DFN Package (Notes 5, 6) . . . . . . . . . . . . . .
42
4.5
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . .+150°C
Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C
Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
Recommended Operating Conditions
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +3V to +40V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions can adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
5. JA is measured in free air with the component mounted on a high-effective thermal conductivity test board with “direct attach” features. See TB379
for details.
6. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications TA = -40°C to +125°C, VIN = 3V to 40V, unless otherwise noted. Typical values are at TA = +25°C. Boldface
limits apply across the junction temperature range, -40°C to +125°C
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 9)
TYP
MAX
(Note 9)
UNIT
40
V
SUPPLY VOLTAGE
VIN Voltage Range
VIN
3
VIN Quiescent Supply Current
IQ
VFB = 0.7V, SYNC = 0V, fSW = VCC
80
VIN Shutdown Supply Current
ISD
EN = 0V, VIN = 40V (Note 7)
2
4
µA
VCC Voltage
VCC
VIN = 6V, IOUT = 0 to 10mA
5.1
5.7
V
2.75
2.95
V
4.5
µA
POWER-ON RESET
VCC POR Threshold
Rising edge
Falling edge
2.35
2.6
V
FS pin = VCC
430
500
570
kHz
Resistor from the FS pin to GND = 340kΩ
240
300
360
kHz
OSCILLATOR
Nominal Switching Frequency
fSW
Resistor from the FS pin to GND = 32.4kΩ
2000
kHz
Minimum Off-Time
tMIN_OFF
VIN = 3V
150
ns
Minimum On-Time
tMIN_ON
(Note 10)
90
ns
FS Voltage
Synchronization Frequency
VFS
RFS = 100kΩ
SYNC
0.39
0.4
300
SYNC Pulse Width
0.41
V
2000
kHz
100
ns
ERROR AMPLIFIER
Error Amplifier Transconductance Gain
gm
FB Leakage Current
Current Sense Amplifier Gain
FB Voltage
FN8870 Rev.1.00
Mar 15, 2019
External compensation
165
230
295
µA/V
Internal compensation
50
VFB = 0.6V
1
150
nA
0.46
0.5
0.54
V/A
TA = -40°C to +85°C
0.590
0.599
0.606
V
TA = -40°C to +125°C
0.590
0.599
0.607
V
RT
µA/V
Page 7 of 21
ISL854102
Electrical Specifications TA = -40°C to +125°C, VIN = 3V to 40V, unless otherwise noted. Typical values are at TA = +25°C. Boldface
limits apply across the junction temperature range, -40°C to +125°C (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 9)
TYP
MAX
(Note 9)
UNIT
90
94
%
POWER-GOOD
Lower PG Threshold - VFB Rising
Lower PG Threshold - VFB Falling
82.5
Upper PG Threshold - VFB Rising
116.5
Upper PG Threshold - VFB Falling
107
%
86
120
%
112
%
%
PG Propagation Delay
Percentage of the soft-start time
10
PG Low Voltage
ISINK = 3mA, EN = VCC, VFB = 0V
0.05
0.3
V
4.2
5.5
6.5
µA
1.5
2.4
3.4
ms
TRACKING AND SOFT-START
Soft-Start Charging Current
ISS
Internal Soft-Start Ramp Time
EN/SS = VCC
FAULT PROTECTION
Thermal Shutdown Temperature
TSD
Rising threshold
150
°C
THYS
Hysteresis
20
°C
Current Limit Blanking Time
tOCON
17
Clock
pulses
Overcurrent and Auto Restart Period
tOCOFF
8
SS cycle
Positive Peak Current Limit
IPLIMIT
PFM Peak Current Limit
(Note 8)
IPK_PFM
1.4
1.6
1.8
A
0.34
0.4
0.5
A
Zero Cross Threshold
Negative Current Limit
15
INLIMIT
(Note 8)
-0.67
mA
-0.6
-0.53
A
POWER MOSFET
High-Side
RHDS
IPHASE = 100mA, VCC = 5V
250
350
mΩ
Low-Side
RLDS
IPHASE = 100mA, VCC = 5V
90
130
mΩ
300
nA
PHASE Leakage Current
PHASE Rise Time
EN = PHASE = 0V
tRISE
VIN = 40V
10
ns
1
V
EN/SYNC
Input Threshold
Falling edge, logic low
0.4
Rising edge, logic high
1.2
-0.5
1.4
V
0.5
µA
EN Logic Input Leakage Current
EN = 0V/40V
SYNC Logic Input Leakage Current
SYNC = 0V
10
100
nA
SYNC = 5V
1.0
1.55
µA
NOTES:
7. Test condition: VIN = 40V, FB forced above regulation point (0.6V), switching and power MOSFET gate charging current not included.
8. Established by both current sense amplifier gain test and current sense amplifier output test at IL = 0A.
9. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
10. Minimum on-time required to maintain loop stability.
FN8870 Rev.1.00
Mar 15, 2019
Page 8 of 21
ISL854102
Efficiency Curves
fSW = 500kHz, TA = +25°C
100
95
95
90
90
85
EFFICIENCY (%)
EFFICIENCY (%)
85
80
75
70
60
55
75
70
65
VIN=12V
VIN=15V
60
VIN=15V
VIN=24V
55
VIN=24V
VIN=12V
65
80
50
50
0
0.1
0.2 0.3 0.4 0.5 0.6 0.7
0.8
0.9
1
1.1
0
1.2
0.1
0.2
0.3 0.4 0.5
0.7
0.8 0.9
1
1.1
1.2
FIGURE 6. EFFICIENCY vs LOAD, PFM, VOUT = 5V, L1 = 22µH
FIGURE 7. EFFICIENCY vs LOAD, PWM, VOUT = 5V, L1 = 22µH,
100
100
95
95
90
90
85
85
80
75
70
80
75
70
VIN=12V
65
VIN=12V
60
VIN=15V
60
VIN=15V
55
VIN=24V
55
VIN=24V
50
0
0.1 0.2 0.3
0.4 0.5 0.6 0.7 0.8 0.9
OUTPUT LOAD (A)
1
1.1
65
50
1.2
0
0.1
0.2
0.3 0.4 0.5 0.6
0.7 0.8 0.9
1
1.1 1.2
OUTPUT LOAD (A)
FIGURE 8. EFFICIENCY vs LOAD, PFM, VOUT = 3.3V, L1 = 22µH
FIGURE 9. EFFICIENCY vs LOAD, PWM, VOUT = 3.3V, L1 = 22µH
5.100
5.021
VIN=12V
5.080
VIN=15V
5.060
VIN=24V
5.040
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
0.6
OUTPUT LOAD (A)
EFFICIENCY (%)
EFFICIENCY (%)
OUTPUT LOAD (A)
VIN=33V
5.020
5.000
4.980
4.960
4.940
4.920
5.019
5.017
VIN=12V
5.015
5.013
VIN=24V
VIN=15V
VIN=33V
5.011
5.009
5.007
5.005
5.003
5.001
4.999
4.997
4.995
4.900
0
0.1
0.2
0.3 0.4 0.5
0.6 0.7
0.8 0.9
1
1.1
OUTPUT LOAD (A)
FIGURE 10. VOUT REGULATION vs LOAD, PFM, VOUT = 5V,
FN8870 Rev.1.00
Mar 15, 2019
1.2
0
0.1
0.2 0.3 0.4 0.5 0.6
0.7 0.8
0.9
1
1.1
1.2
OUTPUT LOAD (A)
FIGURE 11. VOUT REGULATION vs LOAD, PWM, VOUT = 5V
Page 9 of 21
ISL854102
Efficiency Curves
fSW = 500kHz, TA = +25°C (Continued)
3.450
3.350
VIN=12V
3.410
VIN=24V
3.390
VIN=12V
3.347
VIN=15V
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
3.430
VIN=33V
3.370
3.350
3.330
3.310
3.290
VIN=15V
3.344
VIN=24V
3.341
VIN=33V
3.338
3.335
3.332
3.329
3.326
3.323
3.270
3.320
3.250
0
0.1
0.2 0.3 0.4 0.5
0.6 0.7 0.8
0.9
1
1.1
0
1.2
FIGURE 12. VOUT REGULATION vs LOAD, PFM, VOUT = 3.3V
Measurements
0.2
0.4
0.6
0.8
1
1.2
OUTPUT LOAD (A)
OUTPUT LOAD (A)
FIGURE 13. VOUT REGULATION vs LOAD vs LOAD, PWM, VOUT = 3.3V
fSW = 500kHz, VIN = 24V, VOUT = 3.3V, TA = +25°C
LX 20V/DIV
LX 20V/DIV
VOUT 2V/DIV
VOUT 2V/DIV
EN 20V/DIV
EN 20V/DIV
PG 2V/DIV
PG 2V/DIV
5ms/DIV
5ms/DIV
FIGURE 14. START-UP AT NO LOAD, PFM
FIGURE 15. START-UP AT NO LOAD, PWM
LX 20V/DIV
LX 20V/DIV
VOUT 2V/DIV
VOUT 2V/DIV
EN 20V/DIV
EN 20V/DIV
PG 2V/DIV
PG 2V/DIV
100ms/DIV
100ms/DIV
FIGURE 16. SHUTDOWN AT NO LOAD, PFM
FIGURE 17. SHUTDOWN AT NO LOAD, PWM
FN8870 Rev.1.00
Mar 15, 2019
Page 10 of 21
ISL854102
Measurements
fSW = 500kHz, VIN = 24V, VOUT = 3.3V, TA = +25°C (Continued)
LX 20V/DIV
LX 20V/DIV
VOUT 2V/DIV
VOUT 2V/DIV
IL 1A/DIV
IL 1A/DIV
PG 2V/DIV
PG 2V/DIV
5ms/DIV
200µs/DIV
FIGURE 18. START-UP AT 1.2A
FIGURE 19. SHUTDOWN AT 1.2A
LX 20V/DIV
LX 20V/DIV
VOUT 20mV/DIV
VOUT 20mV/DIV
IL 20mA/DIV
IL 20mA/DIV
10ms/DIV
1µs/DIV
FIGURE 20. STEADY STATE AT NO LOAD, PFM
FIGURE 21. STEADY STATE AT NO LOAD, PWM
LX 20V/DIV
LX 20V/DIV
VOUT 50mV/DIV
VOUT 10mV/DIV
IL 200mA/DIV
IL 1A/DIV
1µs/DIV
10µs/DIV
FIGURE 22. STEADY STATE AT 1.2A LOAD
FIGURE 23. LIGHT LOAD OPERATION AT 20mA, PFM
FN8870 Rev.1.00
Mar 15, 2019
Page 11 of 21
ISL854102
Measurements
fSW = 500kHz, VIN = 24V, VOUT = 3.3V, TA = +25°C (Continued)
LX 20V/DIV
VOUT 100mV/DIV
VOUT 10mV/DIV
IL 200mA/DIV
IL 1A/DIV
1µs/DIV
200µs/DIV
FIGURE 24. LIGHT LOAD OPERATION AT 20mA
FIGURE 25. LOAD TRANSIENT, PFM
LX 20V/DIV
VOUT 100mV/DIV
VOUT 2V/DIV
IL 1A/DIV
IL 1A/DIV
PG 5V/DIV
200µs/DIV
50µs/DIV
FIGURE 26. LOAD TRANSIENT, PWM
FIGURE 27. OVERCURRENT PROTECTION, PWM
LX 20V/DIV
LX 20V/DIV
VOUT 2V/DIV
SYNC 2V/DIV
IL 1A/DIV
PG 5V/DIV
10ms/DIV
FIGURE 28. OVERCURRENT PROTECTION HICCUP, PWM
FN8870 Rev.1.00
Mar 15, 2019
200ns/DIV
FIGURE 29. SYNC AT 1.2A LOAD, PWM
Page 12 of 21
ISL854102
Measurements
fSW = 500kHz, VIN = 24V, VOUT = 3.3V, TA = +25°C (Continued)
LX 20V/DIV
LX 20V/DIV
VOUT 5V/DIV
VOUT 5V/DIV
IL 1A/DIV
IL 500mA/DIV
PG 2V/DIV
PG 2V/DIV
20µs/DIV
200µs/DIV
FIGURE 30. NEGATIVE CURRENT LIMIT, PWM
FIGURE 31. NEGATIVE CURRENT LIMIT RECOVERY, PWM
Detailed Description
Power-Good
The ISL854102 combines a synchronous buck PWM controller
with integrated power switches. The buck controller drives
internal high-side and low-side N-channel MOSFETs to deliver
load current up to 1.2A. The buck regulator can operate from an
unregulated DC source, such as a battery, with a voltage ranging
from +3V to +40V. An internal LDO provides bias to the low
voltage portions of the IC.
Peak current mode control is used to simplify feedback loop
compensation and reject input voltage variation. User selectable
internal feedback loop compensation further simplifies design.
The ISL854102 switches at a default of 500kHz.
The buck regulator is equipped with an internal current sensing
circuit and the peak current limit threshold is typically set at
1.6A.
Power-On Reset
The ISL854102 automatically initializes upon receipt of the input
power supply and continually monitors the EN pin state. If EN is
held below its logic rising threshold, the IC is held in shutdown
and consumes typically 2µA from the VIN supply. If EN exceeds
its logic rising threshold, the regulator enables the bias LDO and
begins to monitor the VCC pin voltage. When the VCC pin voltage
clears its rising POR threshold, the controller initializes the
switching regulator circuits. If VCC never clears the rising POR
threshold, the controller does not allow the switching regulator to
operate. If VCC falls below its falling POR threshold while the
switching regulator is operating, the switching regulator is shut
down until VCC returns.
Soft-Start
To avoid large inrush current, VOUT is slowly increased at start-up
to its final regulated value. Soft-start time is determined by the
SS pin connection. If SS is pulled to VCC, an internal 2ms timer is
selected for soft-start. For other soft-start times, connect a
capacitor from SS to GND. In this case, a 5.5µA current pulls up
the SS voltage and the FB pin follows this ramp until it reaches
the 600mV reference level. The soft-start time for this case is
described by Equation 1:
Time ms = C nF 0.109
FN8870 Rev.1.00
Mar 15, 2019
(EQ. 1)
PG is the open-drain output of a window comparator that
continuously monitors the buck regulator output voltage from the
FB pin. PG is actively held low when EN is low and during the
buck regulator soft-start period. After the soft-start period
completes, PG becomes high impedance if the FB pin is within
the range specified in the “Electrical Specifications” on page 8. If
FB exits the specified window, PG is pulled low until FB returns.
Over-temperature faults also force PG low until the fault
condition is cleared by an attempt to soft-start. There is an
internal 5MΩ internal pull-up resistor.
PWM Control Scheme
The ISL854102 employs peak current-mode Pulse-Width
Modulation (PWM) control for fast transient response and
pulse-by-pulse current limiting, as shown in the “Functional Block
Diagram” on page 5. The current loop consists of the current
sensing circuit, slope compensation ramp, PWM comparator,
oscillator, and latch. Current sense transresistance is typically
500mV/A and slope compensation rate, Se, is typically 450mV/T,
where T is the switching cycle period. The control reference for the
current loop comes from the error amplifier’s output (VCOMP).
A PWM cycle begins when a clock pulse sets the PWM latch and the
upper FET is turned on. Current begins to ramp up in the upper FET
and inductor. This current is sensed (VCSA), converted to a voltage
and summed with the slope compensation signal. This combined
signal is compared to VCOMP and when the signal is equal to VCOMP,
the latch is reset. Upon latch reset, the upper FET is turned off and
the lower FET turned on allowing current to ramp down in the
inductor. The lower FET remains on until the clock initiates another
PWM cycle. Figure 33 on page 14 shows the typical operating
waveforms during the PWM operation. The dotted lines illustrate the
sum of the current sense and slope compensation signal.
The output voltage is regulated as the error amplifier varies
VCOMP and therefore varies the output inductor current. The error
amplifier is a transconductance type and its output (COMP) is
terminated with a series RC network to GND. This termination is
internal (150k/54pF) if the COMP pin is tied to VCC. Additionally,
the transconductance for COMP = VCC is 50µA/V vs 230µA/V for
external RC connection. Its noninverting input is internally
connected to a 600mV reference voltage and its inverting input is
connected to the output voltage from the FB pin and its
associated divider network.
Page 13 of 21
ISL854102
PWM
DCM
PULSE SKIP
PWM
DCM
CLOCK
8 CYCLES
IL
LOAD CURRENT
0
VOUT
FIGURE 32. DCM MODE OPERATION WAVEFORMS
issued at a frequency equal to the converter’s programmed PWM
operating frequency.
VCOMP
Due to the pulsed current nature of PFM mode, the converter can
supply limited current to the load. If load current rises beyond the
limit, VOUT begins to decline. A second comparator signals an FB
voltage 2% lower than the 600mV reference and forces the
converter to return to PWM operation.
VCSA
DUTY
CYCLE
Output Voltage Selection
IL
The regulator output voltage is programmed using an external
resistor divider to scale VOUT relative to the internal reference
voltage. The scaled voltage is applied to the inverting input of the
error amplifier; see Figure 34.
VOUT
FIGURE 33. PWM OPERATION WAVEFORMS
Light Load Operation
At light loads, converter efficiency can be improved by enabling
variable frequency operation (PFM). Connecting the SYNC pin to
GND allows the controller to choose such operation
automatically when the load current is low. Figure 32 shows the
DCM operation. The IC enters DCM mode when eight consecutive
cycles of inductor current crossing zero are detected. This
corresponds to a load current equal to 1/2 the peak-to-peak
inductor ripple current and set by Equation 2:
The output voltage programming resistor, R3, depends on the
value chosen for the feedback resistor, R2, and the needed
output voltage, VOUT, of the regulator. Equation 3 describes the
relationship between VOUT and resistor values.
R 2 x0.6V
R 3 = ---------------------------------V OUT – 0.6V
(EQ. 3)
If the needed output voltage is 0.6V, then R3 is left unpopulated
and R2 is 0Ω.
VOUT
FB
(EQ. 2
EA
+
-
V OUT 1 – D
----------------------------------OUT =
2L f SW
R2
R3
0.6V
REFERENCE
where D = duty cycle, fSW = switching frequency, L = inductor
value, IOUT = output loading current, and VOUT = output voltage.
While operating in PFM mode, the regulator controls the output
voltage with a simple comparator and pulsed FET current. A
comparator indicates the point at which FB is equal to the
600mV reference, at which time the regulator begins providing
pulses of current until FB is moved above the 600mV reference
by 1%. The current pulses are approximately 400mA and are
FN8870 Rev.1.00
Mar 15, 2019
FIGURE 34. EXTERNAL RESISTOR DIVIDER
Protection Features
The ISL854102 is protected from overcurrent, negative
overcurrent, and over-temperature. The protection circuits
operate automatically.
Page 14 of 21
ISL854102
During PWM on-time, current through the upper FET is monitored
and compared to a nominal 1.6A peak overcurrent limit. In the
event that current reaches the limit, the upper FET is turned off
until the next switching cycle. In this way, FET peak current is
always well limited.
If the overcurrent condition persists for 17 sequential clock
cycles, the regulator begins its hiccup sequence. In this case,
both FETs are turned off and PG is pulled low. This condition is
maintained for eight soft-start periods, after which the regulator
attempts a normal soft-start.
if output fault persists, the regulator repeats the hiccup
sequence indefinitely. There is no danger even if the output is
shorted during soft-start.
is shorted very quickly, FB may collapse below 5/8ths of
If VOUT
its target value before 17 cycles of overcurrent are detected. The
ISL854102 recognizes this condition and begins to lower its
switching frequency proportional to the FB pin voltage. This
adjustment ensures that the inductor does not run away under
any circumstance (even with VOUT near 0V).
Negative Current Limit
If an external source somehow drives current into VOUT, the
controller attempts to regulate VOUT by reversing its inductor
current to absorb the externally sourced current. If the external
source is low impedance, the current may be reversed to
unacceptable levels and the controller initiates its negative
current limit protection. Similar to normal overcurrent, the
negative current protection is realized by monitoring the current
through the lower FET. When the valley point of the inductor
current reaches negative current limit, the lower FET is turned off
and the upper FET is forced on until current reaches the Positive
current limit or an internal clock signal is issued. At this point, the
lower FET is allowed to operate. If the current is pulled to the
negative limit again on the next cycle, the upper FET is forced on
again and the current is forced to 1/6th of the positive current
limit. Next, the controller turns off both FETs and waits for COMP
to indicate a return to normal operation. During this time, the
controller applies a 100Ω load from PHASE to PGND and
attempts to discharge the output. Negative current limit is a
pulse-by-pulse style operation and recovery is automatic.
the upper FET on for multiple clock cycles. To prevent the boot
capacitor from discharging, the lower FET is forced on for
approximately 200ns every 10 clock cycles.
Application Guidelines
Simplifying the Design
While the ISL854102 offers user programmed options for most
parameters, the easiest implementation with fewest
components involves selecting internal settings for SS, COMP,
and FS. Table 1 on page 4 provides component value selections
for a variety of output voltages and allows you to implement
solutions with a minimum of effort.
Operating Frequency
The ISL854102 operates at a default switching frequency of
500kHz if the FS pin is tied to VCC. Tie a resistor from the FS pin
to GND to program the switching frequency from 300kHz to
2MHz, as shown in Equation 4.
R FS k = 108.75k t – 0.2s 1s
(EQ. 4)
Where:
t is the switching period in µs.
400
300
RFS (kΩ)
Overcurrent Protection
200
100
0
250
500
750
1000
1250
1500
1750
2000
fSW (kHz)
FIGURE 35. RFS SELECTION vs fSW
Over-Temperature Protection
Minimum On/Off-Time Limitation
Over-temperature protection limits maximum junction
temperature in the ISL854102. When junction temperature (TJ)
exceeds +150°C, both FETs are turned off and the controller
waits for the temperature to decrease by approximately 20°C.
During this time PG is pulled low. When temperature is within an
acceptable range, the controller initiates a normal soft-start
sequence. For continuous operation, do not exceed the +125°C
junction temperature rating.
Minimum on-time (tMIN_ON) is the shortest duration of time that
the HS FET can be turned on and minimum off time (tMIN_OFF) is
the shortest duration of time that the HS FET can be turned off.
The typical tMIN_ON is 90ns and the typical tMIN_OFF is 150ns.
For a given tMIN_ON and tMIN_OFF, a higher switching frequency
results in a narrower range of allowed duty cycle, which
translates to a smaller allowed VIN range.
Boot Undervoltage Protection
If the boot capacitor voltage falls below 1.8V, the boot
undervoltage protection circuit turns on the lower FET for 400ns
to recharge the capacitor. This operation may arise during long
periods of no switching such as PFM no load situations. In PWM
operation near dropout (VIN near VOUT), the regulator can hold
FN8870 Rev.1.00
Mar 15, 2019
For a given output voltage (VOUT) and switching frequency (fSW),
the maximum allowed voltage is given by (Equation 5):
V OUT
V IN max = --------------------------------------f SW t MIN_ON
(EQ. 5)
The minimum allowed voltage is given by (Equation 6):
Page 15 of 21
ISL854102
(EQ. 6)
Table 3 shows the recommended switching frequencies for the
various VOUT to operate up to the maximum VIN (40V).
TABLE 3. RECOMMENDED SWITCHING FREQUENCIES FOR VARIOUS
VOUT
VIN (max) (V)
VOUT (V)
fSW (kHz)
40
5
500
40
3.3
500
40
2.5
500
40
1.8
300
For the ceramic capacitors (low ESR):
(EQ. 8)
where I is the inductor’s peak-to-peak ripple current, fSW is the
switching frequency and COUT is the output capacitor.
If using electrolytic capacitors,
The frequency of operation can be synchronized up to 2MHz by
an external signal applied to the SYNC pin. The rising edge on the
SYNC triggers the rising edge of PHASE. To properly synchronize,
the external source must be at least 10% greater than the
programmed free running IC frequency.
Output Inductor Selection
The inductor value determines the converter’s ripple current.
Choosing an inductor current requires a somewhat arbitrary
choice of ripple current, I. A reasonable starting point is 30% of
total load current. The inductor value can then be calculated
using Equation 7:
(EQ. 7)
Buck Regulator Output Capacitor Selection
An output capacitor is required to filter the inductor current. The
current mode control loop allows the use of low ESR ceramic
capacitors and thus supports very small circuit implementations
on the PC board. Electrolytic and polymer capacitors can also be
used.
While ceramic capacitors offer excellent overall performance
and reliability, the actual in-circuit capacitance must be
considered. Ceramic capacitors are rated using large
peak-to-peak voltage swings and with no DC bias. In the DC/DC
converter application, these conditions do not reflect reality. As a
result, the actual capacitance may be considerably lower than
the advertised value. Consult the manufacturer’s datasheet to
determine the actual in-application capacitance. Most
manufacturers publish capacitance vs DC bias so that this effect
can be easily accommodated. The effects of AC voltage are not
frequently published, however, an assumption of ~20% further
reduction generally suffices. The result of these considerations
V OUTripple = I*ESR
(EQ. 9)
Loop Compensation Design
When COMP is not connected to VCC, the COMP pin is active for
external loop compensation. The ISL854102 uses constant
frequency peak current mode control architecture to achieve a
fast loop transient response. An accurate current sensing pilot
device in parallel with the upper MOSFET is used for peak current
control signal and overcurrent protection. The inductor is not
considered as a state variable since its peak current is constant,
and the system becomes a single order system. It is much easier
to design a Type II compensator to stabilize the loop than to
implement voltage mode control. Peak current mode control has
an inherent input voltage feed-forward function to achieve good
line regulation. Figure 36 shows the small signal model of the
synchronous buck regulator.
^
iin
V^in
+
+
Increasing the value of inductance reduces the ripple current and
thus, the ripple voltage. However, the larger inductance value
may reduce the converter’s response time to a load transient.
The inductor current rating should be such that it does not
saturate in overcurrent conditions. For typical ISL854102
applications, inductor values generally lie in the 10µH to 47µH
range. In general, higher VOUT causes higher inductance.
FN8870 Rev.1.00
Mar 15, 2019
Use the following equations to calculate the required
capacitance for ripple voltage. Additional capacitance can be
used.
I
V OUTripple = ------------------------------------8 f SW C OUT
Synchronization Control
V IN – V OUT V OUT
L = -------------------------------- ---------------V IN
f SW I
may mean an effective capacitance 50% lower than nominal and
this value should be used in all design calculations. Nonetheless,
ceramic capacitors are a very good choice in many applications
due to their reliability and extremely low ESR.
GAIN (VLOOP (S(fi))
V OUT
V IN min = --------------------------------------------------1 – f SW t MIN_OFF
ILd^ 1:D
^
iL LP
RLP
vo^
Vind^
Rc
RT
Co
Ro
Ti(S)
d^
K
Fm
+
Tv(S)
He(S)
^
V
comp
-Av(S)
FIGURE 36. SMALL SIGNAL MODEL OF SYNCHRONOUS BUCK
REGULATOR
Page 16 of 21
ISL854102
Put compensator zero 2 to 5 times fc.
Vo
R2
1
C 3 = ---------------f c R 2
C3
VFB
VREF
R3
-
(EQ. 13)
VCOMP
Example: VIN = 12V, VO = 5V, IO = 1.2A, fSW = 500kHz,
R2 = 90.9kΩ, Co = 22µF/5mΩ, L = 39µH, fc = 50kHz, then
compensator resistance R6:
R6
R 6 = 22.75 10 50kHz 5V 22F = 125.12k
GM
+
3
C7
(EQ. 14)
It is acceptable to use 124kΩ as the closest standard value for
R6.
C6
5V 22 F
C 6 = ------------------------------ = 0.88nF
1A 124k
FIGURE 37. TYPE II COMPENSATOR
Figure 37 shows the type II compensator and its transfer function
is expressed as shown in Equation 10:
S
S
1 + ------------ 1 + -------------
GM R 3
cz1
cz2
vˆ COMP
- = -------------------------------------------------------- --------------------------------------------------------------A v S = ------------------ C6 + C7 R2 + R3
S
S
vˆ FB
S 1 + ------------- 1 + -------------
cp1
cp2
(EQ. 10)
where:
R2 + R3
C6 + C7
1
1
cz1 = --------------- , cz2 = --------------- cp1 = ----------------------- cp2 = ----------------------R6 C6 C7
C3 R2 R3
R6 C6
R2 C3
Compensator design goal:
• High DC gain
• Choose loop bandwidth fc less than 100kHz
• Gain margin: >10dB
• Phase margin: >40°
The compensator design procedure is as follows:
(EQ. 15)
5m 22F
1
C 7 = max (---------------------------------,----------------------------------------------------) = (0.88pF,5.1pF)
124k
500kHz 124k
(EQ. 16)
It is also acceptable to use the closest standard values for C6 and
C7. There is approximately 3pF parasitic capacitance from VCOMP
to GND; Therefore, C7 is optional. Use C6 = 1500pF and
C7 = OPEN.
1
C 3 = -------------------------------------------------- = 70pF
50kHz 90.9k
(EQ. 17)
Use C3 = 68pF. Note that C3 may increase the loop bandwidth
from previous estimated value. Figure 38 shows the simulated
voltage loop gain. It is shown that it has a 75kHz loop bandwidth
with a 61° phase margin and 6dB gain margin. It may be more
desirable to achieve an increased gain margin, which can be
accomplished by lowering R6 by 20% to 30%. In practice,
ceramic capacitors have significant derating on voltage and
temperature, depending on the type. See the ceramic capacitor
datasheet for more details.
The loop gain at crossover frequency of fc has a unity gain.
Therefore, the compensator resistance R6 is determined by
Equation 11.
2f c V o C o R t
3
R 6 = ---------------------------------- = 22.75 10 f c V o C o
GM V FB
(EQ. 11)
where GM is the transconductance, gm, of the voltage error
amplifier in each phase. Compensator capacitor C6 is then given
by Equation 12.
Ro Co Vo Co
Rc Co
1
C 6 = --------------- = --------------- ,C 7 = max (--------------,----------------------)
R6
Io R6
R 6 f SW R 6
(EQ. 12)
Put one compensator pole at zero frequency to achieve high DC
gain, and put another compensator pole at either ESR zero
frequency or half switching frequency, whichever is lower in
Equation 12. An optional zero can boost the phase margin. CZ2
is a zero due to R2 and C3.
FN8870 Rev.1.00
Mar 15, 2019
Page 17 of 21
ISL854102
Place the feedback divider close to the FB pin and do not route
any feedback components near PHASE or BOOT. If external
components are used for SS, COMP, or FS, the same advice
applies.
60
45
CSS
CSS
15
RFS
RFS
CVIN
CVIN
0
-15
-30
100
1k
10k
100k
1M
FREQUENCY (Hz)
L1
L1
180
COUT
COUT
150
PHASE (°)
0.50”
CVCC
CVCC
GAIN (dB)
30
120
0.47”
90
FIGURE 39. PRINTED CIRCUIT BOARD POWER PLANES AND ISLANDS
60
30
0
100
1k
10k
FREQUENCY (Hz)
100k
1M
FIGURE 38. SIMULATED LOOP GAIN
Layout Considerations
Proper layout of the power converter minimizes EMI and noise,
and ensures first pass success of the design. Printed Circuit
Board (PCB) layouts are provided in multiple formats on the
Renesas website. In addition, Figure 39 illustrates the important
points in PCB layout. In reality, PCB layout of the ISL854102 is
quite simple.
A multilayer PCB with GND plane is recommended. Figure 39
shows the connections of the critical components in the
converter. Note that capacitors CIN and COUT can each represent
multiple physical capacitors. The most critical connections are to
tie the PGND pin to the package GND pad and then use vias to
directly connect the GND pad to the system GND plane. This
connection of the GND pad to system plane ensures a low
impedance path for all return current and an excellent thermal
path to dissipate heat. With this connection made, place the high
frequency MLCC input capacitor near the VIN pin and use vias
directly at the capacitor pad to tie the capacitor to the system
GND plane.
The boot capacitor is easily placed on the PCB side opposite the
controller IC and two vias directly connect the capacitor to BOOT
and PHASE.
Place a 1µF MLCC near the VCC pin and directly connect its
return with a via to the system GND plane.
FN8870 Rev.1.00
Mar 15, 2019
Page 18 of 21
ISL854102
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, however, not
warranted. Please visit our website to make sure you have the latest revision.
DATE
REVISION
Mar 15, 2019
FN8870.1
Updated links throughout document.
Added Related Literature section
Updated the Ordering Information table by adding tape and reel parts, evaluation board, demonstration
boards, and updated notes.
Under Light Load Operation section changed 300mA to 400mA and 1% to 2%.
Added Minimum On/Off-Time Limitation section.
Removed About Intersil section.
Updated Disclaimer.
Jul 1, 2016
FN8870.0
Initial Release
FN8870 Rev.1.00
Mar 15, 2019
CHANGE
Page 19 of 21
ISL854102
Package Outline Drawing
For the most recent package outline drawing, see L12.4x3.
L12.4x3
12 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE
Rev 3, 3/15
3.30 +0.10/-0.15
4.00
6
PIN 1
INDEX AREA
2X 2.50
A
10X 0.50
PIN #1 INDEX AREA
B
6
1
12 X 0.40 ±0.10
6
1.70 +0.10/-0.15
3.00
(4X)
0.15
7
12
TOP VIEW
0.10M C A B
4 12 x 0.23 +0.07/-0.05
BOTTOM VIEW
SEE DETAIL "X"
(3.30)
6
0.10 C
1
C
1.00 MAX
SEATING PLANE
0.08 C
SIDE VIEW
2.80
(1.70)
C
0.2 REF
5
12 X 0.60
7
12
0. 00 MIN.
0. 05 MAX.
(12 X 0.23)
(10X 0.5)
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance: Decimal ± 0.05
4. Dimension applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature and
may be located on any of the 4 sides (or ends).
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Compliant to JEDEC MO-229 V4030D-4 issue E.
FN8870 Rev.1.00
Mar 15, 2019
Page 20 of 21
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