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ISL91107IRTAZ-T7A

ISL91107IRTAZ-T7A

  • 厂商:

    RENESAS(瑞萨)

  • 封装:

    WFQFN20_EP

  • 描述:

    Buck-Boost Switching Regulator IC Positive Adjustable 1V 1 Output 2A 20-WFQFN Exposed Pad

  • 数据手册
  • 价格&库存
ISL91107IRTAZ-T7A 数据手册
DATASHEET ISL91107IR FN8687 Rev 0.00 March 2, 2015 High Efficiency Buck-Boost Regulator with 4.1A Switches The ISL91107IR is a highly-integrated buck-boost switching regulator that accepts input voltages either above or below the regulated output voltage. Unlike other buck-boost regulators, this regulator automatically transitions between operating modes without significant output disturbance. This device is capable of delivering up to 2A of output current (PVIN = 2.8V, VOUT = 3.3V) and provides excellent efficiency due to its fully synchronous 4-switch architecture. No-load quiescent current of only 45µA also optimizes efficiency under light load conditions. The ISL91107IR is designed for standalone applications and supports 3.3V fixed output voltages or variable output voltages with an external resistor divider. Output voltages as low as 1V or as high as 5.2V are supported using an external resistor divider. The ISL91107IR requires only a single inductor and very few external components. Power supply solution size is minimized by its 2.5MHz switching frequency, allowing small size external components. The ISL91107IR is available in a 3x4 20 Ld TQFN package. Features • Accepts input voltages above or below regulated output voltage • Automatic and seamless transitions between buck and boost modes • Input voltage range: 1.8V to 5.5V • Output current: up to 2A (PVIN = 2.8V, VOUT = 3.3V) • High efficiency: up to 96% • 45µA quiescent current maximizes light load efficiency • 2.5MHz switching frequency minimizes external component size • Selectable forced PWM mode • Fully protected for short-circuit, over-temperature and undervoltage • Small 3mmx4mm TQFN package Applications • Smartphones and tablet PCs • Wireless communication devices • Optical modules networking equipment C1 22µF 100 ISL91107IRTNZ PVIN VIN MODE EN LX1 LX2 VOUT FB 95 L1 1µH VIN = 3.6V 90 V OUT = 3.3V C2 2x22µF SGND PGND EFFICIENCY (%) V IN = 1.8V TO 5.5V 85 80 VIN = 2.7V VIN = 4.2V VIN = 3V 75 70 VIN = 2.5V 65 60 0.001 FIGURE 1. TYPICAL ISL91107IRTNZ APPLICATION FN8687 Rev 0.00 March 2, 2015 0.01 0.1 1.0 3.0 LOAD CURRENT (A) FIGURE 2. EFFICIENCY vs OUTPUT CURRENT (VOUT = 3.3V) Page 1 of 13 ISL91107IR Block Diagram LX1 LX1 LX2 LX2 PVIN PVIN GATE GATE DRIVERS DRIVERS AND ANTI& ANTISHOOT-THRU SHOOT THRU EN EN - + EN EN REVERSE CURRENT VOUT VOUT  E S R E V E R T N E R R U C SOFT SOFT DISCHARGE DISCHARGE EN EN EN EN VIN VIN PGND PGND VVREF REF PVIN PVIN MONITOR MONITOR VOUT VOUT CLAMP CLAMP THERMAL THERMAL SHUTDOWN SHUTDOWN PWM PWM CONTROL CONTROL MODE MODE CURRENT CURRENT DETECT DETECT EN EN EN VOUT VOUT MONITOR MONITOR EN EN EN + OSC OSC - FB FB + REF REF ERROR ERROR  AMP AMP VOLTAGE VOLTAGE PROG. PROG. SGND SGND FN8687 Rev 0.00 March 2, 2015 Page 2 of 13 ISL91107IR Pin Configuration Pin Descriptions PIN # PIN NAMES 17 VOUT 18 VOUT 19 VOUT 20 VOUT ISL91107IR (20 LD TQFN) TOP VIEW LX2 1 16 FB LX2 2 15 SGND PGND 3 14 MODE THERMAL PAD PVIN 10 9 11 NC PVIN LX1 6 8 12 VIN PVIN LX1 5 7 13 EN PVIN PGND 4 DESCRIPTION 7, 8, 9, 10 PVIN Power input. Range: 1.8V to 5.5V. Connect 22µF capacitor to PGND. 12 VIN Supply input. Range: 1.8V to 5.5V. 5, 6 LX1 Inductor connection, input side. 13 EN Logic input for enable. Drive HIGH to enable device, LOW to disable. Do not leave this pin floating 3, 4 PGND Power ground for high switching current. 14 MODE Logic input, HIGH for auto PFM mode. LOW for forced PWM operation. Do not leave this pin floating 1, 2 LX2 15 SGND Analog ground pin 17, 18, 19, 20 VOUT Buck-boost output. Connect 2x22µF capacitor to PGND. 16 FB - EPAD Inductor connection, output side. Voltage feedback pin. Thermal pad. Connect to PGND Ordering Information PART NUMBER (Notes 1, 2, 3) PART MARKING VOUT (V) TEMP RANGE (°C) PACKAGE (RoHS Compliant) PKG. DWG. # ISL91107IRTNZ (Note 1) 107N 3.3 -40 to +85 20 Ld TQFN L20.3x4A ISL91107IRTAZ (Note 1) 107A Adj -40 to +85 20 Ld TQFN L20.3x4A ISL91107IRN-EVZ Evaluation Board for ISL91107IRTNZ for 3.3 Voltage Output ISL91107IRA-EVZ Evaluation Board for ISL91107IRTAZ for ADJ Voltage Output NOTES: 1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pbfree products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see product information page for ISL91107IR. For more information on MSL, please see tech brief TB363. FN8687 Rev 0.00 March 2, 2015 Page 3 of 13 ISL91107IR Absolute Maximum Ratings Thermal Information PVIN, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.5V LX1, LX2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.5V FB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.5V SGND, PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 0.3V All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.5V ESD Rating Human Body Model (Tested per JESD22-A114E) . . . . . . . . . . . . . . . . 3kV Machine Model (Tested per JESD22-A115-A) . . . . . . . . . . . . . . . . . . 250V Latch-up (Tested per JESD-78B; Class 2, Level A) . . . . . . . . . . . . . . 100mA Thermal Resistance (Typical) JA (°C/W) JC (°C/W) 3x4mm TQFN Package (Notes 4, 5). . . . . . 41 5.5 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+125°C Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493 Recommended Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C Supply Voltage (VIN) Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.8V to 5.5V Load Current (IOUT) Range (DC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0A to 2A CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 4. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 5. For JC, the “case temp” location is the center of the exposed metal pad on the package underside. Analog Specifications VIN = PVIN = EN = 3.6V, VOUT = 3.3V, L1 = 1µH, C1 = 1x22µF, C2 = 2x22µF, TA = +25°C. Boldface limits apply across the recommended operating temperature range, -40°C to +85°C and input voltage range (1.8V to 5.5V). SYMBOL PARAMETER TEST CONDITIONS MIN (Note 6) TYP MAX (Note 6) UNITS 5.5 V POWER SUPPLY VIN VUVLO Input Voltage Range VIN Undervoltage Lockout Threshold 1.8 Rising Falling IVIN ISD VIN Supply Current VIN Supply Current, Shutdown 1.75 1.60 PFM mode, no external load on VOUT, no switching, VIN ≤ 5V 45 PFM mode, no external load on VOUT, with switching 60 EN = SGND, VIN ≤ 5V 1.795 V 1.71 V 0.05 60 µA 0.6 µA OUTPUT VOLTAGE REGULATION VOUT VFB Output Voltage Accuracy IOUT = 1mA, PWM mode -2 +2 % IOUT = 1mA, PFM mode -3 +4 % Feedback Voltage For adjustable version only VOUT/ VIN Line Regulation, PWM Mode IOUT = 500mA, MODE = SGND, VIN step from 2.3V to 5.5V 0.788 ±0.005 0.8 mV/mV VOUT/ IOUT Load Regulation, PWM Mode VIN = 3.7V, MODE = SGND, IOUT step from 0mA to 500mA ±0.005 mV/mA VOUT/ VIN Line Regulation, PFM Mode IOUT = 100mA, MODE = VIN, VIN step from 2.3V to 5.5V ±12.5 mV/V VOUT/ IOUT Load Regulation, PFM Mode VIN = 3.7V, MODE = VIN, IOUT step from 0mA to 100mA ±0.4 mV/mA VCLAMP Output Voltage Clamp Rising 5.35 VCLAMP_HS Output Voltage Clamp Hysteresis 0.812 V 5.85 400 V mV DC/DC SWITCHING SPECIFICATIONS fSW tONMIN Oscillator Frequency 2.5 ≤ VIN ≤ 5V 2.25 Minimum On Time 2.5 2.75 80 MHz ns IPFETLEAK LX1 Pin Leakage Current -0.1 0.1 µA INFETLEAK LX2 Pin Leakage Current -0.1 0.1 µA FN8687 Rev 0.00 March 2, 2015 Page 4 of 13 ISL91107IR Analog Specifications VIN = PVIN = EN = 3.6V, VOUT = 3.3V, L1 = 1µH, C1 = 1x22µF, C2 = 2x22µF, TA = +25°C. Boldface limits apply across the recommended operating temperature range, -40°C to +85°C and input voltage range (1.8V to 5.5V). (Continued) SYMBOL PARAMETER TEST CONDITIONS MIN (Note 6) TYP MAX (Note 6) UNITS SOFT-START and SOFT DISCHARGE tSS RDISCHG Soft-start Time VOUT Soft-discharge ON-resistance Time from when EN signal asserts to when output voltage ramp starts. 1 ms Time from when output voltage ramp starts to when output voltage reaches 95% of its nominal value with device operating in buck mode. VIN = 4V, IOUT = 200mA 1 ms Time from when output voltage ramp starts to when output voltage reaches 95% of its nominal value with device operating in boost mode. VIN = 2V, IOUT = 200mA 2 ms VIN = 3.6V, EN < VIL 35 Ω VIN = 3.6V 55 mΩ POWER MOSFET rDSON_P P-channel MOSFET ON-resistance RDSON_N N-channel MOSFET ON-resistance VIN = 3.6V IPK_LMT P-channel MOSFET Peak Current Limit VIN = 3.6V 47 3.8 4.1 mΩ 4.8 A PFM/PWM TRANSITION Load Current Threshold, PFM to PWM VIN = 3V, VOUT = 3.3V 375 mA Load Current Threshold, PWM to PFM VIN = 3V, VOUT = 3.3V 300 mA Thermal Shutdown 150 °C Thermal Shutdown Hysteresis 30 °C THERMAL SHUTDOWN LOGIC INPUTS ILEAK Input Leakage VIH Input HIGH Voltage VIL Input LOW Voltage 0.05 0.1 µA 1.4 V 0.4 V NOTE: 6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. FN8687 Rev 0.00 March 2, 2015 Page 5 of 13 ISL91107IR Typical Performance Curves C1 = 22µF, C2 = 2x22µF, VOUT = 3.3V, IOUT = 0A to 2A. Unless otherwise noted, operating conditions are: TA = +25°C, VIN = EN = 3.6V, L = 1µH, 80 18 78 16 76 14 72 TA = +85°C 70 68 TA = +25°C 8 TA = -40°C 4 64 62 2 TA = -40°C 2.0 2.5 3.0 3.5 4.0 VIN (V) 5.0 4.5 0 1.5 5.5 FIGURE 3. QUIESCENT CURRENT vs INPUT VOLTAGE (MODE = HIGH, VOUT = 3.3V) 2.5 3.5 VIN (V) 4.5 100 fSW,TA = +25°C 2.45 2.40 2.35 2.30 fSW,TA = -40°C 2.25 2.20 1.5 2.5 3.5 VIN (V) 4.5 MOSFET ON-RESISTANCE (mΩ) fSW,TA = +85°C 2.50 90 80 P-CHANNEL MOSFET 70 60 50 N-CHANNEL MOSFET 40 30 1.5 5.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VIN (V) FIGURE 5. SWITCHING FREQUENCY vs INPUT VOLTAGE FIGURE 6. MOSFET ON-RESISTANCE vs INPUT VOLTAGE 100 3.300 VIN = 3.3V 3.295 95 5.5 FIGURE 4. QUIESCENT CURRENT vs INPUT VOLTAGE (MODE = LOW, VOUT = 3.3V) 2.55 OSCILLATOR FREQUENCY (MHz) TA = +85°C 10 6 66 60 TA = +25°C 12 IQ (mA) IQ (µA) 74 LOAD = 100mA 90 VOUT (V) EFFICIENCY (%) 3.290 LOAD = 10mA 85 3.285 VIN = 3.8V VIN = 4.2V 3.280 3.275 LOAD = 1mA 3.270 80 3.265 75 1.5 2.5 3.5 4.5 VIN (V) FIGURE 7. LIGHT-LOAD EFFICIENCY vs INPUT VOLTAGE (VOUT = 3.3V) FN8687 Rev 0.00 March 2, 2015 5.5 3.260 1 10 100 1000 LOAD CURRENT (mA) FIGURE 8. OUTPUT VOLTAGE vs LOAD CURRENT Page 6 of 13 ISL91107IR Typical Performance Curves Unless otherwise noted, operating conditions are: TA = +25°C, VIN = EN = 3.6V, L = 1µH, C1 = 22µF, C2 = 2x22µF, VOUT = 3.3V, IOUT = 0A to 2A. (Continued) 100 95 180 VIN = 3V VIN = 2.5V 160 140 85 80 VIN = 1.8V 75 120 IQ (µA) EFFICIENCY (%) 90 VIN = 3.8V 70 100 VIN = 5V 65 80 60 60 55 50 1 10 100 LOAD CURRENT (mA) 40 1000 VIN = 3.3V 80 5 6 70 VIN = 3.8V VIN = 4.2V VIN = 3V 60 3.275 50 40 3.265 VIN = 3V 3.260 30 20 1 VIN = 3.3V 3.255 VIN = 3.8V 10 VIN = 4.2V 3.270 VOUT (V) EFFICIENCY (%) 4 3.280 90 10 100 LOAD CURRENT (mA) 3.250 1000 FIGURE 11. EFFICIENCY vs LOAD CURRENT (MODE = LOW, VOUT = 3.3V) 1 10 100 LOAD CURRENT (mA) 1000 FIGURE 12. OUTPUT VOLTAGE vs LOAD CURRENT (MODE = LOW, VOUT = 3.265V) 3.5 400 350 3.0 MAX IOUT, TA = +25°C 2.5 MAX IOUT, TA = +85°C 2.0 1.5 1.0 0.5 LOAD CURRENT (mA) MAXIMUM OUTPUT CURRENT (A) 3 FIGURE 10. SUPPLY CURRENT (SWITCHING) (VOUT = 5V) 100 0 2 VIN (V) FIGURE 9. EFFICIENCY vs LOAD CURRENT (VOUT = 2V) 0 1 300 PFM->PWM 250 200 150 PWM->PFM 100 50 1.5 2.5 3.5 VIN (V) 4.5 FIGURE 13. MAXIMUM OUTPUT CURRENT vs INPUT VOLTAGE (VOUT = 3.3V) FN8687 Rev 0.00 March 2, 2015 5.5 0 1.5 2.0 2.5 3.0 3.5 VIN (V) 4.0 4.5 5.0 5.5 FIGURE 14. PFMPWM TRANSITION THRESHOLDS vs VIN (VOUT = 3.3V) Page 7 of 13 ISL91107IR Typical Performance Curves Unless otherwise noted, operating conditions are: TA = +25°C, VIN = EN = 3.6V, L = 1µH, C1 = 22µF, C2 = 2x22µF, VOUT = 3.3V, IOUT = 0A to 2A. (Continued) 100 VIN = 3.6V EFFICIENCY (%) 95 VIN = 4.5V 90 85 VIN = 3V VIN = 4.2V VIN = 3.3V 80 75 70 0.001 0.01 0.1 1.0 3.0 LOAD CURRENT (A) FIGURE 15. EFFICIENCY vs OUTPUT CURRENT (VOUT = 5V) VIN (1V/DIV) VIN (1V/DIV) VOUT (AC, 50mV/DIV) VOUT (AC, 50mV/DIV) LOAD (1A/DIV) LOAD (1A/DIV) 100µs/DIV 100µs/DIV FIGURE 16. 0A TO 1A LOAD TRANSIENT, VOUT = 3.3V FIGURE 17. 0A TO 1A LOAD TRANSIENT, VOUT = 3.3V VIN (1V/DIV) VIN (1V/DIV) VIN (1V/DIV) VOUT (AC, 200mV/DIV) VOUT LOAD (1A/DIV) LOAD (1A/DIV) (AC, 500mV/DIV) 100µs/DIV FIGURE 18. 0A TO 1A LOAD TRANSIENT, VIN = 3V, VOUT = 5V FN8687 Rev 0.00 March 2, 2015 100µs/DIV FIGURE 19. 0A TO 2A LOAD TRANSIENT, VIN = 3.6V, VOUT = 5V Page 8 of 13 ISL91107IR Typical Performance Curves Unless otherwise noted, operating conditions are: TA = +25°C, VIN = EN = 3.6V, L = 1µH, C1 = 22µF, C2 = 2x22µF, VOUT = 3.3V, IOUT = 0A to 2A. (Continued) VIN (1V/DIV) VOUT (1V/DIV) VIN (2V/DIV) VOUT (50mV/DIV) EN (2V/DIV) INDUCTOR CURRENT (500mA/DIV) 1ms/DIV 1ms/DIV FIGURE 20. 3.6V TO 3V LINE TRANSIENT RESPONSE, VOUT = 3.3V, LOAD = 1.5A Functional Description Functional Overview Refer to the “Block Diagram” on page 2. The ISL91107IR implements a complete buck-boost switching regulator with PWM controller, internal switches, references, protection circuitry and control inputs. The PWM controller automatically switches between buck and boost modes as necessary to maintain a steady output voltage with changing input voltages and dynamic external loads. Internal Supply and References Referring to the “Block Diagram” on page 2, the ISL91107IR provides two power input pins. The PVIN pin supplies input power to the DC/DC converter, while the VIN pin provides operating voltage source required for stable VREF generation. Separate ground pins (SGND and PGND) are provided to avoid problems caused by ground shift due to the high switching currents. Enable Input A master enable pin EN allows the device to be enabled. Driving EN LOW invokes a power-down mode, where most internal device functions are disabled. Soft Discharge When the device is disabled by driving EN LOW, an internal resistor between VOUT and SGND is activated. This internal resistor has a typical resistance of 35Ω. POR Sequence and Soft-start Bringing the EN pin HIGH allows the device to power-up. A number of events occur during the start-up sequence. The internal voltage reference powers up and stabilizes. The device then starts to operate. There is a 1ms (typical) delay between assertion of the EN pin and the start of the switching regulator soft-start ramp. FN8687 Rev 0.00 March 2, 2015 FIGURE 21. START-UP WITH VIN = 4V, RLOAD = 1.5A, VOUT = 3.3V The soft-start feature minimizes output voltage overshoot and input inrush currents. During soft-start, the reference voltage is ramped to provide a ramping VOUT voltage. While output voltage is lower than approximately 20% of the target output voltage, switching frequency is reduced to a fraction of the normal switching frequency to aid in producing low duty cycles necessary to avoid input inrush current spikes. Once the output voltage exceeds 20% of the target voltage, the switching frequency is increased to its nominal value. When the target output voltage is higher than the input voltage, there will be a transition from buck mode to boost mode during the soft-start sequence. At the time of this transition, the ramp rate of the reference voltage is decreased, such that the output voltage slew rate is decreased. This provides a slower output voltage slew rate. The VOUT ramp time is not constant for all operating conditions. Soft-start into boost mode will take longer than soft-start into buck mode. The total soft-start time into buck operating mode is typically 2ms, whereas the typical soft-start time into boost mode operating mode is typically 3ms. Increasing the load current will increase these typical soft-start times. Overcurrent Protection The ISL91107IR provides short-circuit protection by monitoring the FB voltage. When FB voltage is sensed to be lower than a certain threshold, the PWM oscillator frequency is reduced in order to protect the device from damage. The P-channel MOSFET peak current limit remains active during this state. Undervoltage Lockout The undervoltage lockout (UVLO) feature prevents abnormal operation in the event that the supply voltage is too low to guarantee proper operation. When the VIN voltage falls below the UVLO threshold, the regulator is disabled. Page 9 of 13 ISL91107IR Thermal Shutdown Operation with VIN Close to VOUT A built-in thermal protection feature protects the ISL91107IR if the die temperature reaches +150°C (typical). At this die temperature, the regulator is completely shut down. The die temperature continues to be monitored in this thermal-shutdown mode. When the die temperature falls to +120°C (typical), the device will resume normal operation. When the output voltage is close to the input voltage, the ISL91107IR will rapidly and smoothly switch from boost-to-buck mode as needed to maintain the regulated output voltage. This behavior provides excellent efficiency and very low output voltage ripple. When exiting thermal shutdown, the ISL91107IR will execute its soft-start sequence. Buck-Boost Conversion Topology The ISL91107IR operates in either buck or boost mode. When operating in conditions where VIN is close to VOUT, the ISL91107IR alternates between buck and boost mode as necessary to provide a regulated output voltage. L1 LX1 SWITCH A LX2 Component Selection The fixed output versions of the ISL91107IR require only three external power components to implement the buck boost converter: an inductor, an input capacitor and an output capacitor. VIN = 1.8V TO 5.5V C1 22µF SWITCH D PVIN Applications Information VOUT ISL91107IRTAZ PVIN LX1 L1 1µH VIN MODE LX2 EN SWITCH B SWITCH C VOUT = 3.3V VOUT FB R1 187k R2 60.4k C4 22pF C2 2x22µF SGND PGND FIGURE 22. BUCK-BOOST TOPOLOGY Figure 22 shows a simplified diagram of the internal switches and external inductor. PWM Operation In buck PWM mode, Switch D is continuously closed and Switch C is continuously open. Switches A and B operate as a synchronous buck converter when in this mode. In boost PWM mode, Switch A remains closed and Switch B remains open. Switches C and D operate as a synchronous boost converter when in this mode. PFM Operation During PFM operation in buck mode, Switch D is continuously closed and Switch C is continuously open. Switches A and B operate in discontinuous mode during PFM operation. During PFM operation in boost mode, the ISL91107IR closes Switch A and Switch C to ramp up the current in the inductor. When the inductor current reaches a certain threshold, the device turns OFF Switches A and C, then turns ON Switches B and D. With Switches B and D closed, output voltage increases as the inductor current ramps down. In most operating conditions, there will be multiple PFM pulses to charge up the output capacitor. These pulses continue until VOUT has achieved the upper threshold of the PFM hysteretic controller. Switching then stops and remains stopped until VOUT decays to the lower threshold of the hysteretic PFM controller. FIGURE 23. TYPICAL APPLICATION The adjustable ISL91107IR version requires three additional components to program the output voltage. Two external resistors program the output voltage and a small capacitor is added to improve stability and response. Setting and controlling the output voltage of the ISL91107IR (adjustable output version) can be accomplished by selecting the external resistor values. Equation 1 can be used to derive the R1 and R2 resistor values: R 1  V OUT = 0.8V   1 + ------- R 2  (EQ. 1) When designing a PCB, include an SGND guard band around the feedback resistor network to reduce noise and improve accuracy and stability. Resistors R1 and R2 should be positioned close to the FB pin. Inductor Selection An inductor with high frequency core material (e.g., ferrite core) should be used to minimize core losses and provide good efficiency. The inductor must be able to handle the peak switching currents without saturating. A 1µH inductor with ≥4.1A saturation current rating is recommended. Select an inductor with low DCR to provide good FN8687 Rev 0.00 March 2, 2015 Page 10 of 13 ISL91107IR efficiency. In applications where radiated noise must be minimized, a toroidal or shielded inductor can be used. TABLE 1. INDUCTOR VENDOR INFORMATION MANUFACTURER MFR P/N DESCRIPTION Cyntec PIFE32251B-1R0MS 1µH, 3.2x2.5x1.2mm TOKO DFE322512C 1µH, 3.2x2.5x1.2mm PVIN and VOUT Capacitor Selection The input and output capacitors should be ceramic X5R type with low ESL and ESR. The recommended input capacitor value is 22µF, as this would provide adequate RMS current to minimize the input voltage ripple. A minimum of 10µF is required to maintain full functionality of the part. The recommended output capacitor is 2x22µF, 10V, X5R. Note that the effective value of a ceramic capacitor derates with DC voltage bias across it. This derating may be up to 70% of the rated capacitance. TABLE 2. CAPACITOR VENDOR INFORMATION MANUFACTURER PN DESCRIPTION Murata GRM188R61A226ME15D 22µF, 0603, 10V, X5R TDK C1608X5R1A226M080AC 22µF, 0603, 10V, X5R Refer to the capacitor datasheet to ensure the combined effective output capacitance is at least 14µF for proper operation over the entire recommended load current range. Low output capacitance may lead to large output voltage drop during load transient or unstable operation. FN8687 Rev 0.00 March 2, 2015 Recommended PCB Layout Correct PCB layout is critical for proper operation of the ISL91107IR. The following are some general guidelines for the recommended layout: 1. The input and output capacitors should be positioned as close to the IC as possible. 2. The ground connections of the input and output capacitors should be kept as short as possible. The objective is to minimize the current loop between the ground pads of the input and output capacitors and the PGND pins of the IC. Use vias, if required, to take advantage of a PCB ground layer underneath the regulator. 3. The analog ground pin (SGND) should be connected to a large/low-noise ground plane on the top or an intermediate layer on the PCB, away from the switching current path of PGND. This ensures a low noise signal ground reference. 4. Minimize the trace lengths on the feedback loop to avoid switching noise pick-up. Vias should be avoided on the feedback loop to minimize the effect of board parasitic, particularly during load transients. 5. The LX1 and LX2 traces should be short and must be routed on the same layer as the IC. FIGURE 24. RECOMMENDED LAYOUT Page 11 of 13 ISL91107IR Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest revision. DATE REVISION March 2, 2015 FN8687.0 CHANGE Initial Release. About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support © Copyright Intersil Americas LLC 2015. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN8687 Rev 0.00 March 2, 2015 Page 12 of 13 ISL91107IR Package Outline Drawing L20.3x4A 20 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 0, 6/10 3.00 0.10 M C A B 0.05 M C 4 20x 0.25 +0.05 17 -0.07 A B A 16x 0.50 6 PIN #1 INDEX AREA 20 16 1 6 PIN 1 INDEX AREA 4.00 2.65 +/0.10 -0.15 11 0.10 (4X) A 10 VIEW "A-A" TOP VIEW 6 20x 0.40+/-0.10 1.65 +0.10 -0.15 7 BOTTOM VIEW SEE DETAIL "X" 0.10 C SEATING PLANE 0.08 C 0.80 MAX C SIDE VIEW (3.80) (2.65) (16x 0.50) (20x 0.25) (20x 0.60) C 0 . 2 REF (1.65) (2.80) 0 . 00 MIN. 0 . 05 MAX. TYPICAL RECOMMENDED LAND PATTERN DETAIL "X" NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to ASME Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal ± 0.05 4. Dimension applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be 7. JEDEC reference drawing: MO-220VEGD-NJI. either a mold or mark feature. FN8687 Rev 0.00 March 2, 2015 Page 13 of 13
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